22323 lines
2.9 MiB
22323 lines
2.9 MiB
; --------------------------------------------------------------------------------
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; @Title: M2L31 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2024-07-26 NEJ
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: Generated (TRACE32, build: 171280.), based on:
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; M2L31.svd (Ver. 1.0)
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; @Core: Cortex-M23
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; @Chip: M2L31CGDAE, M2L31CIDAE, M2L31KGDAE, M2L31KIDAE, M2L31LD4AE, M2L31LE4AE,
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; M2L31LG4AE, M2L31LGDAE, M2L31LIDAE, M2L31SE4AE, M2L31SG4AE, M2L31SGDAE,
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; M2L31SIDAE, M2L31XD4AE, M2L31YD4AE, M2L31YE4AE, M2L31YG4AE, M2L31YGDAE,
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; M2L31YIDAE, M2L31ZD4AE, M2L31ZE4AE
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; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perm2l31.per 18174 2024-07-30 14:17:27Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M23)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 29. " EXTEXCLALL ,LDREX and STREX instructions use the Global Exclusive Monitor" "Only on Shared regions,Always"
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newline
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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newline
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/o Main Extension,Reserved,Reserved,Reserved"
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newline
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xD20=Cortex-M23"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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group.long 0xD04++0x13
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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newline
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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newline
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
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newline
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
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newline
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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newline
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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newline
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bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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newline
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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group.long 0xD1C++0x0B
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
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hexmask.long.byte 0x04 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x08 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x08 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x08 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x08 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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newline
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bitfld.long 0x08 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x08 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x08 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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newline
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bitfld.long 0x08 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x08 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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bitfld.long 0x08 5. " NMIACT ,NMI exception status" "Not active,Active"
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newline
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bitfld.long 0x08 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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bitfld.long 0x08 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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bitfld.long 0x08 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
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newline
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bitfld.long 0x08 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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bitfld.long 0x08 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
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bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
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textline " "
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
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wgroup.long 0xF58++0x23
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line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
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line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
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line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
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hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
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line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
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line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
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hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
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line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
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hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
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tree.end
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width 11.
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tree "CoreSight Identification Registers"
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "DPIDR0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "DPIDR1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "DPIDR2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
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hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
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line.long 0x0c "DPIDR3,Peripheral ID3"
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hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
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hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
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rgroup.long 0xFD0++0x03
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line.long 0x00 "PID4,Peripheral Identification Register 4"
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hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
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hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
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rgroup.long 0xFF0++0x0F
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line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
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hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
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line.long 0x04 "DCIDR1,Component ID1"
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hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
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hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
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line.long 0x08 "DCIDR2,Component ID2"
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hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
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line.long 0x0C "DCIDR3,Component ID3"
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hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
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tree.end
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width 0x0B
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,,,,4,,,,8,,,,,,,,16,?..."
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bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
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bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
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bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
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|
newline
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|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
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bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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newline
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hgroup.long 0xDA0++0x03
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|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Memory attribute encoding for MPU regions with an AttrIndex of 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Memory attribute encoding for MPU regions with an AttrIndex of 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Memory attribute encoding for MPU regions with an AttrIndex of 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Memory attribute encoding for MPU regions with an AttrIndex of 0"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ATTR7 ,Memory attribute encoding for MPU regions with an AttrIndex of 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " ATTR6 ,Memory attribute encoding for MPU regions with an AttrIndex of 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " ATTR5 ,Memory attribute encoding for MPU regions with an AttrIndex of 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ATTR4 ,Memory attribute encoding for MPU regions with an AttrIndex of 4"
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,,,,4,,,,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hgroup.long 0xDDC++0x03 "Region 8 (not accessible)"
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RBAR8,SAU Region Base Address Register 8"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RLAR8,SAU Region Limit Address Register 8"
|
|
hgroup.long 0xDDC++0x03 "Region 9 (not accessible)"
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RBAR9,SAU Region Base Address Register 9"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RLAR9,SAU Region Limit Address Register 9"
|
|
hgroup.long 0xDDC++0x03 "Region 10 (not accessible)"
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RBAR10,SAU Region Base Address Register 10"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RLAR10,SAU Region Limit Address Register 10"
|
|
hgroup.long 0xDDC++0x03 "Region 11 (not accessible)"
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RBAR11,SAU Region Base Address Register 11"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RLAR11,SAU Region Limit Address Register 11"
|
|
hgroup.long 0xDDC++0x03 "Region 12 (not accessible)"
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RBAR12,SAU Region Base Address Register 12"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RLAR12,SAU Region Limit Address Register 12"
|
|
hgroup.long 0xDDC++0x03 "Region 13 (not accessible)"
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RBAR13,SAU Region Base Address Register 13"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RLAR13,SAU Region Limit Address Register 13"
|
|
hgroup.long 0xDDC++0x03 "Region 14 (not accessible)"
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RBAR14,SAU Region Base Address Register 14"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RLAR14,SAU Region Limit Address Register 14"
|
|
hgroup.long 0xDDC++0x03 "Region 15 (not accessible)"
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RBAR15,SAU Region Base Address Register 15"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RLAR15,SAU Region Limit Address Register 15"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-239,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 24.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 24.
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 11.
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
width 13.
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x0F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x0F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
width 13.
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
textline " "
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
rbitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)==0x1)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x4)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xC)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xF)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
endif
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)==0x1)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x4)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xC)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xF)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
endif
|
|
group.long (0x70+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)==0x1)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x4)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xC)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xF)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)==0x1)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x4)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xC)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xF)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
endif
|
|
group.long (0x90+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)==0x1)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x4)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xC)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xF)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
endif
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION8,DWT Function Register 8"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)==0x1)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x4)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xC)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xF)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
endif
|
|
group.long (0xB0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION9,DWT Function Register 9"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)==0x1)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x4)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xC)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xF)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
endif
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION10,DWT Function Register 10"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)==0x1)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x4)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xC)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xF)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
endif
|
|
group.long (0xD0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION11,DWT Function Register 11"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)==0x1)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x4)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xC)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xF)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
endif
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION12,DWT Function Register 12"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)==0x1)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x4)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xC)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xF)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
endif
|
|
group.long (0xF0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION13,DWT Function Register 13"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x4)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xC)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xF)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
endif
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION14,DWT Function Register 14"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x4)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xC)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xF)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
endif
|
|
group.long (0x110+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION15,DWT Function Register 15"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
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|
newline
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endif
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tree.end
|
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tree.end
|
|
AUTOINDENT.POP
|
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tree.end
|
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tree "ACMP (Analog Comparator Controller)"
|
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base ad:0x0
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tree "ACMP01"
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base ad:0x40045000
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group.long 0x0++0x13
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line.long 0x0 "ACMP_CTL0,Analog Comparator 0 Control Register"
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bitfld.long 0x0 30.--31. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?"
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bitfld.long 0x0 28.--29. "MODESEL,Comparator Power Mode Selection" "0: Low power mode comparator AVDD current 1uA,1: Low power mode comparator AVDD current 2uA,?,?"
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newline
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bitfld.long 0x0 24.--26. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,?,?,?,?,?,?,?"
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bitfld.long 0x0 20.--21. "FCLKDIV,Comparator Output Filter Clock Divider" "0: Comparator output filter clock = PCLK,1: Comparator output filter clock = PCLK/2,?,?"
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bitfld.long 0x0 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected"
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bitfld.long 0x0 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
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newline
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bitfld.long 0x0 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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bitfld.long 0x0 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP0 output is sampled 1 consecutive PCLK,?,?,?,?,?,?"
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bitfld.long 0x0 12. "OUTSEL,Comparator Output Select" "0: Comparator 0 output to ACMP0_O pin is unfiltered..,1: Comparator 0 output to ACMP0_O pin is from.."
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bitfld.long 0x0 8.--10. "POSSEL,Comparator Positive Input Selection" "0: ACMP0_P0 pin,1: ACMP0_P1 pin,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "NEGSEL,Comparator Negative Input Selection\nNote: NEGSEL must select 0x1 in calibration mode." "0: ACMP0_N pin,1: Internal comparator reference voltage (CRV0),?,?,?,?,?,?"
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bitfld.long 0x0 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled"
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bitfld.long 0x0 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled. If WKEN.."
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bitfld.long 0x0 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 0 Disabled,1: Comparator 0 Enabled"
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line.long 0x4 "ACMP_CTL1,Analog Comparator 1 Control Register"
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bitfld.long 0x4 30.--31. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF1 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?"
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bitfld.long 0x4 28.--29. "MODESEL,Comparator Power Mode Selection" "0: low power mode comparator AVDD current 1uA,1: low power mode comparator AVDD current 2uA,?,?"
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bitfld.long 0x4 24.--26. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,?,?,?,?,?,?,?"
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bitfld.long 0x4 20.--21. "FCLKDIV,Comparator Output Filter Clock Divider" "0: comparator output filter clock = PCLK,1: comparator output filter clock = PCLK/2,?,?"
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newline
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bitfld.long 0x4 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode is Selected"
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bitfld.long 0x4 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
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newline
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bitfld.long 0x4 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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bitfld.long 0x4 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP1 output is sampled 1 consecutive PCLK,?,?,?,?,?,?"
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newline
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bitfld.long 0x4 12. "OUTSEL,Comparator Output Select" "0: Comparator 1 output to ACMP1_O pin is unfiltered..,1: Comparator 1 output to ACMP1_O pin is from.."
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bitfld.long 0x4 8.--10. "POSSEL,Comparator Positive Input Selection" "0: ACMP1_P0 pin,1: ACMP1_P1 pin,?,?,?,?,?,?"
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newline
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bitfld.long 0x4 4.--6. "NEGSEL,Comparator Negative Input Selection\nNote: NEGSEL must select 0x1 in calibration mode." "0: ACMP1_N pin,1: Internal comparator reference voltage (CRV1),?,?,?,?,?,?"
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bitfld.long 0x4 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled"
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newline
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bitfld.long 0x4 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled. If WKEN.."
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bitfld.long 0x4 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 1 Disabled,1: Comparator 1 Enabled"
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line.long 0x8 "ACMP_STATUS,Analog Comparator 01 Status Register"
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bitfld.long 0x8 16. "ACMPWO,Comparator Window Output\nThis bit shows the output status of window compare mode" "0: The positive input voltage is outside the window,1: The positive input voltage is in the window"
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bitfld.long 0x8 13. "ACMPS1,Comparator 1 Status\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0." "0,1"
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bitfld.long 0x8 12. "ACMPS0,Comparator 0 Status \nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0." "0,1"
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bitfld.long 0x8 9. "WKIF1,Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
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bitfld.long 0x8 8. "WKIF0,Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
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bitfld.long 0x8 5. "ACMPO1,Comparator 1 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0." "0,1"
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bitfld.long 0x8 4. "ACMPO0,Comparator 0 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0." "0,1"
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bitfld.long 0x8 1. "ACMPIF1,Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[31:30]) is detected on comparator 1 output. This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.\nNote: Write 1 to clear.." "0,1"
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bitfld.long 0x8 0. "ACMPIF0,Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[31:30]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.\nNote: Write 1 to.." "0,1"
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line.long 0xC "ACMP_VREF,Analog Comparator 01 Reference Voltage Control Register"
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bitfld.long 0xC 24. "CRV1EN,CRV1 Enable Bit" "0: CRV1 Disabled,1: CRV1 Enabled"
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bitfld.long 0xC 22. "CRV1SSEL,CRV1 Source Voltage Selection" "0: AVDD is selected as CRV1 source voltage,1: The reference voltage defined by SYS_VREFCTL.."
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newline
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hexmask.long.byte 0xC 16.--21. 1. "CRV1SEL,Comparator1 Reference Voltage Setting"
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bitfld.long 0xC 8. "CRV0EN,CRV0 Enable Bit" "0: CRV0 Disabled,1: CRV0 Enabled"
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newline
|
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bitfld.long 0xC 6. "CRV0SSEL,CRV0 Source Voltage Selection" "0: AVDD is selected as CRV0 source voltage,1: The reference voltage defined by SYS_VREFCTL.."
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hexmask.long.byte 0xC 0.--5. 1. "CRV0SEL,Comparator0 Reference Voltage Setting"
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line.long 0x10 "ACMP_CALCTL,Analog Comparator 01 Calibration Control Register"
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bitfld.long 0x10 1. "CALTRG1,Comparator1 Calibration Trigger Bit\nNote 1: Before this bit is enabled ACMPEN(ACMP_CTL1[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will auto clear this bit when the next.." "0: Calibration is stopped,1: Before this bit is enabled"
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bitfld.long 0x10 0. "CALTRG0,Comparator0 Calibration Trigger Bit\nNote 1: Before this bit is enabled ACMPEN(ACMP_CTL0[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will auto clear this bit when the next.." "0: Calibration is stopped,1: Before this bit is enabled"
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rgroup.long 0x14++0x3
|
|
line.long 0x0 "ACMP_CALSR,Analog Comparator 01 Calibration Status Register"
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|
bitfld.long 0x0 4. "DONE1,Comparator1 Calibration Done Status\nNote: This bit is is cleared by writing 1 into it." "0: Calibrating,1: Calibration done"
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bitfld.long 0x0 0. "DONE0,Comparator0 Calibration Done Status\nNote: This bit is is cleared by writing 1 into it." "0: Calibrating,1: Calibration done"
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tree.end
|
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tree "ACMP45"
|
|
base ad:0x400C9000
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group.long 0x0++0x3
|
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line.long 0x0 "ACMP_CTL2,Analog Comparator 2 Control Register"
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bitfld.long 0x0 30.--31. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF2 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?"
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bitfld.long 0x0 28.--29. "MODESEL,Comparator Power Mode Selection" "0: Low power mode comparator AVDD current 1uA,1: Low power mode comparator AVDD current 2uA,?,?"
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newline
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bitfld.long 0x0 24.--26. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,?,?,?,?,?,?,?"
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bitfld.long 0x0 20.--21. "FCLKDIV,Comparator Output Filter Clock Divider" "0: Comparator output filter clock = PCLK,1: Comparator output filter clock = PCLK/2,?,?"
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newline
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bitfld.long 0x0 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
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bitfld.long 0x0 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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bitfld.long 0x0 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP2 output is sampled 1 consecutive PCLK,?,?,?,?,?,?"
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bitfld.long 0x0 12. "OUTSEL,Comparator Output Select" "0: Comparator 2 output to ACMP2_O pin is unfiltered..,1: Comparator 2 output to ACMP2_O pin is from.."
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newline
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bitfld.long 0x0 8.--10. "POSSEL,Comparator Positive Input Selection" "0: ACMP2_P0 pin,1: ACMP2_P1 pin,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "NEGSEL,Comparator Negative Input Selection\nNote: NEGSEL must select 0x1 in calibration mode." "0: ACMP2_N pin,1: Internal comparator reference voltage (CRV2),?,?,?,?,?,?"
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newline
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bitfld.long 0x0 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 2 output inverse Disabled,1: Comparator 2 output inverse Enabled"
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bitfld.long 0x0 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 2 interrupt Disabled,1: Comparator 2 interrupt Enabled. If WKEN.."
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newline
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bitfld.long 0x0 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 2 Disabled,1: Comparator 2 Enabled"
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group.long 0x8++0xB
|
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line.long 0x0 "ACMP_STATUS2,Analog Comparator 2 Status Register"
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bitfld.long 0x0 12. "ACMPS2,Comparator 2 Status \nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 2 is disabled i.e. ACMPEN (ACMP_CTL2[0]) is cleared to 0." "0,1"
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bitfld.long 0x0 8. "WKIF2,Comparator 2 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP2 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
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newline
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bitfld.long 0x0 4. "ACMPO2,Comparator 2 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 2 is disabled i.e. ACMPEN (ACMP_CTL2[0]) is cleared to 0." "0,1"
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bitfld.long 0x0 0. "ACMPIF2,Comparator 2 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL2[31:30]) is detected on comparator 2 output. This will generate an interrupt if ACMPIE (ACMP_CTL2[1]) is set to 1.\nNote: Write 1 to.." "0,1"
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line.long 0x4 "ACMP_VREF2,Analog Comparator 2 Reference Voltage Control Register"
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bitfld.long 0x4 8. "CRV2EN,CRV2 Enable Bit" "0: CRV2 Disabled,1: CRV2 Enabled"
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bitfld.long 0x4 6. "CRV2SSEL,CRV2 Source Voltage Selection" "0: AVDD is selected as CRV2 source voltage,1: The reference voltage defined by SYS_VREFCTL.."
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newline
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hexmask.long.byte 0x4 0.--5. 1. "CRV2SEL,Comparator2 Reference Voltage Setting"
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line.long 0x8 "ACMP_CALCTL2,Analog Comparator 2 Calibration Control Register"
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bitfld.long 0x8 0. "CALTRG2,Comparator 2 Calibration Trigger Bit\nNote 1: Before this bit is enabled ACMPEN(ACMP_CTL2[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will auto clear this bit when the next.." "0: Calibration is stopped,1: Before this bit is enabled"
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rgroup.long 0x14++0x3
|
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line.long 0x0 "ACMP_CALSR2,Analog Comparator 2 Calibration Status Register"
|
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bitfld.long 0x0 0. "DONE2,Comparator2 Calibration Done Status\nNote: This bit is is cleared by writing 1 into it." "0: Calibrating,1: Calibration done"
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tree.end
|
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tree.end
|
|
tree "CANFD (Controller Area Network with Flexible DataRate)"
|
|
base ad:0x0
|
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tree "CANFD0"
|
|
base ad:0x40020000
|
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rgroup.long 0xC++0xB
|
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line.long 0x0 "CANFD_DBTP,Data Bit Timing Prescaler Register (P*)"
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bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
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hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
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newline
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
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hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Re-Synchronization Jump Width"
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line.long 0x4 "CANFD_TEST,Test Register (P*)"
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bitfld.long 0x4 7. "RX,Receive Pin\nMonitors the actual value of pin CANx_RXD" "0: The CAN bus is dominant (CANx_RXD = 0),1: The CAN bus is recessive (CANx_RXD = 1)"
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bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CANx_TXD controlled by the CAN Core..,1: Sample Point can be monitored at pin CANx_TXD,?,?"
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newline
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bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode is disabled,1: Loop Back Mode is enabled (refer to 0 TEST Mode)"
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line.long 0x8 "CANFD_RWD,RAM Watchdog (P*)"
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hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value \nActual Message RAM Watchdog Counter Value."
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hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Conguration \nStart value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled."
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group.long 0x18++0x3
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line.long 0x0 "CANFD_CCCR,CC Control Register (Pp*)"
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bitfld.long 0x0 15. "NISO,Non ISO Operation\nIf this bit is set the CAN FD controller uses the CAN FD frame format as specied by the Bosch CAN FD Specication V1.0." "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
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bitfld.long 0x0 14. "TXP,Transmit Pause\nIf this bit is set the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to 0)." "0: Transmit pause disabled,1: Transmit pause enabled"
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newline
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bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
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bitfld.long 0x0 12. "PXHD,Protocol Exception Handling Disable\nNote: When protocol exception handling is disabled the controller will transmit an error frame when it detects a protocol exception condition." "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
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newline
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bitfld.long 0x0 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
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bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
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newline
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bitfld.long 0x0 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
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bitfld.long 0x0 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
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newline
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bitfld.long 0x0 5. "MON,Bus Monitoring Mode\nBit MON can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the Host at any time." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
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bitfld.long 0x0 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.."
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newline
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bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: The Controller may be set in power down by.."
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bitfld.long 0x0 2. "ASM,Restricted Operation Mode\nBit ASM can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the software at any time. This bit will be set automatically set to 1 when the Tx handler was not able to read data from the.." "0: Normal CAN operation,1: Restricted Operation Mode active"
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newline
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bitfld.long 0x0 1. "CCE,Conguration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
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bitfld.long 0x0 0. "INIT,Initialization\nNote: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been.." "0: Normal Operation,1: Initialization is started"
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rgroup.long 0x1C++0x13
|
|
line.long 0x0 "CANFD_NBTP,Nominal Bit Timing Prescaler Register (P*)"
|
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hexmask.long.byte 0x0 25.--31. 1. "NSJW,Nominal Re-Synchronization Jump Width"
|
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hexmask.long.word 0x0 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler\nThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual.."
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
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hexmask.long.byte 0x0 0.--6. 1. "NTSEG2,Nominal Time segment after sample point\nNote: With a CAN Core clock (cclk) of 8 MHz the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s."
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line.long 0x4 "CANFD_TSCC,Timestamp Counter Conguration (P*)"
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hexmask.long.byte 0x4 16.--19. 1. "TCP,Timestamp Counter Prescaler\nCongures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
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bitfld.long 0x4 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
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|
line.long 0x8 "CANFD_TSCV,Timestamp Counter Value (C*)"
|
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hexmask.long.word 0x8 0.--15. 1. "TSC,Timestamp Counter\nNote: A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not caused by write access to CANFD_TSCV."
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line.long 0xC "CANFD_TOCC,Timeout Counter Conguration (P*)"
|
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hexmask.long.word 0xC 16.--31. 1. "TOP,Timeout Period\nStart value of the Timeout Counter (down-counter). Congures the Timeout Period."
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bitfld.long 0xC 1.--2. "TOS,Timeout Select\nWhen operating in Continuous mode a write to CANFD_TOCV presets the counter to the value congured by TOP (CANFD_TOCC[31:16]) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs an empty FIFO.." "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
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newline
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bitfld.long 0xC 0. "ETOC,Enable Timeout Counter\nNote: For use of timeout function with CAN FD refer to 0." "0: Timeout Counter disabled,1: Timeout Counter enabled"
|
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line.long 0x10 "CANFD_TOCV,Timeout Counter Value (C*)"
|
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hexmask.long.word 0x10 0.--15. 1. "TOC,Timeout Counter\nThe filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the conguration of TCP (CANFD_TSCC[19:16]). When decremented to zero interrupt ag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. Start and.."
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rgroup.long 0x40++0xB
|
|
line.long 0x0 "CANFD_ECR,Error Counter Register (X*)"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging\nThe counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached."
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bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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newline
|
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter values between 0 and 127."
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter values between 0 and 255.\nNote: When ASM (CANFD_CCCR[2]) is set the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected but CEL is still.."
|
|
line.long 0x4 "CANFD_PSR,Protocol Status Register (XS*)"
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hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value\nPosition of the secondary sample point dened by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (CANFD_TDCR[[14:8]). The SSP position is in the data phase the number of minimum time quata.."
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bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message\nThis bit is set independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RFDF reading bytes 3/2/1 has no impact." "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF ag set has.."
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bitfld.long 0x4 12. "RBRS,BRS ag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RBRS reading bytes 3/2/1 has no impact." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS ag set"
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bitfld.long 0x4 11. "RESI,ESI ag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance ltering." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI ag set"
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bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code\nType of last error that occurred in the data phase of a CAN FD format frame with its BRS ag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS ag set has been.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The CAN FD controller is not Bus_Off,1: The CAN FD controller is in Bus_Off state"
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bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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bitfld.long 0x4 5. "EP,Error Passive" "0: The CAN FD controller is in the Error_Active..,1: The CAN FD controller is in the Error_Passive.."
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bitfld.long 0x4 3.--4. "ACT,Activity\nMonitors the module's CAN communication state." "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,?,?"
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bitfld.long 0x4 0.--2. "LEC,Last Error Code\nThe LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error." "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,?,?,?,?,?,?"
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line.long 0x8 "CANFD_TDCR,Transmitter Delay Compensation Register (P*)"
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hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset\nOffset value dening the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. Valid values are 0 to 127 mtq."
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hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length\nDenes the minimum value for the SSP position dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when.."
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group.long 0x50++0xF
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line.long 0x0 "CANFD_IR,Interrupt Register"
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bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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bitfld.long 0x0 28. "PED,Protocol Error in Data Phase\nNote: Data bit time is used" "0: No protocol error in data phase,1: Protocol error in data phase detected (DLEC.."
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase\nNote: Nominal bit time is used" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
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bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
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bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
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bitfld.long 0x0 22. "ELO,Error Logging Overow" "0: CAN Error Logging Counter did not overow,1: Overow of CAN Error Logging Counter occurred"
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer\nThe flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0: No Rx Buffer updated,1: At least one received message stored into an Rx.."
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bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure\nThe ag is set when the Rx Handler\n• Has not completed acceptance ltering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance ltering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
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bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO ll level below watermark,1: Tx Event FIFO ll level reached watermark"
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bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
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bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
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bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
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bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
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bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 ll level below watermark,1: Rx FIFO 1 ll level reached watermark"
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bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
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bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 ll level below watermark,1: Rx FIFO 0 ll level reached watermark"
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bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
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line.long 0x4 "CANFD_IE,Interrupt Enable"
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bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 22. "ELOE,Error Logging Overow Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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line.long 0x8 "CANFD_ILS,Interrupt Line Select"
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bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
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bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
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bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
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bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
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bitfld.long 0x8 22. "ELOL,Error Logging Overow Interrupt Line" "0,1"
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bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line ." "0,1"
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bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line ." "0,1"
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
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bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
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bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
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bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
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bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
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bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
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bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
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bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
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bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
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bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
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bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
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bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
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bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
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bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
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bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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line.long 0xC "CANFD_ILE,Interrupt Line Enable"
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bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_can_int1 disabled,1: Interrupt line m_can_int1 enabled"
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bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_can_int0 disabled,1: Interrupt line m_can_int0 enabled"
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rgroup.long 0x80++0xB
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line.long 0x0 "CANFD_GFC,Global Filter Conguration (P*)"
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bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard\nDenes how received messages with 11-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended\nDenes how received messages with 29-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
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bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
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line.long 0x4 "CANFD_SIDFC,Standard ID Filter Conguration (P*)"
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hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
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hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address\nStart address of standard Message ID lter list (32-bit word address refer to Figure 011)."
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line.long 0x8 "CANFD_XIDFC,Extended ID Filter Conguration (P*)"
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hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
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hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address\nStart address of extended Message ID lter list (32-bit word address refer to Figure 011)"
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rgroup.long 0x90++0x7
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line.long 0x0 "CANFD_XIDAM,Extended ID AND Mask (P*)"
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hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask\nFor acceptance ltering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."
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line.long 0x4 "CANFD_HPMS,High Priority Message Status"
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bitfld.long 0x4 15. "FLST,Filter List\nIndicates the lter list of the matching lter element." "0: Standard Filter List,1: Extended Filter List"
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hexmask.long.byte 0x4 8.--14. 1. "FIDX,Filter Index\nIndex of matching filter element. Range is 0 to LSS (CANFD_SIDFC[23:16]) - 1 or LSE (CANFD_XIDFC[22:16]) - 1"
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bitfld.long 0x4 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
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hexmask.long.byte 0x4 0.--5. 1. "BIDX,Buffer Index"
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group.long 0x98++0x7
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line.long 0x0 "CANFD_NDAT1,New Data 1"
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hexmask.long 0x0 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 0 to 31. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
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line.long 0x4 "CANFD_NDAT2,New Data 2"
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hexmask.long 0x4 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 32 to 63. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
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rgroup.long 0xA0++0x7
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line.long 0x0 "CANFD_RXF0C,Rx FIFO 0 Conguration (P*)"
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bitfld.long 0x0 31. "F0OM,FIFO 0 Operation Mode\nFIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
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hexmask.long.byte 0x0 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
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hexmask.long.byte 0x0 16.--22. 1. "F0S,Rx FIFO 0 Size\nThe Rx FIFO 0 elements are indexed from 0 to F0S-1"
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hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address\nStart address of Rx FIFO 0 in Message RAM (32-bit word address)."
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line.long 0x4 "CANFD_RXF0S,Rx FIFO 0 Status"
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bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "?,1: Rx FIFO 0 message lost also set after write.."
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bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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hexmask.long.byte 0x4 16.--21. 1. "F0PI,Rx FIFO 0 Put Index\nRx FIFO 0 write index pointer range 0 to 63."
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hexmask.long.byte 0x4 8.--13. 1. "F0GI,Rx FIFO 0 Get Index\nRx FIFO 0 read index pointer range 0 to 63."
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hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level\nNumber of elements stored in Rx FIFO 0 range 0 to 64"
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group.long 0xA8++0x3
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line.long 0x0 "CANFD_RXF0A,Rx FIFO 0 Acknowledge"
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hexmask.long.byte 0x0 0.--5. 1. "F0A,Rx FIFO 0 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]).."
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rgroup.long 0xAC++0xB
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line.long 0x0 "CANFD_RXBC,Rx Buffer Conguration (P*)"
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hexmask.long.word 0x0 2.--15. 1. "RBSA,Rx Buffer Start Address\nCongures the start address of the Rx Buffers section in the Message RAM (32-bit word address)."
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line.long 0x4 "CANFD_RXF1C,Rx FIFO 1 Conguration (P*)"
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bitfld.long 0x4 31. "F1OM,FIFO 1 Operation Mode\nFIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
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hexmask.long.byte 0x4 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
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hexmask.long.byte 0x4 16.--22. 1. "F1S,Rx FIFO 1 Size\nThe Rx FIFO 1 elements are indexed from 0 to F1S - 1"
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hexmask.long.word 0x4 2.--15. 1. "F1SA,Rx FIFO 1 Start Address\nStart address of Rx FIFO 1 in Message RAM (32-bit word address refer to Figure 011)."
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line.long 0x8 "CANFD_RXF1S,Rx FIFO 1 Status"
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bitfld.long 0x8 25. "RF1L,Rx FIFO 1 Message Lost" "?,1: Rx FIFO 1 message lost also set after write.."
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bitfld.long 0x8 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
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hexmask.long.byte 0x8 16.--21. 1. "F1PI,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1 range 0 to 64."
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hexmask.long.byte 0x8 8.--13. 1. "F1GI,Rx FIFO 1 Get Index\nRx FIFO 1 read index pointer range 0 to 63."
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hexmask.long.byte 0x8 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1 range 0 to 64"
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group.long 0xB8++0x3
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line.long 0x0 "CANFD_RXF1A,Rx FIFO 1 Acknowledge"
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hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]).."
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rgroup.long 0xBC++0x13
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line.long 0x0 "CANFD_RXESC,Rx Buffer / FIFO Element Size Conguration (P*)"
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bitfld.long 0x0 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 0 Data Field Size\nNote: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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line.long 0x4 "CANFD_TXBC,Tx Buffer Conguration (P*)"
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bitfld.long 0x4 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
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hexmask.long.byte 0x4 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
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hexmask.long.byte 0x4 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
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hexmask.long.word 0x4 2.--15. 1. "TBSA,Tx Buffers Start Address\nStart address of Tx Buffers section in Message RAM (32-bit word address refer to Figure 011).\nNote: The sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers.."
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line.long 0x8 "CANFD_TXFQS,Tx FIFO/Queue Status"
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bitfld.long 0x8 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue is not full,1: Tx FIFO/Queue is full"
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hexmask.long.byte 0x8 16.--20. 1. "TFQP,Tx FIFO/Queue Put Index\nTx FIFO/Queue write index pointer range 0 to 31."
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hexmask.long.byte 0x8 8.--12. 1. "TFG,Tx FIFO Get Index"
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hexmask.long.byte 0x8 0.--5. 1. "TFFL,Tx FIFO Free Level\nNote: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.\nExample: For.."
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line.long 0xC "CANFD_TXESC,Tx Buffer Element Size Conguration (P*)"
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bitfld.long 0xC 0.--2. "TBDS,Tx Buffer Data Field Size\nNote: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TBDS(CANFD_TXESC[2:0]) the bytes not defined by the Tx Buffer are transmitted as 0xCC.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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line.long 0x10 "CANFD_TXBRP,Tx Buffer Request Pending"
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hexmask.long 0x10 0.--31. 1. "TRPn,Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register.."
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group.long 0xD0++0x7
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line.long 0x0 "CANFD_TXBAR,Tx Buffer Add Request"
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hexmask.long 0x0 0.--31. 1. "ARn,Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR.."
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line.long 0x4 "CANFD_TXBCR,Tx Buffer Cancellation Request"
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hexmask.long 0x4 0.--31. 1. "CRn,Cancellation Request\nEach Tx Buffer has its own Cancellation Request bit. Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one.."
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rgroup.long 0xD8++0x7
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line.long 0x0 "CANFD_TXBTO,Tx Buffer Transmission Occurred"
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hexmask.long 0x0 0.--31. 1. "TOn,Transmission Occurred\nEach Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to.."
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line.long 0x4 "CANFD_TXBCF,Tx Buffer Cancellation Finished"
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hexmask.long 0x4 0.--31. 1. "CFn,Cancellation Finished\nEach Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. In case the corresponding CANFD_TXBRP bit was not set.."
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group.long 0xE0++0x7
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line.long 0x0 "CANFD_TXBTIE,Tx Buffer Transmission Interrupt Enable"
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hexmask.long 0x0 0.--31. 1. "TIEn,Transmission Interrupt Enable\nEach Tx Buffer has its own Transmission Interrupt enable bit."
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line.long 0x4 "CANFD_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
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hexmask.long 0x4 0.--31. 1. "CFIEn,Cancellation Finished Interrupt Enable\nEach Tx Buffer has its own Cancellation Finished Interrupt Enable bit."
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rgroup.long 0xF0++0x7
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line.long 0x0 "CANFD_TXEFC,Tx Event FIFO Conguration (P*)"
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hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
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hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size\nThe Tx Event FIFO elements are indexed from 0 to EFS - 1"
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hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address\nStart address of Tx Event FIFO in Message RAM (32-bit word address refer to Figure 011)."
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line.long 0x4 "CANFD_TXEFS,Tx Event FIFO Status"
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bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element Lost\nThis bit is a copy of interrupt ag TEFL (CANFD_IR[15]). When TEFL is reset this bit is also reset." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
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bitfld.long 0x4 24. "EFF,Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
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hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO Put Index\nTx Event FIFO write index pointer range 0 to 31"
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hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index\nTx Event FIFO read index pointer range 0 to 31"
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hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level\nNumber of elements stored in Tx Event FIFO range 0 to 32"
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group.long 0xF8++0x3
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line.long 0x0 "CANFD_TXEFA,Tx Event FIFO Acknowledge"
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hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index\nAfter the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index EFGI.."
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tree.end
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tree "CANFD1"
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base ad:0x40024000
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rgroup.long 0xC++0xB
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line.long 0x0 "CANFD_DBTP,Data Bit Timing Prescaler Register (P*)"
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bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
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hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
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hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Re-Synchronization Jump Width"
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line.long 0x4 "CANFD_TEST,Test Register (P*)"
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bitfld.long 0x4 7. "RX,Receive Pin\nMonitors the actual value of pin CANx_RXD" "0: The CAN bus is dominant (CANx_RXD = 0),1: The CAN bus is recessive (CANx_RXD = 1)"
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bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0: Reset value CANx_TXD controlled by the CAN Core..,1: Sample Point can be monitored at pin CANx_TXD,?,?"
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bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode is disabled,1: Loop Back Mode is enabled (refer to 0 TEST Mode)"
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line.long 0x8 "CANFD_RWD,RAM Watchdog (P*)"
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hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value \nActual Message RAM Watchdog Counter Value."
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hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Conguration \nStart value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled."
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group.long 0x18++0x3
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line.long 0x0 "CANFD_CCCR,CC Control Register (Pp*)"
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bitfld.long 0x0 15. "NISO,Non ISO Operation\nIf this bit is set the CAN FD controller uses the CAN FD frame format as specied by the Bosch CAN FD Specication V1.0." "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
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bitfld.long 0x0 14. "TXP,Transmit Pause\nIf this bit is set the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to 0)." "0: Transmit pause disabled,1: Transmit pause enabled"
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bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
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bitfld.long 0x0 12. "PXHD,Protocol Exception Handling Disable\nNote: When protocol exception handling is disabled the controller will transmit an error frame when it detects a protocol exception condition." "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
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bitfld.long 0x0 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
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bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
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bitfld.long 0x0 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
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bitfld.long 0x0 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
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bitfld.long 0x0 5. "MON,Bus Monitoring Mode\nBit MON can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the Host at any time." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
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bitfld.long 0x0 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested. When clock stop is.."
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newline
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bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: The Controller may be set in power down by.."
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bitfld.long 0x0 2. "ASM,Restricted Operation Mode\nBit ASM can only be set by the Host when both CCE and INIT are set to 1. The bit can be reset by the software at any time. This bit will be set automatically set to 1 when the Tx handler was not able to read data from the.." "0: Normal CAN operation,1: Restricted Operation Mode active"
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newline
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bitfld.long 0x0 1. "CCE,Conguration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
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bitfld.long 0x0 0. "INIT,Initialization\nNote: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been.." "0: Normal Operation,1: Initialization is started"
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rgroup.long 0x1C++0x13
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line.long 0x0 "CANFD_NBTP,Nominal Bit Timing Prescaler Register (P*)"
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hexmask.long.byte 0x0 25.--31. 1. "NSJW,Nominal Re-Synchronization Jump Width"
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hexmask.long.word 0x0 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler\nThe value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual.."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
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hexmask.long.byte 0x0 0.--6. 1. "NTSEG2,Nominal Time segment after sample point\nNote: With a CAN Core clock (cclk) of 8 MHz the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s."
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line.long 0x4 "CANFD_TSCC,Timestamp Counter Conguration (P*)"
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hexmask.long.byte 0x4 16.--19. 1. "TCP,Timestamp Counter Prescaler\nCongures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
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bitfld.long 0x4 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
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line.long 0x8 "CANFD_TSCV,Timestamp Counter Value (C*)"
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hexmask.long.word 0x8 0.--15. 1. "TSC,Timestamp Counter\nNote: A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not caused by write access to CANFD_TSCV."
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line.long 0xC "CANFD_TOCC,Timeout Counter Conguration (P*)"
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hexmask.long.word 0xC 16.--31. 1. "TOP,Timeout Period\nStart value of the Timeout Counter (down-counter). Congures the Timeout Period."
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bitfld.long 0xC 1.--2. "TOS,Timeout Select\nWhen operating in Continuous mode a write to CANFD_TOCV presets the counter to the value congured by TOP (CANFD_TOCC[31:16]) and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs an empty FIFO.." "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
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newline
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bitfld.long 0xC 0. "ETOC,Enable Timeout Counter\nNote: For use of timeout function with CAN FD refer to 0." "0: Timeout Counter disabled,1: Timeout Counter enabled"
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line.long 0x10 "CANFD_TOCV,Timeout Counter Value (C*)"
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hexmask.long.word 0x10 0.--15. 1. "TOC,Timeout Counter\nThe filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the conguration of TCP (CANFD_TSCC[19:16]). When decremented to zero interrupt ag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. Start and.."
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rgroup.long 0x40++0xB
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line.long 0x0 "CANFD_ECR,Error Counter Register (X*)"
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hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging\nThe counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached."
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bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter values between 0 and 127."
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hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter values between 0 and 255.\nNote: When ASM (CANFD_CCCR[2]) is set the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected but CEL is still.."
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line.long 0x4 "CANFD_PSR,Protocol Status Register (XS*)"
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hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value\nPosition of the secondary sample point dened by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (CANFD_TDCR[[14:8]). The SSP position is in the data phase the number of minimum time quata.."
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bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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newline
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message\nThis bit is set independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RFDF reading bytes 3/2/1 has no impact." "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF ag set has.."
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bitfld.long 0x4 12. "RBRS,BRS ag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance ltering.\nNote: Byte access: Reading byte 0 will reset RBRS reading bytes 3/2/1 has no impact." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS ag set"
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newline
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bitfld.long 0x4 11. "RESI,ESI ag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance ltering." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI ag set"
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bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code\nType of last error that occurred in the data phase of a CAN FD format frame with its BRS ag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS ag set has been.." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The CAN FD controller is not Bus_Off,1: The CAN FD controller is in Bus_Off state"
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bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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newline
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bitfld.long 0x4 5. "EP,Error Passive" "0: The CAN FD controller is in the Error_Active..,1: The CAN FD controller is in the Error_Passive.."
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bitfld.long 0x4 3.--4. "ACT,Activity\nMonitors the module's CAN communication state." "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,?,?"
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newline
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bitfld.long 0x4 0.--2. "LEC,Last Error Code\nThe LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error." "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,?,?,?,?,?,?"
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line.long 0x8 "CANFD_TDCR,Transmitter Delay Compensation Register (P*)"
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hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset\nOffset value dening the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. Valid values are 0 to 127 mtq."
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hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length\nDenes the minimum value for the SSP position dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when.."
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group.long 0x50++0xF
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line.long 0x0 "CANFD_IR,Interrupt Register"
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bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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bitfld.long 0x0 28. "PED,Protocol Error in Data Phase\nNote: Data bit time is used" "0: No protocol error in data phase,1: Protocol error in data phase detected (DLEC.."
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newline
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase\nNote: Nominal bit time is used" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
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bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
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newline
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
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bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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newline
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
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bitfld.long 0x0 22. "ELO,Error Logging Overow" "0: CAN Error Logging Counter did not overow,1: Overow of CAN Error Logging Counter occurred"
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newline
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer\nThe flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0: No Rx Buffer updated,1: At least one received message stored into an Rx.."
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bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
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newline
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure\nThe ag is set when the Rx Handler\n• Has not completed acceptance ltering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance ltering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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newline
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
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bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
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newline
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO ll level below watermark,1: Tx Event FIFO ll level reached watermark"
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bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
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newline
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
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bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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newline
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
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bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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newline
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bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
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bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
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newline
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bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 ll level below watermark,1: Rx FIFO 1 ll level reached watermark"
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bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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newline
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bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
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bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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newline
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bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 ll level below watermark,1: Rx FIFO 0 ll level reached watermark"
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bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
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line.long 0x4 "CANFD_IE,Interrupt Enable"
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bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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newline
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
newline
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overow Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
newline
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bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
newline
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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|
newline
|
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
newline
|
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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|
newline
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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newline
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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|
newline
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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|
newline
|
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bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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newline
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bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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newline
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bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
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bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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newline
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bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt is Disabled,1: Interrupt is Enabled"
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|
line.long 0x8 "CANFD_ILS,Interrupt Line Select"
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bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
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bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
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newline
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
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|
newline
|
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
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|
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|
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overow Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line ." "0,1"
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line ." "0,1"
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|
newline
|
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
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bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
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newline
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
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bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
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newline
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
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bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
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newline
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
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|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
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newline
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
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|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
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newline
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
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|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
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newline
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bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
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bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
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newline
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bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
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newline
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bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
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bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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line.long 0xC "CANFD_ILE,Interrupt Line Enable"
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bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_can_int1 disabled,1: Interrupt line m_can_int1 enabled"
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bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_can_int0 disabled,1: Interrupt line m_can_int0 enabled"
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rgroup.long 0x80++0xB
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line.long 0x0 "CANFD_GFC,Global Filter Conguration (P*)"
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bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard\nDenes how received messages with 11-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended\nDenes how received messages with 29-bit IDs that do not match any element of the lter list are treated." "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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newline
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
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bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
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line.long 0x4 "CANFD_SIDFC,Standard ID Filter Conguration (P*)"
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hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
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hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address\nStart address of standard Message ID lter list (32-bit word address refer to Figure 011)."
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line.long 0x8 "CANFD_XIDFC,Extended ID Filter Conguration (P*)"
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hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
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hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address\nStart address of extended Message ID lter list (32-bit word address refer to Figure 011)"
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rgroup.long 0x90++0x7
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line.long 0x0 "CANFD_XIDAM,Extended ID AND Mask (P*)"
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hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask\nFor acceptance ltering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."
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line.long 0x4 "CANFD_HPMS,High Priority Message Status"
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bitfld.long 0x4 15. "FLST,Filter List\nIndicates the lter list of the matching lter element." "0: Standard Filter List,1: Extended Filter List"
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hexmask.long.byte 0x4 8.--14. 1. "FIDX,Filter Index\nIndex of matching filter element. Range is 0 to LSS (CANFD_SIDFC[23:16]) - 1 or LSE (CANFD_XIDFC[22:16]) - 1"
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newline
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bitfld.long 0x4 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
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hexmask.long.byte 0x4 0.--5. 1. "BIDX,Buffer Index"
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group.long 0x98++0x7
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line.long 0x0 "CANFD_NDAT1,New Data 1"
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hexmask.long 0x0 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 0 to 31. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
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line.long 0x4 "CANFD_NDAT2,New Data 2"
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hexmask.long 0x4 0.--31. 1. "NDn,New Data\nThe register holds the New Data ags of Rx Buffers 32 to 63. The ags are set when the respective Rx Buffer has been updated from a received frame. The ags remain set until the Host clears them. A flag is cleared by writing a 1 to the.."
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rgroup.long 0xA0++0x7
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line.long 0x0 "CANFD_RXF0C,Rx FIFO 0 Conguration (P*)"
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bitfld.long 0x0 31. "F0OM,FIFO 0 Operation Mode\nFIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
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hexmask.long.byte 0x0 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
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newline
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hexmask.long.byte 0x0 16.--22. 1. "F0S,Rx FIFO 0 Size\nThe Rx FIFO 0 elements are indexed from 0 to F0S-1"
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hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address\nStart address of Rx FIFO 0 in Message RAM (32-bit word address)."
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line.long 0x4 "CANFD_RXF0S,Rx FIFO 0 Status"
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bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "?,1: Rx FIFO 0 message lost also set after write.."
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bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 is not full,1: Rx FIFO 0 is full"
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newline
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hexmask.long.byte 0x4 16.--21. 1. "F0PI,Rx FIFO 0 Put Index\nRx FIFO 0 write index pointer range 0 to 63."
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hexmask.long.byte 0x4 8.--13. 1. "F0GI,Rx FIFO 0 Get Index\nRx FIFO 0 read index pointer range 0 to 63."
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newline
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hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level\nNumber of elements stored in Rx FIFO 0 range 0 to 64"
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group.long 0xA8++0x3
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line.long 0x0 "CANFD_RXF0A,Rx FIFO 0 Acknowledge"
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hexmask.long.byte 0x0 0.--5. 1. "F0A,Rx FIFO 0 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]).."
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rgroup.long 0xAC++0xB
|
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line.long 0x0 "CANFD_RXBC,Rx Buffer Conguration (P*)"
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hexmask.long.word 0x0 2.--15. 1. "RBSA,Rx Buffer Start Address\nCongures the start address of the Rx Buffers section in the Message RAM (32-bit word address)."
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line.long 0x4 "CANFD_RXF1C,Rx FIFO 1 Conguration (P*)"
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bitfld.long 0x4 31. "F1OM,FIFO 1 Operation Mode\nFIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)." "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
|
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hexmask.long.byte 0x4 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
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newline
|
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hexmask.long.byte 0x4 16.--22. 1. "F1S,Rx FIFO 1 Size\nThe Rx FIFO 1 elements are indexed from 0 to F1S - 1"
|
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hexmask.long.word 0x4 2.--15. 1. "F1SA,Rx FIFO 1 Start Address\nStart address of Rx FIFO 1 in Message RAM (32-bit word address refer to Figure 011)."
|
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line.long 0x8 "CANFD_RXF1S,Rx FIFO 1 Status"
|
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bitfld.long 0x8 25. "RF1L,Rx FIFO 1 Message Lost" "?,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x8 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 is not full,1: Rx FIFO 1 is full"
|
|
newline
|
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hexmask.long.byte 0x8 16.--21. 1. "F1PI,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1 range 0 to 64."
|
|
hexmask.long.byte 0x8 8.--13. 1. "F1GI,Rx FIFO 1 Get Index\nRx FIFO 1 read index pointer range 0 to 63."
|
|
newline
|
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hexmask.long.byte 0x8 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1 range 0 to 64"
|
|
group.long 0xB8++0x3
|
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line.long 0x0 "CANFD_RXF1A,Rx FIFO 1 Acknowledge"
|
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hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]).."
|
|
rgroup.long 0xBC++0x13
|
|
line.long 0x0 "CANFD_RXESC,Rx Buffer / FIFO Element Size Conguration (P*)"
|
|
bitfld.long 0x0 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
bitfld.long 0x0 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
newline
|
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bitfld.long 0x0 0.--2. "F0DS,Rx FIFO 0 Data Field Size\nNote: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
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line.long 0x4 "CANFD_TXBC,Tx Buffer Conguration (P*)"
|
|
bitfld.long 0x4 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
|
|
hexmask.long.byte 0x4 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x4 2.--15. 1. "TBSA,Tx Buffers Start Address\nStart address of Tx Buffers section in Message RAM (32-bit word address refer to Figure 011).\nNote: The sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers.."
|
|
line.long 0x8 "CANFD_TXFQS,Tx FIFO/Queue Status"
|
|
bitfld.long 0x8 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue is not full,1: Tx FIFO/Queue is full"
|
|
hexmask.long.byte 0x8 16.--20. 1. "TFQP,Tx FIFO/Queue Put Index\nTx FIFO/Queue write index pointer range 0 to 31."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--12. 1. "TFG,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x8 0.--5. 1. "TFFL,Tx FIFO Free Level\nNote: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.\nExample: For.."
|
|
line.long 0xC "CANFD_TXESC,Tx Buffer Element Size Conguration (P*)"
|
|
bitfld.long 0xC 0.--2. "TBDS,Tx Buffer Data Field Size\nNote: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TBDS(CANFD_TXESC[2:0]) the bytes not defined by the Tx Buffer are transmitted as 0xCC.." "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
line.long 0x10 "CANFD_TXBRP,Tx Buffer Request Pending"
|
|
hexmask.long 0x10 0.--31. 1. "TRPn,Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register.."
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "CANFD_TXBAR,Tx Buffer Add Request"
|
|
hexmask.long 0x0 0.--31. 1. "ARn,Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR.."
|
|
line.long 0x4 "CANFD_TXBCR,Tx Buffer Cancellation Request"
|
|
hexmask.long 0x4 0.--31. 1. "CRn,Cancellation Request\nEach Tx Buffer has its own Cancellation Request bit. Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one.."
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "CANFD_TXBTO,Tx Buffer Transmission Occurred"
|
|
hexmask.long 0x0 0.--31. 1. "TOn,Transmission Occurred\nEach Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to.."
|
|
line.long 0x4 "CANFD_TXBCF,Tx Buffer Cancellation Finished"
|
|
hexmask.long 0x4 0.--31. 1. "CFn,Cancellation Finished\nEach Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. In case the corresponding CANFD_TXBRP bit was not set.."
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "CANFD_TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
hexmask.long 0x0 0.--31. 1. "TIEn,Transmission Interrupt Enable\nEach Tx Buffer has its own Transmission Interrupt enable bit."
|
|
line.long 0x4 "CANFD_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
hexmask.long 0x4 0.--31. 1. "CFIEn,Cancellation Finished Interrupt Enable\nEach Tx Buffer has its own Cancellation Finished Interrupt Enable bit."
|
|
rgroup.long 0xF0++0x7
|
|
line.long 0x0 "CANFD_TXEFC,Tx Event FIFO Conguration (P*)"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size\nThe Tx Event FIFO elements are indexed from 0 to EFS - 1"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address\nStart address of Tx Event FIFO in Message RAM (32-bit word address refer to Figure 011)."
|
|
line.long 0x4 "CANFD_TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element Lost\nThis bit is a copy of interrupt ag TEFL (CANFD_IR[15]). When TEFL is reset this bit is also reset." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
|
|
bitfld.long 0x4 24. "EFF,Event FIFO Full" "0: Tx Event FIFO is not full,1: Tx Event FIFO is full"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO Put Index\nTx Event FIFO write index pointer range 0 to 31"
|
|
hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index\nTx Event FIFO read index pointer range 0 to 31"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level\nNumber of elements stored in Tx Event FIFO range 0 to 32"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "CANFD_TXEFA,Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index\nAfter the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index EFGI.."
|
|
tree.end
|
|
tree.end
|
|
tree "CLK (Clock Controller)"
|
|
base ad:0x40000200
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CLK_PWRCTL,System Power-down Control Register"
|
|
bitfld.long 0x0 31. "HXTMD,HXT Bypass Mode (Write Protect)\nNote 2: This bit is write protected. Refer to the SYS_REGCTL register." "0: HXT work as crystal mode. PF.2 and PF.3 are..,1: HXT works as external clock mode. PF.3 is.."
|
|
bitfld.long 0x0 28.--30. "MIRCFSEL,MIRC Frequency Select Bits (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Internal middle speed RC oscillator frerquency..,1: Internal middle speed RC oscillator frerquency..,?,?,?,?,?,?"
|
|
newline
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bitfld.long 0x0 26. "MIRCEN,MIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 1/2/4/8 MHz internal multiple speed RC..,1: 1/2/4/8 MHz internal multiple speed RC.."
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bitfld.long 0x0 24.--25. "MIRCSTBS,MIRC Stable Count Select (Write Protect )\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: MIRC stable count is 128 clocks,1: MIRC stable count is 32 clocks,?,?"
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bitfld.long 0x0 20.--22. "HXTGAIN,HXT Gain Control Bit (Write Protect)\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled crystal will consume more power than gain control off. \nNote: These bits are write.." "0: HXT frequency is from 1 MHz to 4 MHz,1: HXT frequency is from 8 MHz to 12 MHz,?,?,?,?,?,?"
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bitfld.long 0x0 18. "HIRC48MEN,HIRC48M Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
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bitfld.long 0x0 16.--17. "HIRCSTBS,HIRC Stable Count Select (Write Protect )\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: HIRC stable count is 64 clocks,1: HIRC stable count is 24 clocks,?,?"
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bitfld.long 0x0 14.--15. "HIRC48MSTBS,HIRC48M Stable Count Select (Write Protect )\nNote: Thes bits are write protected. Refer to the SYS_REGLCTL register." "0: HIRC48M stable count is 1024 clocks,1: HIRC48M stable count is 512 clocks,?,?"
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bitfld.long 0x0 12. "HXTSELTYP,HXT Crystal Type Select Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Select INV type,1: Select GM type"
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bitfld.long 0x0 7. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode this bit.." "0: Chip will not enter Power-down mode after CPU..,1: Chip enters Power-down mode after CPU sleep.."
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bitfld.long 0x0 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' it indicates that resume from Power-down mode'. \nThe flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.\nNote 1: Write 1 to.." "?,1: Write 1 to clear the bit to 0"
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bitfld.long 0x0 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote 1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up interrupt Disabled,1: The interrupt will occur when both PDWKIF and.."
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bitfld.long 0x0 3. "LIRCEN,LIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32 kHz internal low speed RC oscillator (LIRC)..,1: 32 kHz internal low speed RC oscillator (LIRC).."
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bitfld.long 0x0 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 12 MHz internal high speed RC oscillator (HIRC)..,1: 12 MHz internal high speed RC oscillator (HIRC).."
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bitfld.long 0x0 1. "LXTEN,LXT Enable Bit (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: When LXT is enabled PF.4(X32_OUT) and PF.5(X32_IN) must be set as input mode." "0: 32.768 kHz external low speed crystal (LXT)..,1: This bit is write protected"
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bitfld.long 0x0 0. "HXTEN,HXT Enable Bit (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: When HXT is enabled PF.2(XT1_OUT) and PF.3(XT1_IN) must be set as input mode." "0: 4~32 MHz external high speed crystal (HXT)..,1: This bit is write protected"
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line.long 0x4 "CLK_AHBCLK0,AHB Devices Clock Enable Control Register 0"
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bitfld.long 0x4 31. "GPHCKEN,GPIOH Clock Enable Bit" "0: GPIOH port clock Disabled,1: GPIOH port clock Enabled"
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bitfld.long 0x4 30. "GPGCKEN,GPIOG Clock Enable Bit" "0: GPIOG port clock Disabled,1: GPIOG port clock Enabled"
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bitfld.long 0x4 29. "GPFCKEN,GPIOF Clock Enable Bit" "0: GPIOF port clock Disabled,1: GPIOF port clock Enabled"
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bitfld.long 0x4 28. "GPECKEN,GPIOE Clock Enable Bit" "0: GPIOE port clock Disabled,1: GPIOE port clock Enabled"
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bitfld.long 0x4 27. "GPDCKEN,GPIOD Clock Enable Bit" "0: GPIOD port clock Disabled,1: GPIOD port clock Enabled"
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bitfld.long 0x4 26. "GPCCKEN,GPIOC Clock Enable Bit" "0: GPIOC port clock Disabled,1: GPIOC port clock Enabled"
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bitfld.long 0x4 25. "GPBCKEN,GPIOB Clock Enable Bit" "0: GPIOB port clock Disabled,1: GPIOB port clock Enabled"
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bitfld.long 0x4 24. "GPACKEN,GPIOA Clock Enable Bit" "0: GPIOA port clock Disabled,1: GPIOA port clock Enabled"
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bitfld.long 0x4 23. "FMCFDIS,FMC Clock Force Disable Bit \nNote: User should make sure program no FLASH access during this bit is 1" "0: FMC clock Enabled,1: FMC clock force Disable to save power"
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bitfld.long 0x4 16. "USBHCKEN,USB HOST Controller Clock Enable Bit" "0: USB HOST peripheral clock Disabled,1: USB HOST peripheral clock Enabled"
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bitfld.long 0x4 15. "FMCIDLE,Flash Memory Controller Clock Enable Bit in IDLE Mode" "0: FMC clock Disabled when chip is under IDLE mode,1: FMC clock Enabled when chip is under IDLE mode"
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bitfld.long 0x4 13. "KSCKEN,Key Store Clock Enable Bit" "0: Key Store clock Disabled,1: Key Store clock Enabled"
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bitfld.long 0x4 12. "CRPTCKEN,Cryptographic Accelerator Clock Enable Bit" "0: Cryptographic Accelerator clock Disabled,1: Cryptographic Accelerator clock Enabled"
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bitfld.long 0x4 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled"
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bitfld.long 0x4 4. "STCKEN,System Tick Clock Enable Bit" "0: System tick clock Disabled,1: System tick clock Enabled"
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bitfld.long 0x4 3. "EBICKEN,EBI Controller Clock Enable Bit" "0: EBI peripheral clock Disabled,1: EBI peripheral clock Enabled"
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bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
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bitfld.long 0x4 1. "PDMA0CKEN,PDMA0 Controller Clock Enable Bit" "0: PDMA0 peripheral clock Disabled,1: PDMA0 peripheral clock Enabled"
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line.long 0x8 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0"
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bitfld.long 0x8 31. "TRNGCKEN,TRNG Clock Enable Bit" "0: TRNG clock Disabled,1: TRNG clock Enabled"
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bitfld.long 0x8 28. "EADC0CKEN,EADC0 Clock Enable Bit" "0: EADC0 clock Disabled,1: EADC0 clock Enabled"
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bitfld.long 0x8 27. "USBDCKEN,USB Device Clock Enable Bit" "0: USB device clock Disabled,1: USB device clock Enabled"
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bitfld.long 0x8 26. "OTGCKEN,USB OTG Clock Enable Bit" "0: USB OTG clock Disabled,1: USB OTG clock Enabled"
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bitfld.long 0x8 23. "UART7CKEN,UART7 Clock Enable Bit" "0: UART7 clock Disabled,1: UART7 clock Enabled"
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bitfld.long 0x8 22. "UART6CKEN,UART6 Clock Enable Bit" "0: UART6 clock Disabled,1: UART6 clock Enabled"
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bitfld.long 0x8 21. "UART5CKEN,UART5 Clock Enable Bit" "0: UART5 clock Disabled,1: UART5 clock Enabled"
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bitfld.long 0x8 20. "UART4CKEN,UART4 Clock Enable Bit" "0: UART4 clock Disabled,1: UART4 clock Enabled"
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bitfld.long 0x8 19. "UART3CKEN,UART3 Clock Enable Bit" "0: UART3 clock Disabled,1: UART3 clock Enabled"
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bitfld.long 0x8 18. "UART2CKEN,UART2 Clock Enable Bit" "0: UART2 clock Disabled,1: UART2 clock Enabled"
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bitfld.long 0x8 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
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bitfld.long 0x8 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
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bitfld.long 0x8 15. "SPI2CKEN,SPI2 Clock Enable Bit" "0: SPI2 clock Disabled,1: SPI2 clock Enabled"
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bitfld.long 0x8 14. "SPI1CKEN,SPI1 Clock Enable Bit" "0: SPI1 clock Disabled,1: SPI1 clock Enabled"
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bitfld.long 0x8 13. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 clock Disabled,1: SPI0 clock Enabled"
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bitfld.long 0x8 12. "QSPI0CKEN,QSPI0 Clock Enable Bit" "0: QSPI0 clock Disabled,1: QSPI0 clock Enabled"
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bitfld.long 0x8 11. "I2C3CKEN,I2C3 Clock Enable Bit" "0: I2C3 clock Disabled,1: I2C3 clock Enabled"
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bitfld.long 0x8 10. "I2C2CKEN,I2C2 Clock Enable Bit" "0: I2C2 clock Disabled,1: I2C2 clock Enabled"
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bitfld.long 0x8 9. "I2C1CKEN,I2C1 Clock Enable Bit" "0: I2C1 clock Disabled,1: I2C1 clock Enabled"
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bitfld.long 0x8 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
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bitfld.long 0x8 7. "ACMP01CKEN,ACMP01 Clock Enable Bit" "0: ACMP01 clock Disabled,1: ACMP01 clock Enabled"
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bitfld.long 0x8 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO clock Disabled,1: CLKO clock Enabled"
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bitfld.long 0x8 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
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bitfld.long 0x8 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
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bitfld.long 0x8 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
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bitfld.long 0x8 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
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bitfld.long 0x8 1. "RTCCKEN,Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCCKSEL (RTC_LXTCTL[7]). It can be selected to external low speed crystal oscillator (LXT) or.." "0: RTC clock Disabled,1: RTC clock Enabled"
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line.long 0xC "CLK_APBCLK1,APB Devices Clock Enable Control Register 1"
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bitfld.long 0xC 27. "ECAP1CKEN,ECAP1 Clock Enable Bit" "0: ECAP1 clock Disabled,1: ECAP1 clock Enabled"
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bitfld.long 0xC 26. "ECAP0CKEN,ECAP0 Clock Enable Bit" "0: ECAP0 clock Disabled,1: ECAP0 clock Enabled"
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bitfld.long 0xC 25. "TKCKEN,TK Clock Enable Bit" "0: TK clock Disabled,1: TK clock Enabled"
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bitfld.long 0xC 23. "EQEI1CKEN,EQEI1 Clock Enable Bit" "0: EQEI1 clock Disabled,1: EQEI1 clock Enabled"
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bitfld.long 0xC 22. "EQEI0CKEN,EQEI0 Clock Enable Bit" "0: EQEI0 clock Disabled,1: EQEI0 clock Enabled"
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bitfld.long 0xC 17. "EPWM1CKEN,EPWM1 Clock Enable Bit" "0: EPWM1 clock Disabled,1: EPWM1 clock Enabled"
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bitfld.long 0xC 16. "EPWM0CKEN,EPWM0 Clock Enable Bit" "0: EPWM0 clock Disabled,1: EPWM0 clock Enabled"
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bitfld.long 0xC 12. "DACEN,DAC Clock Enable Bit" "0: DAC clock Disabled,1: DAC clock Enabled"
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bitfld.long 0xC 11. "WWDTCKEN,Window Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Window Watchdog timer clock Disabled,1: Window Watchdog timer clock Enabled"
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bitfld.long 0xC 9. "USCI1CKEN,USCI1 Clock Enable Bit" "0: USCI1 clock Disabled,1: USCI1 clock Enabled"
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bitfld.long 0xC 8. "USCI0CKEN,USCI0 Clock Enable Bit" "0: USCI0 clock Disabled,1: USCI0 clock Enabled"
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bitfld.long 0xC 6. "SPI3CKEN,SPI3 Clock Enable Bit" "0: SPI3 clock Disabled,1: SPI3 clock Enabled"
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line.long 0x10 "CLK_CLKSEL0,Clock Source Select Control Register 0"
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bitfld.long 0x10 26.--27. "CANFD1SEL,CANFD1 Clock Source Selection (Write Protect)" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 48 MHz internal high speed RC..,?,?"
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bitfld.long 0x10 24.--25. "CANFD0SEL,CANFD0 Clock Source Selection (Write Protect)" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 48 MHz internal high speed RC..,?,?"
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bitfld.long 0x10 12.--14. "HCLK1SEL,HCLK1 Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\nNote: HIRC48M_divider2 is not work at NPD3/NPD4/NPD5/SPD0~2/DPD0~1 power down mode change to.." "0: Clock source from HIRC,1: Clock source from MIRC,?,?,?,?,?,?"
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bitfld.long 0x10 10.--11. "EADC0SEL,EADC0 Clock Source Selection (Write Protect)" "?,1: Clock source from PLL,?,?"
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bitfld.long 0x10 8. "USBSEL,USB Clock Source Selection (Write Protect)" "0: Clock source from HIRC48M,1: Clock source from PLL"
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bitfld.long 0x10 3.--5. "STCLKSEL,Cortex-M4 SysTick Clock Source Selection (Write Protect)" "0: Clock source from HXT,1: Clock source from LXT,?,?,?,?,?,?"
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bitfld.long 0x10 0.--2. "HCLK0SEL,HCLK0 Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from HXT,1: Clock source from LXT,?,?,?,?,?,?"
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line.long 0x14 "CLK_CLKSEL1,Clock Source Select Control Register 1"
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bitfld.long 0x14 30.--31. "WWDTSEL,Window Watchdog Timer Clock Source Selection" "0,1,2,3"
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bitfld.long 0x14 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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hexmask.long.byte 0x14 4.--7. 1. "CLKOSEL,Clock Divider Clock Source Selection"
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line.long 0x18 "CLK_CLKSEL2,Clock Source Select Control Register 2"
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bitfld.long 0x18 12.--14. "SPI1SEL,SPI1 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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bitfld.long 0x18 7. "TKSEL,TK Clock Source Selection\nNote: The TKSEL cannot be changed when TK is operating. Used should make TK disable before change TKSEL and reset TK after change TKSEL." "0: Clock source from 12 MHz internal high speed RC..,1: Clock source from 1/2/4/8 MHz internal middle.."
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bitfld.long 0x18 4.--6. "SPI0SEL,SPI0 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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bitfld.long 0x18 2.--3. "QSPI0SEL,QSPI0 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?"
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bitfld.long 0x18 1. "EPWM1SEL,EPWM1 Clock Source Selection\nThe peripheral clock source of EPWM1 is defined by EPWM1SEL." "0: Clock source from SRHCLK0,1: Clock source from PCLK1"
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bitfld.long 0x18 0. "EPWM0SEL,EPWM0 Clock Source Selection\nThe peripheral clock source of EPWM0 is defined by EPWM0SEL." "0: Clock source from SRHCLK0,1: Clock source from PCLK0"
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line.long 0x1C "CLK_CLKSEL3,Clock Source Select Control Register 3"
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bitfld.long 0x1C 12.--14. "SPI3SEL,SPI3 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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bitfld.long 0x1C 8.--10. "SPI2SEL,SPI2 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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bitfld.long 0x1C 7. "PWM1SEL,PWM1 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM1SEL." "0: Clock source from SRHCLK0,1: Clock source from PCLK1"
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bitfld.long 0x1C 6. "PWM0SEL,PWM0 Clock Source Selection\nThe peripheral clock source of PWM0 is defined by PWM0SEL." "0: Clock source from SRHCLK0,1: Clock source from PCLK0"
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line.long 0x20 "CLK_CLKDIV0,Clock Divider Number Register 0"
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hexmask.long.byte 0x20 16.--23. 1. "EADC0DIV,EADC0 Clock Divide Number from EADC0 Clock Source"
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hexmask.long.byte 0x20 12.--15. 1. "UART1DIV,UART1 Clock Divide Number from UART1 Clock Source"
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hexmask.long.byte 0x20 8.--11. 1. "UART0DIV,UART0 Clock Divide Number from UART0 Clock Source"
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hexmask.long.byte 0x20 4.--7. 1. "USBDIV,USB Clock Divide Number from USB Clock"
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hexmask.long.byte 0x20 0.--3. 1. "HCLK0DIV,HCLK0 Clock Divide Number from HCLK0 Clock Source\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
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group.long 0x30++0x1B
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line.long 0x0 "CLK_CLKDIV4,Clock Divider Number Register 4"
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hexmask.long.byte 0x0 20.--23. 1. "UART7DIV,UART7 Clock Divide Number from UART7 Clock Source"
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hexmask.long.byte 0x0 16.--19. 1. "UART6DIV,UART6 Clock Divide Number from UART6 Clock Source"
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hexmask.long.byte 0x0 12.--15. 1. "UART5DIV,UART5 Clock Divide Number from UART5 Clock Source"
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hexmask.long.byte 0x0 8.--11. 1. "UART4DIV,UART4 Clock Divide Number from UART4 Clock Source"
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hexmask.long.byte 0x0 4.--7. 1. "UART3DIV,UART3 Clock Divide Number from UART3 Clock Source"
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hexmask.long.byte 0x0 0.--3. 1. "UART2DIV,UART2 Clock Divide Number from UART2 Clock Source"
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line.long 0x4 "CLK_PCLKDIV,APB Clock Divider Register"
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bitfld.long 0x4 4.--6. "APB1DIV,APB1 Clock Divider\nAPB1 clock can be divided from HCLK0." "0: PCLK1 frequency is HCLK0,1: PCLK1 frequency is 1/2 HCLK0,?,?,?,?,?,?"
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bitfld.long 0x4 0.--2. "APB0DIV,APB0 Clock Divider\nAPB0 clock can be divided from HCLK0." "0: PCLK0 frequency is HCLK0,1: PCLK0 frequency is 1/2 HCLK0,?,?,?,?,?,?"
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line.long 0x8 "CLK_APBCLK2,APB Devices Clock Enable Control Register 2"
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bitfld.long 0x8 15. "UTCPD0CKEN,UTCPD0 Clock Enable Bit" "0: UTCPD0 clock Disabled,1: UTCPD0 clock Enabled"
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bitfld.long 0x8 9. "PWM1CKEN,PWM1 Clock Enable Bit" "0: PWM1 clock Disabled,1: PWM1 clock Enabled"
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bitfld.long 0x8 8. "PWM0CKEN,PWM0 Clock Enable Bit" "0: PWM0 clock Disabled,1: PWM0 clock Enabled"
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bitfld.long 0x8 7. "ACMP2CKEN,ACMP2 Clock Enable Bit" "0: ACMP2 clock Disabled,1: ACMP2 clock Enabled"
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line.long 0xC "CLK_CLKDIV5,Clock Divider Number Register 5"
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hexmask.long.byte 0xC 4.--7. 1. "CANFD1DIV,CANFD1 Clock Divide Number from CANFD1 Clock Source"
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hexmask.long.byte 0xC 0.--3. 1. "CANFD0DIV,CANFD0 Clock Divide Number from CANFD0 Clock Source"
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line.long 0x10 "CLK_PLLCTL,PLL Control Register"
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bitfld.long 0x10 23. "STBSEL,PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL stable time is 2500 PLL source clock..,1: PLL stable time is 7000 PLL source clock.."
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bitfld.long 0x10 19. "PLLSRC,PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL source clock from 4~32 MHz external..,1: PLL source clock from 12 MHz internal high-speed.."
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bitfld.long 0x10 18. "OE,PLL FOUT Enable Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
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bitfld.long 0x10 17. "BP,PLL Bypass Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN"
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bitfld.long 0x10 16. "PD,Power-down Mode (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL is in normal mode,1: PLL is in Power-down mode (default)"
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line.long 0x14 "CLK_PLLCTL2,PLL Control Register 2"
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hexmask.long.word 0x14 16.--27. 1. "FRDIV,PLL Fractional Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
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bitfld.long 0x14 14.--15. "OUTDIV,PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0,1,2,3"
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hexmask.long.byte 0x14 9.--13. 1. "INDIV,PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
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hexmask.long.word 0x14 0.--8. 1. "FBDIV,PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
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line.long 0x18 "CLK_CLKSEL4,Clock Source Select Control Register 4"
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bitfld.long 0x18 28.--30. "UART7SEL,UART7 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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bitfld.long 0x18 24.--26. "UART6SEL,UART6 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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bitfld.long 0x18 20.--22. "UART5SEL,UART5 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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bitfld.long 0x18 16.--18. "UART4SEL,UART4 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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bitfld.long 0x18 12.--14. "UART3SEL,UART3 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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bitfld.long 0x18 8.--10. "UART2SEL,UART2 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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bitfld.long 0x18 4.--6. "UART1SEL,UART1 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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bitfld.long 0x18 0.--2. "UART0SEL,UART0 Clock Source Selection" "0: Clock source from 4~32 MHz external high speed..,1: Clock source from PLL,?,?,?,?,?,?"
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rgroup.long 0x50++0x3
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line.long 0x0 "CLK_STATUS,Clock Status Monitor Register"
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bitfld.long 0x0 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1.\nNote: This bit.." "0: Clock switching success,1: Clock switching failure"
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bitfld.long 0x0 6. "HIRC48MSTB,HIRC48M Clock Source Stable Flag (Read Only)" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
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bitfld.long 0x0 5. "MIRCSTB,MIRC Clock Source Stable Flag (Read Only)" "0: 1/2/4/8 MHz internal high speed RC oscillator..,1: 1/2/4/8 MHz internal high speed RC oscillator.."
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bitfld.long 0x0 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: 12 MHz internal high speed RC oscillator (HIRC)..,1: 12 MHz internal high speed RC oscillator (HIRC).."
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bitfld.long 0x0 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: 32 kHz internal low speed RC oscillator (LIRC)..,1: 32 kHz internal low speed RC oscillator (LIRC).."
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bitfld.long 0x0 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled"
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bitfld.long 0x0 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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bitfld.long 0x0 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)" "0: 4~32 MHz external high speed crystal oscillator..,1: 4~32 MHz external high speed crystal oscillator.."
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group.long 0x58++0x3
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line.long 0x0 "CLK_AHBCLK1,AHB Devices Clock Enable Control Register 1"
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bitfld.long 0x0 28. "HCLK1EN,HCLK1 Clock Enable Bit" "0: HCLK1 clock Disabled,1: HCLK1 clock Enabled"
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bitfld.long 0x0 21. "CANFD1CKEN,CANFD1 Clock Enable Bit" "0: CANFD1 clock Disabled,1: CANFD1 clock Enabled"
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bitfld.long 0x0 20. "CANFD0CKEN,CANFD0 Clock Enable Bit" "0: CANFD0 clock Disabled,1: CANFD0 clock Enabled"
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bitfld.long 0x0 17. "CANRAM1EN,CANFD1 Message SRAM Clock Enable Bit" "0: CANFD1 Message SRAM clock Disabled,1: CANFD1 Message SRAM clock Enabled"
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bitfld.long 0x0 16. "CANRAM0EN,CANFD0 Message SRAM Clock Enable Bit" "0: CANFD0 Message SRAM clock Disabled,1: CANFD0 Message SRAM clock Enabled"
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group.long 0x60++0x3
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line.long 0x0 "CLK_CLKOCTL,Clock Output Control Register"
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bitfld.long 0x0 6. "CLK1HZEN,Clock Output 1Hz Enable Bit" "0: 1 Hz clock output for 32.768 kHz frequency..,1: 1 Hz clock output for 32.768 kHz frequency.."
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bitfld.long 0x0 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
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bitfld.long 0x0 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled"
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hexmask.long.byte 0x0 0.--3. 1. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]."
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group.long 0x70++0x13
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line.long 0x0 "CLK_CLKDCTL,Clock Fail Detector Control Register"
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bitfld.long 0x0 17. "HXTFQIEN,HXT Clock Frequency Range Detector Interrupt Enable Bit" "0: 4~32 MHz external high speed crystal oscillator..,1: 4~32 MHz external high speed crystal oscillator.."
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bitfld.long 0x0 16. "HXTFQDEN,HXT Clock Frequency Range Detector Enable Bit\nNote: HIRC must be enabled and stabled before enabling HXT clock frequency monitor." "0: 4~32 MHz external high speed crystal oscillator..,1: 4~32 MHz external high speed crystal oscillator.."
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bitfld.long 0x0 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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bitfld.long 0x0 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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bitfld.long 0x0 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: 4~32 MHz external high speed crystal oscillator..,1: 4~32 MHz external high speed crystal oscillator.."
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bitfld.long 0x0 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: 4~32 MHz external high speed crystal oscillator..,1: 4~32 MHz external high speed crystal oscillator.."
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line.long 0x4 "CLK_CLKDSTS,Clock Fail Detector Status Register"
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bitfld.long 0x4 8. "HXTFQIF,HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)\nNote 1: Write 1 to clear the bit to 0.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~32 MHz external high speed crystal oscillator..,1: Write 1 to clear the bit to 0"
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bitfld.long 0x4 1. "LXTFIF,LXT Clock Fail Interrupt Flag (Write Protect)\nNote 1: Write 1 to clear the bit to 0. \nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32.768 kHz external low speed crystal oscillator..,1: Write 1 to clear the bit to 0"
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bitfld.long 0x4 0. "HXTFIF,HXT Clock Fail Interrupt Flag (Write Protect)\nNote 1: Write 1 to clear the bit to 0.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~32 MHz external high speed crystal oscillator..,1: Write 1 to clear the bit to 0"
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line.long 0x8 "CLK_CDUPB,Clock Frequency Range Detector Upper Boundary Register"
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hexmask.long.word 0x8 0.--10. 1. "UPERBD,HXT Clock Frequency Range Detector Upper Boundary Value\nThe bits define the maximum value of frequency range detector window.\nWhen HXT frequency higher than this maximum frequency value the HXT Clock Frequency Range Detector Interrupt Flag.."
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line.long 0xC "CLK_CDLOWB,Clock Frequency Range Detector Lower Boundary Register"
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hexmask.long.word 0xC 0.--10. 1. "LOWERBD,HXT Clock Frequency Range Detector Lower Boundary Value\nThe bits define the minimum value of frequency range detector window.\nWhen HXT frequency lower than this minimum frequency value the HXT Clock Frequency Range Detector Interrupt Flag.."
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line.long 0x10 "CLK_STOPREQ,Clock Stop Request Register"
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bitfld.long 0x10 1. "CANFD1REQ,CANFD1 Clock Stop Request" "0,1"
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bitfld.long 0x10 0. "CANFD0REQ,CANFD0 Clock Stop Request" "0,1"
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rgroup.long 0x84++0x3
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line.long 0x0 "CLK_STOPACK,Clock Stop Acknowledge Register"
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bitfld.long 0x0 1. "CANFD1ACK,CANFD1 Clock Stop Acknowledge" "0,1"
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bitfld.long 0x0 0. "CANFD0ACK,CANFD0 Clock Stop Acknowledge" "0,1"
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group.long 0x90++0x23
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line.long 0x0 "CLK_PMUCTL,Power Manager Control Register"
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bitfld.long 0x0 20. "CARETDIS,Cache RAM Retention Disable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Cache RAM retention when chip enters..,1: Cache RAM shut down when chip enters.."
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bitfld.long 0x0 16. "LSRETSEL,LPSRAM Retention Range Select Bit (Write Protect)\nSelect LPSRAM retention range when chip enters NPD3/NPD4/NPD5/SPD0~2/DPD0~1 mode.\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: This bit should be set 1 if.." "0: LPSRAM shut down,1: This bit is write protected"
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bitfld.long 0x0 8.--10. "SRETSEL,SRAM Retention Range Select Bit (Write Protect)\nSelect SRAM retention range when chip enters NPD3/NPD4/NPD5/SPD0~2 mode.\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: Users should make sure program stack is.." "0: No SRAM retention,1: This bit is write protected,2: Users should make sure program stack is within..,?,?,?,?,?"
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hexmask.long.byte 0x0 0.--3. 1. "PDMSEL,Power-down Mode Selection (Write Protect)\nThese bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
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line.long 0x4 "CLK_PMUSTS,Power Manager Status Register"
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bitfld.long 0x4 31. "CLRWK,Clear Wake-up Flag" "0: Not cleared,1: Clear all wake-up flags"
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rbitfld.long 0x4 27. "GPDWK1,GPD Wake-up 1 Flag (Read Only)\nThis flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode was requested by a transition of selected one GPD group pins. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31].." "0,1"
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rbitfld.long 0x4 26. "GPCWK1,GPC Wake-up 1 Flag (Read Only)\nThis flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode was requested by a transition of selected one GPC group pins. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31].." "0,1"
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rbitfld.long 0x4 25. "GPBWK1,GPB Wake-up 1 Flag (Read Only)\nThis flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode was requested by a transition of selected one GPB group pins.\nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when.." "0,1"
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rbitfld.long 0x4 24. "GPAWK1,GPA Wake-up 1 Flag (Read Only)\nThis flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode was requested by a transition of selected one GPA group pins. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31].." "0,1"
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rbitfld.long 0x4 18. "ACMPWK2,ACMP2 Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD0~2) was requested with a ACMP2 transition. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD0~2 mode." "0,1"
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rbitfld.long 0x4 17. "ACMPWK1,ACMP1 Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD0~2) was requested with a ACMP1 transition. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD0~2 mode." "0,1"
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rbitfld.long 0x4 16. "ACMPWK0,ACMP0 Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD0~2) was requested with a ACMP0 transition. \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD0~2 mode." "0,1"
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rbitfld.long 0x4 15. "RSTWK,RST pin Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from NPD3/NPD4/NPD5 or Deep Power-down mode (DPD0~1) or Standby Power-down mode (SPD0~2) was requested with a RST pin trigger happened. \nNote: This flag needs to be.." "0,1"
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rbitfld.long 0x4 13. "BODWK,BOD Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from NPD3/NPD4/NPD5 or Standby Power-down mode (SPD0~2) was requested with a BOD happened.\nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering.." "0,1"
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rbitfld.long 0x4 12. "LVRWK,LVR Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from NPD3/NPD4/NPD5 or Standby Power-down mode (SPD0~2) was requested with a LVR happened.\nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering.." "0,1"
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rbitfld.long 0x4 11. "GPDWK0,GPD Wake-up 0 Flag (Read Only)\nThis flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode (SPD0~2) was requested by a transition of selected one GPD group pins. \nNote: This flag needs to be cleared by setting.." "0,1"
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rbitfld.long 0x4 10. "GPCWK0,GPC Wake-up 0 Flag (Read Only)\nThis flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode (SPD0~2) was requested by a transition of selected one GPC group pins. \nNote: This flag needs to be cleared by setting.." "0,1"
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rbitfld.long 0x4 9. "GPBWK0,GPB Wake-up 0 Flag (Read Only)\nThis flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode (SPD0~2) was requested by a transition of selected one GPB group pins.\nNote: This flag needs to be cleared by setting.." "0,1"
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rbitfld.long 0x4 8. "GPAWK0,GPA Wake-up 0 Flag (Read Only)\nThis flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode (SPD0~2) was requested by a transition of selected one GPA group pins. \nNote: This flag needs to be cleared by setting.." "0,1"
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rbitfld.long 0x4 7. "WKPIN5,Pin5 Wake-up Flag( Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PA.12). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering.." "0,1"
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rbitfld.long 0x4 6. "WKPIN4,Pin4 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PF.6). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD0/DPD1.." "0,1"
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rbitfld.long 0x4 5. "WKPIN3,Pin3 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.12). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering.." "0,1"
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rbitfld.long 0x4 4. "WKPIN2,Pin2 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.2). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD0/DPD1.." "0,1"
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rbitfld.long 0x4 3. "WKPIN1,Pin1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.0). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD0/DPD1.." "0,1"
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rbitfld.long 0x4 2. "RTCWK,RTC Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from NPD3/NPD4/NPD5 or Deep Power-down mode (DPD0~1) or Standby Power-down (SPD0~2) mode was requested with a RTC alarm tick time or tamper happened.\nNote: This flag needs to.." "0,1"
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rbitfld.long 0x4 1. "TMRWK,Timer Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from NPD0~5 or Deep Power-down mode (DPD0~1) or Standby Power-down (SPD0~2) mode was requested by wakeup timer time-out.\nNote: This flag needs to be cleared by setting.." "0,1"
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rbitfld.long 0x4 0. "WKPIN0,Pin0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0). \nNote: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD0~1.." "0,1"
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line.long 0x8 "CLK_PMUWKCTL,Power Manager Wake-up Control Register"
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bitfld.long 0x8 31. "DISAUTOC,Disable Auto Clear Wakeup flag (Write Protect)\nNote 1:This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2:Wakeup from NPD3/NPD4/NPD5 this bits keep original setting.\nNote 3:Wakeup from SPD0~2/DPD0~1 this bits.." "0: When CPU enter NPD3/NPD4/NPD5/SPD0~2/DPD0~1 all..,1: This bit is write protected"
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bitfld.long 0x8 26.--27. "WKPINEN5,Wake-up Pin5 Enable Bit (Write Protect)\nThis is control register for GPA.12 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Wake-up pin disable at Deep Power-down mode,1: Wake-up pin rising edge enabled at Deep..,?,?"
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bitfld.long 0x8 24.--25. "WKPINEN4,Wake-up Pin4 Enable Bit (Write Protect)\nThis is control register for GPF.6 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.\nNote: Setting IOCTLSEL(RTC_LXTCTL[8]) to avoid GPF6 unexpected falling edge." "0: Wake-up pin disable at Deep Power-down mode,1: Wake-up pin rising edge enabled at Deep..,?,?"
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bitfld.long 0x8 22.--23. "WKPINEN3,Wake-up Pin3 Enable Bit (Write Protect)\nThis is control register for GPB.12 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Wake-up pin disable at Deep Power-down mode,1: Wake-up pin rising edge enabled at Deep..,?,?"
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bitfld.long 0x8 20.--21. "WKPINEN2,Wake-up Pin2 Enable Bit (Write Protect)\nThis is control register for GPB.2 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Wake-up pin disable at Deep Power-down mode,1: Wake-up pin rising edge enabled at Deep..,?,?"
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bitfld.long 0x8 18.--19. "WKPINEN1,Wake-up Pin1 Enable Bit (Write Protect)\nThis is control register for GPB.0 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Wake-up pin disable at Deep Power-down mode,1: Wake-up pin rising edge enabled at Deep..,?,?"
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bitfld.long 0x8 16.--17. "WKPINEN0,Wake-up Pin0 Enable Bit (Write Protect)\nThis is control register for GPC.0 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Wake-up pin disable at Deep Power-down mode,1: Wake-up pin rising edge enabled at Deep..,?,?"
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hexmask.long.byte 0x8 8.--11. 1. "WKTMRIS,Wake-up Timer Time-out Interval Select (Write Protect)\nThese bits control wake-up timer time-out interval when chip at DPD/SPD mode.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
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bitfld.long 0x8 7. "RTCWKEN,RTC Wake-up Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: RTC wake-up disable at Deep Power-down mode or..,1: RTC wake-up enabled at Deep Power-down mode or.."
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bitfld.long 0x8 6. "ACMPWKEN,ACMP Standby Power-down Mode Wake-up Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: Set FILTSEL(ACMP_CTLx[15:13]) for comparator output filter count selection the filter clock is LIRC in.." "0: ACMP wake-up disable at Standby Power-down mode,1: ACMP wake-up enabled at Standby Power-down mode"
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bitfld.long 0x8 1. "WKTMRMOD,Wake-up Timer Mode (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Wake-up timer started when entering any of..,1: Wake-up timer started immedially when WKTMREN.."
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bitfld.long 0x8 0. "WKTMREN,Wake-up Timer Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Wake-up timer Disabled,1: Wake-up timer Enabled"
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line.long 0xC "CLK_PWDBCTL,GPIO Pin WKIO De-bounce Control Register"
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hexmask.long.byte 0xC 0.--3. 1. "SWKDBCLKSEL,WKIO De-bounce Sampling Cycle Selection\nNote: De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC)."
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line.long 0x10 "CLK_PAPWCTL,GPA Pin WKIO Control Register"
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bitfld.long 0x10 27. "NMR1,GPA Pin 1 Function Enable at Normal Run Mode Select\nNote: Enable this bit and the WKIO function is enabled immediately." "0: GPA group pin 1 wake-up function enable when..,1: GPA group pin 1 wake-up function enable when.."
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bitfld.long 0x10 26. "TRIGM1,GPA Pin 1 Wake-up Pin trigger Mode Select" "0: GPA group pin 1 wake-up chip Enabled trigger ip..,1: GPA group pin 1 wake-up chip Disabled trigger ip.."
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bitfld.long 0x10 24. "DBEN1,GPA Pin 1 Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: GPA group pin 1 Wakeup-I/O pin De-bounce..,1: GPA group pin 1 Wakeup-I/O pin De-bounce.."
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hexmask.long.byte 0x10 20.--23. 1. "WKPSEL1,GPA Pin 1 Wakeup-I/O Pin Select"
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bitfld.long 0x10 18. "PFWKEN1,GPA Pin 1 Falling Edge Detect Enable Bit" "0: GPA group pin 1 falling edge detect function..,1: GPA group pin 1 falling edge detect function.."
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bitfld.long 0x10 17. "PRWKEN1,GPA Pin 1 Rising Edge Detect Enable Bit" "0: GPA group pin 1 rising edge detect function..,1: GPA group pin 1 rising edge detect function.."
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bitfld.long 0x10 16. "WKEN1,GPA Pin 1 Wake-up Enable Bit" "0: GPA group pin 1 wake-up function Disabled,1: GPA group pin 1 wake-up function Enabled"
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bitfld.long 0x10 11. "NMR0,GPA Pin 0 Function Enable at Normal Run Mode Select\nNote: Enable this bit and the I/O wake-up function is enabled immediately." "0: GPA group pin 0 wake-up function enable when..,1: GPA group pin 0 wake-up function enable when.."
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bitfld.long 0x10 10. "TRIGM0,GPA Pin 0 Wake-up Pin Trigger Mode Select" "0: GPA group pin 0 wake-up chip Enabled trigger ip..,1: GPA group pin 0 wake-up chip Disabled trigger ip.."
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bitfld.long 0x10 8. "DBEN0,GPA Pin 0 Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: GPA group pin 0 Wake-up-I/O pin De-bounce..,1: GPA group pin 0 Wakeup-I/O pin De-bounce.."
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hexmask.long.byte 0x10 4.--7. 1. "WKPSEL0,GPA Pin 0 Wakeup-I/O Pin Select"
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bitfld.long 0x10 2. "PFWKEN0,GPA Pin 0 Falling Edge Detect Enable Bit" "0: GPA group pin 0 falling edge detect function..,1: GPA group pin 0 falling edge detect function.."
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bitfld.long 0x10 1. "PRWKEN0,GPA Pin 0 Rising Edge Detect Enable Bit" "0: GPA group pin 0 rising edge detect function..,1: GPA group pin 0 rising edge detect function.."
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bitfld.long 0x10 0. "WKEN0,GPA Pin 0 Wake-up-I/O Enable Bit" "0: GPA group pin 0 Wake-up-I/O function Disabled,1: GPA group pin 0 Wakeup-I/O function Enabled"
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line.long 0x14 "CLK_PBPWCTL,GPB Pin WKIO Control Register"
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bitfld.long 0x14 27. "NMR1,GPB Pin 1 Function Enable at Normal Run Mode Select\nNote: Enable this bit and the WKIO function is enabled immediately." "0: GPB group pin 1 wake-up function enable when..,1: GPB group pin 1 wake-up function enable when.."
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bitfld.long 0x14 26. "TRIGM1,GPB Pin 1 Wake-up Pin Trigger Mode Select" "0: GPB group pin 1 wake-up chip Enabled trigger ip..,1: GPB group pin 1 wake-up chip Disabled trigger ip.."
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bitfld.long 0x14 24. "DBEN1,GPB Pin 1 Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: GPB group pin 1 Wakeup-I/O pin De-bounce..,1: GPB group pin 1 Wakeup-I/O pin De-bounce.."
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hexmask.long.byte 0x14 20.--23. 1. "WKPSEL1,GPB Pin 1 Wakeup-I/O Pin Select"
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bitfld.long 0x14 18. "PFWKEN1,GPB Pin 1 Falling Edge Detect Enable Bit" "0: GPB group pin 1 falling edge detect function..,1: GPB group pin 1 falling edge detect function.."
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bitfld.long 0x14 17. "PRWKEN1,GPB Pin 1 Rising Edge Detect Enable Bit" "0: GPB group pin 1 rising edge detect function..,1: GPB group pin 1 rising edge detect function.."
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bitfld.long 0x14 16. "WKEN1,GPB Pin 1 Wake-up Enable Bit" "0: GPB group pin 1 wake-up function Disabled,1: GPB group pin 1 wake-up function Enabled"
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bitfld.long 0x14 11. "NMR0,GPB Pin 0 Function Enable at Normal Run Mode Select\nNote: Enable this bit and the I/O wake-up function is enabled immediately." "0: GPB group pin 0 wake-up function enable when..,1: GPB group pin 0 wake-up function enable when.."
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bitfld.long 0x14 10. "TRIGM0,GPB Pin 0 Wake-up Pin Trigger Mode Select" "0: GPB group pin 0 wake-up chip Enabled trigger ip..,1: GPB group pin 0 wake-up chip Disabled trigger ip.."
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bitfld.long 0x14 8. "DBEN0,GPB Pin 0 Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: GPB group pin 0 Wakeup-I/O pin De-bounce..,1: GPB group pin 0 Wakeup-I/O pin De-bounce.."
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hexmask.long.byte 0x14 4.--7. 1. "WKPSEL0,GPB Pin 0 Wakeup-I/O Pin Select"
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bitfld.long 0x14 2. "PFWKEN0,GPB Pin 0 Falling Edge Detect Enable Bit" "0: GPB group pin 0 falling edge detect function..,1: GPB group pin 0 falling edge detect function.."
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bitfld.long 0x14 1. "PRWKEN0,GPB Pin 0 Rising Edge Detect Enable Bit" "0: GPB group pin 0 rising edge detect function..,1: GPB group pin 0 rising edge detect function.."
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bitfld.long 0x14 0. "WKEN0,GPB Pin 0 Wakeup-I/O Enable Bit" "0: GPB group pin 0 Wakeup-I/O function Disabled,1: GPB group pin 0 Wakeup-I/O function Enabled"
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line.long 0x18 "CLK_PCPWCTL,GPC Pin WKIO Control Register"
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bitfld.long 0x18 27. "NMR1,GPC Pin 1 Function Enable at Normal Run Mode Select\nNote: Enable this bit and the WKIO function is enabled immediately." "0: GPC group pin 1 wake-up function enabled when..,1: GPC group pin 1 wake-up function enabled when.."
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bitfld.long 0x18 26. "TRIGM1,GPC Pin 1 Wake-up Pin Trigger Mode Select" "0: GPC group pin 1 wake-up chip Enabled trigger ip..,1: GPC group pin 1 wake-up chip Disabled trigger ip.."
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bitfld.long 0x18 24. "DBEN1,GPC Pin 1 Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: GPC group pin 1 Wakeup-I/O pin De-bounce..,1: GPC group pin 1 Wakeup-I/O pin De-bounce.."
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hexmask.long.byte 0x18 20.--23. 1. "WKPSEL1,GPC Pin 1 Wakeup-I/O Pin Select"
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bitfld.long 0x18 18. "PFWKEN1,GPC Pin 1 Falling Edge Detect Enable Bit" "0: GPC group pin 1 falling edge detect function..,1: GPC group pin 1 falling edge detect function.."
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bitfld.long 0x18 17. "PRWKEN1,GPC Pin 1 Rising Edge Detect Enable Bit" "0: GPC group pin 1 rising edge detect function..,1: GPC group pin 1 rising edge detect function.."
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bitfld.long 0x18 16. "WKEN1,GPC Pin 1 Wake-up Enable Bit" "0: GPC group pin 1 wake-up function Disabled,1: GPC group pin 1 wake-up function Enabled"
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bitfld.long 0x18 11. "NMR0,GPC Pin 0 Function Enable at Normal Run Mode Select\nNote: Enable this bit and the I/O wake-up function is enabled immediately." "0: GPC group pin 0 wake-up function enabled when..,1: GPC group pin 0 wake-up function enabled when.."
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bitfld.long 0x18 10. "TRIGM0,GPC Pin 0 Wake-up Pin trigger Mode Select" "0: GPC group pin 0 wake-up chip Enabled trigger ip..,1: GPC group pin 0 wake-up chip Disabled trigger ip.."
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bitfld.long 0x18 8. "DBEN0,GPC Pin 0 Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: GPC group pin 0 Wakeup-I/O pin De-bounce..,1: GPC group pin 0 Wakeup-I/O pin De-bounce.."
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hexmask.long.byte 0x18 4.--7. 1. "WKPSEL0,GPC Pin 0 Wakeup-I/O Pin Select"
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bitfld.long 0x18 2. "PFWKEN0,GPC Pin 0 Falling Edge Detect Enable Bit" "0: GPC group pin 0 falling edge detect function..,1: GPC group pin 0 falling edge detect function.."
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bitfld.long 0x18 1. "PRWKEN0,GPC Pin 0 Rising Edge Detect Enable Bit" "0: GPC group pin 0 rising edge detect function..,1: GPC group pin 0 rising edge detect function.."
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bitfld.long 0x18 0. "WKEN0,GPC Pin 0 Wakeup-I/O Enable Bit" "0: GPC group pin 0 Wakeup-I/O function Disabled,1: GPC group pin 0 Wakeup-I/O function Enabled"
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line.long 0x1C "CLK_PDPWCTL,GPD Pin WKIO Control Register"
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bitfld.long 0x1C 27. "NMR1,GPD Pin 1 Function Enable at Normal Run Mode Select\nNote: Enable this bit and the WKIO function is enabled immediately." "0: GPD group pin 1 wake-up function enable when..,1: GPD group pin 1 wake-up function enable when.."
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bitfld.long 0x1C 26. "TRIGM1,GPD Pin 1 Wake-up Pin Trigger Mode Select" "0: GPD group pin 1 wake-up chip Enabled trigger ip..,1: GPD group pin 1 wake-up chip Disabled trigger ip.."
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bitfld.long 0x1C 24. "DBEN1,GPD Pin 1 Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: GPD group pin 1 Wakeup-I/O pin De-bounce..,1: GPD group pin 1 Wakeup-I/O pin De-bounce.."
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hexmask.long.byte 0x1C 20.--23. 1. "WKPSEL1,GPD Pin 1 Wakeup-I/O Pin Select"
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bitfld.long 0x1C 18. "PFWKEN1,GPD Pin 1 Falling Edge Detect Enable Bit" "0: GPD group pin 1 falling edge detect function..,1: GPD group pin 1 falling edge detect function.."
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bitfld.long 0x1C 17. "PRWKEN1,GPD Pin 1 Rising Edge Detect Enable Bit" "0: GPD group pin 1 rising edge detect function..,1: GPD group pin 1 rising edge detect function.."
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newline
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bitfld.long 0x1C 16. "WKEN1,GPD Pin 1 Wake-up Enable Bit" "0: GPD group pin 1 wake-up function Disabled,1: GPD group pin 1 wake-up function Enabled"
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bitfld.long 0x1C 11. "NMR0,GPD Pin 0 Function Enable at Normal Run Mode Select\nNote: Enable this bit and the I/O wake-up function is enabled immediately." "0: GPD group pin 0 wake-up function enable when..,1: GPD group pin 0 wake-up function enable when.."
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bitfld.long 0x1C 10. "TRIGM0,GPD Pin 0 Wake-up Pin Trigger Mode Select" "0: GPD group pin 0 wake-up chip Enabled trigger ip..,1: GPD group pin 0 wake-up chip Disabled trigger ip.."
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bitfld.long 0x1C 8. "DBEN0,GPD Pin 0 Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: GPD group pin 0 Wakeup-I/O pin De-bounce..,1: GPD group pin 0 Wakeup-I/O pin De-bounce.."
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hexmask.long.byte 0x1C 4.--7. 1. "WKPSEL0,GPD Pin 0 Wakeup-I/O Pin Select"
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bitfld.long 0x1C 2. "PFWKEN0,GPD Pin 0 Falling Edge Detect Enable Bit" "0: GPD group pin 0 falling edge detect function..,1: GPD group pin 0 falling edge detect function.."
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newline
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bitfld.long 0x1C 1. "PRWKEN0,GPD Pin 0 Rising Edge Detect Enable Bit" "0: GPD group pin 0 rising edge detect function..,1: GPD group pin 0 rising edge detect function.."
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bitfld.long 0x1C 0. "WKEN0,GPD Pin 0 Wakeup-I/O Enable Bit" "0: GPD group pin 0 Wakeup-I/O function Disabled,1: GPD group pin 0 Wakeup-I/O function Enabled"
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line.long 0x20 "CLK_IOPDCTL,GPIO Power-down Control Register"
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bitfld.long 0x20 8. "DPDHOLDEN,Deep-Power-Down Mode GPIO Hold Enable Bit" "0: When GPIO enters deep power-down mode all I/O..,1: When GPIO enters deep power-down mode all I/O.."
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bitfld.long 0x20 0. "IOHR,GPIO Hold Release\nWhen GPIO enters deep power-down mode or standby power-down mode all I/O status are hold to keep normal operating status. After chip was waked up from deep power-down mode or standby power-down mode the I/O are still keep hold.." "0,1"
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group.long 0xC0++0x7
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line.long 0x0 "CLK_PMUINTC,Power Manager Interrupt Control Register"
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bitfld.long 0x0 15. "WKIOD1IE,Wakeup-I/O GPD group Pin 1 Interrupt Enable Bit" "0: Wakeup-I/O interrupt function Disabled,1: Wakeup-I/O interrupt function Enabled"
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bitfld.long 0x0 14. "WKIOC1IE,Wakeup-I/O GPC group Pin 1 Interrupt Enable Bit" "0: Wakeup-I/O interrupt function Disabled,1: Wakeup-I/O interrupt function Enabled"
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newline
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bitfld.long 0x0 13. "WKIOB1IE,Wakeup-I/O GPB group Pin 1 Interrupt Enable Bit" "0: Wakeup-I/O interrupt function Disabled,1: Wakeup-I/O interrupt function Enabled"
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bitfld.long 0x0 12. "WKIOA1IE,Wakeup-I/O GPA group Pin 1 Interrupt Enable Bit" "0: Wakeup-I/O interrupt function Disabled,1: Wakeup-I/O interrupt function Enabled"
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bitfld.long 0x0 11. "WKIOD0IE,Wakeup-I/O GPD group Pin 0 Interrupt Enable Bit" "0: Wakeup-I/O interrupt function Disabled,1: Wakeup-I/O interrupt function Enabled"
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bitfld.long 0x0 10. "WKIOC0IE,Wakeup-I/O GPC group Pin 0 Interrupt Enable Bit" "0: Wakeup-I/O interrupt function Disabled,1: Wakeup-I/O interrupt function Enabled"
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newline
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bitfld.long 0x0 9. "WKIOB0IE,Wakeup-I/O GPB group Pin 0 Interrupt Enable Bit" "0: Wakeup-I/O interrupt function Disabled,1: Wakeup-I/O interrupt function Enabled"
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bitfld.long 0x0 8. "WKIOA0IE,Wakeup-I/O GPA group Pin 0 Interrupt Enable Bit" "0: Wakeup-I/O interrupt function Disabled,1: Wakeup-I/O interrupt function Enabled"
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newline
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bitfld.long 0x0 0. "WKTMRIE,Wakeup-Timer Interrupt Enable Bit" "0: Wakeup-Timer interrupt function Disabled,1: Wakeup-Timer interrupt function Enabled"
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line.long 0x4 "CLK_PMUINTS,Power Manager Interrupt Status Register"
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bitfld.long 0x4 15. "WKIOD1IF,Wakeup-I/O GPD group Pin 1 Interrupt Flag\nThis flag indicates that Wakeup-I/O interrupt happened.\nNote: Software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x4 14. "WKIOC1IF,Wakeup-I/O GPC group Pin 1 Interrupt Flag\nThis flag indicates that Wakeup-I/O interrupt happened.\nNote: Software can clear this bit by writing 1 to it." "0,1"
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newline
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bitfld.long 0x4 13. "WKIOB1IF,Wakeup-I/O GPB group Pin 1 Interrupt Flag\nThis flag indicates that Wakeup-I/O interrupt happened.\nNote: Software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x4 12. "WKIOA1IF,Wakeup-I/O GPA group Pin 1 Interrupt Flag\nThis flag indicates that Wakeup-I/O interrupt happened.\nNote: Software can clear this bit by writing 1 to it." "0,1"
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newline
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bitfld.long 0x4 11. "WKIOD0IF,Wakeup-I/O GPD group Pin 0 Interrupt Flag\nThis flag indicates that Wakeup-I/O interrupt happened.\nNote: Software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x4 10. "WKIOC0IF,Wakeup-I/O GPC group Pin 0 Interrupt Flag\nThis flag indicates that Wakeup-I/O interrupt happened.\nNote: Software can clear this bit by writing 1 to it." "0,1"
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newline
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bitfld.long 0x4 9. "WKIOB0IF,Wakeup-I/O GPB group Pin 0 Interrupt Flag\nThis flag indicates that Wakeup-I/O interrupt happened.\nNote: Software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x4 8. "WKIOA0IF,Wakeup-I/O GPA group Pin 0 Interrupt Flag\nThis flag indicates that Wakeup-I/O interrupt happened.\nNote: Software can clear this bit by writing 1 to it." "0,1"
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newline
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bitfld.long 0x4 0. "WKTMRIF,Wakeup-Timer Interrupt Flag\nThis flag indicates that Wakeup-Timer interrupt happened.\nNote: Software can clear this bit by writing 1 to it." "0,1"
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tree.end
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tree "CRC (Cyclic Redundancy Check)"
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base ad:0x40031000
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group.long 0x0++0xB
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line.long 0x0 "CRC_CTL,CRC Control Register"
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bitfld.long 0x0 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode." "?,1: CRC-8 Polynomial mode,?,?"
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bitfld.long 0x0 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode the valid data in CRC_DAT.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode.\nData length is..,?,?"
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bitfld.long 0x0 27. "CHKSFMT,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register." "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled"
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bitfld.long 0x0 26. "DATFMT,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register." "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled"
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newline
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bitfld.long 0x0 25. "CHKSREV,Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB." "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled"
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bitfld.long 0x0 24. "DATREV,Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB." "0: Bit order reversed for CRC write data in Disabled,1: Bit order reversed for CRC write data in Enabled.."
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bitfld.long 0x0 1. "CHKSINIT,Checksum Initialization\nNote: This bit will be cleared automatically." "0: No effect,1: Initial checksum value by auto reload CRC_SEED.."
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bitfld.long 0x0 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled"
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line.long 0x4 "CRC_DAT,CRC Write Data Register"
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hexmask.long 0x4 0.--31. 1. "DATA,CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits; if.."
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line.long 0x8 "CRC_SEED,CRC Seed Register"
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hexmask.long 0x8 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1])."
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rgroup.long 0xC++0x3
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line.long 0x0 "CRC_CHECKSUM,CRC Checksum Register"
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hexmask.long 0x0 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result.\nNote: Data in CRC_CHECKSUM register has different length when user chooses different operation polynomial modes. \nFor example:\nIf final checksum result is 0x12 in CRC-8.."
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group.long 0x10++0x3
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line.long 0x0 "CRC_POLYNOMIAL,CRC Polynomial Register"
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hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC Polynomial Value Results\nThis field indicates the value of CRC polynomial."
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group.long 0x40++0xF
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line.long 0x0 "CRC_DMACTL,CRC DMA Mode Control Register"
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bitfld.long 0x0 8. "INTEN,CRC DMA Mode Interrupt Enable Bit\nEnable CRC DMA mode interrupt." "0,1"
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bitfld.long 0x0 4. "ABORT,CRC DMA Operation Abort Bit\nWrite 1 to abort the operation of CRC DMA." "0,1"
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newline
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bitfld.long 0x0 1. "PAUSE,CRC DMA Pause Bit\nBit to set CRC DMA to pause the operation. When write\nThis bit is read-as-1 when the CRC DMA is paused." "0: Continue the CRCDMA operation when CRCDMA is..,1: Pause the CRCDMA operation"
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bitfld.long 0x0 0. "START,CRC DMA Start Bit\nSet CRC DMA to start operation.\nThis bit is read-as-1 when the CRC DMA is operating.\nThis bit can be set to 1 when all DMASTS flags are cleared to zero." "0,1"
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line.long 0x4 "CRC_DMASTS,CRC DMA Mode Status Register"
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eventfld.long 0x4 3. "ACCERR,DMA Access Error Flag (Write 1 to Clear)\nIndicates the operation of DMA mode is aborted due to access error.\nNote: Write 1 to clear the interrupt flag." "0,1"
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eventfld.long 0x4 2. "CFGERR,Configuration Error Flag (Write 1 to Clear)\nIndicates the configuration to run DMA operation is invalid and the operation of DMA mode is canceled.\nNote: Write 1 to clear the interrupt flag." "0,1"
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eventfld.long 0x4 1. "ABORTED,DMA Operation Aborted Flag (Write 1 to Clear)\nIndicates the operation of DMA mode is aborted due to user setting CRC_DMACTL[4]. \nNote: Write 1 to clear the interrupt flag." "0,1"
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eventfld.long 0x4 0. "FINISH,DMA Operation Finish Flag (Write 1 to Clear)\nIndicates the operation of DMA mode is finished successfully.\nNote: Write 1 to clear the interrupt flag." "0,1"
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line.long 0x8 "CRC_SADDR,CRC DMA Source Address Register"
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hexmask.long 0x8 2.--31. 1. "SADDR,CRC DMA Source Address\nDMA source address\nThis value should be less than 0xE000_0000"
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line.long 0xC "CRC_DMACNT,CRC DMA Word Count Register"
|
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hexmask.long 0xC 2.--27. 1. "DMACNT,CRC DMA Operation Word Count\nIndicates words for DMA to read."
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tree.end
|
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tree "CRYPTO (Cryptographic Accelerator)"
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base ad:0x40032000
|
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group.long 0x0++0xB
|
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line.long 0x0 "CRYPTO_INTEN,Crypto Interrupt Enable Control Register"
|
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bitfld.long 0x0 17. "PRNGEIEN,PRNG Error Flag Enable Bit" "0: PRNG error interrupt flag Disabled,1: PRNG error interrupt flag Enabled"
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bitfld.long 0x0 16. "PRNGIEN,PRNG Interrupt Enable Bit" "0: PRNG interrupt Disabled,1: PRNG interrupt Enabled"
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newline
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bitfld.long 0x0 1. "AESEIEN,AES Error Flag Enable Bit" "0: AES error interrupt flag Disabled,1: AES error interrupt flag Enabled"
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bitfld.long 0x0 0. "AESIEN,AES Interrupt Enable Bit\nNote: In DMA mode an interrupt will be triggered when an amount of data set in AES_DMA_CNT is fed into the AES engine.\nIn Non-DMA mode an interrupt will be triggered when the AES engine finishes the operation." "0: AES interrupt Disabled,1: AES interrupt Enabled"
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line.long 0x4 "CRYPTO_INTSTS,Crypto Interrupt Flag"
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bitfld.long 0x4 17. "PRNGEIF,PRNG Error Flag\nThis register includes operating and setting error. The detail flag is shown in CRYPTO_PRNG_STS register.\nNote: This bit is cleared by writing 1 and it has no effect by writing 0." "0: No PRNG error,1: PRNG error interrupt"
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bitfld.long 0x4 16. "PRNGIF,PRNG Finish Interrupt Flag\nNote: This bit is cleared by writing 1 and it has no effect by writing 0." "0: No PRNG interrupt,1: PRNG done interrupt"
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bitfld.long 0x4 1. "AESEIF,AES Error Flag\nThis register includes operating and setting error. The detail flag is shown in CRYPTO_AES_STS register.\nNote: This bit is cleared by writing 1 and it has no effect by writing 0." "0: No AES error,1: AES error interrupt"
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bitfld.long 0x4 0. "AESIF,AES Finish Interrupt Flag\nNote: This bit is cleared by writing 1 and it has no effect by writing 0." "0: No AES interrupt,1: AES done interrupt"
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line.long 0x8 "CRYPTO_PRNG_CTL,PRNG Control Register"
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bitfld.long 0x8 16. "SEEDSRC,Seed Source\nNote: When SEEDRLD is set to 0 this bit (SEEDSRC) is meaningless." "0: Seed is from TRNG,1: Seed is from PRNG seed register"
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rbitfld.long 0x8 8. "BUSY,PRNG Busy (Read Only)\nNote: This bit is equal to the busy bit of CRYPTO_PRNG_STS[0]." "0: PRNG engine is idle,1: PRNG engine is generating CRYPTO_PRNG_KEYx"
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bitfld.long 0x8 2.--4. "KEYSZ,PRNG Generate Key Size" "0: 128 bits,1: 163 bits,?,?,?,?,?,?"
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bitfld.long 0x8 1. "SEEDRLD,Reload New Seed for PRNG Engine" "0: Generating key based on the current seed,1: Reload new seed"
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newline
|
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bitfld.long 0x8 0. "START,Start PRNG Engine" "0: Stop PRNG engine,1: Generate new key and store the new key to.."
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "CRYPTO_PRNG_SEED,Seed for PRNG"
|
|
hexmask.long 0x0 0.--31. 1. "SEED,Seed for PRNG (Write Only)\nThe bits store the seed for PRNG engine.\nNote: In TRNG+PRNG mode the seed is from TRNG engine and it will not be stored in this register."
|
|
rgroup.long 0x10++0x23
|
|
line.long 0x0 "CRYPTO_PRNG_KEY0,PRNG Generated Key0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
|
|
line.long 0x4 "CRYPTO_PRNG_KEY1,PRNG Generated Key1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
|
|
line.long 0x8 "CRYPTO_PRNG_KEY2,PRNG Generated Key2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
|
|
line.long 0xC "CRYPTO_PRNG_KEY3,PRNG Generated Key3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
|
|
line.long 0x10 "CRYPTO_PRNG_KEY4,PRNG Generated Key4"
|
|
hexmask.long 0x10 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
|
|
line.long 0x14 "CRYPTO_PRNG_KEY5,PRNG Generated Key5"
|
|
hexmask.long 0x14 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
|
|
line.long 0x18 "CRYPTO_PRNG_KEY6,PRNG Generated Key6"
|
|
hexmask.long 0x18 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
|
|
line.long 0x1C "CRYPTO_PRNG_KEY7,PRNG Generated Key7"
|
|
hexmask.long 0x1C 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG."
|
|
line.long 0x20 "CRYPTO_PRNG_STS,PRNG Status Register"
|
|
bitfld.long 0x20 18. "TRNGERR,True Random Number Generator Error Flag" "0: No error,1: Getting random number or seed failed"
|
|
bitfld.long 0x20 0. "BUSY,PRNG Busy Flag \nNote: This bit is equal to the busy bit of CRYPTO_PRNG_CTL[8]." "0: PRNG engine is idle,1: PRNG engine is generating CRYPTO_PRNG_KEYx"
|
|
rgroup.long 0x50++0xF
|
|
line.long 0x0 "CRYPTO_AES_FDBCK0,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x0 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
line.long 0x4 "CRYPTO_AES_FDBCK1,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x4 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
line.long 0x8 "CRYPTO_AES_FDBCK2,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x8 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
line.long 0xC "CRYPTO_AES_FDBCK3,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0xC 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CRYPTO_AES_CTL,AES Control Register"
|
|
bitfld.long 0x0 31. "KEYPRT,Protect Key\nRead as a flag to reflect KEYPRT." "0: No effect,1: Protect the content of the AES key from reading."
|
|
hexmask.long.byte 0x0 26.--30. 1. "KEYUNPRT,Unprotect Key\nWriting 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is to unprotect the AES key.\nThe KEYUNPRT can be read and written. When it is written as the AES engine is operating BUSY flag is 1 there would be no effect.."
|
|
newline
|
|
bitfld.long 0x0 25. "KINSWAP,AES Engine Input Key and Initial Vector Swap" "0: Keep the original order,1: The order that CPU feeds key and initial vector.."
|
|
bitfld.long 0x0 24. "KOUTSWAP,AES Engine Output Key Initial Vector and Feedback Swap" "0: Keep the original order,1: The order that CPU reads key initial vector and.."
|
|
newline
|
|
bitfld.long 0x0 23. "INSWAP,AES Engine Input Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the accelerator.."
|
|
bitfld.long 0x0 22. "OUTSWAP,AES Engine Output Data Swap" "0: Keep the original order,1: The order that CPU reads data from the.."
|
|
newline
|
|
bitfld.long 0x0 16. "ENCRYPTO,AES Encryption/Decryption" "0: AES engine executes decryption operation,1: AES engine executes encryption operation"
|
|
hexmask.long.byte 0x0 8.--15. 1. "OPMODE,AES Engine Operation Modes"
|
|
newline
|
|
bitfld.long 0x0 7. "DMAEN,AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode and data movement from/to the engine is done by DMA logic." "0: AES DMA engine Disabled,1: AES_DMA engine Enabled"
|
|
bitfld.long 0x0 6. "DMACSCAD,AES Engine DMA with Cascade Mode\nNote: The last two blocks of AES-CBC-CS1/2/3 must be in the last cascade operation." "0: DMA cascade function Disabled,1: In DMA cascade mode software can update DMA.."
|
|
newline
|
|
bitfld.long 0x0 5. "DMALAST,AES Last Block\nIn DMA mode this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode this bit must be set when feeding in the last block of data in ECB CBC CTR OFB and CFB mode and feeding in the (last-1) block of.." "0,1"
|
|
bitfld.long 0x0 2.--3. "KEYSZ,AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1 updating this register has no effect." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,AES Engine Stop\nNote: This bit is always 0 when it is read back." "0: No effect,1: Stop AES engine"
|
|
bitfld.long 0x0 0. "START,AES Engine Start\nNote: This bit is always 0 when it is read back." "0: No effect,1: Start AES engine. BUSY flag will be set"
|
|
rgroup.long 0x104++0x3
|
|
line.long 0x0 "CRYPTO_AES_STS,AES Engine Flag"
|
|
bitfld.long 0x0 20. "BUSERR,AES DMA Access Bus Error Flag" "0: No error,1: Bus error will stop DMA operation and AES engine"
|
|
bitfld.long 0x0 18. "OUTBUFERR,AES Out Buffer Error Flag" "0: No error,1: Error happened during getting the result from.."
|
|
newline
|
|
bitfld.long 0x0 17. "OUTBUFFULL,AES Out Buffer Full Flag" "0: AES output buffer is not full,1: AES output buffer is full and software needs to.."
|
|
bitfld.long 0x0 16. "OUTBUFEMPTY,AES Out Buffer Empty" "0: AES output buffer is not empty. There are some..,1: AES output buffer is empty. Software cannot get.."
|
|
newline
|
|
bitfld.long 0x0 12. "CNTERR,CRYPTO_AES_CNT Setting Error" "0: No error in CRYPTO_AES_CNT setting,1: CRYPTO_AES_CNT is 0 if DMAEN (CRYPTO_AES_CTL[7]).."
|
|
bitfld.long 0x0 10. "INBUFERR,AES Input Buffer Error Flag" "0: No error,1: Error happened during feeding data to the AES.."
|
|
newline
|
|
bitfld.long 0x0 9. "INBUFFULL,AES Input Buffer Full Flag" "0: AES input buffer is not full. Software can feed..,1: AES input buffer is full. Software cannot feed.."
|
|
bitfld.long 0x0 8. "INBUFEMPTY,AES Input Buffer Empty" "0: There are some data in input buffer waiting for..,1: AES input buffer is empty. Software needs to.."
|
|
newline
|
|
bitfld.long 0x0 0. "BUSY,AES Engine Busy" "0: The AES engine is idle or finished,1: The AES engine is under processing"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "CRYPTO_AES_DATIN,AES Engine Data Input Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATIN,AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRYPTO_AES_STS. Feed data as INBUFFULL is 0."
|
|
rgroup.long 0x10C++0x3
|
|
line.long 0x0 "CRYPTO_AES_DATOUT,AES Engine Data Output Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATOUT,AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRYPTO_AES_STS. Get data as OUTBUFEMPTY is 0."
|
|
group.long 0x110++0x3B
|
|
line.long 0x0 "CRYPTO_AES_KEY0,AES Key Word 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3 CRYPTO_AES_KEY2 .."
|
|
line.long 0x4 "CRYPTO_AES_KEY1,AES Key Word 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3 CRYPTO_AES_KEY2 .."
|
|
line.long 0x8 "CRYPTO_AES_KEY2,AES Key Word 2 Register"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3 CRYPTO_AES_KEY2 .."
|
|
line.long 0xC "CRYPTO_AES_KEY3,AES Key Word 3 Register"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3 CRYPTO_AES_KEY2 .."
|
|
line.long 0x10 "CRYPTO_AES_KEY4,AES Key Word 4 Register"
|
|
hexmask.long 0x10 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3 CRYPTO_AES_KEY2 .."
|
|
line.long 0x14 "CRYPTO_AES_KEY5,AES Key Word 5 Register"
|
|
hexmask.long 0x14 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3 CRYPTO_AES_KEY2 .."
|
|
line.long 0x18 "CRYPTO_AES_KEY6,AES Key Word 6 Register"
|
|
hexmask.long 0x18 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3 CRYPTO_AES_KEY2 .."
|
|
line.long 0x1C "CRYPTO_AES_KEY7,AES Key Word 7 Register"
|
|
hexmask.long 0x1C 0.--31. 1. "KEY,CRYPTO_AES_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key. \n{CRYPTO_AES_KEY3 CRYPTO_AES_KEY2 .."
|
|
line.long 0x20 "CRYPTO_AES_IV0,AES Initial Vector Word 0 Register"
|
|
hexmask.long 0x20 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AES_IV0 CRYPTO_AES_IV1 CRYPTO_AES_IV2 and CRYPTO_AES_IV3) are for AES operating in CBC CFB and OFB mode. Four registers (CRYPTO_AES_IV0 CRYPTO_AES_IV1 CRYPTO_AES_IV2 and CRYPTO_AES_IV3) act as.."
|
|
line.long 0x24 "CRYPTO_AES_IV1,AES Initial Vector Word 1 Register"
|
|
hexmask.long 0x24 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AES_IV0 CRYPTO_AES_IV1 CRYPTO_AES_IV2 and CRYPTO_AES_IV3) are for AES operating in CBC CFB and OFB mode. Four registers (CRYPTO_AES_IV0 CRYPTO_AES_IV1 CRYPTO_AES_IV2 and CRYPTO_AES_IV3) act as.."
|
|
line.long 0x28 "CRYPTO_AES_IV2,AES Initial Vector Word 2 Register"
|
|
hexmask.long 0x28 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AES_IV0 CRYPTO_AES_IV1 CRYPTO_AES_IV2 and CRYPTO_AES_IV3) are for AES operating in CBC CFB and OFB mode. Four registers (CRYPTO_AES_IV0 CRYPTO_AES_IV1 CRYPTO_AES_IV2 and CRYPTO_AES_IV3) act as.."
|
|
line.long 0x2C "CRYPTO_AES_IV3,AES Initial Vector Word 3 Register"
|
|
hexmask.long 0x2C 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AES_IV0 CRYPTO_AES_IV1 CRYPTO_AES_IV2 and CRYPTO_AES_IV3) are for AES operating in CBC CFB and OFB mode. Four registers (CRYPTO_AES_IV0 CRYPTO_AES_IV1 CRYPTO_AES_IV2 and CRYPTO_AES_IV3) act as.."
|
|
line.long 0x30 "CRYPTO_AES_SADDR,AES DMA Source Address Register"
|
|
hexmask.long 0x30 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source.."
|
|
line.long 0x34 "CRYPTO_AES_DADDR,AES DMA Destination Address Register"
|
|
hexmask.long 0x34 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be.."
|
|
line.long 0x38 "CRYPTO_AES_CNT,AES Byte Count Register"
|
|
hexmask.long 0x38 0.--31. 1. "CNT,AES Byte Count\nThe CRYPTO_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRYPTO_AES_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_AES_CNT can be read and written. Writing to.."
|
|
tree.end
|
|
tree "DAC (Digital to Analog Controller)"
|
|
base ad:0x40047000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DAC0_CTL,DAC0 Control Register"
|
|
bitfld.long 0x0 18. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled"
|
|
bitfld.long 0x0 17. "GPIOEN,GPIO Mode Enable Bit" "0: GPIO pin can output DAC0_OUT voltage,1: GPIO pin can be used as other MFP"
|
|
newline
|
|
bitfld.long 0x0 16. "GRPEN,DAC Group Mode Enable Bit" "0: DAC0 and DAC1 are not grouped,1: DAC0 and DAC1 are grouped"
|
|
bitfld.long 0x0 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: data is 12 bits,1: data is 8 bits,?,?"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,?,?"
|
|
bitfld.long 0x0 10. "LALIGN,DAC Data Left-aligned Enabled Bit" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
hexmask.long.byte 0x0 5.--8. 1. "TRGSEL,Trigger Source Selection"
|
|
bitfld.long 0x0 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled"
|
|
bitfld.long 0x0 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled"
|
|
bitfld.long 0x0 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled"
|
|
line.long 0x4 "DAC0_SWTRG,DAC0 Software Trigger Control Register"
|
|
bitfld.long 0x4 0. "SWTRG,Software Trigger\nNote: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; reading this bit will always get 0." "0: Software trigger Disabled,1: Software trigger Enabled"
|
|
line.long 0x8 "DAC0_DAT,DAC0 Data Holding Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "DACDAT,DAC0 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller.."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DAC0_DATOUT,DAC0 Data Output Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly."
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "DAC0_STATUS,DAC0 Status Register"
|
|
rbitfld.long 0x0 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for next conversion,1: DAC is busy in conversion"
|
|
bitfld.long 0x0 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit." "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit is set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0." "0: DAC is in conversion state,1: DAC conversion finish"
|
|
line.long 0x4 "DAC0_TCTL,DAC0 Timing Control Register"
|
|
hexmask.long.word 0x4 0.--9. 1. "SETTLET,DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 72 MHz and DAC conversion settling time is 1.."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "DAC_GRPDAT,DAC Group Mode Data Holding Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DAC1DAT,DAC1 12-bit Holding Data\nIn group mode user can write these bits for DAC1 12-bit conversion data. The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.\n12.."
|
|
hexmask.long.word 0x0 0.--15. 1. "DAC0DAT,DAC0 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC.."
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "DAC1_CTL,DAC1 Control Register"
|
|
bitfld.long 0x0 18. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled"
|
|
bitfld.long 0x0 17. "GPIOEN,GPIO Mode Enable Bit" "0: GPIO pin can output DAC0_OUT voltage,1: GPIO pin can be used as other MFP"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: Data is 12 bits,1: Data is 8 bits,?,?"
|
|
bitfld.long 0x0 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,?,?"
|
|
newline
|
|
bitfld.long 0x0 10. "LALIGN,DAC Data Left-aligned Enable Control" "0: Right alignment,1: Left alignment"
|
|
hexmask.long.byte 0x0 5.--8. 1. "TRGSEL,Trigger Source Selection"
|
|
newline
|
|
bitfld.long 0x0 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled"
|
|
bitfld.long 0x0 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled"
|
|
bitfld.long 0x0 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled"
|
|
line.long 0x4 "DAC1_SWTRG,DAC1 Software Trigger Control Register"
|
|
bitfld.long 0x4 0. "SWTRG,Software Trigger\nNote: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0." "0: Software trigger Disabled,1: Software trigger Enabled"
|
|
line.long 0x8 "DAC1_DAT,DAC1 Data Holding Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "DACDAT,DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller.."
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "DAC1_DATOUT,DAC1 Data Output Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly."
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "DAC1_STATUS,DAC1 Status Register"
|
|
rbitfld.long 0x0 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for next conversion,1: DAC is busy in conversion"
|
|
bitfld.long 0x0 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit." "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0." "0: DAC is in conversion state,1: DAC conversion finished"
|
|
line.long 0x4 "DAC1_TCTL,DAC1 Timing Control Register"
|
|
hexmask.long.word 0x4 0.--9. 1. "SETTLET,DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 72 MHz and DAC conversion settling time is 1.."
|
|
tree.end
|
|
tree "EADC (Enhanced 12-bit Analog to Digital Converter)"
|
|
base ad:0x40043000
|
|
rgroup.long 0x0++0x4F
|
|
line.long 0x0 "EADC_DAT0,EADC Data Register 0 for Sample Module 0"
|
|
bitfld.long 0x0 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x0 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x0 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x4 "EADC_DAT1,EADC Data Register 1 for Sample Module 1"
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bitfld.long 0x4 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x4 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x4 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x8 "EADC_DAT2,EADC Data Register 2 for Sample Module 2"
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bitfld.long 0x8 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x8 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x8 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0xC "EADC_DAT3,EADC Data Register 3 for Sample Module 3"
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bitfld.long 0xC 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0xC 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0xC 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x10 "EADC_DAT4,EADC Data Register 4 for Sample Module 4"
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bitfld.long 0x10 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x10 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x10 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x14 "EADC_DAT5,EADC Data Register 5 for Sample Module 5"
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bitfld.long 0x14 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x14 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x14 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x18 "EADC_DAT6,EADC Data Register 6 for Sample Module 6"
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bitfld.long 0x18 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x18 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x18 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x1C "EADC_DAT7,EADC Data Register 7 for Sample Module 7"
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bitfld.long 0x1C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x1C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x1C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x20 "EADC_DAT8,EADC Data Register 8 for Sample Module 8"
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bitfld.long 0x20 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x20 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x20 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x24 "EADC_DAT9,EADC Data Register 9 for Sample Module 9"
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bitfld.long 0x24 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x24 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x24 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x28 "EADC_DAT10,EADC Data Register 10 for Sample Module 10"
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bitfld.long 0x28 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x28 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x28 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x2C "EADC_DAT11,EADC Data Register 11 for Sample Module 11"
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bitfld.long 0x2C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x2C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x2C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x30 "EADC_DAT12,EADC Data Register 12 for Sample Module 12"
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bitfld.long 0x30 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x30 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x30 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x34 "EADC_DAT13,EADC Data Register 13 for Sample Module 13"
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bitfld.long 0x34 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x34 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x34 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x38 "EADC_DAT14,EADC Data Register 14 for Sample Module 14"
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bitfld.long 0x38 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x38 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x38 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x3C "EADC_DAT15,EADC Data Register 15 for Sample Module 15"
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bitfld.long 0x3C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x3C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x3C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x40 "EADC_DAT16,EADC Data Register 16 for Sample Module 16"
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bitfld.long 0x40 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x40 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x40 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x44 "EADC_DAT17,EADC Data Register 17 for Sample Module 17"
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bitfld.long 0x44 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x44 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x44 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x48 "EADC_DAT18,EADC Data Register 18 for Sample Module 18"
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bitfld.long 0x48 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x48 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x48 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x4C "EADC_CURDAT,EADC PDMA Current Transfer Data Register"
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hexmask.long 0x4C 0.--30. 1. "CURDAT,EADC PDMA Current Transfer Data (Read Only)"
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group.long 0x50++0x3
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line.long 0x0 "EADC_CTL,EADC Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "INTDELAY3,ADC Start Of Conversion ADINT3 Delay Cycle Selection\nStart of conversion interrupt ADINT3 will delay INTDELAY3 PCLK cycles to generate interrupt. The function support delay 1 PCLK to 15 PCLK cycles user can select one of the options according.."
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hexmask.long.byte 0x0 24.--27. 1. "INTDELAY2,ADC Start Of Conversion ADINT2 Delay Cycle Selection\nStart of conversion interrupt ADINT2 will delay INTDELAY2 PCLK cycles to generate interrupt. The function support delay 1 PCLK to 15 PCLK cycles user can select one of the options according.."
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hexmask.long.byte 0x0 20.--23. 1. "INTDELAY1,ADC Start Of Conversion ADINT1 Delay Cycle Selection\nStart of conversion interrupt ADINT1 will delay INTDELAY1 PCLK cycles to generate interrupt. The function support delay 1 PCLK to 15 PCLK cycles user can select one of the options according.."
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hexmask.long.byte 0x0 16.--19. 1. "INTDELAY0,ADC Start Of Conversion ADINT0 Delay Cycle Selection\nStart of conversion interrupt ADINT0 will delay INTDELAY0 PCLK cycles to generate interrupt. The function support delay 1 PCLK to 15 PCLK cycles user can select one of the options according.."
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bitfld.long 0x0 9. "DMOF,ADC Differential Input Mode Output Format" "0: ADC conversion result will be filled in RESULT..,1: ADC conversion result will be filled in RESULT.."
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bitfld.long 0x0 8. "DIFFEN,Differential Analog Input Mode Enable Bit" "0: Single-end analog input mode,1: Differential analog input mode"
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bitfld.long 0x0 5. "ADCIEN3,Specific Sample Module EADC ADINT3 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module EADC conversion. If EADCIEN3 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT3 interrupt..,1: Specific sample module EADC ADINT3 interrupt.."
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bitfld.long 0x0 4. "ADCIEN2,Specific Sample Module EADC ADINT2 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module EADC conversion. If EADCIEN2 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT2 interrupt..,1: Specific sample module EADC ADINT2 interrupt.."
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bitfld.long 0x0 3. "ADCIEN1,Specific Sample Module EADC ADINT1 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module EADC conversion. If EADCIEN1 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT1 interrupt..,1: Specific sample module EADC ADINT1 interrupt.."
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bitfld.long 0x0 2. "ADCIEN0,Specific Sample Module EADC ADINT0 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module EADC conversion. If ADCIEN0 bit is set then conversion end interrupt request.." "0: Specific sample module EADC ADINT0 interrupt..,1: Specific sample module EADC ADINT0 interrupt.."
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bitfld.long 0x0 1. "ADCRST,EADC Converter Control Circuits Reset\nNote: EADCRST bit remains 1 during EADC reset when EADC reset end the EADCRST bit is automatically cleared to 0." "0: No effect,1: Cause EADC control circuits reset to initial.."
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bitfld.long 0x0 0. "ADCEN,EADC Converter Enable Bit\nNote: Before starting EADC conversion function this bit should be set to 1. Clear it to 0 to disable EADC converter analog circuit power consumption." "0: EADC Disabled,1: EADC Enabled"
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wgroup.long 0x54++0x3
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line.long 0x0 "EADC_SWTRG,EADC Sample Module Software Start Register"
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hexmask.long 0x0 0.--30. 1. "SWTRG,EADC Sample Module 0~30 Software Force to Start EADC Conversion\nNote: After writing this register to start EADC conversion the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the.."
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group.long 0x58++0xB
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line.long 0x0 "EADC_PENDSTS,EADC Start of Conversion Pending Flag Register"
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hexmask.long 0x0 0.--30. 1. "STPF,EADC Sample Module 0~30 Start of Conversion Pending Flag\nRead Operation:"
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line.long 0x4 "EADC_OVSTS,EADC Sample Module Start of Conversion Overrun Flag Register"
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hexmask.long 0x4 0.--30. 1. "SPOVF,EADC SAMPLE0~30 Overrun Flag\nNote: This bit is cleared by writing 1 to it."
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line.long 0x8 "EADC_CTL1,EADC Control1 Register"
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bitfld.long 0x8 23. "CMP3TRG,ADC Comparator 3 Trigger EPWM Brake Enable Bit" "0: Comparator 3 trigger EPWM brake is disabled,1: Comparator 3 trigger EPWM brake is enabled"
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bitfld.long 0x8 22. "CMP2TRG,ADC Comparator 2 Trigger EPWM Brake Enable Bit" "0: Comparator 2 trigger EPWM brake is disabled,1: Comparator 2 trigger EPWM brake is enabled"
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bitfld.long 0x8 21. "CMP1TRG,ADC Comparator 1 Trigger EPWM Brake Enable Bit" "0: Comparator 1 trigger EPWM brake is disabled,1: Comparator 1 trigger EPWM brake is enabled"
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bitfld.long 0x8 20. "CMP0TRG,ADC Comparator 0 Trigger EPWM Brake Enable Bit" "0: Comparator 0 trigger EPWM brake is disabled,1: Comparator 0 trigger EPWM brake is enabled"
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bitfld.long 0x8 8. "FDETCHEN,Floating Detect Channel Enable Bit" "0: Floating Detect Channel Disabled,1: Floating Detect Channel Enabled"
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bitfld.long 0x8 4.--5. "RESSEL,Resolution Select Bits" "0: ADC resolution 12 bits,1: ADC resolution 10 bits,?,?"
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bitfld.long 0x8 1. "DISCHEN,Discharge Enable\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable." "0: Channel discharge Disabled,1: Channel discharge Enabled"
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bitfld.long 0x8 0. "PRECHEN,Precharge Enable\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable." "0: Channel precharge Disabled,1: Channel precharge Enabled"
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group.long 0x80++0x4B
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line.long 0x0 "EADC_SCTL0,EADC Sample Module 0 Control Register"
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hexmask.long.byte 0x0 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x0 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x0 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x0 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x0 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x0 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x0 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x0 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x4 "EADC_SCTL1,EADC Sample Module 1 Control Register"
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hexmask.long.byte 0x4 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x4 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x4 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x4 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x4 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x4 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x4 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x4 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x8 "EADC_SCTL2,EADC Sample Module 2 Control Register"
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hexmask.long.byte 0x8 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x8 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x8 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x8 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x8 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x8 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x8 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x8 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0xC "EADC_SCTL3,EADC Sample Module 3 Control Register"
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hexmask.long.byte 0xC 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0xC 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0xC 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0xC 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0xC 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0xC 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0xC 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0xC 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x10 "EADC_SCTL4,EADC Sample Module 4 Control Register"
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hexmask.long.byte 0x10 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x10 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x10 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x10 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x10 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x10 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x10 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x10 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x14 "EADC_SCTL5,EADC Sample Module 5 Control Register"
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hexmask.long.byte 0x14 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x14 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x14 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x14 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x14 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x14 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x14 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x14 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x18 "EADC_SCTL6,EADC Sample Module 6 Control Register"
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hexmask.long.byte 0x18 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x18 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x18 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x18 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x18 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x18 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x18 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x18 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x1C "EADC_SCTL7,EADC Sample Module 7 Control Register"
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hexmask.long.byte 0x1C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x1C 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x1C 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x1C 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x1C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x1C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x1C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x1C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x20 "EADC_SCTL8,EADC Sample Module 8 Control Register"
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hexmask.long.byte 0x20 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x20 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x20 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x20 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x20 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x20 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x20 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x20 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x24 "EADC_SCTL9,EADC Sample Module 9 Control Register"
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hexmask.long.byte 0x24 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x24 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x24 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x24 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x24 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x24 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x24 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x24 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x28 "EADC_SCTL10,EADC Sample Module 10 Control Register"
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hexmask.long.byte 0x28 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x28 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x28 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x28 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x28 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x28 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x28 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x28 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x2C "EADC_SCTL11,EADC Sample Module 11 Control Register"
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hexmask.long.byte 0x2C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x2C 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x2C 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x2C 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x2C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x2C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x2C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x2C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x30 "EADC_SCTL12,EADC Sample Module 12 Control Register"
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hexmask.long.byte 0x30 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x30 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x30 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x30 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x30 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x30 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x30 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x30 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x34 "EADC_SCTL13,EADC Sample Module 13 Control Register"
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hexmask.long.byte 0x34 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x34 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x34 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x34 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x34 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x34 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x34 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x34 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x38 "EADC_SCTL14,EADC Sample Module 14 Control Register"
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hexmask.long.byte 0x38 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x38 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x38 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x38 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x38 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x38 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x38 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x38 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x3C "EADC_SCTL15,EADC Sample Module 15 Control Register"
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hexmask.long.byte 0x3C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x3C 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x3C 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x3C 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x3C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x3C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x3C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x3C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x40 "EADC_SCTL16,EADC Sample Module 16 Control Register"
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hexmask.long.byte 0x40 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x40 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x40 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x40 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x40 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x40 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x40 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x40 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x44 "EADC_SCTL17,EADC Sample Module 17 Control Register"
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hexmask.long.byte 0x44 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x44 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x44 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x44 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x44 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x44 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x44 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x44 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x48 "EADC_SCTL18,EADC Sample Module 18 Control Register"
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hexmask.long.byte 0x48 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x48 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x48 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x48 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x48 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x48 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x48 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x48 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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group.long 0xD0++0x1F
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line.long 0x0 "EADC_INTSRC0,EADC Interrupt 0 Source Enable Control Register."
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bitfld.long 0x0 30. "SPLIE30,Sample Module 30 Interrupt Enable Bit" "0: Sample Module 30 interrupt Disabled,1: Sample Module 30 interrupt Enabled"
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bitfld.long 0x0 29. "SPLIE29,Sample Module 29 Interrupt Enable Bit" "0: Sample Module 29 interrupt Disabled,1: Sample Module 29 interrupt Enabled"
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bitfld.long 0x0 28. "SPLIE28,Sample Module 28 Interrupt Enable Bit" "0: Sample Module 28 interrupt Disabled,1: Sample Module 28 interrupt Enabled"
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bitfld.long 0x0 27. "SPLIE27,Sample Module 27 Interrupt Enable Bit" "0: Sample Module 27 interrupt Disabled,1: Sample Module 27 interrupt Enabled"
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bitfld.long 0x0 26. "SPLIE26,Sample Module 26 Interrupt Enable Bit" "0: Sample Module 26 interrupt Disabled,1: Sample Module 26 interrupt Enabled"
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bitfld.long 0x0 25. "SPLIE25,Sample Module 25 Interrupt Enable Bit" "0: Sample Module 25 interrupt Disabled,1: Sample Module 25 interrupt Enabled"
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bitfld.long 0x0 24. "SPLIE24,Sample Module 24 Interrupt Enable Bit" "0: Sample Module 24 interrupt Disabled,1: Sample Module 24 interrupt Enabled"
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bitfld.long 0x0 23. "SPLIE23,Sample Module 23 Interrupt Enable Bit" "0: Sample Module 23 interrupt Disabled,1: Sample Module 23 interrupt Enabled"
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bitfld.long 0x0 22. "SPLIE22,Sample Module 22 Interrupt Enable Bit" "0: Sample Module 22 interrupt Disabled,1: Sample Module 22 interrupt Enabled"
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bitfld.long 0x0 21. "SPLIE21,Sample Module 21 Interrupt Enable Bit" "0: Sample Module 21 interrupt Disabled,1: Sample Module 21 interrupt Enabled"
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bitfld.long 0x0 20. "SPLIE20,Sample Module 20 Interrupt Enable Bit" "0: Sample Module 20 interrupt Disabled,1: Sample Module 20 interrupt Enabled"
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bitfld.long 0x0 19. "SPLIE19,Sample Module 19 Interrupt Enable Bit" "0: Sample Module 19 interrupt Disabled,1: Sample Module 19 interrupt Enabled"
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bitfld.long 0x0 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x0 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x0 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x0 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x0 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x0 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x0 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x0 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x0 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x0 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x0 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x0 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x0 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x0 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x0 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x0 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x0 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x0 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x0 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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line.long 0x4 "EADC_INTSRC1,EADC Interrupt 1 Source Enable Control Register."
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bitfld.long 0x4 30. "SPLIE30,Sample Module 30 Interrupt Enable Bit" "0: Sample Module 30 interrupt Disabled,1: Sample Module 30 interrupt Enabled"
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bitfld.long 0x4 29. "SPLIE29,Sample Module 29 Interrupt Enable Bit" "0: Sample Module 29 interrupt Disabled,1: Sample Module 29 interrupt Enabled"
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newline
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bitfld.long 0x4 28. "SPLIE28,Sample Module 28 Interrupt Enable Bit" "0: Sample Module 28 interrupt Disabled,1: Sample Module 28 interrupt Enabled"
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bitfld.long 0x4 27. "SPLIE27,Sample Module 27 Interrupt Enable Bit" "0: Sample Module 27 interrupt Disabled,1: Sample Module 27 interrupt Enabled"
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bitfld.long 0x4 26. "SPLIE26,Sample Module 26 Interrupt Enable Bit" "0: Sample Module 26 interrupt Disabled,1: Sample Module 26 interrupt Enabled"
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bitfld.long 0x4 25. "SPLIE25,Sample Module 25 Interrupt Enable Bit" "0: Sample Module 25 interrupt Disabled,1: Sample Module 25 interrupt Enabled"
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bitfld.long 0x4 24. "SPLIE24,Sample Module 24 Interrupt Enable Bit" "0: Sample Module 24 interrupt Disabled,1: Sample Module 24 interrupt Enabled"
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bitfld.long 0x4 23. "SPLIE23,Sample Module 23 Interrupt Enable Bit" "0: Sample Module 23 interrupt Disabled,1: Sample Module 23 interrupt Enabled"
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bitfld.long 0x4 22. "SPLIE22,Sample Module 22 Interrupt Enable Bit" "0: Sample Module 22 interrupt Disabled,1: Sample Module 22 interrupt Enabled"
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bitfld.long 0x4 21. "SPLIE21,Sample Module 21 Interrupt Enable Bit" "0: Sample Module 21 interrupt Disabled,1: Sample Module 21 interrupt Enabled"
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bitfld.long 0x4 20. "SPLIE20,Sample Module 20 Interrupt Enable Bit" "0: Sample Module 20 interrupt Disabled,1: Sample Module 20 interrupt Enabled"
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bitfld.long 0x4 19. "SPLIE19,Sample Module 19 Interrupt Enable Bit" "0: Sample Module 19 interrupt Disabled,1: Sample Module 19 interrupt Enabled"
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bitfld.long 0x4 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x4 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x4 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x4 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x4 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x4 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x4 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x4 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x4 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x4 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x4 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x4 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x4 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x4 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x4 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x4 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x4 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x4 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x4 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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line.long 0x8 "EADC_INTSRC2,EADC Interrupt 2 Source Enable Control Register."
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bitfld.long 0x8 30. "SPLIE30,Sample Module 30 Interrupt Enable Bit" "0: Sample Module 30 interrupt Disabled,1: Sample Module 30 interrupt Enabled"
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bitfld.long 0x8 29. "SPLIE29,Sample Module 29 Interrupt Enable Bit" "0: Sample Module 29 interrupt Disabled,1: Sample Module 29 interrupt Enabled"
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bitfld.long 0x8 28. "SPLIE28,Sample Module 28 Interrupt Enable Bit" "0: Sample Module 28 interrupt Disabled,1: Sample Module 28 interrupt Enabled"
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bitfld.long 0x8 27. "SPLIE27,Sample Module 27 Interrupt Enable Bit" "0: Sample Module 27 interrupt Disabled,1: Sample Module 27 interrupt Enabled"
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bitfld.long 0x8 26. "SPLIE26,Sample Module 26 Interrupt Enable Bit" "0: Sample Module 26 interrupt Disabled,1: Sample Module 26 interrupt Enabled"
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bitfld.long 0x8 25. "SPLIE25,Sample Module 25 Interrupt Enable Bit" "0: Sample Module 25 interrupt Disabled,1: Sample Module 25 interrupt Enabled"
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bitfld.long 0x8 24. "SPLIE24,Sample Module 24 Interrupt Enable Bit" "0: Sample Module 24 interrupt Disabled,1: Sample Module 24 interrupt Enabled"
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bitfld.long 0x8 23. "SPLIE23,Sample Module 23 Interrupt Enable Bit" "0: Sample Module 23 interrupt Disabled,1: Sample Module 23 interrupt Enabled"
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bitfld.long 0x8 22. "SPLIE22,Sample Module 22 Interrupt Enable Bit" "0: Sample Module 22 interrupt Disabled,1: Sample Module 22 interrupt Enabled"
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bitfld.long 0x8 21. "SPLIE21,Sample Module 21 Interrupt Enable Bit" "0: Sample Module 21 interrupt Disabled,1: Sample Module 21 interrupt Enabled"
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bitfld.long 0x8 20. "SPLIE20,Sample Module 20 Interrupt Enable Bit" "0: Sample Module 20 interrupt Disabled,1: Sample Module 20 interrupt Enabled"
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bitfld.long 0x8 19. "SPLIE19,Sample Module 19 Interrupt Enable Bit" "0: Sample Module 19 interrupt Disabled,1: Sample Module 19 interrupt Enabled"
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bitfld.long 0x8 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x8 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x8 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x8 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x8 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x8 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x8 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x8 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x8 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x8 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x8 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x8 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x8 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x8 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x8 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x8 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x8 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x8 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x8 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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line.long 0xC "EADC_INTSRC3,EADC Interrupt 3 Source Enable Control Register."
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bitfld.long 0xC 30. "SPLIE30,Sample Module 30 Interrupt Enable Bit" "0: Sample Module 30 interrupt Disabled,1: Sample Module 30 interrupt Enabled"
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bitfld.long 0xC 29. "SPLIE29,Sample Module 29 Interrupt Enable Bit" "0: Sample Module 29 interrupt Disabled,1: Sample Module 29 interrupt Enabled"
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bitfld.long 0xC 28. "SPLIE28,Sample Module 28 Interrupt Enable Bit" "0: Sample Module 28 interrupt Disabled,1: Sample Module 28 interrupt Enabled"
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bitfld.long 0xC 27. "SPLIE27,Sample Module 27 Interrupt Enable Bit" "0: Sample Module 27 interrupt Disabled,1: Sample Module 27 interrupt Enabled"
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bitfld.long 0xC 26. "SPLIE26,Sample Module 26 Interrupt Enable Bit" "0: Sample Module 26 interrupt Disabled,1: Sample Module 26 interrupt Enabled"
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bitfld.long 0xC 25. "SPLIE25,Sample Module 25 Interrupt Enable Bit" "0: Sample Module 25 interrupt Disabled,1: Sample Module 25 interrupt Enabled"
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bitfld.long 0xC 24. "SPLIE24,Sample Module 24 Interrupt Enable Bit" "0: Sample Module 24 interrupt Disabled,1: Sample Module 24 interrupt Enabled"
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bitfld.long 0xC 23. "SPLIE23,Sample Module 23 Interrupt Enable Bit" "0: Sample Module 23 interrupt Disabled,1: Sample Module 23 interrupt Enabled"
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bitfld.long 0xC 22. "SPLIE22,Sample Module 22 Interrupt Enable Bit" "0: Sample Module 22 interrupt Disabled,1: Sample Module 22 interrupt Enabled"
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bitfld.long 0xC 21. "SPLIE21,Sample Module 21 Interrupt Enable Bit" "0: Sample Module 21 interrupt Disabled,1: Sample Module 21 interrupt Enabled"
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bitfld.long 0xC 20. "SPLIE20,Sample Module 20 Interrupt Enable Bit" "0: Sample Module 20 interrupt Disabled,1: Sample Module 20 interrupt Enabled"
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bitfld.long 0xC 19. "SPLIE19,Sample Module 19 Interrupt Enable Bit" "0: Sample Module 19 interrupt Disabled,1: Sample Module 19 interrupt Enabled"
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bitfld.long 0xC 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0xC 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0xC 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0xC 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0xC 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0xC 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0xC 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0xC 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0xC 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0xC 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0xC 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0xC 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0xC 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0xC 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0xC 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0xC 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0xC 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0xC 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0xC 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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line.long 0x10 "EADC_CMP0,EADC Result Compare Register 0"
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hexmask.long.word 0x10 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
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bitfld.long 0x10 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode the CMPCNT setting only follow EADC_CMP0 EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x10 8.--11. 1. "CMPMCNT,Compare Match Count"
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hexmask.long.byte 0x10 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x10 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x10 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x10 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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line.long 0x14 "EADC_CMP1,EADC Result Compare Register 1"
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hexmask.long.word 0x14 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
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bitfld.long 0x14 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode the CMPCNT setting only follow EADC_CMP0 EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x14 8.--11. 1. "CMPMCNT,Compare Match Count"
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hexmask.long.byte 0x14 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x14 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x14 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x14 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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line.long 0x18 "EADC_CMP2,EADC Result Compare Register 2"
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hexmask.long.word 0x18 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
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bitfld.long 0x18 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode the CMPCNT setting only follow EADC_CMP0 EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x18 8.--11. 1. "CMPMCNT,Compare Match Count"
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hexmask.long.byte 0x18 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x18 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x18 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x18 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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line.long 0x1C "EADC_CMP3,EADC Result Compare Register 3"
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hexmask.long.word 0x1C 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
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bitfld.long 0x1C 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\nNote: When in compare window mode the CMPCNT setting only follow EADC_CMP0 EADC_CMP2 registers" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x1C 8.--11. 1. "CMPMCNT,Compare Match Count"
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hexmask.long.byte 0x1C 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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bitfld.long 0x1C 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x1C 1. "ADCMPIE,EADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x1C 0. "ADCMPEN,EADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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rgroup.long 0xF0++0x7
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line.long 0x0 "EADC_STATUS0,EADC Status Register 0"
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hexmask.long.word 0x0 16.--31. 1. "OV,EADC_DAT0~15 Overrun Flag"
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hexmask.long.word 0x0 0.--15. 1. "VALID,EADC_DAT0~15 Data Valid Flag"
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line.long 0x4 "EADC_STATUS1,EADC Status Register 1"
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hexmask.long.word 0x4 16.--30. 1. "OV,EADC_DAT16~30 Overrun Flag"
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hexmask.long.word 0x4 0.--14. 1. "VALID,EADC_DAT16~30 Data Valid Flag"
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group.long 0xF8++0x3
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line.long 0x0 "EADC_STATUS2,EADC Status Register 2"
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rbitfld.long 0x0 27. "AOV,for All Sample Module EADC Result Data Register Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any OVn Flag is equal to 1." "0: None of sample module data register overrun flag..,1: Any one of sample module data register overrun.."
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rbitfld.long 0x0 26. "AVALID,for All Sample Module EADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1." "0: None of sample module data register valid flag..,1: Any one of sample module data register valid.."
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rbitfld.long 0x0 25. "STOVF,for All EADC Sample Module Start of Conversion Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any SPOVFn Flag is equal to 1." "0: None of sample module event overrun flag SPOVFn..,1: Any one of sample module event overrun flag.."
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rbitfld.long 0x0 24. "ADOVIF,All EADC Interrupt Flag Overrun Bits Check (Read Only)\nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1." "0: None of ADINT interrupt flag ADOVIFn n=0~3 is..,1: Any one of ADINT interrupt flag ADOVIFn n=0~3 is.."
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rbitfld.long 0x0 23. "BUSY,Busy/Idle (Read Only)\nNote: This flag will be high after 4*EADC_CLK cycles when the trigger source is coming." "0: EADC is in idle state,1: EADC is busy at conversion"
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hexmask.long.byte 0x0 16.--20. 1. "CHANNEL,Current Conversion Channel (Read Only)"
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rbitfld.long 0x0 15. "ADCMPO3,EADC Compare 3 Output Status (Read Only)\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT3..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x0 14. "ADCMPO2,EADC Compare 2 Output Status (Read Only)\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT2..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x0 13. "ADCMPO1,EADC Compare 1 Output Status (Read Only)\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT1..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x0 12. "ADCMPO0,EADC Compare 0 Output Status (Read Only)\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT0..,1: Conversion result in EADC_DAT great than or.."
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bitfld.long 0x0 11. "ADOVIF3,EADC ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT3 interrupt flag is not overwritten to 1,1: ADINT3 interrupt flag is overwritten to 1"
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bitfld.long 0x0 10. "ADOVIF2,EADC ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT2 interrupt flag is not overwritten to 1,1: ADINT2 interrupt flag is s overwritten to 1"
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bitfld.long 0x0 9. "ADOVIF1,EADC ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT1 interrupt flag is not overwritten to 1,1: ADINT1 interrupt flag is overwritten to 1"
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bitfld.long 0x0 8. "ADOVIF0,EADC ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it." "0: ADINT0 interrupt flag is not overwritten to 1,1: ADINT0 interrupt flag is overwritten to 1"
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bitfld.long 0x0 7. "ADCMPF3,EADC Compare 3 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP3.."
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bitfld.long 0x0 6. "ADCMPF2,EADC Compare 2 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP2.."
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bitfld.long 0x0 5. "ADCMPF1,EADC Compare 1 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP1.."
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bitfld.long 0x0 4. "ADCMPF0,EADC Compare 0 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP0.."
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bitfld.long 0x0 3. "ADIF3,EADC ADINT3 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT3 interrupt pulse received,1: This bit is cleared by writing 1 to it"
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bitfld.long 0x0 2. "ADIF2,EADC ADINT2 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it. \nNote 2: This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT2 interrupt pulse received,1: This bit is cleared by writing 1 to it"
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bitfld.long 0x0 1. "ADIF1,EADC ADINT1 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT1 interrupt pulse received,1: This bit is cleared by writing 1 to it"
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bitfld.long 0x0 0. "ADIF0,EADC ADINT0 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: This bit indicates whether an EADC conversion of specific sample module has been completed" "0: No ADINT0 interrupt pulse received,1: This bit is cleared by writing 1 to it"
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rgroup.long 0xFC++0x13
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line.long 0x0 "EADC_STATUS3,EADC Status Register 3"
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hexmask.long.byte 0x0 0.--4. 1. "CURSPL,EADC Current Sample Module (Read Only)\nThis register shows the current EADC is controlled by which sample module control logic modules.\nIf the EADC is Idle the bit filed will set to 0x1F."
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line.long 0x4 "EADC_DDAT0,EADC Double Data Register 0 for Sample Module 0"
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bitfld.long 0x4 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
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bitfld.long 0x4 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x4 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
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line.long 0x8 "EADC_DDAT1,EADC Double Data Register 1 for Sample Module 1"
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bitfld.long 0x8 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
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bitfld.long 0x8 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x8 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
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line.long 0xC "EADC_DDAT2,EADC Double Data Register 2 for Sample Module 2"
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bitfld.long 0xC 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
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bitfld.long 0xC 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0xC 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
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line.long 0x10 "EADC_DDAT3,EADC Double Data Register 3 for Sample Module 3"
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bitfld.long 0x10 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
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bitfld.long 0x10 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Double Data in RESULT (EADC_DDATn[15:0] n=0~3)..,1: Double Data in RESULT (EADC_DDATn[15:0] n=0~3).."
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hexmask.long.word 0x10 0.--15. 1. "RESULT,EADC Conversion Results\nThis field contains 12 bits conversion results.\nThe 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]."
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group.long 0x114++0x7
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line.long 0x0 "EADC_CALCTL,EADC Calibration Control Register"
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bitfld.long 0x0 1. "CALIE,Calibration Interrupt Enable Bit" "0: Calibration interrupt Disabled,1: Calibration interrupt Enabled"
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bitfld.long 0x0 0. "CAL,Calibration Enable Bit\nNote: This bit is hardware auto cleared when calibration is done" "0: Calibration Disabled,1: Calibration Enabled"
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line.long 0x4 "EADC_CALSR,EADC Calibration Status Register"
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bitfld.long 0x4 16. "CALIF,Calibration Finish Interrupt Flag\nIf calibration is finished this flag will be set to 1. It is cleared by writing 1 to it." "0,1"
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group.long 0x130++0x3
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line.long 0x0 "EADC_PDMACTL,EADC PDMA Control Register"
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hexmask.long 0x0 0.--30. 1. "PDMATEN,PDMA Transfer Enable Bit\nWhen EADC conversion is completed the converted data is loaded into EADC_DATn (n: 0 ~ 30) register user can enable this bit to generate a PDMA data transfer request."
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group.long 0x140++0x4B
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line.long 0x0 "EADC_M0CTL1,EADC Sample Module 0 Control Register 1"
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bitfld.long 0x0 20. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x0 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x0 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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bitfld.long 0x0 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x0 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x4 "EADC_M1CTL1,EADC Sample Module 1 Control Register 1"
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bitfld.long 0x4 20. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x4 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x4 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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bitfld.long 0x4 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x4 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x8 "EADC_M2CTL1,EADC Sample Module 2 Control Register 1"
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bitfld.long 0x8 20. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x8 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x8 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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bitfld.long 0x8 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x8 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0xC "EADC_M3CTL1,EADC Sample Module 3 Control Register 1"
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bitfld.long 0xC 20. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0xC 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0xC 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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bitfld.long 0xC 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0xC 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x10 "EADC_M4CTL1,EADC Sample Module 4 Control Register 1"
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bitfld.long 0x10 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x10 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x10 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x10 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x14 "EADC_M5CTL1,EADC Sample Module 5 Control Register 1"
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bitfld.long 0x14 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x14 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x14 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x14 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x18 "EADC_M6CTL1,EADC Sample Module 6 Control Register 1"
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bitfld.long 0x18 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x18 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x18 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x18 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x1C "EADC_M7CTL1,EADC Sample Module 7 Control Register 1"
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bitfld.long 0x1C 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x1C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x1C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x1C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x20 "EADC_M8CTL1,EADC Sample Module 8 Control Register 1"
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bitfld.long 0x20 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x20 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x20 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x20 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x24 "EADC_M9CTL1,EADC Sample Module 9 Control Register 1"
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bitfld.long 0x24 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x24 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x24 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x24 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x28 "EADC_M10CTL1,EADC Sample Module 10 Control Register 1"
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bitfld.long 0x28 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x28 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x28 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x28 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x2C "EADC_M11CTL1,EADC Sample Module 11 Control Register 1"
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bitfld.long 0x2C 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x2C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x2C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x2C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x30 "EADC_M12CTL1,EADC Sample Module 12 Control Register 1"
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bitfld.long 0x30 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x30 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x30 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x30 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x34 "EADC_M13CTL1,EADC Sample Module 13 Control Register 1"
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bitfld.long 0x34 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x34 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x34 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x34 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x38 "EADC_M14CTL1,EADC Sample Module 14 Control Register 1"
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bitfld.long 0x38 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x38 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x38 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
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bitfld.long 0x38 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x3C "EADC_M15CTL1,EADC Sample Module 15 Control Register 1"
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bitfld.long 0x3C 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x3C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
|
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bitfld.long 0x3C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
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bitfld.long 0x3C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x40 "EADC_M16CTL1,EADC Sample Module 16 Control Register 1"
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bitfld.long 0x40 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x40 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
|
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newline
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bitfld.long 0x40 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
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bitfld.long 0x40 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x44 "EADC_M17CTL1,EADC Sample Module 17 Control Register 1"
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bitfld.long 0x44 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x44 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
|
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newline
|
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bitfld.long 0x44 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
|
bitfld.long 0x44 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x48 "EADC_M18CTL1,EADC Sample Module 18 Control Register 1"
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bitfld.long 0x48 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x48 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
|
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newline
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bitfld.long 0x48 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
|
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bitfld.long 0x48 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
|
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rgroup.long 0x200++0x2F
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line.long 0x0 "EADC_DAT19,EADC Data Register 19 for Sample Module 19"
|
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bitfld.long 0x0 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x0 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x4 "EADC_DAT20,EADC Data Register 20 for Sample Module 20"
|
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bitfld.long 0x4 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x4 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
|
|
newline
|
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hexmask.long.word 0x4 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x8 "EADC_DAT21,EADC Data Register 21 for Sample Module 21"
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bitfld.long 0x8 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x8 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0xC "EADC_DAT22,EADC Data Register 22 for Sample Module 22"
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bitfld.long 0xC 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0xC 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
|
|
newline
|
|
hexmask.long.word 0xC 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
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line.long 0x10 "EADC_DAT23,EADC Data Register 23 for Sample Module 23"
|
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bitfld.long 0x10 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x10 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
|
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line.long 0x14 "EADC_DAT24,EADC Data Register 24 for Sample Module 24"
|
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bitfld.long 0x14 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
bitfld.long 0x14 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
|
|
line.long 0x18 "EADC_DAT25,EADC Data Register 25 for Sample Module 25"
|
|
bitfld.long 0x18 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
bitfld.long 0x18 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
|
|
line.long 0x1C "EADC_DAT26,EADC Data Register 26 for Sample Module 26"
|
|
bitfld.long 0x1C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
bitfld.long 0x1C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
|
|
line.long 0x20 "EADC_DAT27,EADC Data Register 27 for Sample Module 27"
|
|
bitfld.long 0x20 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
bitfld.long 0x20 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
|
|
newline
|
|
hexmask.long.word 0x20 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
|
|
line.long 0x24 "EADC_DAT28,EADC Data Register 28 for Sample Module 28"
|
|
bitfld.long 0x24 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
bitfld.long 0x24 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
|
|
line.long 0x28 "EADC_DAT29,EADC Data Register 29 for Sample Module 29"
|
|
bitfld.long 0x28 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
bitfld.long 0x28 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
|
|
newline
|
|
hexmask.long.word 0x28 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
|
|
line.long 0x2C "EADC_DAT30,EADC Data Register 30 for Sample Module 30"
|
|
bitfld.long 0x2C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
bitfld.long 0x2C 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
|
|
newline
|
|
hexmask.long.word 0x2C 0.--15. 1. "RESULT,EADC Conversion Result\nThis field contains 12 bits conversion result. The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nNote: When operating in oversampling mode .."
|
|
group.long 0x230++0x5F
|
|
line.long 0x0 "EADC_SCTL19,EADC Sample Module 19 Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
|
|
bitfld.long 0x0 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
|
|
newline
|
|
bitfld.long 0x0 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
|
|
hexmask.long.byte 0x0 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
|
|
bitfld.long 0x0 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
|
|
newline
|
|
bitfld.long 0x0 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
|
|
hexmask.long.byte 0x0 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
|
|
line.long 0x4 "EADC_SCTL20,EADC Sample Module 20 Control Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x4 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x4 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x4 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x4 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x4 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x4 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x4 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x8 "EADC_SCTL21,EADC Sample Module 21 Control Register"
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hexmask.long.byte 0x8 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x8 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x8 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x8 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x8 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x8 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x8 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x8 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0xC "EADC_SCTL22,EADC Sample Module 22 Control Register"
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hexmask.long.byte 0xC 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0xC 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0xC 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0xC 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0xC 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0xC 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0xC 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0xC 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x10 "EADC_SCTL23,EADC Sample Module 23 Control Register"
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hexmask.long.byte 0x10 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x10 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x10 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x10 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x10 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x10 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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bitfld.long 0x10 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x10 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x14 "EADC_SCTL24,EADC Sample Module 24 Control Register"
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hexmask.long.byte 0x14 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x14 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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bitfld.long 0x14 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x14 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x14 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x14 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x14 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x14 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x18 "EADC_SCTL25,EADC Sample Module 25 Control Register"
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hexmask.long.byte 0x18 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x18 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x18 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x18 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x18 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x18 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x18 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x18 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x1C "EADC_SCTL26,EADC Sample Module 26 Control Register"
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hexmask.long.byte 0x1C 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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bitfld.long 0x1C 23. "EXTFEN,EADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when EADC selects EADC0_ST..,1: Falling edge Enabled when EADC selects EADC0_ST.."
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newline
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bitfld.long 0x1C 22. "EXTREN,EADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when EADC selects EADC0_ST..,1: Rising edge Enabled when EADC selects EADC0_ST.."
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hexmask.long.byte 0x1C 16.--21. 1. "TRGSEL,EADC Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x1C 8.--15. 1. "TRGDLYCNT,EADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x1C 6.--7. "TRGDLYDIV,EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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newline
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bitfld.long 0x1C 5. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at EADC start.."
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hexmask.long.byte 0x1C 0.--4. 1. "CHSEL,EADC Sample Module Channel Selection"
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line.long 0x20 "EADC_SCTL27,EADC Sample Module 27 Control Register"
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hexmask.long.byte 0x20 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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line.long 0x24 "EADC_SCTL28,EADC Sample Module 28 Control Register"
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hexmask.long.byte 0x24 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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line.long 0x28 "EADC_SCTL29,EADC Sample Module 29 Control Register"
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hexmask.long.byte 0x28 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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line.long 0x2C "EADC_SCTL30,EADC Sample Module 30 Control Register"
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hexmask.long.byte 0x2C 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen EADC converting at high conversion rate the sampling time of analog input voltage may not be enough if input channel loading is heavy and software can extend EADC sampling time after trigger source is coming to.."
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line.long 0x30 "EADC_M19CTL1,EADC Sample Module 19 Control Register 1"
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bitfld.long 0x30 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x30 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x30 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x30 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x34 "EADC_M20CTL1,EADC Sample Module 20 Control Register 1"
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bitfld.long 0x34 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x34 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x34 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x34 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x38 "EADC_M21CTL1,EADC Sample Module 21 Control Register 1"
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bitfld.long 0x38 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x38 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x38 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x38 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x3C "EADC_M22CTL1,EADC Sample Module 22 Control Register 1"
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bitfld.long 0x3C 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x3C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x3C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x3C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x40 "EADC_M23CTL1,EADC Sample Module 23 Control Register 1"
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bitfld.long 0x40 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x40 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x40 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x40 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x44 "EADC_M24CTL1,EADC Sample Module 24 Control Register 1"
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bitfld.long 0x44 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x44 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x44 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x44 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x48 "EADC_M25CTL1,EADC Sample Module 25 Control Register 1"
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bitfld.long 0x48 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x48 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x48 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x48 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x4C "EADC_M26CTL1,EADC Sample Module 26 Control Register 1"
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bitfld.long 0x4C 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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hexmask.long.byte 0x4C 4.--7. 1. "ACU,Number of Accumulated Conversion Results Selection"
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newline
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bitfld.long 0x4C 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x4C 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned in..,1: The conversion result will be left aligned in.."
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line.long 0x50 "EADC_M27CTL1,EADC Sample Module 27 Control Register 1"
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bitfld.long 0x50 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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line.long 0x54 "EADC_M28CTL1,EADC Sample Module 28 Control Register 1"
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bitfld.long 0x54 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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line.long 0x58 "EADC_M29CTL1,EADC Sample Module 29 Control Register 1"
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bitfld.long 0x58 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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line.long 0x5C "EADC_M30CTL1,EADC Sample Module 30 Control Register 1"
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bitfld.long 0x5C 16.--17. "EXTSTDIV,EADC Extended Sampling Time Clock Divider Selection\nClock frequency for extending sampling time:" "0: EADC_CLK/1,1: EADC_CLK/2,?,?"
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tree.end
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tree "EBI (External Bus Interface)"
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base ad:0x40010000
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group.long 0x0++0x7
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line.long 0x0 "EBI_CTL0,External Bus Interface Bank0 Control Register"
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bitfld.long 0x0 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit is only available in EBI_CTL0 register." "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
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bitfld.long 0x0 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field is only available in EBI_CTL0 register." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:" "0: HCLK/1,1: HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x0 4. "CACCESS,Continuous Data Access Mode\nWhen continuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request." "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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newline
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bitfld.long 0x0 3. "ADSEPEN,EBI Address/Data Bus Separate Mode Enable Bit" "0: Address/Data Bus Separate Mode Disabled,1: Address/Data Bus Separate Mode Enabled"
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bitfld.long 0x0 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)." "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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newline
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bitfld.long 0x0 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit." "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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bitfld.long 0x0 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI." "0: EBI function Disabled,1: EBI function Enabled"
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line.long 0x4 "EBI_TCTL0,External Bus Interface Bank0 Timing Control Register"
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hexmask.long.byte 0x4 24.--27. 1. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state."
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bitfld.long 0x4 23. "WAHDOFF,Access Hold Time Disable Control When Write" "0: Data Access Hold Time (tAHD) during EBI writing..,1: Data Access Hold Time (tAHD) during EBI writing.."
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newline
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bitfld.long 0x4 22. "RAHDOFF,Access Hold Time Disable Control When Read" "0: Data Access Hold Time (tAHD) during EBI reading..,1: Data Access Hold Time (tAHD) during EBI reading.."
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hexmask.long.byte 0x4 12.--15. 1. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished W2X idle cycle is inserted and EBI_nCS return to idle state."
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newline
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bitfld.long 0x4 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 3.--7. 1. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)."
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group.long 0x10++0x7
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line.long 0x0 "EBI_CTL1,External Bus Interface Bank1 Control Register"
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bitfld.long 0x0 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit is only available in EBI_CTL0 register." "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
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bitfld.long 0x0 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field is only available in EBI_CTL0 register." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:" "0: HCLK/1,1: HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x0 4. "CACCESS,Continuous Data Access Mode\nWhen continuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request." "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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newline
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bitfld.long 0x0 3. "ADSEPEN,EBI Address/Data Bus Separate Mode Enable Bit" "0: Address/Data Bus Separate Mode Disabled,1: Address/Data Bus Separate Mode Enabled"
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bitfld.long 0x0 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)." "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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newline
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bitfld.long 0x0 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit." "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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bitfld.long 0x0 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI." "0: EBI function Disabled,1: EBI function Enabled"
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line.long 0x4 "EBI_TCTL1,External Bus Interface Bank1 Timing Control Register"
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hexmask.long.byte 0x4 24.--27. 1. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state."
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bitfld.long 0x4 23. "WAHDOFF,Access Hold Time Disable Control When Write" "0: Data Access Hold Time (tAHD) during EBI writing..,1: Data Access Hold Time (tAHD) during EBI writing.."
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bitfld.long 0x4 22. "RAHDOFF,Access Hold Time Disable Control When Read" "0: Data Access Hold Time (tAHD) during EBI reading..,1: Data Access Hold Time (tAHD) during EBI reading.."
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hexmask.long.byte 0x4 12.--15. 1. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished W2X idle cycle is inserted and EBI_nCS return to idle state."
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bitfld.long 0x4 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 3.--7. 1. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)."
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group.long 0x20++0x7
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line.long 0x0 "EBI_CTL2,External Bus Interface Bank2 Control Register"
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bitfld.long 0x0 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit is only available in EBI_CTL0 register." "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
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bitfld.long 0x0 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field is only available in EBI_CTL0 register." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:" "0: HCLK/1,1: HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x0 4. "CACCESS,Continuous Data Access Mode\nWhen continuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request." "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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bitfld.long 0x0 3. "ADSEPEN,EBI Address/Data Bus Separate Mode Enable Bit" "0: Address/Data Bus Separate Mode Disabled,1: Address/Data Bus Separate Mode Enabled"
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bitfld.long 0x0 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)." "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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bitfld.long 0x0 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit." "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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bitfld.long 0x0 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI." "0: EBI function Disabled,1: EBI function Enabled"
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line.long 0x4 "EBI_TCTL2,External Bus Interface Bank2 Timing Control Register"
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hexmask.long.byte 0x4 24.--27. 1. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state."
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bitfld.long 0x4 23. "WAHDOFF,Access Hold Time Disable Control When Write" "0: Data Access Hold Time (tAHD) during EBI writing..,1: Data Access Hold Time (tAHD) during EBI writing.."
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bitfld.long 0x4 22. "RAHDOFF,Access Hold Time Disable Control When Read" "0: Data Access Hold Time (tAHD) during EBI reading..,1: Data Access Hold Time (tAHD) during EBI reading.."
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hexmask.long.byte 0x4 12.--15. 1. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished W2X idle cycle is inserted and EBI_nCS return to idle state."
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bitfld.long 0x4 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 3.--7. 1. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)."
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tree.end
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tree "ECAP (Enhanced Input Capture Timer)"
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base ad:0x0
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tree "ECAP0"
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base ad:0x400B4000
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group.long 0x0++0x1F
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line.long 0x0 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider."
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line.long 0x4 "ECAP_HLD0,Input Capture Hold Register 0"
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hexmask.long.tbyte 0x4 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
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line.long 0x8 "ECAP_HLD1,Input Capture Hold Register 1"
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hexmask.long.tbyte 0x8 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
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line.long 0xC "ECAP_HLD2,Input Capture Hold Register 2"
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hexmask.long.tbyte 0xC 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
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line.long 0x10 "ECAP_CNTCMP,Input Capture Compare Register"
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hexmask.long.tbyte 0x10 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register"
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line.long 0x14 "ECAP_CTL0,Input Capture Control Register 0"
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bitfld.long 0x14 29. "CAPEN,Input Capture Timer/Counter Enable Bit" "0: Input Capture function Disabled,1: Input Capture function Enabled"
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bitfld.long 0x14 28. "CMPEN,Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP if ECAP_CNT value reaches ECAP_CNTCMP the flag CAPCMPF will be set." "0: The compare function Disabled,1: The compare function Enabled"
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bitfld.long 0x14 25. "CMPCLREN,Input Capture Counter Cleared by Compare-match Control" "0: Compare-match event (CAPCMPF) can clear capture..,1: Compare-match event (CAPCMPF) can clear capture.."
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bitfld.long 0x14 24. "CNTEN,Input Capture Counter Start Counting Control\nSetting this bit to 1 the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the ." "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
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bitfld.long 0x14 21. "CMPIEN,CAPCMPF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPCMPF can trigger Input Capture..,1: The flag CAPCMPF can trigger Input Capture.."
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bitfld.long 0x14 20. "OVIEN,CAPOVF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPOVF can trigger Input Capture..,1: The flag CAPOVF can trigger Input Capture.."
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bitfld.long 0x14 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Bit" "0: The flag CAPTF2 can trigger Input Capture..,1: The flag CAPTF2 can trigger Input Capture.."
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bitfld.long 0x14 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Bit" "0: The flag CAPTF1 can trigger Input Capture..,1: The flag CAPTF1 can trigger Input Capture.."
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bitfld.long 0x14 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Bit" "0: The flag CAPTF0 can trigger Input Capture..,1: The flag CAPTF0 can trigger Input Capture.."
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bitfld.long 0x14 12.--13. "CAPSEL2,CAP2 Input Source Selection" "0: CAP2 input is from port pin ICAP2,1: CAP2 input is from signal ACMP2_O,?,?"
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bitfld.long 0x14 10.--11. "CAPSEL1,CAP1 Input Source Selection" "0: CAP1 input is from port pin ICAP1,1: CAP1 input is from signal ACMP1_O,?,?"
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bitfld.long 0x14 8.--9. "CAPSEL0,CAP0 Input Source Selection" "0: CAP0 input is from port pin ICAP0,1: CAP0 input is from signal ACMP0_O,?,?"
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newline
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bitfld.long 0x14 6. "IC2EN,Port Pin IC2 Input to Input Capture Unit Enable Bit" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
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bitfld.long 0x14 5. "IC1EN,Port Pin IC1 Input to Input Capture Unit Enable Bit" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
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newline
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bitfld.long 0x14 4. "IC0EN,Port Pin IC0 Input to Input Capture Unit Enable Bit" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
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bitfld.long 0x14 3. "CAPNFDIS,Input Capture Noise Filter Disable Bit" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled (Bypass)"
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bitfld.long 0x14 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: ECAP_CLK,1: ECAP_CLK/2,?,?,?,?,?,?"
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line.long 0x18 "ECAP_CTL1,Input Capture Control Register 1"
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bitfld.long 0x18 22. "CAP2CLREN,Capture Counter Cleared by Capture Event2 Control" "0: Event CAPTE2 can clear capture counter..,1: Event CAPTE2 can clear capture counter.."
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bitfld.long 0x18 21. "CAP1CLREN,Capture Counter Cleared by Capture Event1 Control" "0: Event CAPTE1 can clear capture counter..,1: Event CAPTE1 can clear capture counter.."
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newline
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bitfld.long 0x18 20. "CAP0CLREN,Capture Counter Cleared by Capture Event0 Control" "0: Event CAPTE0 can clear capture counter..,1: Event CAPTE0 can clear capture counter.."
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bitfld.long 0x18 16.--17. "CNTSRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source." "0: ECAP_CLK (default),1: CAP0,?,?"
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bitfld.long 0x18 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]." "0: ECAP_CLK/1,1: ECAP_CLK/4,?,?,?,?,?,?"
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bitfld.long 0x18 11. "OVRLDEN,Capture Counter's Reload Function Triggered by Overflow Enable Bit" "0: The reload triggered by CAPOV Disabled,1: The reload triggered by CAPOV Enabled"
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bitfld.long 0x18 10. "CAP2RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit" "0: The reload triggered by Event CAPTE2 Disabled,1: The reload triggered by Event CAPTE2 Enabled"
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bitfld.long 0x18 9. "CAP1RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit" "0: The reload triggered by Event CAPTE1 Disabled,1: The reload triggered by Event CAPTE1 Enabled"
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newline
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bitfld.long 0x18 8. "CAP0RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit" "0: The reload triggered by Event CAPTE0 Disabled,1: The reload triggered by Event CAPTE0 Enabled"
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bitfld.long 0x18 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only rising edge change only or both edge changes" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
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newline
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bitfld.long 0x18 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
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bitfld.long 0x18 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
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line.long 0x1C "ECAP_STATUS,Input Capture Status Register"
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rbitfld.long 0x1C 10. "CAP2,Value of Input Channel 2 CAP2 (Read Only)\nReflecting the value of input channel 2 CAP2.\nNote: The bit is read only and write is ignored." "0,1"
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rbitfld.long 0x1C 9. "CAP1,Value of Input Channel 1 CAP1 (Read Only)\nReflecting the value of input channel 1 CAP1\nNote: The bit is read only and write is ignored." "0,1"
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newline
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rbitfld.long 0x1C 8. "CAP0,Value of Input Channel 0 CAP0 (Read Only)\nReflecting the value of input channel 0 CAP0\nNote: The bit is read only and write is ignored." "0,1"
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bitfld.long 0x1C 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to 0.\nNote: This bit is only cleared by writing 1 to it." "0: No overflow event has occurred since last clear,1: Overflow event(s) has/have occurred since last.."
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bitfld.long 0x1C 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it." "0: ECAP_CNT has not matched ECAP_CNTCMP value since..,1: ECAP_CNT has matched ECAP_CNTCMP value at least.."
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bitfld.long 0x1C 2. "CAPTF2,Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP2..,1: At least a valid edge change has been detected.."
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newline
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bitfld.long 0x1C 1. "CAPTF1,Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP1..,1: At least a valid edge change has been detected.."
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bitfld.long 0x1C 0. "CAPTF0,Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP0..,1: At least a valid edge change has been detected.."
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tree.end
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tree "ECAP1"
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base ad:0x400B5000
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group.long 0x0++0x1F
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line.long 0x0 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider."
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line.long 0x4 "ECAP_HLD0,Input Capture Hold Register 0"
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hexmask.long.tbyte 0x4 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
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line.long 0x8 "ECAP_HLD1,Input Capture Hold Register 1"
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hexmask.long.tbyte 0x8 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
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line.long 0xC "ECAP_HLD2,Input Capture Hold Register 2"
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hexmask.long.tbyte 0xC 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
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line.long 0x10 "ECAP_CNTCMP,Input Capture Compare Register"
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hexmask.long.tbyte 0x10 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register"
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line.long 0x14 "ECAP_CTL0,Input Capture Control Register 0"
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bitfld.long 0x14 29. "CAPEN,Input Capture Timer/Counter Enable Bit" "0: Input Capture function Disabled,1: Input Capture function Enabled"
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bitfld.long 0x14 28. "CMPEN,Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP if ECAP_CNT value reaches ECAP_CNTCMP the flag CAPCMPF will be set." "0: The compare function Disabled,1: The compare function Enabled"
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bitfld.long 0x14 25. "CMPCLREN,Input Capture Counter Cleared by Compare-match Control" "0: Compare-match event (CAPCMPF) can clear capture..,1: Compare-match event (CAPCMPF) can clear capture.."
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bitfld.long 0x14 24. "CNTEN,Input Capture Counter Start Counting Control\nSetting this bit to 1 the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the ." "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
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newline
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bitfld.long 0x14 21. "CMPIEN,CAPCMPF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPCMPF can trigger Input Capture..,1: The flag CAPCMPF can trigger Input Capture.."
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bitfld.long 0x14 20. "OVIEN,CAPOVF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPOVF can trigger Input Capture..,1: The flag CAPOVF can trigger Input Capture.."
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newline
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bitfld.long 0x14 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Bit" "0: The flag CAPTF2 can trigger Input Capture..,1: The flag CAPTF2 can trigger Input Capture.."
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bitfld.long 0x14 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Bit" "0: The flag CAPTF1 can trigger Input Capture..,1: The flag CAPTF1 can trigger Input Capture.."
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newline
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bitfld.long 0x14 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Bit" "0: The flag CAPTF0 can trigger Input Capture..,1: The flag CAPTF0 can trigger Input Capture.."
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bitfld.long 0x14 12.--13. "CAPSEL2,CAP2 Input Source Selection" "0: CAP2 input is from port pin ICAP2,1: CAP2 input is from signal ACMP2_O,?,?"
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newline
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bitfld.long 0x14 10.--11. "CAPSEL1,CAP1 Input Source Selection" "0: CAP1 input is from port pin ICAP1,1: CAP1 input is from signal ACMP1_O,?,?"
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bitfld.long 0x14 8.--9. "CAPSEL0,CAP0 Input Source Selection" "0: CAP0 input is from port pin ICAP0,1: CAP0 input is from signal ACMP0_O,?,?"
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newline
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bitfld.long 0x14 6. "IC2EN,Port Pin IC2 Input to Input Capture Unit Enable Bit" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
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bitfld.long 0x14 5. "IC1EN,Port Pin IC1 Input to Input Capture Unit Enable Bit" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
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newline
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bitfld.long 0x14 4. "IC0EN,Port Pin IC0 Input to Input Capture Unit Enable Bit" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
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bitfld.long 0x14 3. "CAPNFDIS,Input Capture Noise Filter Disable Bit" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled (Bypass)"
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newline
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bitfld.long 0x14 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: ECAP_CLK,1: ECAP_CLK/2,?,?,?,?,?,?"
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line.long 0x18 "ECAP_CTL1,Input Capture Control Register 1"
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bitfld.long 0x18 22. "CAP2CLREN,Capture Counter Cleared by Capture Event2 Control" "0: Event CAPTE2 can clear capture counter..,1: Event CAPTE2 can clear capture counter.."
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bitfld.long 0x18 21. "CAP1CLREN,Capture Counter Cleared by Capture Event1 Control" "0: Event CAPTE1 can clear capture counter..,1: Event CAPTE1 can clear capture counter.."
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newline
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bitfld.long 0x18 20. "CAP0CLREN,Capture Counter Cleared by Capture Event0 Control" "0: Event CAPTE0 can clear capture counter..,1: Event CAPTE0 can clear capture counter.."
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bitfld.long 0x18 16.--17. "CNTSRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source." "0: ECAP_CLK (default),1: CAP0,?,?"
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newline
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bitfld.long 0x18 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]." "0: ECAP_CLK/1,1: ECAP_CLK/4,?,?,?,?,?,?"
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bitfld.long 0x18 11. "OVRLDEN,Capture Counter's Reload Function Triggered by Overflow Enable Bit" "0: The reload triggered by CAPOV Disabled,1: The reload triggered by CAPOV Enabled"
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newline
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bitfld.long 0x18 10. "CAP2RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit" "0: The reload triggered by Event CAPTE2 Disabled,1: The reload triggered by Event CAPTE2 Enabled"
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bitfld.long 0x18 9. "CAP1RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit" "0: The reload triggered by Event CAPTE1 Disabled,1: The reload triggered by Event CAPTE1 Enabled"
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newline
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bitfld.long 0x18 8. "CAP0RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit" "0: The reload triggered by Event CAPTE0 Disabled,1: The reload triggered by Event CAPTE0 Enabled"
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bitfld.long 0x18 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only rising edge change only or both edge changes" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
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newline
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bitfld.long 0x18 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
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bitfld.long 0x18 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
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line.long 0x1C "ECAP_STATUS,Input Capture Status Register"
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rbitfld.long 0x1C 10. "CAP2,Value of Input Channel 2 CAP2 (Read Only)\nReflecting the value of input channel 2 CAP2.\nNote: The bit is read only and write is ignored." "0,1"
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rbitfld.long 0x1C 9. "CAP1,Value of Input Channel 1 CAP1 (Read Only)\nReflecting the value of input channel 1 CAP1\nNote: The bit is read only and write is ignored." "0,1"
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newline
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rbitfld.long 0x1C 8. "CAP0,Value of Input Channel 0 CAP0 (Read Only)\nReflecting the value of input channel 0 CAP0\nNote: The bit is read only and write is ignored." "0,1"
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bitfld.long 0x1C 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to 0.\nNote: This bit is only cleared by writing 1 to it." "0: No overflow event has occurred since last clear,1: Overflow event(s) has/have occurred since last.."
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newline
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bitfld.long 0x1C 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it." "0: ECAP_CNT has not matched ECAP_CNTCMP value since..,1: ECAP_CNT has matched ECAP_CNTCMP value at least.."
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bitfld.long 0x1C 2. "CAPTF2,Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP2..,1: At least a valid edge change has been detected.."
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newline
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bitfld.long 0x1C 1. "CAPTF1,Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP1..,1: At least a valid edge change has been detected.."
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bitfld.long 0x1C 0. "CAPTF0,Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP0..,1: At least a valid edge change has been detected.."
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tree.end
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tree.end
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tree "EPWM (Enhanced Pulse Width Modulation)"
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base ad:0x0
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tree "EPWM0"
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base ad:0x40058000
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group.long 0x0++0xB
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line.long 0x0 "EPWM_CTL0,EPWM Control Register 0"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nEPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode acknowledgement effects EPWM output,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled EPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each EPWM channel are..,1: Unify the EPWM_CH2 and EPWM_CH4 to output the.."
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bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 13. "WINLDEN5,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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newline
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bitfld.long 0x0 12. "WINLDEN4,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 11. "WINLDEN3,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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newline
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bitfld.long 0x0 10. "WINLDEN2,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 9. "WINLDEN1,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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newline
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bitfld.long 0x0 8. "WINLDEN0,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 5. "CTRLD5,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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newline
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bitfld.long 0x0 4. "CTRLD4,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 3. "CTRLD3,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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newline
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bitfld.long 0x0 2. "CTRLD2,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 1. "CTRLD1,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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newline
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bitfld.long 0x0 0. "CTRLD0,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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line.long 0x4 "EPWM_CTL1,EPWM Control Register 1"
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bitfld.long 0x4 26. "OUTMODE4,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x4 25. "OUTMODE2,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
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newline
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bitfld.long 0x4 24. "OUTMODE0,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x4 21. "CNTMODE5,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x4 20. "CNTMODE4,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 19. "CNTMODE3,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x4 18. "CNTMODE2,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 17. "CNTMODE1,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x4 16. "CNTMODE0,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 10.--11. "CNTTYPE5,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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newline
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bitfld.long 0x4 8.--9. "CNTTYPE4,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 6.--7. "CNTTYPE3,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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newline
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bitfld.long 0x4 4.--5. "CNTTYPE2,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 2.--3. "CNTTYPE1,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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newline
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bitfld.long 0x4 0.--1. "CNTTYPE0,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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line.long 0x8 "EPWM_SYNC,EPWM Synchronization Register"
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bitfld.long 0x8 26. "PHSDIR4,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x8 25. "PHSDIR2,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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newline
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bitfld.long 0x8 24. "PHSDIR0,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x8 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of pin SYNC is passed to the negative..,1: The inversed state of pin SYNC is passed to the.."
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newline
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bitfld.long 0x8 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x8 16. "SNFLTEN,EPWM0_SYNC_IN Noise Filter Enable Bits" "0: Noise filter of input pin EPWM0_SYNC_IN Disabled,1: Noise filter of input pin EPWM0_SYNC_IN Enabled"
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bitfld.long 0x8 12.--13. "SINSRC4,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
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bitfld.long 0x8 10.--11. "SINSRC2,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
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bitfld.long 0x8 8.--9. "SINSRC0,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
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newline
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bitfld.long 0x8 2. "PHSEN4,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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bitfld.long 0x8 1. "PHSEN2,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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newline
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bitfld.long 0x8 0. "PHSEN0,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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wgroup.long 0xC++0x3
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line.long 0x0 "EPWM_SWSYNC,EPWM Software Control Synchronization Register"
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bitfld.long 0x0 2. "SWSYNC4,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
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bitfld.long 0x0 1. "SWSYNC2,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
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newline
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bitfld.long 0x0 0. "SWSYNC0,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
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group.long 0x10++0x3
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line.long 0x0 "EPWM_CLKSRC,EPWM Clock Source Register"
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bitfld.long 0x0 16.--18. "ECLKSRC4,EPWM_CH45 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "ECLKSRC2,EPWM_CH23 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 0.--2. "ECLKSRC0,EPWM_CH01 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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group.long 0x20++0xB
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line.long 0x0 "EPWM_CNTEN,EPWM Counter Enable Register"
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bitfld.long 0x0 5. "CNTEN5,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x0 4. "CNTEN4,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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newline
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bitfld.long 0x0 3. "CNTEN3,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x0 2. "CNTEN2,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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newline
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bitfld.long 0x0 1. "CNTEN1,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x0 0. "CNTEN0,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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line.long 0x4 "EPWM_CNTCLR,EPWM Clear Counter Register"
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bitfld.long 0x4 5. "CNTCLR5,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x4 4. "CNTCLR4,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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newline
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bitfld.long 0x4 3. "CNTCLR3,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x4 2. "CNTCLR2,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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newline
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bitfld.long 0x4 1. "CNTCLR1,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x4 0. "CNTCLR0,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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line.long 0x8 "EPWM_LOAD,EPWM Load Register"
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bitfld.long 0x8 5. "LOAD5,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x8 4. "LOAD4,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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newline
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bitfld.long 0x8 3. "LOAD3,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x8 2. "LOAD2,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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newline
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bitfld.long 0x8 1. "LOAD1,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x8 0. "LOAD0,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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group.long 0x30++0x17
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line.long 0x0 "EPWM_PERIOD0,EPWM Period Register 0"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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line.long 0x4 "EPWM_PERIOD1,EPWM Period Register 1"
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hexmask.long.word 0x4 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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line.long 0x8 "EPWM_PERIOD2,EPWM Period Register 2"
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hexmask.long.word 0x8 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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line.long 0xC "EPWM_PERIOD3,EPWM Period Register 3"
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hexmask.long.word 0xC 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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line.long 0x10 "EPWM_PERIOD4,EPWM Period Register 4"
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hexmask.long.word 0x10 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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line.long 0x14 "EPWM_PERIOD5,EPWM Period Register 5"
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hexmask.long.word 0x14 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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group.long 0x50++0x17
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line.long 0x0 "EPWM_CMPDAT0,EPWM Comparator Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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line.long 0x4 "EPWM_CMPDAT1,EPWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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line.long 0x8 "EPWM_CMPDAT2,EPWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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line.long 0xC "EPWM_CMPDAT3,EPWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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line.long 0x10 "EPWM_CMPDAT4,EPWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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line.long 0x14 "EPWM_CMPDAT5,EPWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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group.long 0x80++0xB
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line.long 0x0 "EPWM_PHS0_1,EPWM Counter Phase Register 0/1"
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hexmask.long.word 0x0 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
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line.long 0x4 "EPWM_PHS2_3,EPWM Counter Phase Register 2/3"
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hexmask.long.word 0x4 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
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line.long 0x8 "EPWM_PHS4_5,EPWM Counter Phase Register 4/5"
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hexmask.long.word 0x8 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
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rgroup.long 0x90++0x17
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line.long 0x0 "EPWM_CNT0,EPWM Counter Register 0"
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bitfld.long 0x0 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x0 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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line.long 0x4 "EPWM_CNT1,EPWM Counter Register 1"
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bitfld.long 0x4 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x4 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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line.long 0x8 "EPWM_CNT2,EPWM Counter Register 2"
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bitfld.long 0x8 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x8 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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line.long 0xC "EPWM_CNT3,EPWM Counter Register 3"
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bitfld.long 0xC 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0xC 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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line.long 0x10 "EPWM_CNT4,EPWM Counter Register 4"
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bitfld.long 0x10 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x10 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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line.long 0x14 "EPWM_CNT5,EPWM Counter Register 5"
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bitfld.long 0x14 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x14 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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group.long 0xB0++0x2B
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line.long 0x0 "EPWM_WGCTL0,EPWM Generation Register 0"
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bitfld.long 0x0 26.--27. "PRDPCTL5,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 24.--25. "PRDPCTL4,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 20.--21. "PRDPCTL2,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 16.--17. "PRDPCTL0,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 8.--9. "ZPCTL4,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 4.--5. "ZPCTL2,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 0.--1. "ZPCTL0,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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line.long 0x4 "EPWM_WGCTL1,EPWM Generation Register 1"
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bitfld.long 0x4 26.--27. "CMPDCTL5,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 24.--25. "CMPDCTL4,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 20.--21. "CMPDCTL2,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 16.--17. "CMPDCTL0,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 8.--9. "CMPUCTL4,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 4.--5. "CMPUCTL2,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 0.--1. "CMPUCTL0,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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line.long 0x8 "EPWM_MSKEN,EPWM Mask Enable Register"
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bitfld.long 0x8 5. "MSKEN5,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 4. "MSKEN4,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 2. "MSKEN2,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 0. "MSKEN0,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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line.long 0xC "EPWM_MSK,EPWM Mask Data Register"
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bitfld.long 0xC 5. "MSKDAT5,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 4. "MSKDAT4,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 3. "MSKDAT3,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 2. "MSKDAT2,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 1. "MSKDAT1,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 0. "MSKDAT0,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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line.long 0x10 "EPWM_BNF,EPWM Brake Noise Filter Register"
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bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select\nFor EPWM0 setting:" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
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bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select\nFor EPWM0 setting:" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
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bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: brake pin event will be detected if EPWMx_BRAKE1..,1: brake pin event will be detected if EPWMx_BRAKE1.."
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bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 8. "BRK1NFEN,EPWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 1 Disabled,1: Noise filter of EPWM Brake 1 Enabled"
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bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: brake pin event will be detected if EPWMx_BRAKE0..,1: brake pin event will be detected if EPWMx_BRAKE0.."
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bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK0FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "BRK0NFEN,EPWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 0 Disabled,1: Noise filter of EPWM Brake 0 Enabled"
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line.long 0x14 "EPWM_FAILBRK,EPWM System Fail Brake Control Register"
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bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger EPWM Brake Function Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x14 2. "RAMBRKEN,SRAM Parity Error Detection Trigger EPWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger EPWM Brake Function Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger EPWM Brake Function Enable Bit" "0: Brake Function triggered by CSS detection Disabled,1: Brake Function triggered by CSS detection Enabled"
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line.long 0x18 "EPWM_BRKCTL0_1,EPWM Brake Edge Detect Control Register 0/1"
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bitfld.long 0x18 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x18 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x18 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x18 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x18 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x18 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x18 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x18 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x18 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x18 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x18 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x18 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x18 6. "VBSNBKEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x18 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x18 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x18 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x18 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x18 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x1C "EPWM_BRKCTL2_3,EPWM Brake Edge Detect Control Register 2/3"
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bitfld.long 0x1C 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x1C 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x1C 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x1C 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x1C 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x1C 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x1C 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x1C 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x1C 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x1C 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x1C 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x1C 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x1C 6. "VBSNBKEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x1C 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x1C 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x1C 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x20 "EPWM_BRKCTL4_5,EPWM Brake Edge Detect Control Register 4/5"
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bitfld.long 0x20 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x20 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x20 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x20 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x20 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x20 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x20 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x20 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x20 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x20 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x20 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x20 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x20 6. "VBSNBKEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x20 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x20 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x20 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x20 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x20 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x24 "EPWM_POLCTL,EPWM Pin Polar Inverse Register"
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bitfld.long 0x24 5. "PINV5,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 4. "PINV4,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 3. "PINV3,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 2. "PINV2,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 1. "PINV1,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 0. "PINV0,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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line.long 0x28 "EPWM_POEN,EPWM Output Enable Register"
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bitfld.long 0x28 5. "POEN5,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 4. "POEN4,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 3. "POEN3,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 2. "POEN2,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 1. "POEN1,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 0. "POEN0,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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wgroup.long 0xDC++0x3
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line.long 0x0 "EPWM_SWBRK,EPWM Software Brake Control Register"
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bitfld.long 0x0 10. "BRKLTRG4,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 9. "BRKLTRG2,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 8. "BRKLTRG0,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 2. "BRKETRG4,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 1. "BRKETRG2,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 0. "BRKETRG0,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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group.long 0xE0++0xF
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line.long 0x0 "EPWM_INTEN0,EPWM Interrupt Enable Register 0"
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bitfld.long 0x0 29. "CMPDIEN5,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 28. "CMPDIEN4,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 26. "CMPDIEN2,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 24. "CMPDIEN0,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 20. "CMPUIEN4,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 18. "CMPUIEN2,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 16. "CMPUIEN0,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 13. "PIEN5,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 12. "PIEN4,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 11. "PIEN3,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 10. "PIEN2,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 9. "PIEN1,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 8. "PIEN0,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 5. "ZIEN5,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 4. "ZIEN4,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 3. "ZIEN3,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 2. "ZIEN2,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 1. "ZIEN1,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 0. "ZIEN0,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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line.long 0x4 "EPWM_INTEN1,EPWM Interrupt Enable Register 1"
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bitfld.long 0x4 10. "BRKLIEN4_5,EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x4 9. "BRKLIEN2_3,EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x4 8. "BRKLIEN0_1,EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x4 2. "BRKEIEN4_5,EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled"
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bitfld.long 0x4 1. "BRKEIEN2_3,EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled"
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bitfld.long 0x4 0. "BRKEIEN0_1,EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled"
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line.long 0x8 "EPWM_INTSTS0,EPWM Interrupt Flag Register 0"
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bitfld.long 0x8 29. "CMPDIF5,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 28. "CMPDIF4,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 27. "CMPDIF3,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 26. "CMPDIF2,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 25. "CMPDIF1,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 24. "CMPDIF0,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 21. "CMPUIF5,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 20. "CMPUIF4,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 19. "CMPUIF3,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 18. "CMPUIF2,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 17. "CMPUIF1,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 16. "CMPUIF0,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 13. "PIF5,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 12. "PIF4,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 11. "PIF3,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 10. "PIF2,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 9. "PIF1,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 8. "PIF0,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 5. "ZIF5,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 4. "ZIF4,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 3. "ZIF3,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 2. "ZIF2,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 1. "ZIF1,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 0. "ZIF0,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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line.long 0xC "EPWM_INTSTS1,EPWM Interrupt Flag Register 1"
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rbitfld.long 0xC 29. "BRKLSTS5,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 28. "BRKLSTS4,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 27. "BRKLSTS3,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 26. "BRKLSTS2,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 25. "BRKLSTS1,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 24. "BRKLSTS0,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 21. "BRKESTS5,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 20. "BRKESTS4,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 19. "BRKESTS3,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 18. "BRKESTS2,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 17. "BRKESTS1,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 16. "BRKESTS0,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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bitfld.long 0xC 13. "BRKLIF5,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 12. "BRKLIF4,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 11. "BRKLIF3,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 10. "BRKLIF2,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 9. "BRKLIF1,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 8. "BRKLIF0,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 5. "BRKEIF5,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 4. "BRKEIF4,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 3. "BRKEIF3,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 2. "BRKEIF2,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 1. "BRKEIF1,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 0. "BRKEIF0,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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group.long 0xF4++0x17
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line.long 0x0 "EPWM_DACTRGEN,EPWM Trigger DAC Enable Register"
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bitfld.long 0x0 29. "CDTRGEN5,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 28. "CDTRGEN4,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 27. "CDTRGEN3,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 26. "CDTRGEN2,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 25. "CDTRGEN1,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 24. "CDTRGEN0,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 21. "CUTRGEN5,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 20. "CUTRGEN4,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 19. "CUTRGEN3,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 18. "CUTRGEN2,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 17. "CUTRGEN1,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 16. "CUTRGEN0,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 13. "PTE5,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 12. "PTE4,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 11. "PTE3,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 10. "PTE2,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 9. "PTE1,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 8. "PTE0,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 5. "ZTE5,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 4. "ZTE4,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 3. "ZTE3,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 2. "ZTE2,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 1. "ZTE1,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 0. "ZTE0,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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line.long 0x4 "EPWM_EADCTS0,EPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x4 31. "TRGEN3,EPWM_CH3 Trigger EADC Enable Bit" "0: EPWM_CH3 Trigger EADC function Disabled,1: EPWM_CH3 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 24.--28. 1. "TRGSEL3,EPWM_CH3 Trigger EADC Source Select"
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bitfld.long 0x4 23. "TRGEN2,EPWM_CH2 Trigger EADC Enable Bit" "0: EPWM_CH2 Trigger EADC function Disabled,1: EPWM_CH2 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 16.--20. 1. "TRGSEL2,EPWM_CH2 Trigger EADC Source Select"
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bitfld.long 0x4 15. "TRGEN1,EPWM_CH1 Trigger EADC Enable Bit" "0: EPWM_CH1 Trigger EADC function Disabled,1: EPWM_CH1 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 8.--12. 1. "TRGSEL1,EPWM_CH1 Trigger EADC Source Select"
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bitfld.long 0x4 7. "TRGEN0,EPWM_CH0 Trigger EADC Enable Bit" "0: EPWM_CH0 Trigger EADC function Disabled,1: EPWM_CH0 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 0.--4. 1. "TRGSEL0,EPWM_CH0 Trigger EADC Source Select"
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line.long 0x8 "EPWM_EADCTS1,EPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x8 15. "TRGEN5,EPWM_CH5 Trigger EADC Enable Bit" "0: EPWM_CH5 Trigger EADC function Disabled,1: EPWM_CH5 Trigger EADC function Enabled"
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hexmask.long.byte 0x8 8.--12. 1. "TRGSEL5,EPWM_CH5 Trigger EADC Source Select"
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bitfld.long 0x8 7. "TRGEN4,EPWM_CH4 Trigger EADC Enable Bit" "0: EPWM_CH4 Trigger EADC function Disabled,1: EPWM_CH4 Trigger EADC function Enabled"
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hexmask.long.byte 0x8 0.--4. 1. "TRGSEL4,EPWM_CH4 Trigger EADC Source Select"
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line.long 0xC "EPWM_FTCMPDAT0_1,EPWM Free Trigger Compare Register 0/1"
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hexmask.long.word 0xC 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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line.long 0x10 "EPWM_FTCMPDAT2_3,EPWM Free Trigger Compare Register 2/3"
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hexmask.long.word 0x10 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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line.long 0x14 "EPWM_FTCMPDAT4_5,EPWM Free Trigger Compare Register 4/5"
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hexmask.long.word 0x14 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x110++0x3
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line.long 0x0 "EPWM_SSCTL,EPWM Synchronous Start Control Register"
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bitfld.long 0x0 8.--9. "SSRC,EPWM Synchronous Start Source Select Bits" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,?,?"
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bitfld.long 0x0 5. "SSEN5,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 4. "SSEN4,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 3. "SSEN3,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 2. "SSEN2,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 1. "SSEN1,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 0. "SSEN0,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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wgroup.long 0x114++0x3
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line.long 0x0 "EPWM_SSTRG,EPWM Synchronous Start Trigger Register"
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bitfld.long 0x0 0. "CNTSEN,EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
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group.long 0x118++0xB
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line.long 0x0 "EPWM_LEBCTL,EPWM Leading Edge Blanking Control Register"
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bitfld.long 0x0 16.--17. "TRGTYPE,EPWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source rising..,1: When detect leading edge blanking source falling..,2: When detect leading edge blanking source rising..,3: Reserved."
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bitfld.long 0x0 10. "SRCEN4,EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH4..,1: EPWM Leading Edge Blanking Source from EPWM_CH4.."
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bitfld.long 0x0 9. "SRCEN2,EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH2..,1: EPWM Leading Edge Blanking Source from EPWM_CH2.."
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bitfld.long 0x0 8. "SRCEN0,EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH0..,1: EPWM Leading Edge Blanking Source from EPWM_CH0.."
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bitfld.long 0x0 0. "LEBEN,EPWM Leading Edge Blanking Enable Bit" "0: EPWM Leading Edge Blanking Disabled,1: EPWM Leading Edge Blanking Enabled"
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line.long 0x4 "EPWM_LEBCNT,EPWM Leading Edge Blanking Counter Register"
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hexmask.long.word 0x4 0.--8. 1. "LEBCNT,EPWM Leading Edge Blanking Counter"
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line.long 0x8 "EPWM_STATUS,EPWM Status Register"
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bitfld.long 0x8 24. "DACTRGF,DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No DAC start of conversion trigger event has..,1: A DAC start of conversion trigger event has.."
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bitfld.long 0x8 23. "LPADCTRGF,LPADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No LPADC start of conversion trigger event has..,1: A LPADC start of conversion trigger event has.."
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bitfld.long 0x8 21. "EADCTRGF5,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 20. "EADCTRGF4,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 19. "EADCTRGF3,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 18. "EADCTRGF2,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 17. "EADCTRGF1,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 16. "EADCTRGF0,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 10. "SYNCINF4,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x8 9. "SYNCINF2,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x8 8. "SYNCINF0,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x8 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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group.long 0x130++0x17
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line.long 0x0 "EPWM_IFA0,EPWM Interrupt Flag Accumulator Register 0"
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bitfld.long 0x0 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0x0 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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line.long 0x4 "EPWM_IFA1,EPWM Interrupt Flag Accumulator Register 1"
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bitfld.long 0x4 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x4 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x4 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0x4 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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line.long 0x8 "EPWM_IFA2,EPWM Interrupt Flag Accumulator Register 2"
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bitfld.long 0x8 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x8 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x8 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0x8 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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line.long 0xC "EPWM_IFA3,EPWM Interrupt Flag Accumulator Register 3"
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bitfld.long 0xC 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0xC 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0xC 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0xC 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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line.long 0x10 "EPWM_IFA4,EPWM Interrupt Flag Accumulator Register 4"
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bitfld.long 0x10 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x10 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x10 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0x10 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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line.long 0x14 "EPWM_IFA5,EPWM Interrupt Flag Accumulator Register 5"
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bitfld.long 0x14 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x14 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x14 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0x14 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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group.long 0x150++0xB
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line.long 0x0 "EPWM_AINTSTS,EPWM Accumulator Interrupt Flag Register"
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bitfld.long 0x0 5. "IFAIF5,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 4. "IFAIF4,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 3. "IFAIF3,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 2. "IFAIF2,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 1. "IFAIF1,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 0. "IFAIF0,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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line.long 0x4 "EPWM_AINTEN,EPWM Accumulator Interrupt Enable Register"
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bitfld.long 0x4 5. "IFAIEN5,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 4. "IFAIEN4,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 3. "IFAIEN3,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 2. "IFAIEN2,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 1. "IFAIEN1,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 0. "IFAIEN0,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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line.long 0x8 "EPWM_APDMACTL,EPWM Accumulator PDMA Control Register"
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bitfld.long 0x8 5. "APDMAEN5,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 4. "APDMAEN4,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 3. "APDMAEN3,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 2. "APDMAEN2,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 1. "APDMAEN1,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 0. "APDMAEN0,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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group.long 0x160++0x37
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line.long 0x0 "EPWM_FDEN,EPWM Fault Detect Enable Register"
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bitfld.long 0x0 21. "FDCKS5,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 20. "FDCKS4,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 19. "FDCKS3,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 18. "FDCKS2,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 17. "FDCKS1,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 16. "FDCKS0,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 13. "FDODIS5,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 12. "FDODIS4,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 11. "FDODIS3,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 10. "FDODIS2,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 9. "FDODIS1,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 8. "FDODIS0,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 5. "FDEN5,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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bitfld.long 0x0 4. "FDEN4,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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bitfld.long 0x0 3. "FDEN3,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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bitfld.long 0x0 2. "FDEN2,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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bitfld.long 0x0 1. "FDEN1,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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bitfld.long 0x0 0. "FDEN0,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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line.long 0x4 "EPWM_FDCTL0,EPWM Fault Detect Control Register 0"
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bitfld.long 0x4 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0x4 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x4 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0x4 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0x4 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0x8 "EPWM_FDCTL1,EPWM Fault Detect Control Register 1"
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bitfld.long 0x8 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0x8 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x8 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0x8 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0x8 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0xC "EPWM_FDCTL2,EPWM Fault Detect Control Register 2"
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bitfld.long 0xC 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0xC 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0xC 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0xC 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0xC 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0x10 "EPWM_FDCTL3,EPWM Fault Detect Control Register 3"
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bitfld.long 0x10 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0x10 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x10 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0x10 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0x10 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0x14 "EPWM_FDCTL4,EPWM Fault Detect Control Register 4"
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bitfld.long 0x14 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0x14 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x14 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0x14 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0x14 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0x18 "EPWM_FDCTL5,EPWM Fault Detect Control Register 5"
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bitfld.long 0x18 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0x18 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x18 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0x18 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0x18 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0x1C "EPWM_FDIEN,EPWM Fault Detect Interrupt Enable Register"
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bitfld.long 0x1C 5. "FDIEN5,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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bitfld.long 0x1C 4. "FDIEN4,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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bitfld.long 0x1C 3. "FDIEN3,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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bitfld.long 0x1C 2. "FDIEN2,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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bitfld.long 0x1C 1. "FDIEN1,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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bitfld.long 0x1C 0. "FDIEN0,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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line.long 0x20 "EPWM_FDSTS,EPWM Fault Detect Interrupt Flag Register"
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hexmask.long.byte 0x20 0.--5. 1. "FDIFn,EPWM Channel n Fault Detect Interrupt Flag Bit\nFault Detect Interrupt Flag will be set when detect EPWM output short condition. Software can clear this bit by writing 1 to it."
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line.long 0x24 "EPWM_EADCPSCCTL,EPWM Trigger EADC Prescale Control Register"
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bitfld.long 0x24 5. "PSCEN5,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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bitfld.long 0x24 4. "PSCEN4,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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bitfld.long 0x24 3. "PSCEN3,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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bitfld.long 0x24 2. "PSCEN2,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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bitfld.long 0x24 1. "PSCEN1,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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bitfld.long 0x24 0. "PSCEN0,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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line.long 0x28 "EPWM_EADCPSC0,EPWM Trigger EADC Prescale Register 0"
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hexmask.long.byte 0x28 24.--27. 1. "EADCPSC3,EPWM Channel 3 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC3+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3."
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hexmask.long.byte 0x28 16.--19. 1. "EADCPSC2,EPWM Channel 2 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC2+1) times of EPWM_CH2 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF2."
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hexmask.long.byte 0x28 8.--11. 1. "EADCPSC1,EPWM Channel 1 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC1+1) times of EPWM_CH1 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF1."
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hexmask.long.byte 0x28 0.--3. 1. "EADCPSC0,EPWM Channel 0 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC0+1) times of EPWM_CH0 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF0."
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line.long 0x2C "EPWM_EADCPSC1,EPWM Trigger EADC Prescale Register 1"
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hexmask.long.byte 0x2C 8.--11. 1. "EADCPSC5,EPWM Channel 5 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC5+1) times of EPWM_CH5 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF5."
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hexmask.long.byte 0x2C 0.--3. 1. "EADCPSC4,EPWM Channel 4 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC4+1) times of EPWM_CH4 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF4."
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line.long 0x30 "EPWM_EADCPSCNT0,EPWM Trigger EADC Prescale Counter Register 0"
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hexmask.long.byte 0x30 24.--27. 1. "PSCNT3,EPWM Trigger EADC Prescale Counter 3\nUser can monitor PSCNT3 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN3 is 0.\nNote 2: Write data limitation: PSCNT3 EADCPSC3."
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hexmask.long.byte 0x30 16.--19. 1. "PSCNT2,EPWM Trigger EADC Prescale Counter 2\nUser can monitor PSCNT2 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN2 is 0.\nNote 2: Write data limitation: PSCNT2 EADCPSC2."
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hexmask.long.byte 0x30 8.--11. 1. "PSCNT1,EPWM Trigger EADC Prescale Counter 1\nUser can monitor PSCNT1 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN1 is 0.\nNote 2: Write data limitation: PSCNT1 EADCPSC1."
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hexmask.long.byte 0x30 0.--3. 1. "PSCNT0,EPWM Trigger EADC Prescale Counter 0\nUser can monitor PSCNT0 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN0 is 0.\nNote 2: Write data limitation: PSCNT0 EADCPSC0."
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line.long 0x34 "EPWM_EADCPSCNT1,EPWM Trigger EADC Prescale Counter Register 1"
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hexmask.long.byte 0x34 8.--11. 1. "PSCNT5,EPWM Trigger EADC Prescale Counter 5\nUser can monitor PSCNT5 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN5 is 0.\nNote 2: Write data limitation: PSCNT5 EADCPSC5."
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hexmask.long.byte 0x34 0.--3. 1. "PSCNT4,EPWM Trigger EADC Prescale Counter 4\nUser can monitor PSCNT4 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN4 is 0.\nNote 2: Write data limitation: PSCNT4 EADCPSC4."
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group.long 0x200++0x7
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line.long 0x0 "EPWM_CAPINEN,EPWM Capture Input Enable Register"
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bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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line.long 0x4 "EPWM_CAPCTL,EPWM Capture Control Register"
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bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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rgroup.long 0x208++0x33
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line.long 0x0 "EPWM_CAPSTS,EPWM Capture Status Register"
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bitfld.long 0x0 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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line.long 0x4 "EPWM_RCAPDAT0,EPWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x8 "EPWM_FCAPDAT0,EPWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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line.long 0xC "EPWM_RCAPDAT1,EPWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x10 "EPWM_FCAPDAT1,EPWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x14 "EPWM_RCAPDAT2,EPWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x18 "EPWM_FCAPDAT2,EPWM Falling Capture Data Register 2"
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hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x1C "EPWM_RCAPDAT3,EPWM Rising Capture Data Register 3"
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hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x20 "EPWM_FCAPDAT3,EPWM Falling Capture Data Register 3"
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hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x24 "EPWM_RCAPDAT4,EPWM Rising Capture Data Register 4"
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hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x28 "EPWM_FCAPDAT4,EPWM Falling Capture Data Register 4"
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hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x2C "EPWM_RCAPDAT5,EPWM Rising Capture Data Register 5"
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hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x30 "EPWM_FCAPDAT5,EPWM Falling Capture Data Register 5"
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hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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group.long 0x23C++0x3
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line.long 0x0 "EPWM_PDMACTL,EPWM PDMA Control Register"
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bitfld.long 0x0 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
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bitfld.long 0x0 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order" "0: EPWM_FCAPDAT4/5 is the first captured data to..,1: EPWM_RCAPDAT4/5 is the first captured data to.."
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bitfld.long 0x0 17.--18. "CAPMOD4_5,Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT4/5,?,?"
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bitfld.long 0x0 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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newline
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bitfld.long 0x0 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
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bitfld.long 0x0 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order" "0: EPWM_FCAPDAT2/3 is the first captured data to..,1: EPWM_RCAPDAT2/3 is the first captured data to.."
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newline
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bitfld.long 0x0 9.--10. "CAPMOD2_3,Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT2/3,?,?"
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bitfld.long 0x0 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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bitfld.long 0x0 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
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bitfld.long 0x0 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order" "0: EPWM_FCAPDAT0/1 is the first captured data to..,1: EPWM_RCAPDAT0/1 is the first captured data to.."
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newline
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bitfld.long 0x0 1.--2. "CAPMOD0_1,Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT0/1,?,?"
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bitfld.long 0x0 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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rgroup.long 0x240++0xB
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line.long 0x0 "EPWM_PDMACAP0_1,EPWM Capture Channel 01 PDMA Register"
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hexmask.long.word 0x0 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
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line.long 0x4 "EPWM_PDMACAP2_3,EPWM Capture Channel 23 PDMA Register"
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hexmask.long.word 0x4 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
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line.long 0x8 "EPWM_PDMACAP4_5,EPWM Capture Channel 45 PDMA Register"
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hexmask.long.word 0x8 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
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group.long 0x250++0x73
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line.long 0x0 "EPWM_CAPIEN,EPWM Capture Interrupt Enable Register"
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bitfld.long 0x0 13. "CAPFIEN5,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 12. "CAPFIEN4,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 11. "CAPFIEN3,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 10. "CAPFIEN2,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 9. "CAPFIEN1,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 8. "CAPFIEN0,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 5. "CAPRIEN5,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 4. "CAPRIEN4,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 3. "CAPRIEN3,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 2. "CAPRIEN2,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 1. "CAPRIEN1,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 0. "CAPRIEN0,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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line.long 0x4 "EPWM_CAPIF,EPWM Capture Interrupt Flag Register"
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bitfld.long 0x4 13. "CFLIF5,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 12. "CFLIF4,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 11. "CFLIF3,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 10. "CFLIF2,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 9. "CFLIF1,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 8. "CFLIF0,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 5. "CRLIF5,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 4. "CRLIF4,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 3. "CRLIF3,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 2. "CRLIF2,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 1. "CRLIF1,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 0. "CRLIF0,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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line.long 0x8 "EPWM_CAPNF0,EPWM Capture Input Noise Filter Register 0"
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bitfld.long 0x8 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x8 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0xC "EPWM_CAPNF1,EPWM Capture Input Noise Filter Register 1"
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bitfld.long 0xC 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0xC 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x10 "EPWM_CAPNF2,EPWM Capture Input Noise Filter Register 2"
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bitfld.long 0x10 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x10 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x14 "EPWM_CAPNF3,EPWM Capture Input Noise Filter Register 3"
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bitfld.long 0x14 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x14 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x18 "EPWM_CAPNF4,EPWM Capture Input Noise Filter Register 4"
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bitfld.long 0x18 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x18 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x1C "EPWM_CAPNF5,EPWM Capture Input Noise Filter Register 5"
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bitfld.long 0x1C 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x1C 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x20 "EPWM_EXTETCTL0,EPWM External Event Trigger Control Register 0"
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hexmask.long.byte 0x20 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x20 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x20 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x24 "EPWM_EXTETCTL1,EPWM External Event Trigger Control Register 1"
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hexmask.long.byte 0x24 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x24 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x24 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x28 "EPWM_EXTETCTL2,EPWM External Event Trigger Control Register 2"
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hexmask.long.byte 0x28 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x28 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x28 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x2C "EPWM_EXTETCTL3,EPWM External Event Trigger Control Register 3"
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hexmask.long.byte 0x2C 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x2C 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x2C 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x30 "EPWM_EXTETCTL4,EPWM External Event Trigger Control Register 4"
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hexmask.long.byte 0x30 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x30 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x30 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x34 "EPWM_EXTETCTL5,EPWM External Event Trigger Control Register 5"
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hexmask.long.byte 0x34 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x34 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x34 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x38 "EPWM_SWEOFCTL,EPWM Software Event Output Force Control Register"
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bitfld.long 0x38 10.--11. "OUTACTS5,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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bitfld.long 0x38 8.--9. "OUTACTS4,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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newline
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bitfld.long 0x38 6.--7. "OUTACTS3,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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bitfld.long 0x38 4.--5. "OUTACTS2,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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newline
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bitfld.long 0x38 2.--3. "OUTACTS1,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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bitfld.long 0x38 0.--1. "OUTACTS0,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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line.long 0x3C "EPWM_SWEOFTRG,EPWM Software Event Output Force Trigger Register"
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bitfld.long 0x3C 5. "SWETRG5,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x3C 4. "SWETRG4,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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newline
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bitfld.long 0x3C 3. "SWETRG3,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x3C 2. "SWETRG2,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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newline
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bitfld.long 0x3C 1. "SWETRG1,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x3C 0. "SWETRG0,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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line.long 0x40 "EPWM_CLKPSC0,EPWM Clock Prescale Register 0"
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hexmask.long.word 0x40 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x44 "EPWM_CLKPSC1,EPWM Clock Prescale Register 1"
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hexmask.long.word 0x44 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x48 "EPWM_CLKPSC2,EPWM Clock Prescale Register 2"
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hexmask.long.word 0x48 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x4C "EPWM_CLKPSC3,EPWM Clock Prescale Register 3"
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hexmask.long.word 0x4C 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x50 "EPWM_CLKPSC4,EPWM Clock Prescale Register 4"
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hexmask.long.word 0x50 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x54 "EPWM_CLKPSC5,EPWM Clock Prescale Register 5"
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hexmask.long.word 0x54 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x58 "EPWM_RDTCNT0_1,EPWM Rising Dead-time Counter Register 0/1"
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hexmask.long.word 0x58 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x5C "EPWM_RDTCNT2_3,EPWM Rising Dead-time Counter Register 2/3"
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hexmask.long.word 0x5C 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x60 "EPWM_RDTCNT4_5,EPWM Rising Dead-time Counter Register 4/5"
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hexmask.long.word 0x60 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x64 "EPWM_FDTCNT0_1,EPWM Falling Dead-time Counter Register 0/1"
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hexmask.long.word 0x64 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x68 "EPWM_FDTCNT2_3,EPWM Falling Dead-time Counter Register 2/3"
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hexmask.long.word 0x68 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x6C "EPWM_FDTCNT4_5,EPWM Falling Dead-time Counter Register 4/5"
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hexmask.long.word 0x6C 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x70 "EPWM_DTCTL,EPWM Dead-time Control Register"
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bitfld.long 0x70 16. "DTCKSELn,Dead-time Clock Select for EPWM Pair (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x70 10. "FDTEN4,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
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newline
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bitfld.long 0x70 9. "FDTEN2,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
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bitfld.long 0x70 8. "FDTEN0,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
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newline
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bitfld.long 0x70 2. "RDTEN4,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
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bitfld.long 0x70 1. "RDTEN2,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
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newline
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bitfld.long 0x70 0. "RDTEN0,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
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rgroup.long 0x304++0x2F
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line.long 0x0 "EPWM_PBUF0,EPWM PERIOD0 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0x4 "EPWM_PBUF1,EPWM PERIOD1 Buffer"
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hexmask.long.word 0x4 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0x8 "EPWM_PBUF2,EPWM PERIOD2 Buffer"
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hexmask.long.word 0x8 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0xC "EPWM_PBUF3,EPWM PERIOD3 Buffer"
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hexmask.long.word 0xC 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0x10 "EPWM_PBUF4,EPWM PERIOD4 Buffer"
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hexmask.long.word 0x10 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0x14 "EPWM_PBUF5,EPWM PERIOD5 Buffer"
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hexmask.long.word 0x14 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0x18 "EPWM_CMPBUF0,EPWM CMPDAT0 Buffer"
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hexmask.long.word 0x18 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x1C "EPWM_CMPBUF1,EPWM CMPDAT1 Buffer"
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hexmask.long.word 0x1C 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x20 "EPWM_CMPBUF2,EPWM CMPDAT2 Buffer"
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hexmask.long.word 0x20 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x24 "EPWM_CMPBUF3,EPWM CMPDAT3 Buffer"
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hexmask.long.word 0x24 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x28 "EPWM_CMPBUF4,EPWM CMPDAT4 Buffer"
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hexmask.long.word 0x28 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x2C "EPWM_CMPBUF5,EPWM CMPDAT5 Buffer"
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hexmask.long.word 0x2C 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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rgroup.long 0x340++0xB
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line.long 0x0 "EPWM_FTCBUF0_1,EPWM FTCMPDAT0_1 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
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line.long 0x4 "EPWM_FTCBUF2_3,EPWM FTCMPDAT2_3 Buffer"
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hexmask.long.word 0x4 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
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line.long 0x8 "EPWM_FTCBUF4_5,EPWM FTCMPDAT4_5 Buffer"
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hexmask.long.word 0x8 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
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group.long 0x34C++0x3
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line.long 0x0 "EPWM_FTCI,EPWM FTCMPDAT Indicator Register"
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bitfld.long 0x0 10. "FTCMD4,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 9. "FTCMD2,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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newline
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bitfld.long 0x0 8. "FTCMD0,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 2. "FTCMU4,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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newline
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bitfld.long 0x0 1. "FTCMU2,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 0. "FTCMU0,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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rgroup.long 0x350++0x2F
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line.long 0x0 "EPWM_CPSCBUF0,EPWM CLKPSC0 Buffer"
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hexmask.long.word 0x0 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0x4 "EPWM_CPSCBUF1,EPWM CLKPSC1 Buffer"
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hexmask.long.word 0x4 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0x8 "EPWM_CPSCBUF2,EPWM CLKPSC2 Buffer"
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hexmask.long.word 0x8 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0xC "EPWM_CPSCBUF3,EPWM CLKPSC3 Buffer"
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hexmask.long.word 0xC 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0x10 "EPWM_CPSCBUF4,EPWM CLKPSC4 Buffer"
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hexmask.long.word 0x10 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0x14 "EPWM_CPSCBUF5,EPWM CLKPSC5 Buffer"
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hexmask.long.word 0x14 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0x18 "EPWM_IFACNT0,EPWM Interrupt Flag Accumulator Counter 0"
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hexmask.long.word 0x18 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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line.long 0x1C "EPWM_IFACNT1,EPWM Interrupt Flag Accumulator Counter 1"
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hexmask.long.word 0x1C 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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line.long 0x20 "EPWM_IFACNT2,EPWM Interrupt Flag Accumulator Counter 2"
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hexmask.long.word 0x20 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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line.long 0x24 "EPWM_IFACNT3,EPWM Interrupt Flag Accumulator Counter 3"
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hexmask.long.word 0x24 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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line.long 0x28 "EPWM_IFACNT4,EPWM Interrupt Flag Accumulator Counter 4"
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hexmask.long.word 0x28 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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line.long 0x2C "EPWM_IFACNT5,EPWM Interrupt Flag Accumulator Counter 5"
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hexmask.long.word 0x2C 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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tree.end
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tree "EPWM1"
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base ad:0x40059000
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group.long 0x0++0xB
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line.long 0x0 "EPWM_CTL0,EPWM Control Register 0"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nEPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode acknowledgement effects EPWM output,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled EPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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newline
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bitfld.long 0x0 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each EPWM channel are..,1: Unify the EPWM_CH2 and EPWM_CH4 to output the.."
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bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMP will load to PBUF and CMPBUF.."
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bitfld.long 0x0 13. "WINLDEN5,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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newline
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bitfld.long 0x0 12. "WINLDEN4,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 11. "WINLDEN3,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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newline
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bitfld.long 0x0 10. "WINLDEN2,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 9. "WINLDEN1,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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newline
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bitfld.long 0x0 8. "WINLDEN0,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x0 5. "CTRLD5,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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newline
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bitfld.long 0x0 4. "CTRLD4,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 3. "CTRLD3,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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newline
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bitfld.long 0x0 2. "CTRLD2,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 1. "CTRLD1,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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newline
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bitfld.long 0x0 0. "CTRLD0,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period." "0,1"
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line.long 0x4 "EPWM_CTL1,EPWM Control Register 1"
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bitfld.long 0x4 26. "OUTMODE4,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x4 25. "OUTMODE2,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
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newline
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bitfld.long 0x4 24. "OUTMODE0,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode." "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x4 21. "CNTMODE5,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x4 20. "CNTMODE4,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 19. "CNTMODE3,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x4 18. "CNTMODE2,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 17. "CNTMODE1,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x4 16. "CNTMODE0,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x4 10.--11. "CNTTYPE5,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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newline
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bitfld.long 0x4 8.--9. "CNTTYPE4,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 6.--7. "CNTTYPE3,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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newline
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bitfld.long 0x4 4.--5. "CNTTYPE2,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 2.--3. "CNTTYPE1,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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newline
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bitfld.long 0x4 0.--1. "CNTTYPE0,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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line.long 0x8 "EPWM_SYNC,EPWM Synchronization Register"
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bitfld.long 0x8 26. "PHSDIR4,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x8 25. "PHSDIR2,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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newline
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bitfld.long 0x8 24. "PHSDIR0,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x8 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of pin SYNC is passed to the negative..,1: The inversed state of pin SYNC is passed to the.."
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newline
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bitfld.long 0x8 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x8 16. "SNFLTEN,EPWM0_SYNC_IN Noise Filter Enable Bits" "0: Noise filter of input pin EPWM0_SYNC_IN Disabled,1: Noise filter of input pin EPWM0_SYNC_IN Enabled"
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bitfld.long 0x8 12.--13. "SINSRC4,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
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newline
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bitfld.long 0x8 10.--11. "SINSRC2,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
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bitfld.long 0x8 8.--9. "SINSRC0,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,?,?"
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newline
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bitfld.long 0x8 2. "PHSEN4,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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bitfld.long 0x8 1. "PHSEN2,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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newline
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bitfld.long 0x8 0. "PHSEN0,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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wgroup.long 0xC++0x3
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line.long 0x0 "EPWM_SWSYNC,EPWM Software Control Synchronization Register"
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bitfld.long 0x0 2. "SWSYNC4,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
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bitfld.long 0x0 1. "SWSYNC2,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
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newline
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bitfld.long 0x0 0. "SWSYNC0,Software SYNC Function (Write Only)\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit." "0,1"
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group.long 0x10++0x3
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line.long 0x0 "EPWM_CLKSRC,EPWM Clock Source Register"
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bitfld.long 0x0 16.--18. "ECLKSRC4,EPWM_CH45 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "ECLKSRC2,EPWM_CH23 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 0.--2. "ECLKSRC0,EPWM_CH01 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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group.long 0x20++0xB
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line.long 0x0 "EPWM_CNTEN,EPWM Counter Enable Register"
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bitfld.long 0x0 5. "CNTEN5,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x0 4. "CNTEN4,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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newline
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bitfld.long 0x0 3. "CNTEN3,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x0 2. "CNTEN2,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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newline
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bitfld.long 0x0 1. "CNTEN1,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x0 0. "CNTEN0,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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line.long 0x4 "EPWM_CNTCLR,EPWM Clear Counter Register"
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bitfld.long 0x4 5. "CNTCLR5,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x4 4. "CNTCLR4,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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newline
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bitfld.long 0x4 3. "CNTCLR3,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x4 2. "CNTCLR2,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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newline
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bitfld.long 0x4 1. "CNTCLR1,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x4 0. "CNTCLR0,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n." "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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line.long 0x8 "EPWM_LOAD,EPWM Load Register"
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bitfld.long 0x8 5. "LOAD5,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x8 4. "LOAD4,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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newline
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bitfld.long 0x8 3. "LOAD3,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x8 2. "LOAD2,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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newline
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bitfld.long 0x8 1. "LOAD1,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x8 0. "LOAD0,Re-load EPWM Comparator Register Control Bit" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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group.long 0x30++0x17
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line.long 0x0 "EPWM_PERIOD0,EPWM Period Register 0"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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line.long 0x4 "EPWM_PERIOD1,EPWM Period Register 1"
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hexmask.long.word 0x4 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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line.long 0x8 "EPWM_PERIOD2,EPWM Period Register 2"
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hexmask.long.word 0x8 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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line.long 0xC "EPWM_PERIOD3,EPWM Period Register 3"
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hexmask.long.word 0xC 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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line.long 0x10 "EPWM_PERIOD4,EPWM Period Register 4"
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hexmask.long.word 0x10 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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line.long 0x14 "EPWM_PERIOD5,EPWM Period Register 5"
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hexmask.long.word 0x14 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0."
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group.long 0x50++0x17
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line.long 0x0 "EPWM_CMPDAT0,EPWM Comparator Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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line.long 0x4 "EPWM_CMPDAT1,EPWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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line.long 0x8 "EPWM_CMPDAT2,EPWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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line.long 0xC "EPWM_CMPDAT3,EPWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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line.long 0x10 "EPWM_CMPDAT4,EPWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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line.long 0x14 "EPWM_CMPDAT5,EPWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn complementary mode EPWM_CMPDAT0 EPWM_CMPDAT2 EPWM_CMPDAT4 denote as first compared point and.."
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group.long 0x80++0xB
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line.long 0x0 "EPWM_PHS0_1,EPWM Counter Phase Register 0/1"
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hexmask.long.word 0x0 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
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line.long 0x4 "EPWM_PHS2_3,EPWM Counter Phase Register 2/3"
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hexmask.long.word 0x4 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
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line.long 0x8 "EPWM_PHS4_5,EPWM Counter Phase Register 4/5"
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hexmask.long.word 0x8 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function."
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rgroup.long 0x90++0x17
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line.long 0x0 "EPWM_CNT0,EPWM Counter Register 0"
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bitfld.long 0x0 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x0 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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line.long 0x4 "EPWM_CNT1,EPWM Counter Register 1"
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bitfld.long 0x4 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x4 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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line.long 0x8 "EPWM_CNT2,EPWM Counter Register 2"
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bitfld.long 0x8 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x8 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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line.long 0xC "EPWM_CNT3,EPWM Counter Register 3"
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bitfld.long 0xC 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0xC 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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line.long 0x10 "EPWM_CNT4,EPWM Counter Register 4"
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bitfld.long 0x10 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x10 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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line.long 0x14 "EPWM_CNT5,EPWM Counter Register 5"
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bitfld.long 0x14 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x14 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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group.long 0xB0++0x2B
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line.long 0x0 "EPWM_WGCTL0,EPWM Generation Register 0"
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bitfld.long 0x0 26.--27. "PRDPCTL5,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 24.--25. "PRDPCTL4,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 20.--21. "PRDPCTL2,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 16.--17. "PRDPCTL0,EPWM Period or Center Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type." "0: Do nothing,1: EPWM period (center) point output Low,?,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 8.--9. "ZPCTL4,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 4.--5. "ZPCTL2,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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bitfld.long 0x0 0.--1. "ZPCTL0,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0." "0: Do nothing,1: EPWM zero point output Low,?,?"
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line.long 0x4 "EPWM_WGCTL1,EPWM Generation Register 1"
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bitfld.long 0x4 26.--27. "CMPDCTL5,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 24.--25. "CMPDCTL4,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 20.--21. "CMPDCTL2,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 16.--17. "CMPDCTL0,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare down point output Low,?,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 8.--9. "CMPUCTL4,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 4.--5. "CMPUCTL2,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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bitfld.long 0x4 0.--1. "CMPUCTL0,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: EPWM compare up point output Low,?,?"
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line.long 0x8 "EPWM_MSKEN,EPWM Mask Enable Register"
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bitfld.long 0x8 5. "MSKEN5,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 4. "MSKEN4,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 2. "MSKEN2,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 0. "MSKEN0,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data." "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output MSKDATn.."
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line.long 0xC "EPWM_MSK,EPWM Mask Data Register"
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bitfld.long 0xC 5. "MSKDAT5,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 4. "MSKDAT4,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 3. "MSKDAT3,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 2. "MSKDAT2,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 1. "MSKDAT1,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0xC 0. "MSKDAT0,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled." "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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line.long 0x10 "EPWM_BNF,EPWM Brake Noise Filter Register"
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bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select\nFor EPWM0 setting:" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
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bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select\nFor EPWM0 setting:" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
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bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: brake pin event will be detected if EPWMx_BRAKE1..,1: brake pin event will be detected if EPWMx_BRAKE1.."
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bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 8. "BRK1NFEN,EPWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 1 Disabled,1: Noise filter of EPWM Brake 1 Enabled"
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bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: brake pin event will be detected if EPWMx_BRAKE0..,1: brake pin event will be detected if EPWMx_BRAKE0.."
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bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK0FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "BRK0NFEN,EPWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 0 Disabled,1: Noise filter of EPWM Brake 0 Enabled"
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line.long 0x14 "EPWM_FAILBRK,EPWM System Fail Brake Control Register"
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bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger EPWM Brake Function Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x14 2. "RAMBRKEN,SRAM Parity Error Detection Trigger EPWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger EPWM Brake Function Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger EPWM Brake Function Enable Bit" "0: Brake Function triggered by CSS detection Disabled,1: Brake Function triggered by CSS detection Enabled"
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line.long 0x18 "EPWM_BRKCTL0_1,EPWM Brake Edge Detect Control Register 0/1"
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bitfld.long 0x18 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x18 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x18 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x18 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x18 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x18 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x18 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x18 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x18 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x18 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x18 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x18 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x18 6. "VBSNBKEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x18 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x18 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x18 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x18 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x18 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x1C "EPWM_BRKCTL2_3,EPWM Brake Edge Detect Control Register 2/3"
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bitfld.long 0x1C 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x1C 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x1C 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x1C 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x1C 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x1C 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x1C 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x1C 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x1C 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x1C 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x1C 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x1C 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x1C 6. "VBSNBKEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x1C 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x1C 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x1C 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x20 "EPWM_BRKCTL4_5,EPWM Brake Edge Detect Control Register 4/5"
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bitfld.long 0x20 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x20 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x20 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x20 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x20 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EPWMx brake event will not affect odd channels..,1: EPWM odd channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x20 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx brake event will not affect even channels..,1: EPWM even channel output tri-state when EPWMx..,?,?"
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bitfld.long 0x20 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x20 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x20 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x20 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x20 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x20 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x20 6. "VBSNBKEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x20 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x20 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x20 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x20 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x20 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x24 "EPWM_POLCTL,EPWM Pin Polar Inverse Register"
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bitfld.long 0x24 5. "PINV5,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 4. "PINV4,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 3. "PINV3,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 2. "PINV2,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 1. "PINV1,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x24 0. "PINV0,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin." "0: EPWMx_CHn output pin polar inverse Disabled,1: EPWMx_CHn output pin polar inverse Enabled"
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line.long 0x28 "EPWM_POEN,EPWM Output Enable Register"
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bitfld.long 0x28 5. "POEN5,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 4. "POEN4,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 3. "POEN3,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 2. "POEN2,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 1. "POEN1,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x28 0. "POEN0,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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wgroup.long 0xDC++0x3
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line.long 0x0 "EPWM_SWBRK,EPWM Software Brake Control Register"
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bitfld.long 0x0 10. "BRKLTRG4,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 9. "BRKLTRG2,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 8. "BRKLTRG0,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 2. "BRKETRG4,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 1. "BRKETRG2,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 0. "BRKETRG0,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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group.long 0xE0++0xF
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line.long 0x0 "EPWM_INTEN0,EPWM Interrupt Enable Register 0"
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bitfld.long 0x0 29. "CMPDIEN5,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 28. "CMPDIEN4,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 26. "CMPDIEN2,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 24. "CMPDIEN0,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 20. "CMPUIEN4,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 18. "CMPUIEN2,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 16. "CMPUIEN0,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 13. "PIEN5,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 12. "PIEN4,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 11. "PIEN3,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 10. "PIEN2,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 9. "PIEN1,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 8. "PIEN0,EPWM Period Point Interrupt Enable Bits\nNote 1: When up-down counter type period point means center point.\nNote 2: Odd channels will read always 0 at complementary mode." "0: Period point interrupt Disabled,1: When up-down counter type period point means.."
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bitfld.long 0x0 5. "ZIEN5,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 4. "ZIEN4,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 3. "ZIEN3,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 2. "ZIEN2,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 1. "ZIEN1,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 0. "ZIEN0,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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line.long 0x4 "EPWM_INTEN1,EPWM Interrupt Enable Register 1"
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bitfld.long 0x4 10. "BRKLIEN4_5,EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x4 9. "BRKLIEN2_3,EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x4 8. "BRKLIEN0_1,EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x4 2. "BRKEIEN4_5,EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled"
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bitfld.long 0x4 1. "BRKEIEN2_3,EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled"
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bitfld.long 0x4 0. "BRKEIEN0_1,EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled"
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line.long 0x8 "EPWM_INTSTS0,EPWM Interrupt Flag Register 0"
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bitfld.long 0x8 29. "CMPDIF5,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 28. "CMPDIF4,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 27. "CMPDIF3,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 26. "CMPDIF2,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 25. "CMPDIF1,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 24. "CMPDIF0,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for.." "0,1"
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bitfld.long 0x8 21. "CMPUIF5,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 20. "CMPUIF4,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 19. "CMPUIF3,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 18. "CMPUIF2,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 17. "CMPUIF1,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 16. "CMPUIF0,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel.." "0,1"
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bitfld.long 0x8 13. "PIF5,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 12. "PIF4,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 11. "PIF3,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 10. "PIF2,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 9. "PIF1,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 8. "PIF0,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 5. "ZIF5,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 4. "ZIF4,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 3. "ZIF3,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 2. "ZIF2,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 1. "ZIF1,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x8 0. "ZIF0,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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line.long 0xC "EPWM_INTSTS1,EPWM Interrupt Flag Register 1"
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rbitfld.long 0xC 29. "BRKLSTS5,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 28. "BRKLSTS4,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 27. "BRKLSTS3,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 26. "BRKLSTS2,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 25. "BRKLSTS1,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 24. "BRKLSTS0,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 21. "BRKESTS5,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 20. "BRKESTS4,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 19. "BRKESTS3,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 18. "BRKESTS2,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 17. "BRKESTS1,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 16. "BRKESTS0,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: EPWM channel n edge-detect brake state is released,1: When EPWM channel n edge-detect brake detects a.."
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bitfld.long 0xC 13. "BRKLIF5,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 12. "BRKLIF4,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 11. "BRKLIF3,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 10. "BRKLIF2,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 9. "BRKLIF1,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 8. "BRKLIF0,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n level-detect brake event do not..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0xC 5. "BRKEIF5,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 4. "BRKEIF4,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 3. "BRKEIF3,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 2. "BRKEIF2,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 1. "BRKEIF1,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0xC 0. "BRKEIF0,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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group.long 0xF4++0x17
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line.long 0x0 "EPWM_DACTRGEN,EPWM Trigger DAC Enable Register"
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bitfld.long 0x0 29. "CDTRGEN5,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 28. "CDTRGEN4,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 27. "CDTRGEN3,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 26. "CDTRGEN2,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 25. "CDTRGEN1,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 24. "CDTRGEN0,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote 2:.." "0: EPWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 21. "CUTRGEN5,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 20. "CUTRGEN4,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 19. "CUTRGEN3,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 18. "CUTRGEN2,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 17. "CUTRGEN1,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 16. "CUTRGEN0,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote 2: In.." "0: EPWM Compare Up point trigger DAC function..,1: This bit should keep at 0 when EPWM counter.."
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bitfld.long 0x0 13. "PTE5,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 12. "PTE4,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 11. "PTE3,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 10. "PTE2,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 9. "PTE1,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 8. "PTE0,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 5. "ZTE5,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 4. "ZTE4,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 3. "ZTE3,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 2. "ZTE2,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 1. "ZTE1,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x0 0. "ZTE0,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1." "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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line.long 0x4 "EPWM_EADCTS0,EPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x4 31. "TRGEN3,EPWM_CH3 Trigger EADC Enable Bit" "0: EPWM_CH3 Trigger EADC function Disabled,1: EPWM_CH3 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 24.--28. 1. "TRGSEL3,EPWM_CH3 Trigger EADC Source Select"
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bitfld.long 0x4 23. "TRGEN2,EPWM_CH2 Trigger EADC Enable Bit" "0: EPWM_CH2 Trigger EADC function Disabled,1: EPWM_CH2 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 16.--20. 1. "TRGSEL2,EPWM_CH2 Trigger EADC Source Select"
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bitfld.long 0x4 15. "TRGEN1,EPWM_CH1 Trigger EADC Enable Bit" "0: EPWM_CH1 Trigger EADC function Disabled,1: EPWM_CH1 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 8.--12. 1. "TRGSEL1,EPWM_CH1 Trigger EADC Source Select"
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bitfld.long 0x4 7. "TRGEN0,EPWM_CH0 Trigger EADC Enable Bit" "0: EPWM_CH0 Trigger EADC function Disabled,1: EPWM_CH0 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 0.--4. 1. "TRGSEL0,EPWM_CH0 Trigger EADC Source Select"
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line.long 0x8 "EPWM_EADCTS1,EPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x8 15. "TRGEN5,EPWM_CH5 Trigger EADC Enable Bit" "0: EPWM_CH5 Trigger EADC function Disabled,1: EPWM_CH5 Trigger EADC function Enabled"
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hexmask.long.byte 0x8 8.--12. 1. "TRGSEL5,EPWM_CH5 Trigger EADC Source Select"
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bitfld.long 0x8 7. "TRGEN4,EPWM_CH4 Trigger EADC Enable Bit" "0: EPWM_CH4 Trigger EADC function Disabled,1: EPWM_CH4 Trigger EADC function Enabled"
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hexmask.long.byte 0x8 0.--4. 1. "TRGSEL4,EPWM_CH4 Trigger EADC Source Select"
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line.long 0xC "EPWM_FTCMPDAT0_1,EPWM Free Trigger Compare Register 0/1"
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hexmask.long.word 0xC 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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line.long 0x10 "EPWM_FTCMPDAT2_3,EPWM Free Trigger Compare Register 2/3"
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hexmask.long.word 0x10 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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line.long 0x14 "EPWM_FTCMPDAT4_5,EPWM Free Trigger Compare Register 4/5"
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hexmask.long.word 0x14 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x110++0x3
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line.long 0x0 "EPWM_SSCTL,EPWM Synchronous Start Control Register"
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bitfld.long 0x0 8.--9. "SSRC,EPWM Synchronous Start Source Select Bits" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,?,?"
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bitfld.long 0x0 5. "SSEN5,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 4. "SSEN4,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 3. "SSEN3,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 2. "SSEN2,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 1. "SSEN1,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x0 0. "SSEN0,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)." "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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wgroup.long 0x114++0x3
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line.long 0x0 "EPWM_SSTRG,EPWM Synchronous Start Trigger Register"
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bitfld.long 0x0 0. "CNTSEN,EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
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group.long 0x118++0xB
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line.long 0x0 "EPWM_LEBCTL,EPWM Leading Edge Blanking Control Register"
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bitfld.long 0x0 16.--17. "TRGTYPE,EPWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source rising..,1: When detect leading edge blanking source falling..,2: When detect leading edge blanking source rising..,3: Reserved."
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bitfld.long 0x0 10. "SRCEN4,EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH4..,1: EPWM Leading Edge Blanking Source from EPWM_CH4.."
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bitfld.long 0x0 9. "SRCEN2,EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH2..,1: EPWM Leading Edge Blanking Source from EPWM_CH2.."
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bitfld.long 0x0 8. "SRCEN0,EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit" "0: EPWM Leading Edge Blanking Source from EPWM_CH0..,1: EPWM Leading Edge Blanking Source from EPWM_CH0.."
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bitfld.long 0x0 0. "LEBEN,EPWM Leading Edge Blanking Enable Bit" "0: EPWM Leading Edge Blanking Disabled,1: EPWM Leading Edge Blanking Enabled"
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line.long 0x4 "EPWM_LEBCNT,EPWM Leading Edge Blanking Counter Register"
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hexmask.long.word 0x4 0.--8. 1. "LEBCNT,EPWM Leading Edge Blanking Counter"
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line.long 0x8 "EPWM_STATUS,EPWM Status Register"
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bitfld.long 0x8 24. "DACTRGF,DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No DAC start of conversion trigger event has..,1: A DAC start of conversion trigger event has.."
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bitfld.long 0x8 23. "LPADCTRGF,LPADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No LPADC start of conversion trigger event has..,1: A LPADC start of conversion trigger event has.."
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bitfld.long 0x8 21. "EADCTRGF5,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 20. "EADCTRGF4,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 19. "EADCTRGF3,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 18. "EADCTRGF2,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 17. "EADCTRGF1,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 16. "EADCTRGF0,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x8 10. "SYNCINF4,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x8 9. "SYNCINF2,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x8 8. "SYNCINF0,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1." "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x8 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x8 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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group.long 0x130++0x17
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line.long 0x0 "EPWM_IFA0,EPWM Interrupt Flag Accumulator Register 0"
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bitfld.long 0x0 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0x0 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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line.long 0x4 "EPWM_IFA1,EPWM Interrupt Flag Accumulator Register 1"
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bitfld.long 0x4 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x4 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x4 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0x4 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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line.long 0x8 "EPWM_IFA2,EPWM Interrupt Flag Accumulator Register 2"
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bitfld.long 0x8 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x8 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x8 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0x8 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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line.long 0xC "EPWM_IFA3,EPWM Interrupt Flag Accumulator Register 3"
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bitfld.long 0xC 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0xC 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0xC 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0xC 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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line.long 0x10 "EPWM_IFA4,EPWM Interrupt Flag Accumulator Register 4"
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bitfld.long 0x10 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x10 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x10 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0x10 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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line.long 0x14 "EPWM_IFA5,EPWM Interrupt Flag Accumulator Register 5"
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bitfld.long 0x14 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x14 28.--29. "IFASEL,EPWM_CHn Interrupt Flag Accumulator Source Select" "0: EPWM_CHn zero point,1: EPWM_CHn period in channel n,?,?"
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bitfld.long 0x14 24. "STPMOD,EPWM_CHn Accumulator Stop Mode Enable Bits" "0: EPWM_CHn Stop Mode Disable,1: EPWM_CHn Stop Mode Enable"
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hexmask.long.word 0x14 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period."
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group.long 0x150++0xB
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line.long 0x0 "EPWM_AINTSTS,EPWM Accumulator Interrupt Flag Register"
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bitfld.long 0x0 5. "IFAIF5,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 4. "IFAIF4,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 3. "IFAIF3,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 2. "IFAIF2,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 1. "IFAIF1,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 0. "IFAIF0,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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line.long 0x4 "EPWM_AINTEN,EPWM Accumulator Interrupt Enable Register"
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bitfld.long 0x4 5. "IFAIEN5,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 4. "IFAIEN4,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 3. "IFAIEN3,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 2. "IFAIEN2,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 1. "IFAIEN1,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 0. "IFAIEN0,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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line.long 0x8 "EPWM_APDMACTL,EPWM Accumulator PDMA Control Register"
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bitfld.long 0x8 5. "APDMAEN5,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 4. "APDMAEN4,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 3. "APDMAEN3,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 2. "APDMAEN2,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 1. "APDMAEN1,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 0. "APDMAEN0,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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group.long 0x160++0x37
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line.long 0x0 "EPWM_FDEN,EPWM Fault Detect Enable Register"
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bitfld.long 0x0 21. "FDCKS5,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 20. "FDCKS4,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 19. "FDCKS3,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 18. "FDCKS2,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 17. "FDCKS1,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 16. "FDCKS0,EPWM Channel n Fault Detect Clock Source Select Bit" "0: EPWMx_CLK x denotes 0 or 1,1: EPWMx_CLK divide by prescaler x denotes 0 or 1"
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bitfld.long 0x0 13. "FDODIS5,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 12. "FDODIS4,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 11. "FDODIS3,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 10. "FDODIS2,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 9. "FDODIS1,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 8. "FDODIS0,EPWM Channel n Output Fault Detect Disable Bit" "0: EPWM detect fault and output Enable,1: EPWM detect fault and output Disable"
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bitfld.long 0x0 5. "FDEN5,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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bitfld.long 0x0 4. "FDEN4,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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bitfld.long 0x0 3. "FDEN3,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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bitfld.long 0x0 2. "FDEN2,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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bitfld.long 0x0 1. "FDEN1,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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bitfld.long 0x0 0. "FDEN0,EPWM Fault Detect Function Enable Bit" "0: Fault detect function Disable,1: Fault detect function Enable"
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line.long 0x4 "EPWM_FDCTL0,EPWM Fault Detect Control Register 0"
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bitfld.long 0x4 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0x4 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x4 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0x4 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0x4 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0x8 "EPWM_FDCTL1,EPWM Fault Detect Control Register 1"
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bitfld.long 0x8 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0x8 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x8 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0x8 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0x8 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0xC "EPWM_FDCTL2,EPWM Fault Detect Control Register 2"
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bitfld.long 0xC 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0xC 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0xC 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0xC 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0xC 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0x10 "EPWM_FDCTL3,EPWM Fault Detect Control Register 3"
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bitfld.long 0x10 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0x10 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x10 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0x10 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0x10 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0x14 "EPWM_FDCTL4,EPWM Fault Detect Control Register 4"
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bitfld.long 0x14 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0x14 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x14 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0x14 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0x14 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0x18 "EPWM_FDCTL5,EPWM Fault Detect Control Register 5"
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bitfld.long 0x18 31. "FDDGEN,Fault Detect Deglitch Enable Bit" "0: Fault detect deglitch function Disable,1: Fault detect deglitch function Enable"
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bitfld.long 0x18 28.--29. "FDCKSEL,EPWM Channel Fault Detect Clock Select" "0: FLT_CLK/1,1: FLT_CLK/2,?,?"
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bitfld.long 0x18 16.--18. "DGSMPCYC,Deglitch Sampling Cycle\nFDCKS is set to 0: \nSampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times\nFDCKS is set to 1: \nSampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1.." "0: \nSampling detect signal each EPWMx_CLK *,1: \nSampling detect signal each EPWMx_CLK * CLKPSC *,?,?,?,?,?,?"
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bitfld.long 0x18 15. "FDMSKEN,Fault Detect Mask Enable Bit" "0: Fault detect mask function Disable,1: Fault detect mask function Enable"
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hexmask.long.byte 0x18 0.--6. 1. "TRMSKCNT,Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) *.."
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line.long 0x1C "EPWM_FDIEN,EPWM Fault Detect Interrupt Enable Register"
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bitfld.long 0x1C 5. "FDIEN5,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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bitfld.long 0x1C 4. "FDIEN4,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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bitfld.long 0x1C 3. "FDIEN3,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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bitfld.long 0x1C 2. "FDIEN2,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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bitfld.long 0x1C 1. "FDIEN1,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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bitfld.long 0x1C 0. "FDIEN0,EPWM Channel n Fault Detect Interrupt Enable Bit" "0: EPWM Channel n Fault Detect Interrupt Disable,1: EPWM Channel n Fault Detect Interrupt Enable"
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line.long 0x20 "EPWM_FDSTS,EPWM Fault Detect Interrupt Flag Register"
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hexmask.long.byte 0x20 0.--5. 1. "FDIFn,EPWM Channel n Fault Detect Interrupt Flag Bit\nFault Detect Interrupt Flag will be set when detect EPWM output short condition. Software can clear this bit by writing 1 to it."
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line.long 0x24 "EPWM_EADCPSCCTL,EPWM Trigger EADC Prescale Control Register"
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bitfld.long 0x24 5. "PSCEN5,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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bitfld.long 0x24 4. "PSCEN4,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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bitfld.long 0x24 3. "PSCEN3,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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bitfld.long 0x24 2. "PSCEN2,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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bitfld.long 0x24 1. "PSCEN1,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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bitfld.long 0x24 0. "PSCEN0,EPWM Trigger EADC Pre-scale Function Enable Bits" "0: EPWM Trigger EADC Pre-scale Function Disable,1: EPWM Trigger EADC Pre-scale Function Enable"
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line.long 0x28 "EPWM_EADCPSC0,EPWM Trigger EADC Prescale Register 0"
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hexmask.long.byte 0x28 24.--27. 1. "EADCPSC3,EPWM Channel 3 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC3+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3."
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hexmask.long.byte 0x28 16.--19. 1. "EADCPSC2,EPWM Channel 2 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC2+1) times of EPWM_CH2 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF2."
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hexmask.long.byte 0x28 8.--11. 1. "EADCPSC1,EPWM Channel 1 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC1+1) times of EPWM_CH1 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF1."
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hexmask.long.byte 0x28 0.--3. 1. "EADCPSC0,EPWM Channel 0 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC0+1) times of EPWM_CH0 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF0."
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line.long 0x2C "EPWM_EADCPSC1,EPWM Trigger EADC Prescale Register 1"
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hexmask.long.byte 0x2C 8.--11. 1. "EADCPSC5,EPWM Channel 5 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC5+1) times of EPWM_CH5 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF5."
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hexmask.long.byte 0x2C 0.--3. 1. "EADCPSC4,EPWM Channel 4 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC4+1) times of EPWM_CH4 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF4."
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line.long 0x30 "EPWM_EADCPSCNT0,EPWM Trigger EADC Prescale Counter Register 0"
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hexmask.long.byte 0x30 24.--27. 1. "PSCNT3,EPWM Trigger EADC Prescale Counter 3\nUser can monitor PSCNT3 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN3 is 0.\nNote 2: Write data limitation: PSCNT3 EADCPSC3."
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hexmask.long.byte 0x30 16.--19. 1. "PSCNT2,EPWM Trigger EADC Prescale Counter 2\nUser can monitor PSCNT2 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN2 is 0.\nNote 2: Write data limitation: PSCNT2 EADCPSC2."
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hexmask.long.byte 0x30 8.--11. 1. "PSCNT1,EPWM Trigger EADC Prescale Counter 1\nUser can monitor PSCNT1 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN1 is 0.\nNote 2: Write data limitation: PSCNT1 EADCPSC1."
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hexmask.long.byte 0x30 0.--3. 1. "PSCNT0,EPWM Trigger EADC Prescale Counter 0\nUser can monitor PSCNT0 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN0 is 0.\nNote 2: Write data limitation: PSCNT0 EADCPSC0."
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line.long 0x34 "EPWM_EADCPSCNT1,EPWM Trigger EADC Prescale Counter Register 1"
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hexmask.long.byte 0x34 8.--11. 1. "PSCNT5,EPWM Trigger EADC Prescale Counter 5\nUser can monitor PSCNT5 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN5 is 0.\nNote 2: Write data limitation: PSCNT5 EADCPSC5."
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hexmask.long.byte 0x34 0.--3. 1. "PSCNT4,EPWM Trigger EADC Prescale Counter 4\nUser can monitor PSCNT4 to know the current value in 4-bit trigger EADC prescale counter.\nNote 1: user can write only when PSCEN4 is 0.\nNote 2: Write data limitation: PSCNT4 EADCPSC4."
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group.long 0x200++0x7
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line.long 0x0 "EPWM_CAPINEN,EPWM Capture Input Enable Register"
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bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled. The..,1: EPWM Channel capture input path Enabled. The.."
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line.long 0x4 "EPWM_CAPCTL,EPWM Capture Control Register"
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bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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rgroup.long 0x208++0x33
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line.long 0x0 "EPWM_CAPSTS,EPWM Capture Status Register"
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bitfld.long 0x0 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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bitfld.long 0x0 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding.." "0,1"
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line.long 0x4 "EPWM_RCAPDAT0,EPWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x8 "EPWM_FCAPDAT0,EPWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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line.long 0xC "EPWM_RCAPDAT1,EPWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x10 "EPWM_FCAPDAT1,EPWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x14 "EPWM_RCAPDAT2,EPWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x18 "EPWM_FCAPDAT2,EPWM Falling Capture Data Register 2"
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hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x1C "EPWM_RCAPDAT3,EPWM Rising Capture Data Register 3"
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hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x20 "EPWM_FCAPDAT3,EPWM Falling Capture Data Register 3"
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hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x24 "EPWM_RCAPDAT4,EPWM Rising Capture Data Register 4"
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hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x28 "EPWM_FCAPDAT4,EPWM Falling Capture Data Register 4"
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hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x2C "EPWM_RCAPDAT5,EPWM Rising Capture Data Register 5"
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hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register."
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line.long 0x30 "EPWM_FCAPDAT5,EPWM Falling Capture Data Register 5"
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hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register."
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group.long 0x23C++0x3
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line.long 0x0 "EPWM_PDMACTL,EPWM PDMA Control Register"
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bitfld.long 0x0 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
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bitfld.long 0x0 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order" "0: EPWM_FCAPDAT4/5 is the first captured data to..,1: EPWM_RCAPDAT4/5 is the first captured data to.."
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newline
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bitfld.long 0x0 17.--18. "CAPMOD4_5,Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT4/5,?,?"
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bitfld.long 0x0 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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newline
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bitfld.long 0x0 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
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bitfld.long 0x0 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order" "0: EPWM_FCAPDAT2/3 is the first captured data to..,1: EPWM_RCAPDAT2/3 is the first captured data to.."
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newline
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bitfld.long 0x0 9.--10. "CAPMOD2_3,Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT2/3,?,?"
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bitfld.long 0x0 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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newline
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bitfld.long 0x0 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
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bitfld.long 0x0 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order" "0: EPWM_FCAPDAT0/1 is the first captured data to..,1: EPWM_RCAPDAT0/1 is the first captured data to.."
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newline
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bitfld.long 0x0 1.--2. "CAPMOD0_1,Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved.,1: EPWM_RCAPDAT0/1,?,?"
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bitfld.long 0x0 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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rgroup.long 0x240++0xB
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line.long 0x0 "EPWM_PDMACAP0_1,EPWM Capture Channel 01 PDMA Register"
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hexmask.long.word 0x0 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
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line.long 0x4 "EPWM_PDMACAP2_3,EPWM Capture Channel 23 PDMA Register"
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hexmask.long.word 0x4 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
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line.long 0x8 "EPWM_PDMACAP4_5,EPWM Capture Channel 45 PDMA Register"
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hexmask.long.word 0x8 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA."
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group.long 0x250++0x73
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line.long 0x0 "EPWM_CAPIEN,EPWM Capture Interrupt Enable Register"
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bitfld.long 0x0 13. "CAPFIEN5,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 12. "CAPFIEN4,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 11. "CAPFIEN3,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 10. "CAPFIEN2,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 9. "CAPFIEN1,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 8. "CAPFIEN0,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 5. "CAPRIEN5,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 4. "CAPRIEN4,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 3. "CAPRIEN3,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 2. "CAPRIEN2,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 1. "CAPRIEN1,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 0. "CAPRIEN0,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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line.long 0x4 "EPWM_CAPIF,EPWM Capture Interrupt Flag Register"
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bitfld.long 0x4 13. "CFLIF5,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 12. "CFLIF4,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 11. "CFLIF3,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 10. "CFLIF2,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 9. "CFLIF1,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 8. "CFLIF0,EPWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 5. "CRLIF5,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 4. "CRLIF4,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 3. "CRLIF3,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 2. "CRLIF2,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 1. "CRLIF1,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 0. "CRLIF0,EPWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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line.long 0x8 "EPWM_CAPNF0,EPWM Capture Input Noise Filter Register 0"
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bitfld.long 0x8 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x8 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0xC "EPWM_CAPNF1,EPWM Capture Input Noise Filter Register 1"
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bitfld.long 0xC 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0xC 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x10 "EPWM_CAPNF2,EPWM Capture Input Noise Filter Register 2"
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bitfld.long 0x10 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x10 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x14 "EPWM_CAPNF3,EPWM Capture Input Noise Filter Register 3"
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bitfld.long 0x14 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x14 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x18 "EPWM_CAPNF4,EPWM Capture Input Noise Filter Register 4"
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bitfld.long 0x18 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x18 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x1C "EPWM_CAPNF5,EPWM Capture Input Noise Filter Register 5"
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bitfld.long 0x1C 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x1C 0. "CAPNFEN,Capture Noise Filter Enable Bits" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x20 "EPWM_EXTETCTL0,EPWM External Event Trigger Control Register 0"
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hexmask.long.byte 0x20 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x20 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x20 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x24 "EPWM_EXTETCTL1,EPWM External Event Trigger Control Register 1"
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hexmask.long.byte 0x24 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x24 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x24 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x28 "EPWM_EXTETCTL2,EPWM External Event Trigger Control Register 2"
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hexmask.long.byte 0x28 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x28 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x28 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x2C "EPWM_EXTETCTL3,EPWM External Event Trigger Control Register 3"
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hexmask.long.byte 0x2C 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x2C 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x2C 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x30 "EPWM_EXTETCTL4,EPWM External Event Trigger Control Register 4"
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hexmask.long.byte 0x30 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x30 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x30 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x34 "EPWM_EXTETCTL5,EPWM External Event Trigger Control Register 5"
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hexmask.long.byte 0x34 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x34 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x34 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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line.long 0x38 "EPWM_SWEOFCTL,EPWM Software Event Output Force Control Register"
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bitfld.long 0x38 10.--11. "OUTACTS5,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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bitfld.long 0x38 8.--9. "OUTACTS4,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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newline
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bitfld.long 0x38 6.--7. "OUTACTS3,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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bitfld.long 0x38 4.--5. "OUTACTS2,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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newline
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bitfld.long 0x38 2.--3. "OUTACTS1,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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bitfld.long 0x38 0.--1. "OUTACTS0,Output Action Selection" "0: Do nothing,1: EPWM output Low,?,?"
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line.long 0x3C "EPWM_SWEOFTRG,EPWM Software Event Output Force Trigger Register"
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bitfld.long 0x3C 5. "SWETRG5,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x3C 4. "SWETRG4,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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newline
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bitfld.long 0x3C 3. "SWETRG3,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x3C 2. "SWETRG2,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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newline
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bitfld.long 0x3C 1. "SWETRG1,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x3C 0. "SWETRG0,Software Event Trigger\nWrite 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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line.long 0x40 "EPWM_CLKPSC0,EPWM Clock Prescale Register 0"
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hexmask.long.word 0x40 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x44 "EPWM_CLKPSC1,EPWM Clock Prescale Register 1"
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hexmask.long.word 0x44 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x48 "EPWM_CLKPSC2,EPWM Clock Prescale Register 2"
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hexmask.long.word 0x48 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x4C "EPWM_CLKPSC3,EPWM Clock Prescale Register 3"
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hexmask.long.word 0x4C 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x50 "EPWM_CLKPSC4,EPWM Clock Prescale Register 4"
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hexmask.long.word 0x50 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x54 "EPWM_CLKPSC5,EPWM Clock Prescale Register 5"
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hexmask.long.word 0x54 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale\nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1)."
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line.long 0x58 "EPWM_RDTCNT0_1,EPWM Rising Dead-time Counter Register 0/1"
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hexmask.long.word 0x58 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x5C "EPWM_RDTCNT2_3,EPWM Rising Dead-time Counter Register 2/3"
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hexmask.long.word 0x5C 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x60 "EPWM_RDTCNT4_5,EPWM Rising Dead-time Counter Register 4/5"
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hexmask.long.word 0x60 0.--11. 1. "RDTCNT,Rising Dead-time Counter (Write Protect)\nThe Rising dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x64 "EPWM_FDTCNT0_1,EPWM Falling Dead-time Counter Register 0/1"
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hexmask.long.word 0x64 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x68 "EPWM_FDTCNT2_3,EPWM Falling Dead-time Counter Register 2/3"
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hexmask.long.word 0x68 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x6C "EPWM_FDTCNT4_5,EPWM Falling Dead-time Counter Register 4/5"
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hexmask.long.word 0x6C 0.--11. 1. "FDTCNT,Falling Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x70 "EPWM_DTCTL,EPWM Dead-time Control Register"
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bitfld.long 0x70 16. "DTCKSELn,Dead-time Clock Select for EPWM Pair (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x70 10. "FDTEN4,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
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newline
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bitfld.long 0x70 9. "FDTEN2,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
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bitfld.long 0x70 8. "FDTEN0,Enable Falling Dead-time Insertion for EPWM Pair (Write Protect)\nFalling Dead-time insertion is only active when this pair of complementary EPWM is enabled. If falling dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Falling Dead-time insertion Disabled on the pin..,1: Falling Dead-time insertion Enabled on the pin.."
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bitfld.long 0x70 2. "RDTEN4,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
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bitfld.long 0x70 1. "RDTEN2,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
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bitfld.long 0x70 0. "RDTEN0,Enable Rising Dead-time Insertion for EPWM Pair (Write Protect)\nRising Dead-time insertion is only active when this pair of complementary EPWM is enabled. If rising dead- time insertion is inactive the outputs of pin pair are complementary.." "0: Rising Dead-time insertion Disabled on the pin..,1: Rising Dead-time insertion Enabled on the pin pair"
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rgroup.long 0x304++0x2F
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line.long 0x0 "EPWM_PBUF0,EPWM PERIOD0 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0x4 "EPWM_PBUF1,EPWM PERIOD1 Buffer"
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hexmask.long.word 0x4 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0x8 "EPWM_PBUF2,EPWM PERIOD2 Buffer"
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hexmask.long.word 0x8 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0xC "EPWM_PBUF3,EPWM PERIOD3 Buffer"
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hexmask.long.word 0xC 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0x10 "EPWM_PBUF4,EPWM PERIOD4 Buffer"
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hexmask.long.word 0x10 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0x14 "EPWM_PBUF5,EPWM PERIOD5 Buffer"
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hexmask.long.word 0x14 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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line.long 0x18 "EPWM_CMPBUF0,EPWM CMPDAT0 Buffer"
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hexmask.long.word 0x18 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x1C "EPWM_CMPBUF1,EPWM CMPDAT1 Buffer"
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hexmask.long.word 0x1C 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x20 "EPWM_CMPBUF2,EPWM CMPDAT2 Buffer"
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hexmask.long.word 0x20 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x24 "EPWM_CMPBUF3,EPWM CMPDAT3 Buffer"
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hexmask.long.word 0x24 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x28 "EPWM_CMPBUF4,EPWM CMPDAT4 Buffer"
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hexmask.long.word 0x28 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x2C "EPWM_CMPBUF5,EPWM CMPDAT5 Buffer"
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hexmask.long.word 0x2C 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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rgroup.long 0x340++0xB
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line.long 0x0 "EPWM_FTCBUF0_1,EPWM FTCMPDAT0_1 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
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line.long 0x4 "EPWM_FTCBUF2_3,EPWM FTCMPDAT2_3 Buffer"
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hexmask.long.word 0x4 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
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line.long 0x8 "EPWM_FTCBUF4_5,EPWM FTCMPDAT4_5 Buffer"
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hexmask.long.word 0x8 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer."
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group.long 0x34C++0x3
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line.long 0x0 "EPWM_FTCI,EPWM FTCMPDAT Indicator Register"
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bitfld.long 0x0 10. "FTCMD4,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 9. "FTCMD2,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 8. "FTCMD0,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 2. "FTCMU4,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 1. "FTCMU2,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 0. "FTCMU0,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it." "0,1"
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rgroup.long 0x350++0x2F
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line.long 0x0 "EPWM_CPSCBUF0,EPWM CLKPSC0 Buffer"
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hexmask.long.word 0x0 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0x4 "EPWM_CPSCBUF1,EPWM CLKPSC1 Buffer"
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hexmask.long.word 0x4 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0x8 "EPWM_CPSCBUF2,EPWM CLKPSC2 Buffer"
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hexmask.long.word 0x8 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0xC "EPWM_CPSCBUF3,EPWM CLKPSC3 Buffer"
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hexmask.long.word 0xC 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0x10 "EPWM_CPSCBUF4,EPWM CLKPSC4 Buffer"
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hexmask.long.word 0x10 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0x14 "EPWM_CPSCBUF5,EPWM CLKPSC5 Buffer"
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hexmask.long.word 0x14 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register."
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line.long 0x18 "EPWM_IFACNT0,EPWM Interrupt Flag Accumulator Counter 0"
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hexmask.long.word 0x18 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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line.long 0x1C "EPWM_IFACNT1,EPWM Interrupt Flag Accumulator Counter 1"
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hexmask.long.word 0x1C 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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line.long 0x20 "EPWM_IFACNT2,EPWM Interrupt Flag Accumulator Counter 2"
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hexmask.long.word 0x20 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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line.long 0x24 "EPWM_IFACNT3,EPWM Interrupt Flag Accumulator Counter 3"
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hexmask.long.word 0x24 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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line.long 0x28 "EPWM_IFACNT4,EPWM Interrupt Flag Accumulator Counter 4"
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hexmask.long.word 0x28 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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line.long 0x2C "EPWM_IFACNT5,EPWM Interrupt Flag Accumulator Counter 5"
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hexmask.long.word 0x2C 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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tree.end
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tree.end
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tree "EQEI (Enhanced Quadrature Encoder Interface)"
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base ad:0x0
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tree "EQEI0"
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base ad:0x400B0000
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group.long 0x0++0xF
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line.long 0x0 "EQEI_CNT,EQEI Counter Register"
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hexmask.long 0x0 0.--31. 1. "CNT,Enhanced Quadrature Encoder Interface Counter \nA 32-bit up/down counter. When an effective phase pulse is detected this counter is increased by one if the bit DIRF (EQEI_STATUS[8]) is one or decreased by one if the bit DIRF(EQEI_STATUS[8]) is 0."
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line.long 0x4 "EQEI_CNTHOLD,EQEI Counter Hold Register"
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hexmask.long 0x4 0.--31. 1. "CNTHOLD,Enhanced Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (EQEI_CTL[24]) goes from low to high the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD (EQEI_CNTHOLD[31:0]) register."
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line.long 0x8 "EQEI_CNTLATCH,EQEI Counter Index Latch Register"
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hexmask.long 0x8 0.--31. 1. "CNTLATCH,Enhanced Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (EQEI_STATUS[0]) bit is set the CNT(EQEI_CNT[31:0]) is copied into CNTLATCH (EQEI_CNTLATCH[31:0]) register."
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line.long 0xC "EQEI_CNTCMP,EQEI Counter Compare Register"
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hexmask.long 0xC 0.--31. 1. "CNTCMP,Enhanced Quadrature Encoder Interface Counter Compare"
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group.long 0x14++0x13
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line.long 0x0 "EQEI_CNTMAX,EQEI Pre-set Maximum Count Register"
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hexmask.long 0x0 0.--31. 1. "CNTMAX,Enhanced Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the EQEI counter for the EQEI controller compare-counting mode."
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line.long 0x4 "EQEI_CTL,EQEI Controller Control Register"
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bitfld.long 0x4 29. "EQEIEN,Enhanced Quadrature Encoder Interface Controller Enable Bit" "0: EQEI controller function Disabled,1: EQEI controller function Enabled"
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bitfld.long 0x4 28. "CMPEN,The Compare Function Enable Bit\nThe compare function in EQEI controller is to compare the dynamic counting EQEI_CNT with the compare register CNTCMP( EQEI_CNTCMP[31:0]) if CNT(EQEI_CNT[31:0]) reaches CNTCMP( EQEI_CNTCMP[31:0]) the flag CMPF will.." "0: Compare function Disabled,1: Compare function Enabled"
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bitfld.long 0x4 27. "IDXRLDEN,Index Trigger EQEI_CNT Reload Enable Bit" "0: Reload function Disabled,1: EQEI_CNT re-initialized by Index signal Enabled"
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bitfld.long 0x4 25. "IDXLATEN,Index Latch EQEI_CNT Enable Bit\nIf this bit is set to high the CNT(EQEI_CNT[31:0]) content will be latched into CNTLATCH (EQEI_CNTLATCH[31:0]) at every rising on signal CHX." "0: The index signal latch EQEI counter function..,1: The index signal latch EQEI counter function.."
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bitfld.long 0x4 24. "HOLDCNT,Hold EQEI_CNT Control\nWhen this bit is set from low to high the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD(EQEI_CNTHOLD[31:0]). This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). \nNote: This bit is.." "0: No operation,1: EQEI_CNT content is captured and stored in.."
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bitfld.long 0x4 23. "HOLDTMR3,Hold EQEI_CNT by Timer 3" "0: TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER3_INTSTS[0]) in.."
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newline
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bitfld.long 0x4 22. "HOLDTMR2,Hold EQEI_CNT by Timer 2" "0: TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER2_INTSTS[0]) in.."
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bitfld.long 0x4 21. "HOLDTMR1,Hold EQEI_CNT by Timer 1" "0: TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF (TIMER1_INTSTS[0]) in.."
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newline
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bitfld.long 0x4 20. "HOLDTMR0,Hold EQEI_CNT by Timer 0" "0: TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER0_INTSTS[0]) in.."
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bitfld.long 0x4 19. "IDXIEN,IDXF Trigger EQEI Interrupt Enable Bit" "0: The IDXF can trigger EQEI interrupt Disabled,1: The IDXF can trigger EQEI interrupt Enabled"
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newline
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bitfld.long 0x4 18. "CMPIEN,CMPF Trigger EQEI Interrupt Enable Bit" "0: CMPF can trigger EQEI controller interrupt..,1: CMPF can trigger EQEI controller interrupt Enabled"
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bitfld.long 0x4 17. "DIRIEN,DIRCHGF Trigger EQEI Interrupt Enable Bit" "0: DIRCHGF can trigger EQEI controller interrupt..,1: DIRCHGF can trigger EQEI controller interrupt.."
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newline
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bitfld.long 0x4 16. "OVUNIEN,OVUNF Trigger EQEI Interrupt Enable Bit" "0: OVUNF can trigger EQEI controller interrupt..,1: OVUNF can trigger EQEI controller interrupt.."
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bitfld.long 0x4 15. "IDXRSTEV,IDX Signal Resets Enable Bit in First IDX Reset Event (Write Only)" "0: The next IDX level high signal reset function..,1: The next IDX level high signal reset function.."
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newline
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bitfld.long 0x4 14. "IDXINV,Inverse IDX Input Polarity" "0: Not inverse IDX input polarity,1: IDX input polarity is inversed to EQEI controller"
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bitfld.long 0x4 13. "CHBINV,Inverse QEB Input Polarity" "0: Not inverse QEB input polarity,1: QEB input polarity is inversed to EQEI controller"
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newline
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bitfld.long 0x4 12. "CHAINV,Inverse QEA Input Polarity" "0: Not inverse QEA input polarity,1: QEA input polarity is inversed to EQEI controller"
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bitfld.long 0x4 8.--10. "MODE,EQEI Counting Mode Selection\nThere are seven quadrature encoder pulse counter operation modes.\nNote: User needs to set DIRSRC(EQEI_CTL2[5:4]) when MODE(EQEI_CTL[10:8]) selects to directional counting mode." "0: X4 Free-counting Mode,1: X2 Free-counting Mode,?,?,?,?,?,?"
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newline
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bitfld.long 0x4 7. "IDXRSTEN,IDX Reset EQEI Position Counter Enable Bit\nNote: IDXRLDEN(EQEI_CTL[27]) should be set 1." "0: Reset EQEI position counter in every time IDX..,1: Reset EQEI position counter in first time IDX.."
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bitfld.long 0x4 6. "IDXEN,IDX Input to EQEI Controller Enable Bit" "0: IDX input to EQEI Controller Disabled,1: IDX input to EQEI Controller Enabled"
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bitfld.long 0x4 5. "CHBEN,QEB Input to EQEI Controller Enable Bit" "0: QEB input to EQEI Controller Disabled,1: QEB input to EQEI Controller Enabled"
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bitfld.long 0x4 4. "CHAEN,QEA Input to EQEI Controller Enable Bit" "0: QEA input to EQEI Controller Disabled,1: QEA input to EQEI Controller Enabled"
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newline
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bitfld.long 0x4 3. "NFDIS,EQEI Controller Input Noise Filter Disable Bit" "0: The noise filter of EQEI controller Enabled,1: The noise filter of EQEI controller Disabled"
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bitfld.long 0x4 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock." "0: EQEI_CLK,1: EQEI_CLK/2,?,?,?,?,?,?"
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line.long 0x8 "EQEI_CTL2,EQEI Controller Control Register2"
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bitfld.long 0x8 17. "UTIEIEN,UTIEF Trigger EQEI Interrupt Enable Bit" "0: UTIEF can trigger EQEI controller interrupt..,1: UTIEF can trigger EQEI controller interrupt.."
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bitfld.long 0x8 16. "PHEIEN,PHEF Trigger EQEI Interrupt Enable Bit" "0: PHEF can trigger EQEI controller interrupt..,1: PHEF can trigger EQEI controller interrupt Enabled"
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newline
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bitfld.long 0x8 11. "IDXRSTUTS,IDX Resets Unit Timer Select Bit" "0: Unit timer will not be reset when IDX reset..,1: Resets unit timer or not will follow EQEI_CNT.."
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bitfld.long 0x8 10. "UTEVTRST,Enable Bit to Reset EQEI Position Counter by Unit Timer Event" "0: Reset EQEI position counter feature when unit..,1: Reset EQEI position counter feature when unit.."
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newline
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bitfld.long 0x8 9. "UTHOLDEN,Unit Timer Counter Hold Enable Bit" "0: No operation,1: EQEI_CNT content is captured and stored in.."
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bitfld.long 0x8 8. "UTEN,Unit Timer Function Enable Bit" "0: EQEI unit timer function Disabled,1: EQEI unit timer function Enabled"
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newline
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bitfld.long 0x8 4.--5. "DIRSRC,Direction Signal Source Select" "0: Direction signal is determined from EQEI system..,1: Reserved.,?,?"
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bitfld.long 0x8 1.--2. "CRS,Clock Rate Setting without Quadrature Mode" "0: EQEI counter only counts the falling edge,1: EQEI counter only counts the rising edge,?,?"
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newline
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bitfld.long 0x8 0. "SWAPEN,Swap Function Enable Bit" "0: EQEI swap function Disabled,1: EQEI swap function Enabled"
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line.long 0xC "EQEI_UTCNT,EQEI Unit Timer Counter Register"
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hexmask.long 0xC 0.--31. 1. "UTCNT,Unit Timer Counter \nA 32-bit unit timer counter which may be reset to an initial value when any of the following events occur:"
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line.long 0x10 "EQEI_UTCMP,EQEI Unit Timer Compare Register"
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hexmask.long 0x10 0.--31. 1. "UTCMP,Unit Timer Counter Compare"
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group.long 0x2C++0x3
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line.long 0x0 "EQEI_STATUS,EQEI Controller Status Register"
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bitfld.long 0x0 17. "UTIEF,EQEI Unit Timer Event Flag\nNote: This bit is only cleared by writing 1 to it." "0: No timer event occurs in EQEI unit timer counter,1: Unit timer event occurs in EQEI unit timer counter"
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bitfld.long 0x0 16. "PHEF,EQEI Phase Error Flag\nNote: This bit is only cleared by writing 1 to it." "0: No Phase error occurs in EQEI CHA and CHB,1: Phase error occurs in EQEI CHA and CHB"
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newline
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rbitfld.long 0x0 9. "FIDXEF,First IDX Signal Reset Event Flag (Read Only)" "0: The first IDX reset event has not happened yet,1: The first IDX reset event has happened"
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bitfld.long 0x0 8. "DIRF,EQEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB." "0: EQEI Counter is in down-counting,1: EQEI Counter is in up-counting"
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newline
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bitfld.long 0x0 3. "DIRCHGF,Direction Change Flag\nFlag is set by hardware while EQEI counter counting direction is changed. Software can clear this bit by writing 1 to it.\nNote: This bit is only cleared by writing 1 to it." "0: No change in EQEI counter counting direction,1: EQEI counter counting direction is changed"
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bitfld.long 0x0 2. "OVUNF,EQEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(EQEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (EQEI_CNTMAX[31:0]) to 0 in compare-counting mode. Similarly the flag is set while.." "0: No overflow or underflow occurs in EQEI counter,1: EQEI counter occurs counting overflow or underflow"
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newline
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bitfld.long 0x0 1. "CMPF,Compare-match Flag\nIf the EQEI compare function is enabled the flag is set by hardware while EQEI counter up or down counts and reach to the CNTCMP(EQEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it." "0: EQEI counter does not match with..,1: EQEI counter counts to the same as.."
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bitfld.long 0x0 0. "IDXF,IDX Detected Flag\nWhen the EQEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it." "0: No rising edge detected on signal CHX,1: A rising edge occurs on signal CHX"
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tree.end
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tree "EQEI1"
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base ad:0x400B1000
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group.long 0x0++0xF
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line.long 0x0 "EQEI_CNT,EQEI Counter Register"
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hexmask.long 0x0 0.--31. 1. "CNT,Enhanced Quadrature Encoder Interface Counter \nA 32-bit up/down counter. When an effective phase pulse is detected this counter is increased by one if the bit DIRF (EQEI_STATUS[8]) is one or decreased by one if the bit DIRF(EQEI_STATUS[8]) is 0."
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line.long 0x4 "EQEI_CNTHOLD,EQEI Counter Hold Register"
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hexmask.long 0x4 0.--31. 1. "CNTHOLD,Enhanced Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (EQEI_CTL[24]) goes from low to high the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD (EQEI_CNTHOLD[31:0]) register."
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line.long 0x8 "EQEI_CNTLATCH,EQEI Counter Index Latch Register"
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hexmask.long 0x8 0.--31. 1. "CNTLATCH,Enhanced Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (EQEI_STATUS[0]) bit is set the CNT(EQEI_CNT[31:0]) is copied into CNTLATCH (EQEI_CNTLATCH[31:0]) register."
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line.long 0xC "EQEI_CNTCMP,EQEI Counter Compare Register"
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hexmask.long 0xC 0.--31. 1. "CNTCMP,Enhanced Quadrature Encoder Interface Counter Compare"
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group.long 0x14++0x13
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line.long 0x0 "EQEI_CNTMAX,EQEI Pre-set Maximum Count Register"
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hexmask.long 0x0 0.--31. 1. "CNTMAX,Enhanced Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the EQEI counter for the EQEI controller compare-counting mode."
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line.long 0x4 "EQEI_CTL,EQEI Controller Control Register"
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bitfld.long 0x4 29. "EQEIEN,Enhanced Quadrature Encoder Interface Controller Enable Bit" "0: EQEI controller function Disabled,1: EQEI controller function Enabled"
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bitfld.long 0x4 28. "CMPEN,The Compare Function Enable Bit\nThe compare function in EQEI controller is to compare the dynamic counting EQEI_CNT with the compare register CNTCMP( EQEI_CNTCMP[31:0]) if CNT(EQEI_CNT[31:0]) reaches CNTCMP( EQEI_CNTCMP[31:0]) the flag CMPF will.." "0: Compare function Disabled,1: Compare function Enabled"
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newline
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bitfld.long 0x4 27. "IDXRLDEN,Index Trigger EQEI_CNT Reload Enable Bit" "0: Reload function Disabled,1: EQEI_CNT re-initialized by Index signal Enabled"
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bitfld.long 0x4 25. "IDXLATEN,Index Latch EQEI_CNT Enable Bit\nIf this bit is set to high the CNT(EQEI_CNT[31:0]) content will be latched into CNTLATCH (EQEI_CNTLATCH[31:0]) at every rising on signal CHX." "0: The index signal latch EQEI counter function..,1: The index signal latch EQEI counter function.."
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bitfld.long 0x4 24. "HOLDCNT,Hold EQEI_CNT Control\nWhen this bit is set from low to high the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD(EQEI_CNTHOLD[31:0]). This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). \nNote: This bit is.." "0: No operation,1: EQEI_CNT content is captured and stored in.."
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bitfld.long 0x4 23. "HOLDTMR3,Hold EQEI_CNT by Timer 3" "0: TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER3_INTSTS[0]) in.."
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bitfld.long 0x4 22. "HOLDTMR2,Hold EQEI_CNT by Timer 2" "0: TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER2_INTSTS[0]) in.."
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bitfld.long 0x4 21. "HOLDTMR1,Hold EQEI_CNT by Timer 1" "0: TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF (TIMER1_INTSTS[0]) in.."
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bitfld.long 0x4 20. "HOLDTMR0,Hold EQEI_CNT by Timer 0" "0: TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER0_INTSTS[0]) in.."
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bitfld.long 0x4 19. "IDXIEN,IDXF Trigger EQEI Interrupt Enable Bit" "0: The IDXF can trigger EQEI interrupt Disabled,1: The IDXF can trigger EQEI interrupt Enabled"
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bitfld.long 0x4 18. "CMPIEN,CMPF Trigger EQEI Interrupt Enable Bit" "0: CMPF can trigger EQEI controller interrupt..,1: CMPF can trigger EQEI controller interrupt Enabled"
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bitfld.long 0x4 17. "DIRIEN,DIRCHGF Trigger EQEI Interrupt Enable Bit" "0: DIRCHGF can trigger EQEI controller interrupt..,1: DIRCHGF can trigger EQEI controller interrupt.."
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bitfld.long 0x4 16. "OVUNIEN,OVUNF Trigger EQEI Interrupt Enable Bit" "0: OVUNF can trigger EQEI controller interrupt..,1: OVUNF can trigger EQEI controller interrupt.."
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bitfld.long 0x4 15. "IDXRSTEV,IDX Signal Resets Enable Bit in First IDX Reset Event (Write Only)" "0: The next IDX level high signal reset function..,1: The next IDX level high signal reset function.."
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bitfld.long 0x4 14. "IDXINV,Inverse IDX Input Polarity" "0: Not inverse IDX input polarity,1: IDX input polarity is inversed to EQEI controller"
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bitfld.long 0x4 13. "CHBINV,Inverse QEB Input Polarity" "0: Not inverse QEB input polarity,1: QEB input polarity is inversed to EQEI controller"
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bitfld.long 0x4 12. "CHAINV,Inverse QEA Input Polarity" "0: Not inverse QEA input polarity,1: QEA input polarity is inversed to EQEI controller"
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bitfld.long 0x4 8.--10. "MODE,EQEI Counting Mode Selection\nThere are seven quadrature encoder pulse counter operation modes.\nNote: User needs to set DIRSRC(EQEI_CTL2[5:4]) when MODE(EQEI_CTL[10:8]) selects to directional counting mode." "0: X4 Free-counting Mode,1: X2 Free-counting Mode,?,?,?,?,?,?"
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bitfld.long 0x4 7. "IDXRSTEN,IDX Reset EQEI Position Counter Enable Bit\nNote: IDXRLDEN(EQEI_CTL[27]) should be set 1." "0: Reset EQEI position counter in every time IDX..,1: Reset EQEI position counter in first time IDX.."
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bitfld.long 0x4 6. "IDXEN,IDX Input to EQEI Controller Enable Bit" "0: IDX input to EQEI Controller Disabled,1: IDX input to EQEI Controller Enabled"
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bitfld.long 0x4 5. "CHBEN,QEB Input to EQEI Controller Enable Bit" "0: QEB input to EQEI Controller Disabled,1: QEB input to EQEI Controller Enabled"
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bitfld.long 0x4 4. "CHAEN,QEA Input to EQEI Controller Enable Bit" "0: QEA input to EQEI Controller Disabled,1: QEA input to EQEI Controller Enabled"
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bitfld.long 0x4 3. "NFDIS,EQEI Controller Input Noise Filter Disable Bit" "0: The noise filter of EQEI controller Enabled,1: The noise filter of EQEI controller Disabled"
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bitfld.long 0x4 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock." "0: EQEI_CLK,1: EQEI_CLK/2,?,?,?,?,?,?"
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line.long 0x8 "EQEI_CTL2,EQEI Controller Control Register2"
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bitfld.long 0x8 17. "UTIEIEN,UTIEF Trigger EQEI Interrupt Enable Bit" "0: UTIEF can trigger EQEI controller interrupt..,1: UTIEF can trigger EQEI controller interrupt.."
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bitfld.long 0x8 16. "PHEIEN,PHEF Trigger EQEI Interrupt Enable Bit" "0: PHEF can trigger EQEI controller interrupt..,1: PHEF can trigger EQEI controller interrupt Enabled"
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bitfld.long 0x8 11. "IDXRSTUTS,IDX Resets Unit Timer Select Bit" "0: Unit timer will not be reset when IDX reset..,1: Resets unit timer or not will follow EQEI_CNT.."
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bitfld.long 0x8 10. "UTEVTRST,Enable Bit to Reset EQEI Position Counter by Unit Timer Event" "0: Reset EQEI position counter feature when unit..,1: Reset EQEI position counter feature when unit.."
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bitfld.long 0x8 9. "UTHOLDEN,Unit Timer Counter Hold Enable Bit" "0: No operation,1: EQEI_CNT content is captured and stored in.."
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bitfld.long 0x8 8. "UTEN,Unit Timer Function Enable Bit" "0: EQEI unit timer function Disabled,1: EQEI unit timer function Enabled"
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bitfld.long 0x8 4.--5. "DIRSRC,Direction Signal Source Select" "0: Direction signal is determined from EQEI system..,1: Reserved.,?,?"
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bitfld.long 0x8 1.--2. "CRS,Clock Rate Setting without Quadrature Mode" "0: EQEI counter only counts the falling edge,1: EQEI counter only counts the rising edge,?,?"
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bitfld.long 0x8 0. "SWAPEN,Swap Function Enable Bit" "0: EQEI swap function Disabled,1: EQEI swap function Enabled"
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line.long 0xC "EQEI_UTCNT,EQEI Unit Timer Counter Register"
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hexmask.long 0xC 0.--31. 1. "UTCNT,Unit Timer Counter \nA 32-bit unit timer counter which may be reset to an initial value when any of the following events occur:"
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line.long 0x10 "EQEI_UTCMP,EQEI Unit Timer Compare Register"
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hexmask.long 0x10 0.--31. 1. "UTCMP,Unit Timer Counter Compare"
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group.long 0x2C++0x3
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line.long 0x0 "EQEI_STATUS,EQEI Controller Status Register"
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bitfld.long 0x0 17. "UTIEF,EQEI Unit Timer Event Flag\nNote: This bit is only cleared by writing 1 to it." "0: No timer event occurs in EQEI unit timer counter,1: Unit timer event occurs in EQEI unit timer counter"
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bitfld.long 0x0 16. "PHEF,EQEI Phase Error Flag\nNote: This bit is only cleared by writing 1 to it." "0: No Phase error occurs in EQEI CHA and CHB,1: Phase error occurs in EQEI CHA and CHB"
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rbitfld.long 0x0 9. "FIDXEF,First IDX Signal Reset Event Flag (Read Only)" "0: The first IDX reset event has not happened yet,1: The first IDX reset event has happened"
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bitfld.long 0x0 8. "DIRF,EQEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB." "0: EQEI Counter is in down-counting,1: EQEI Counter is in up-counting"
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bitfld.long 0x0 3. "DIRCHGF,Direction Change Flag\nFlag is set by hardware while EQEI counter counting direction is changed. Software can clear this bit by writing 1 to it.\nNote: This bit is only cleared by writing 1 to it." "0: No change in EQEI counter counting direction,1: EQEI counter counting direction is changed"
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bitfld.long 0x0 2. "OVUNF,EQEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(EQEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (EQEI_CNTMAX[31:0]) to 0 in compare-counting mode. Similarly the flag is set while.." "0: No overflow or underflow occurs in EQEI counter,1: EQEI counter occurs counting overflow or underflow"
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bitfld.long 0x0 1. "CMPF,Compare-match Flag\nIf the EQEI compare function is enabled the flag is set by hardware while EQEI counter up or down counts and reach to the CNTCMP(EQEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it." "0: EQEI counter does not match with..,1: EQEI counter counts to the same as.."
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bitfld.long 0x0 0. "IDXF,IDX Detected Flag\nWhen the EQEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it." "0: No rising edge detected on signal CHX,1: A rising edge occurs on signal CHX"
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tree.end
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tree.end
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tree "GPIO (General Purpose I/Os)"
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base ad:0x40004000
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group.long 0x0++0xF
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line.long 0x0 "PA_MODE,PA I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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line.long 0x4 "PA_DINOFF,PA Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PA_DOUT,PA Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PA_DATMSK,PA Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0x10++0x3
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line.long 0x0 "PA_PIN,PA Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0x14++0x17
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line.long 0x0 "PA_DBEN,PA De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PA_INTTYPE,PA Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PA_INTEN,PA Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PA_INTSRC,PA Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PA_SMTEN,PA Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PA_SLEWCTL,PA High Slew Rate Control Register"
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bitfld.long 0x14 30.--31. "HSREN15,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 28.--29. "HSREN14,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 24.--25. "HSREN12,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 20.--21. "HSREN10,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 16.--17. "HSREN8,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 12.--13. "HSREN6,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 8.--9. "HSREN4,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 4.--5. "HSREN2,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 0.--1. "HSREN0,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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group.long 0x30++0x7
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line.long 0x0 "PA_PUSEL,PA Pull-up and Pull-down Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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line.long 0x4 "PA_DBCTL,PA Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 32 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x40++0xF
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line.long 0x0 "PB_MODE,PB I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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line.long 0x4 "PB_DINOFF,PB Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PB_DOUT,PB Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PB_DATMSK,PB Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0x50++0x3
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line.long 0x0 "PB_PIN,PB Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0x54++0x17
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line.long 0x0 "PB_DBEN,PB De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PB_INTTYPE,PB Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PB_INTEN,PB Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PB_INTSRC,PB Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PB_SMTEN,PB Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PB_SLEWCTL,PB High Slew Rate Control Register"
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bitfld.long 0x14 30.--31. "HSREN15,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 28.--29. "HSREN14,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 24.--25. "HSREN12,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 20.--21. "HSREN10,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 16.--17. "HSREN8,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 12.--13. "HSREN6,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 8.--9. "HSREN4,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 4.--5. "HSREN2,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 0.--1. "HSREN0,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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group.long 0x70++0x7
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line.long 0x0 "PB_PUSEL,PB Pull-up and Pull-down Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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line.long 0x4 "PB_DBCTL,PB Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 32 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x80++0xF
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line.long 0x0 "PC_MODE,PC I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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line.long 0x4 "PC_DINOFF,PC Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PC_DOUT,PC Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PC_DATMSK,PC Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0x90++0x3
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line.long 0x0 "PC_PIN,PC Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0x94++0x17
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line.long 0x0 "PC_DBEN,PC De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PC_INTTYPE,PC Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PC_INTEN,PC Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PC_INTSRC,PC Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PC_SMTEN,PC Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PC_SLEWCTL,PC High Slew Rate Control Register"
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bitfld.long 0x14 30.--31. "HSREN15,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 28.--29. "HSREN14,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 24.--25. "HSREN12,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 20.--21. "HSREN10,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 16.--17. "HSREN8,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 12.--13. "HSREN6,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 8.--9. "HSREN4,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 4.--5. "HSREN2,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 0.--1. "HSREN0,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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group.long 0xB0++0x7
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line.long 0x0 "PC_PUSEL,PC Pull-up and Pull-down Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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line.long 0x4 "PC_DBCTL,PC Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 32 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0xC0++0xF
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line.long 0x0 "PD_MODE,PD I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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line.long 0x4 "PD_DINOFF,PD Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PD_DOUT,PD Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PD_DATMSK,PD Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0xD0++0x3
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line.long 0x0 "PD_PIN,PD Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0xD4++0x17
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line.long 0x0 "PD_DBEN,PD De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PD_INTTYPE,PD Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PD_INTEN,PD Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PD_INTSRC,PD Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PD_SMTEN,PD Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PD_SLEWCTL,PD High Slew Rate Control Register"
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bitfld.long 0x14 30.--31. "HSREN15,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 28.--29. "HSREN14,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 24.--25. "HSREN12,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 20.--21. "HSREN10,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 16.--17. "HSREN8,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 12.--13. "HSREN6,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 8.--9. "HSREN4,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 4.--5. "HSREN2,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 0.--1. "HSREN0,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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group.long 0xF0++0x7
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line.long 0x0 "PD_PUSEL,PD Pull-up and Pull-down Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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line.long 0x4 "PD_DBCTL,PD Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 32 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x100++0xF
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line.long 0x0 "PE_MODE,PE I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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line.long 0x4 "PE_DINOFF,PE Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PE_DOUT,PE Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PE_DATMSK,PE Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0x110++0x3
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line.long 0x0 "PE_PIN,PE Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0x114++0x17
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line.long 0x0 "PE_DBEN,PE De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PE_INTTYPE,PE Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PE_INTEN,PE Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PE_INTSRC,PE Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PE_SMTEN,PE Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PE_SLEWCTL,PE High Slew Rate Control Register"
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bitfld.long 0x14 30.--31. "HSREN15,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 28.--29. "HSREN14,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 24.--25. "HSREN12,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 20.--21. "HSREN10,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 16.--17. "HSREN8,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 12.--13. "HSREN6,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 8.--9. "HSREN4,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 4.--5. "HSREN2,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 0.--1. "HSREN0,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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group.long 0x130++0x7
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line.long 0x0 "PE_PUSEL,PE Pull-up and Pull-down Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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line.long 0x4 "PE_DBCTL,PE Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 32 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x140++0xF
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line.long 0x0 "PF_MODE,PF I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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line.long 0x4 "PF_DINOFF,PF Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PF_DOUT,PF Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PF_DATMSK,PF Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0x150++0x3
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line.long 0x0 "PF_PIN,PF Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0x154++0x17
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line.long 0x0 "PF_DBEN,PF De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PF_INTTYPE,PF Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PF_INTEN,PF Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PF_INTSRC,PF Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PF_SMTEN,PF Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PF_SLEWCTL,PF High Slew Rate Control Register"
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bitfld.long 0x14 30.--31. "HSREN15,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 28.--29. "HSREN14,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 24.--25. "HSREN12,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 20.--21. "HSREN10,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 16.--17. "HSREN8,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 12.--13. "HSREN6,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 8.--9. "HSREN4,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 4.--5. "HSREN2,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 0.--1. "HSREN0,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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group.long 0x170++0x7
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line.long 0x0 "PF_PUSEL,PF Pull-up and Pull-down Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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line.long 0x4 "PF_DBCTL,PF Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 32 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x180++0xF
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line.long 0x0 "PG_MODE,PG I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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line.long 0x4 "PG_DINOFF,PG Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PG_DOUT,PG Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PG_DATMSK,PG Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0x190++0x3
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line.long 0x0 "PG_PIN,PG Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0x194++0x17
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line.long 0x0 "PG_DBEN,PG De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PG_INTTYPE,PG Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PG_INTEN,PG Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PG_INTSRC,PG Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PG_SMTEN,PG Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PG_SLEWCTL,PG High Slew Rate Control Register"
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bitfld.long 0x14 30.--31. "HSREN15,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 28.--29. "HSREN14,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 24.--25. "HSREN12,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 20.--21. "HSREN10,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 16.--17. "HSREN8,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 12.--13. "HSREN6,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 8.--9. "HSREN4,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 4.--5. "HSREN2,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 0.--1. "HSREN0,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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group.long 0x1B0++0x7
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line.long 0x0 "PG_PUSEL,PG Pull-up and Pull-down Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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line.long 0x4 "PG_DBCTL,PG Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 32 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x1C0++0xF
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line.long 0x0 "PH_MODE,PH I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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line.long 0x4 "PH_DINOFF,PH Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PH_DOUT,PH Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: For more information about Px.n please refer to the PIN.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PH_DATMSK,PH Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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bitfld.long 0xC 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
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rgroup.long 0x1D0++0x3
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line.long 0x0 "PH_PIN,PH Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n .." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: For more information about Px.n please.." "0,1"
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group.long 0x1D4++0x17
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line.long 0x0 "PH_DBEN,PH De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PH_INTTYPE,PH Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PH_INTEN,PH Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
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line.long 0xC "PH_INTSRC,PH Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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line.long 0x10 "PH_SMTEN,PH Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-H Pin[n] Input Schmitt Trigger Enable Bit\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PH_SLEWCTL,PH High Slew Rate Control Register"
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bitfld.long 0x14 30.--31. "HSREN15,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 28.--29. "HSREN14,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 26.--27. "HSREN13,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 24.--25. "HSREN12,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 22.--23. "HSREN11,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 20.--21. "HSREN10,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 18.--19. "HSREN9,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 16.--17. "HSREN8,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 14.--15. "HSREN7,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 12.--13. "HSREN6,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 10.--11. "HSREN5,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 8.--9. "HSREN4,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 6.--7. "HSREN3,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 4.--5. "HSREN2,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 2.--3. "HSREN1,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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bitfld.long 0x14 0.--1. "HSREN0,Port A-H Pin[n] High Slew Rate Control\nNote: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Px.n output with normal slew rate mode (maximum..,1: Px.n output with high slew rate mode (maximum 72..,?,?"
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group.long 0x1F0++0x7
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line.long 0x0 "PH_PUSEL,PH Pull-up and Pull-down Selection Register"
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bitfld.long 0x0 30.--31. "PUSEL15,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 28.--29. "PUSEL14,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 26.--27. "PUSEL13,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 24.--25. "PUSEL12,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 22.--23. "PUSEL11,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 20.--21. "PUSEL10,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 18.--19. "PUSEL9,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 16.--17. "PUSEL8,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 14.--15. "PUSEL7,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 12.--13. "PUSEL6,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 10.--11. "PUSEL5,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 8.--9. "PUSEL4,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 6.--7. "PUSEL3,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 4.--5. "PUSEL2,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 2.--3. "PUSEL1,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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bitfld.long 0x0 0.--1. "PUSEL0,Port A-H Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disable,1: Basically,2: For more information about Px,?"
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line.long 0x4 "PH_DBCTL,PH Interrupt De-bounce Control Register"
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rbitfld.long 0x4 31. "DBCLKBUSY,De-bounce Clock Switching Busy Flag (Read Only)\nThis bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). It is cleared after de-bounce clock source switching is finished. De-bounce function can work normally.." "0: De-bounce clock switch done,1: De-bounce clock is switching"
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bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: For more information about Px.n please refer to the PIN CONFIGURATION chapter." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
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bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 32 kHz.."
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hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x450++0x1F
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line.long 0x0 "INT0_INNF,INT0 Input Noise Filter Register"
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bitfld.long 0x0 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0x4 "INT1_INNF,INT1 Input Noise Filter Register"
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bitfld.long 0x4 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x4 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0x8 "INT2_INNF,INT2 Input Noise Filter Register"
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bitfld.long 0x8 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x8 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0xC "INT3_INNF,INT3 Input Noise Filter Register"
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bitfld.long 0xC 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0xC 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0x10 "INT4_INNF,INT4 Input Noise Filter Register"
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bitfld.long 0x10 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0x14 "INT5_INNF,INT5 Input Noise Filter Register"
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bitfld.long 0x14 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x14 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0x18 "INT6_INNF,INT6 Input Noise Filter Register"
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bitfld.long 0x18 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x18 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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line.long 0x1C "INT7_INNF,INT7 Input Noise Filter Register"
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bitfld.long 0x1C 8.--10. "NFCNT,Noise Filter Count\nThe register bits control the filter counter to count from 0 to NFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 4.--6. "NFSEL,Noise Filter Clock Selection" "0: Filter clock is HCLK,1: Filter clock is HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "NFEN,Noise Filter Enable" "0: Noise Filter function Disabled,1: Noise Filter function Enabled"
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group.long 0x490++0x3
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line.long 0x0 "INT_EDETCTL,INT Edge Detect Control Register"
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bitfld.long 0x0 14.--15. "EDETCTL7,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 12.--13. "EDETCTL6,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 10.--11. "EDETCTL5,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 8.--9. "EDETCTL4,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 6.--7. "EDETCTL3,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 4.--5. "EDETCTL2,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 2.--3. "EDETCTL1,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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bitfld.long 0x0 0.--1. "EDETCTL0,INTn Edge Detect Control Bits" "0: Not detect,1: INTn low to high detection Enabled,?,?"
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group.long 0x498++0x7
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line.long 0x0 "INT_EDINTEN,INT Edge Detect Interrupt Enable Control Register"
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bitfld.long 0x0 7. "EDIEN7,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 6. "EDIEN6,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 5. "EDIEN5,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 4. "EDIEN4,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 3. "EDIEN3,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 2. "EDIEN2,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 1. "EDIEN1,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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bitfld.long 0x0 0. "EDIEN0,INTn Edge Detect Interrupt Enable Bit" "0: INTn Edge Detect Interrupt Disabled,1: INTn Edge Detect Interrupt Enabled"
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line.long 0x4 "INT_EDSTS,INT Edge Detect Interrupt Flag Register"
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bitfld.long 0x4 7. "EDIF7,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 6. "EDIF6,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 5. "EDIF5,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 4. "EDIF4,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 3. "EDIF3,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 2. "EDIF2,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 1. "EDIF1,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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bitfld.long 0x4 0. "EDIF0,INTn Edge Detect Interrupt Flag \nNote: This bit is cleared by writing 1 to it." "0: No Edge Detection happened,1: Rising Edge or Falling edge has been detected"
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group.long 0x800++0xBB
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line.long 0x0 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x8 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xC "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x10 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x14 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x18 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x1C "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x20 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x24 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x28 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x2C "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x30 "PA12_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x34 "PA13_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x38 "PA14_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x3C "PA15_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x40 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x40 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x44 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x44 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x48 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x48 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4C "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x4C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x50 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x50 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x54 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x54 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x58 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x58 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x5C "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x5C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x60 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x60 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x64 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x64 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x68 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x68 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x6C "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x6C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x70 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x70 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x74 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x74 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x78 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x78 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x7C "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x7C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x80 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x80 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x84 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x84 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x88 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x88 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x8C "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x8C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x90 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x90 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x94 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x94 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x98 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x98 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x9C "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x9C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xA0 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xA0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xA4 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xA4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xA8 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xA8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xAC "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xAC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xB0 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xB0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xB4 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xB4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xB8 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xB8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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group.long 0x8C0++0xAF
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line.long 0x0 "PD0_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4 "PD1_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x8 "PD2_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xC "PD3_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x10 "PD4_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x14 "PD5_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x18 "PD6_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x1C "PD7_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x20 "PD8_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x24 "PD9_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x28 "PD10_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x2C "PD11_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x30 "PD12_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x34 "PD13_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x38 "PD14_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x3C "PD15_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x40 "PE0_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x40 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x44 "PE1_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x44 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x48 "PE2_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x48 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4C "PE3_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x4C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x50 "PE4_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x50 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x54 "PE5_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x54 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x58 "PE6_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x58 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x5C "PE7_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x5C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x60 "PE8_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x60 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x64 "PE9_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x64 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x68 "PE10_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x68 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x6C "PE11_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x6C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x70 "PE12_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x70 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x74 "PE13_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x74 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x78 "PE14_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x78 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x7C "PE15_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x7C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x80 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x80 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x84 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x84 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x88 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x88 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x8C "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x8C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x90 "PF4_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x90 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x94 "PF5_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x94 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x98 "PF6_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x98 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x9C "PF7_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x9C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xA0 "PF8_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0xA0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xA4 "PF9_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0xA4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xA8 "PF10_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0xA8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xAC "PF11_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0xAC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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group.long 0x988++0xB
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line.long 0x0 "PG2_PDIO,GPIO PG.n Pin Data Input/Output Register"
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bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4 "PG3_PDIO,GPIO PG.n Pin Data Input/Output Register"
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bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x8 "PG4_PDIO,GPIO PG.n Pin Data Input/Output Register"
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bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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group.long 0x9A4++0x1B
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line.long 0x0 "PG9_PDIO,GPIO PG.n Pin Data Input/Output Register"
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bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4 "PG10_PDIO,GPIO PG.n Pin Data Input/Output Register"
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bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x8 "PG11_PDIO,GPIO PG.n Pin Data Input/Output Register"
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bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xC "PG12_PDIO,GPIO PG.n Pin Data Input/Output Register"
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bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x10 "PG13_PDIO,GPIO PG.n Pin Data Input/Output Register"
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bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x14 "PG14_PDIO,GPIO PG.n Pin Data Input/Output Register"
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bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x18 "PG15_PDIO,GPIO PG.n Pin Data Input/Output Register"
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bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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group.long 0x9D0++0x1F
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line.long 0x0 "PH4_PDIO,GPIO PH.n Pin Data Input/Output Register"
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bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4 "PH5_PDIO,GPIO PH.n Pin Data Input/Output Register"
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bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x8 "PH6_PDIO,GPIO PH.n Pin Data Input/Output Register"
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bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xC "PH7_PDIO,GPIO PH.n Pin Data Input/Output Register"
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bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x10 "PH8_PDIO,GPIO PH.n Pin Data Input/Output Register"
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bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x14 "PH9_PDIO,GPIO PH.n Pin Data Input/Output Register"
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bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x18 "PH10_PDIO,GPIO PH.n Pin Data Input/Output Register"
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bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x1C "PH11_PDIO,GPIO PH.n Pin Data Input/Output Register"
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bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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tree.end
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tree "I2C (Inter-Integrated Circuit Serial Interface Controller)"
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base ad:0x0
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tree "I2C0"
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base ad:0x40080000
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group.long 0x0++0xB
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line.long 0x0 "I2C_CTL0,I2C Control Register 0"
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bitfld.long 0x0 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address match read command.\nThis bit is cleared by write 1 to it." "0,1"
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bitfld.long 0x0 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting \nThis bit is cleared by write 1 to it." "0,1"
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newline
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bitfld.long 0x0 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled"
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bitfld.long 0x0 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled"
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newline
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bitfld.long 0x0 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal to..,?,?"
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bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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newline
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
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bitfld.long 0x0 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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newline
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bitfld.long 0x0 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this.." "0,1"
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newline
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
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line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
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hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x8 "I2C_DAT,I2C Data Register"
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hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
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rgroup.long 0xC++0x3
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line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
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hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
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group.long 0x10++0x23
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line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
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hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width. If the pulse width is narrower than the setting((3+N)*PCLK) it will be ignored.\n0 : filter width 3*PCLK \n1 : filter width 4*PCLK\nN : filter width (3+N)*PCKL\nNote: Filter.."
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hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of DIVIDER is 4."
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line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
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bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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newline
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
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hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
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hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
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hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
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hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
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hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
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hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
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hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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group.long 0x3C++0x23
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line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
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bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
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bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
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bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_CTL1,I2C Control Register 1"
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bitfld.long 0x8 10. "SWITCHEN,SCL And SDA Pin Switch Enable Bit\nNote: Original pin configuration table is shown in Basic Configuration chapter." "0: IC use original pin configuration,1: IC switch SCL and SDA pin configuration"
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bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
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bitfld.long 0x8 5. "TWOBUFEN,Two-level Buffer Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus." "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer." "0,1"
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bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer." "0,1"
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
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bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0xC "I2C_STATUS1,I2C Status Register 1"
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rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
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bitfld.long 0xC 7. "UDR,I2C Under Run Status Bit\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 6. "OVR,I2C over Run Status Bit\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 5. "EMPTY,TWO-LEVEL BUFFER EMPTY\nThis bit is set when POINTER is equal to 0.\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 4. "FULL,TWO-LEVEL BUFFER FULL\nThis bit is set when POINTER is equal to 2\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
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hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
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line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
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bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
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bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
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bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
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bitfld.long 0x14 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus.." "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period in.."
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bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
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bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
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bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable. When the address..,1: Device default address Enabled. When the address.."
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter power-down mode the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
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line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
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bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
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bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.\nBus IDLE..,1: SCL low time-out interrupt Enabled.\nBus IDLE.."
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bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
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line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
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bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
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bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred; otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
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bitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit." "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is SMBALERT.."
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bitfld.long 0x1C 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit." "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
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bitfld.long 0x1C 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
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line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
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hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address command code and data frame."
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rgroup.long 0x60++0x3
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line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
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hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
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group.long 0x64++0x7
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line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
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hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCL low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the.."
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line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set."
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tree.end
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tree "I2C1"
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base ad:0x40081000
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group.long 0x0++0xB
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line.long 0x0 "I2C_CTL0,I2C Control Register 0"
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bitfld.long 0x0 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address match read command.\nThis bit is cleared by write 1 to it." "0,1"
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bitfld.long 0x0 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting \nThis bit is cleared by write 1 to it." "0,1"
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bitfld.long 0x0 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled"
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bitfld.long 0x0 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled"
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bitfld.long 0x0 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal to..,?,?"
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bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
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bitfld.long 0x0 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
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line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
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hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x8 "I2C_DAT,I2C Data Register"
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hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
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rgroup.long 0xC++0x3
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line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
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hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
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group.long 0x10++0x23
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line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
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hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width. If the pulse width is narrower than the setting((3+N)*PCLK) it will be ignored.\n0 : filter width 3*PCLK \n1 : filter width 4*PCLK\nN : filter width (3+N)*PCKL\nNote: Filter.."
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hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of DIVIDER is 4."
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line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
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bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
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hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
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hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
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hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
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hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
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hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
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hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
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hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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group.long 0x3C++0x23
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line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
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bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
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bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
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bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_CTL1,I2C Control Register 1"
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bitfld.long 0x8 10. "SWITCHEN,SCL And SDA Pin Switch Enable Bit\nNote: Original pin configuration table is shown in Basic Configuration chapter." "0: IC use original pin configuration,1: IC switch SCL and SDA pin configuration"
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bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
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bitfld.long 0x8 5. "TWOBUFEN,Two-level Buffer Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus." "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer." "0,1"
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bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer." "0,1"
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
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bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0xC "I2C_STATUS1,I2C Status Register 1"
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rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
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bitfld.long 0xC 7. "UDR,I2C Under Run Status Bit\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 6. "OVR,I2C over Run Status Bit\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 5. "EMPTY,TWO-LEVEL BUFFER EMPTY\nThis bit is set when POINTER is equal to 0.\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 4. "FULL,TWO-LEVEL BUFFER FULL\nThis bit is set when POINTER is equal to 2\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
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hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
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line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
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bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
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bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
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bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
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bitfld.long 0x14 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus.." "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period in.."
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bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
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bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
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bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable. When the address..,1: Device default address Enabled. When the address.."
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter power-down mode the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
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line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
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bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
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bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.\nBus IDLE..,1: SCL low time-out interrupt Enabled.\nBus IDLE.."
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bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
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line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
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bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
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bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred; otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
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bitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit." "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is SMBALERT.."
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bitfld.long 0x1C 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit." "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
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bitfld.long 0x1C 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
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line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
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hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address command code and data frame."
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rgroup.long 0x60++0x3
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line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
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hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
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group.long 0x64++0x7
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line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
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hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCL low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the.."
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line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set."
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tree.end
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tree "I2C2"
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base ad:0x40082000
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group.long 0x0++0xB
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line.long 0x0 "I2C_CTL0,I2C Control Register 0"
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bitfld.long 0x0 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address match read command.\nThis bit is cleared by write 1 to it." "0,1"
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bitfld.long 0x0 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting \nThis bit is cleared by write 1 to it." "0,1"
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bitfld.long 0x0 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled"
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bitfld.long 0x0 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled"
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bitfld.long 0x0 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal to..,?,?"
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bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
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bitfld.long 0x0 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
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line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
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hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x8 "I2C_DAT,I2C Data Register"
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hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
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rgroup.long 0xC++0x3
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line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
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hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
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group.long 0x10++0x23
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line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
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hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width. If the pulse width is narrower than the setting((3+N)*PCLK) it will be ignored.\n0 : filter width 3*PCLK \n1 : filter width 4*PCLK\nN : filter width (3+N)*PCKL\nNote: Filter.."
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hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of DIVIDER is 4."
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line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
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bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
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hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
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hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
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hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
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hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
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hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
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hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
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hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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group.long 0x3C++0x23
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line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
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bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
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bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
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bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_CTL1,I2C Control Register 1"
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bitfld.long 0x8 10. "SWITCHEN,SCL And SDA Pin Switch Enable Bit\nNote: Original pin configuration table is shown in Basic Configuration chapter." "0: IC use original pin configuration,1: IC switch SCL and SDA pin configuration"
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bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
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bitfld.long 0x8 5. "TWOBUFEN,Two-level Buffer Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus." "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer." "0,1"
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bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer." "0,1"
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
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bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0xC "I2C_STATUS1,I2C Status Register 1"
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rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
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bitfld.long 0xC 7. "UDR,I2C Under Run Status Bit\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 6. "OVR,I2C over Run Status Bit\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 5. "EMPTY,TWO-LEVEL BUFFER EMPTY\nThis bit is set when POINTER is equal to 0.\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 4. "FULL,TWO-LEVEL BUFFER FULL\nThis bit is set when POINTER is equal to 2\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
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hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
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line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
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bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
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bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
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bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
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bitfld.long 0x14 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus.." "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period in.."
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bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
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bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
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bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable. When the address..,1: Device default address Enabled. When the address.."
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter power-down mode the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
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line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
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bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
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bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.\nBus IDLE..,1: SCL low time-out interrupt Enabled.\nBus IDLE.."
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bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
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line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
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bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
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bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred; otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
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bitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit." "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is SMBALERT.."
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bitfld.long 0x1C 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit." "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
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bitfld.long 0x1C 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
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line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
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hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address command code and data frame."
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rgroup.long 0x60++0x3
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line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
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hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
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group.long 0x64++0x7
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line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
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hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCL low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the.."
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line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set."
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tree.end
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tree "I2C3"
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base ad:0x40083000
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group.long 0x0++0xB
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line.long 0x0 "I2C_CTL0,I2C Control Register 0"
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bitfld.long 0x0 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address match read command.\nThis bit is cleared by write 1 to it." "0,1"
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bitfld.long 0x0 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting \nThis bit is cleared by write 1 to it." "0,1"
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bitfld.long 0x0 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled"
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bitfld.long 0x0 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled"
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bitfld.long 0x0 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal to..,?,?"
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bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
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bitfld.long 0x0 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
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line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
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hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x8 "I2C_DAT,I2C Data Register"
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hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
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rgroup.long 0xC++0x3
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line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
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hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
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group.long 0x10++0x23
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line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
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hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width. If the pulse width is narrower than the setting((3+N)*PCLK) it will be ignored.\n0 : filter width 3*PCLK \n1 : filter width 4*PCLK\nN : filter width (3+N)*PCKL\nNote: Filter.."
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hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of DIVIDER is 4."
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line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
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bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
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hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
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hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
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hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
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bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
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hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
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hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
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hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
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hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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group.long 0x3C++0x23
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line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
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bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
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bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
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bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_CTL1,I2C Control Register 1"
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bitfld.long 0x8 10. "SWITCHEN,SCL And SDA Pin Switch Enable Bit\nNote: Original pin configuration table is shown in Basic Configuration chapter." "0: IC use original pin configuration,1: IC switch SCL and SDA pin configuration"
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bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
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bitfld.long 0x8 5. "TWOBUFEN,Two-level Buffer Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus." "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x8 4. "UDRIEN,I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer." "0,1"
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bitfld.long 0x8 3. "OVRIEN,I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer." "0,1"
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
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bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0xC "I2C_STATUS1,I2C Status Register 1"
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rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
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bitfld.long 0xC 7. "UDR,I2C Under Run Status Bit\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 6. "OVR,I2C over Run Status Bit\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 5. "EMPTY,TWO-LEVEL BUFFER EMPTY\nThis bit is set when POINTER is equal to 0.\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 4. "FULL,TWO-LEVEL BUFFER FULL\nThis bit is set when POINTER is equal to 2\nNote: This bit is read only." "0,1"
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bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
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hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
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line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
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bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
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bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
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bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
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bitfld.long 0x14 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus.." "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period in.."
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bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
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bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
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bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable. When the address..,1: Device default address Enabled. When the address.."
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter power-down mode the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
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line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
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bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
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bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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newline
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.\nBus IDLE..,1: SCL low time-out interrupt Enabled.\nBus IDLE.."
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|
bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
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|
line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
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bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
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bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred; otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
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|
bitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit." "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is SMBALERT.."
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bitfld.long 0x1C 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit." "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
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bitfld.long 0x1C 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
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|
line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
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hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address command code and data frame."
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|
rgroup.long 0x60++0x3
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line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
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|
hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
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|
group.long 0x64++0x7
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line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
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|
hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCL low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the.."
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line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set."
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tree.end
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tree.end
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tree "KS (Key Store)"
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base ad:0x40035000
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group.long 0x0++0xB
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line.long 0x0 "KS_CTL,Key Store Control Register"
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bitfld.long 0x0 15. "IEN,Key Store Interrupt Enable Bit" "0: Key Store interrupt Disabled,1: Key Store interrupt Enabled"
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bitfld.long 0x0 14. "TCLREN,Tamper Event Clear Enable Bit" "0: Key Store does not revoke all OTP keys when..,1: Key Store revokes all OTP keys when tamper event.."
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bitfld.long 0x0 8. "INIT,Key Store Initialization\nUser should check BUSY(KS_STS[2]) is 0 and then write 1 to this bit and START(KS_CTL[0]) Key Store will start initialization.\nAfter the Key Store is initialized INIT will be cleared." "0,1"
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bitfld.long 0x0 1.--3. "OPMODE,Key Store Operation Mode" "0: Read operation,1: Create operation,?,?,?,?,?,?"
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bitfld.long 0x0 0. "START,Key Store Start Control Bit" "0: No operation,1: Start the operation"
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line.long 0x4 "KS_METADATA,Key Store Metadata Register"
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bitfld.long 0x4 30.--31. "DST,Key Location Selection Bits" "0,1,2,3"
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hexmask.long.byte 0x4 20.--25. 1. "NUMBER,Key Number\nBefore read or erase one key operation is started user should write the key number to be operated. When create operation is finished user can read these bits to get its key number."
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bitfld.long 0x4 16.--18. "OWNER,Key Owner Selection Bits" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 8.--12. 1. "SIZE,Key Size Selection Bits"
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bitfld.long 0x4 4. "BS,Booting State Selection Bit" "0: Set key used at all state,1: Set key used at boot loader state 1 (BL1 state)"
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bitfld.long 0x4 2. "READABLE,Key Readable Control Bit" "0: key is un-readable,1: key is readable"
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line.long 0x8 "KS_STS,Key Store Status Register"
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rbitfld.long 0x8 16. "RSTEF,Key Store Reset Error Flag (Read Only)\nThis flag will be cleared if Key Store is initialized." "0: Reset Not occurred during execution,1: Reset occurred during execution. User must check.."
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rbitfld.long 0x8 9. "KRVKF,Key Store Key Revoked Flag (read only)\nIf KSPLOCK(CONFIG2[15:8]) is locked and mass erase occurs Key Store will revoke OTP keys at next initialization. When initialization is finished KRVKF will be set forever." "0: All Keys have not been erased/revoked,1: All Keys have been erased/revoked"
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rbitfld.long 0x8 7. "INITDONE,Key Store Initialization Done Status (Read Only)" "0: Key Store is un-initialized,1: Key Store is initialized"
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rbitfld.long 0x8 6. "TCLRSF,Tamper Event Clear Set Flag (Read Only)" "0: TCLREN(KS_CTL[14]) has been set,1: TCLREN(KS_CTL[14]) has not been set"
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newline
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rbitfld.long 0x8 2. "BUSY,Key Store Busy Flag (Read Only)" "0: Key Store is idle or finished,1: Key Store is busy"
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bitfld.long 0x8 1. "EIF,Key Store Error Flag\nNote: This bit is cleared by writing 1 and it has no effect by writing 0." "0: No Key Store error,1: Key Store error interrupt"
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bitfld.long 0x8 0. "IF,Key Store Finish Interrupt Flag\nNote: This bit is cleared by writing 1 and it has no effect by writing 0." "0: No Key Store interrupt,1: Key Store operation done interrupt"
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group.long 0x20++0x1F
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line.long 0x0 "KS_KEY0,Key Store Entry Key Word 0 Register"
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hexmask.long 0x0 0.--31. 1. "KEY,Key Data (Read/Write Read to Clear)\nThese registers will be cleared if Key Store executes the write operation or CPU completes the reading key."
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line.long 0x4 "KS_KEY1,Key Store Entry Key Word 1 Register"
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hexmask.long 0x4 0.--31. 1. "KEY,Key Data (Read/Write Read to Clear)\nThese registers will be cleared if Key Store executes the write operation or CPU completes the reading key."
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line.long 0x8 "KS_KEY2,Key Store Entry Key Word 2 Register"
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hexmask.long 0x8 0.--31. 1. "KEY,Key Data (Read/Write Read to Clear)\nThese registers will be cleared if Key Store executes the write operation or CPU completes the reading key."
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line.long 0xC "KS_KEY3,Key Store Entry Key Word 3 Register"
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hexmask.long 0xC 0.--31. 1. "KEY,Key Data (Read/Write Read to Clear)\nThese registers will be cleared if Key Store executes the write operation or CPU completes the reading key."
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line.long 0x10 "KS_KEY4,Key Store Entry Key Word 4 Register"
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hexmask.long 0x10 0.--31. 1. "KEY,Key Data (Read/Write Read to Clear)\nThese registers will be cleared if Key Store executes the write operation or CPU completes the reading key."
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line.long 0x14 "KS_KEY5,Key Store Entry Key Word 5 Register"
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hexmask.long 0x14 0.--31. 1. "KEY,Key Data (Read/Write Read to Clear)\nThese registers will be cleared if Key Store executes the write operation or CPU completes the reading key."
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line.long 0x18 "KS_KEY6,Key Store Entry Key Word 6 Register"
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hexmask.long 0x18 0.--31. 1. "KEY,Key Data (Read/Write Read to Clear)\nThese registers will be cleared if Key Store executes the write operation or CPU completes the reading key."
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line.long 0x1C "KS_KEY7,Key Store Entry Key Word 7 Register"
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hexmask.long 0x1C 0.--31. 1. "KEY,Key Data (Read/Write Read to Clear)\nThese registers will be cleared if Key Store executes the write operation or CPU completes the reading key."
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rgroup.long 0x40++0x3
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line.long 0x0 "KS_OTPSTS,Key Store OTP Keys Status Register"
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bitfld.long 0x0 1. "KEY1,OTP Key 1 Used Status\nNote: When chip is in RMA stage this bit will be set to 1 and key is revoked after initialization if key is existed." "0: OTP key 1 is unused,1: OTP key 1 is used"
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bitfld.long 0x0 0. "KEY0,OTP Key 0 Used Status\nNote: When chip is in RMA stage this bit will be set to 1 and key is revoked after initialization if key is existed." "0: OTP key 0 is unused,1: OTP key 0 is used"
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rgroup.long 0xF0++0x3
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line.long 0x0 "KS_RSTERR,Key Store Reset Error Register"
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bitfld.long 0x0 30.--31. "DST,Key Location\nThese bits shows what DST(KS_METADATA[31:30]) is being executed before reset." "0,1,2,3"
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hexmask.long.byte 0x0 20.--25. 1. "NUMBER,Key Number\nThese bits shows what NUMBER(KS_METADATA[25:20]) is being executed before reset."
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bitfld.long 0x0 16.--18. "OWNER,Key Owner Selection\nThese bits shows what OWNER(KS_CTL[18:16]) is being executed before reset." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 1.--3. "OPMODE,Key Store Operation Mode\nThese bits shows what OPMODE(KS_CTL[3:1]) is being executed before reset." "0,1,2,3,4,5,6,7"
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tree.end
|
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tree "LPADC (Low Power Analog-to-Digital Converter)"
|
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base ad:0x400E3000
|
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rgroup.long 0x0++0x6B
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line.long 0x0 "LPADC_ADDR0,ADC Data Register 0"
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bitfld.long 0x0 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x0 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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|
line.long 0x4 "LPADC_ADDR1,ADC Data Register 1"
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bitfld.long 0x4 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x4 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x8 "LPADC_ADDR2,ADC Data Register 2"
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bitfld.long 0x8 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x8 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0xC "LPADC_ADDR3,ADC Data Register 3"
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bitfld.long 0xC 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0xC 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0xC 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x10 "LPADC_ADDR4,ADC Data Register 4"
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bitfld.long 0x10 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x10 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x10 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x14 "LPADC_ADDR5,ADC Data Register 5"
|
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bitfld.long 0x14 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x14 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
|
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hexmask.long.word 0x14 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x18 "LPADC_ADDR6,ADC Data Register 6"
|
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bitfld.long 0x18 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x18 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
|
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hexmask.long.word 0x18 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x1C "LPADC_ADDR7,ADC Data Register 7"
|
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bitfld.long 0x1C 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x1C 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
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newline
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hexmask.long.word 0x1C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x20 "LPADC_ADDR8,ADC Data Register 8"
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bitfld.long 0x20 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x20 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
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hexmask.long.word 0x20 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x24 "LPADC_ADDR9,ADC Data Register 9"
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|
bitfld.long 0x24 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x24 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
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hexmask.long.word 0x24 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x28 "LPADC_ADDR10,ADC Data Register 10"
|
|
bitfld.long 0x28 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
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bitfld.long 0x28 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
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hexmask.long.word 0x28 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x2C "LPADC_ADDR11,ADC Data Register 11"
|
|
bitfld.long 0x2C 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x2C 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
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newline
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hexmask.long.word 0x2C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x30 "LPADC_ADDR12,ADC Data Register 12"
|
|
bitfld.long 0x30 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
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bitfld.long 0x30 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x30 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x34 "LPADC_ADDR13,ADC Data Register 13"
|
|
bitfld.long 0x34 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x34 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x34 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x38 "LPADC_ADDR14,ADC Data Register 14"
|
|
bitfld.long 0x38 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x38 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x38 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x3C "LPADC_ADDR15,ADC Data Register 15"
|
|
bitfld.long 0x3C 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x3C 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x3C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x40 "LPADC_ADDR16,ADC Data Register 16"
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bitfld.long 0x40 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x40 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x40 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x44 "LPADC_ADDR17,ADC Data Register 17"
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bitfld.long 0x44 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x44 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x44 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x48 "LPADC_ADDR18,ADC Data Register 18"
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bitfld.long 0x48 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x48 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x48 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x4C "LPADC_ADDR19,ADC Data Register 19"
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bitfld.long 0x4C 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x4C 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x4C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x50 "LPADC_ADDR20,ADC Data Register 20"
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bitfld.long 0x50 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x50 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x50 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x54 "LPADC_ADDR21,ADC Data Register 21"
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bitfld.long 0x54 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x54 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x54 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x58 "LPADC_ADDR22,ADC Data Register 22"
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bitfld.long 0x58 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x58 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x58 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x5C "LPADC_ADDR23,ADC Data Register 23"
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bitfld.long 0x5C 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x5C 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x5C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x60 "LPADC_ADDR24,ADC Data Register 24"
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bitfld.long 0x60 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x60 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x60 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x64 "LPADC_ADDR25,ADC Data Register 25"
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bitfld.long 0x64 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x64 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x64 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x68 "LPADC_ADDR26,ADC Data Register 26"
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bitfld.long 0x68 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x68 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x68 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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rgroup.long 0x70++0xF
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line.long 0x0 "LPADC_ADDR28,ADC Data Register 28"
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bitfld.long 0x0 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x0 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x4 "LPADC_ADDR29,ADC Data Register 29"
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bitfld.long 0x4 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x4 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0x8 "LPADC_ADDR30,ADC Data Register 30"
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bitfld.long 0x8 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x8 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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line.long 0xC "LPADC_ADDR31,ADC Data Register 31"
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bitfld.long 0xC 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0xC 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0xC 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
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group.long 0x80++0x13
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line.long 0x0 "LPADC_ADCR,ADC Control Register"
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bitfld.long 0x0 31. "DMOF,Differential Input Mode Output Format\nIf user enables differential input mode the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format)." "0: A/D Conversion result will be filled in RSLT at..,1: A/D Conversion result will be filled in RSLT at.."
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bitfld.long 0x0 28.--29. "RESSEL,Resolution Select Bits" "0: ADC resolution 12 bits,1: ADC resolution 10 bits,?,?"
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bitfld.long 0x0 20.--21. "ACMPTES,ACMP Trigger Event Selection" "0: ACMP0/1/2 both edge event as trigger source,1: ACMP0/1/2 rising edge event as trigger source,?,?"
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hexmask.long.byte 0x0 16.--19. 1. "TRGS,Hardware Trigger Source\nNote 1: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits.\nNote 2: These trigger sources are only abaliable when chip is in run and idle mode."
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bitfld.long 0x0 12. "RESET,ADC RESET (Write Protect)\nIf user writes this bit the ADC analog macro will reset. Calibration data in macro will be deleted but registers LPADC will keep.\nNote: This bit is cleared by hardware." "0,1"
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bitfld.long 0x0 11. "ADST,A/D Conversion Start or Calibration Start\nADST bit can be set to 1 from four sources: software external pin LPADC0_ST PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode Single-cycle.." "0: Conversion stops and A/D converter enters idle..,1: Conversion starts or Calibration Start"
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bitfld.long 0x0 10. "DIFFEN,Differential Input Mode Control\nNote: In Differential Input mode only the even number of the two corresponding channels needs to be enabled in ADCHER register. The conversion result will be placed to the corresponding data register of the.." "0: Single-end analog input mode,1: Differential analog input mode"
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bitfld.long 0x0 9. "PTEN,LPPDMA Transfer Enable Bit\nWhen A/D conversion is completed the converted data is loaded into ADDR0~26 and ADDR28~ADDR31. Software can enable this bit to generate a LPPDMA data transfer request." "0: LPPDMA data transfer Disabled,1: LPPDMA data transfer in ADDR0~26 and.."
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bitfld.long 0x0 8. "TRGEN,External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external LPADC0_ST pin EPWM trigger PWM trigger ACMP interrupt event and Timer trigger. If external trigger is enabled the ADST bit can be set to 1 by the selected.." "0: External trigger Disabled,1: External trigger Enabled"
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bitfld.long 0x0 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin LPADC0_ST trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger." "0: Low level,1: High level,?,?"
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bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode Control\nNote 1: When changing the operation mode software should clear ADST bit first.\nNote 2: In Burst mode the A/D conversion result data is always at ADC Data Register 0." "0: Single conversion,1: When changing the operation mode,2: In Burst mode,?"
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bitfld.long 0x0 1. "ADIE,A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit is set to 1." "0: A/D conversion end interrupt function Disabled,1: A/D conversion end interrupt function Enabled"
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bitfld.long 0x0 0. "ADEN,A/D Converter Enable Bit\nNote: Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption." "0: A/D converter Disabled,1: A/D converter Enabled"
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line.long 0x4 "LPADC_ADCHER,ADC Channel Enable Register"
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hexmask.long 0x4 0.--31. 1. "CHEN,Analog Input Channel Enable Control\nSet ADCHER[23:0] bits to enable the corresponding analog external input channel 23 ~ 0. If DIFFEN bit is set to 1 only the even number channel needs to be enabled.\nBesides setting the ADCHER[26:24] bits will.."
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line.long 0x8 "LPADC_ADCMPR0,ADC Compare Register 0"
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hexmask.long.word 0x8 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format)."
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bitfld.long 0x8 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register." "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled"
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hexmask.long.byte 0x8 8.--11. 1. "CMPMCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1) the CMPFx.."
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hexmask.long.byte 0x8 3.--7. 1. "CMPCH,Compare Channel Selection"
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bitfld.long 0x8 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches to (CMPMCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x8 1. "CMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT CMPFx bit will be asserted in the meanwhile if CMPIE bit is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x8 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable LPADC to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register." "0: Compare function Disabled,1: Compare function Enabled"
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line.long 0xC "LPADC_ADCMPR1,ADC Compare Register 1"
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hexmask.long.word 0xC 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format)."
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bitfld.long 0xC 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register." "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled"
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hexmask.long.byte 0xC 8.--11. 1. "CMPMCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1) the CMPFx.."
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hexmask.long.byte 0xC 3.--7. 1. "CMPCH,Compare Channel Selection"
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bitfld.long 0xC 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches to (CMPMCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0xC 1. "CMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT CMPFx bit will be asserted in the meanwhile if CMPIE bit is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0xC 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable LPADC to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register." "0: Compare function Disabled,1: Compare function Enabled"
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line.long 0x10 "LPADC_ADSR0,ADC Status Register0"
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hexmask.long.byte 0x10 27.--31. 1. "CHANNEL,Current Conversion Channel (Read Only)"
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rbitfld.long 0x10 24. "ADPRDY,ADC Power On Ready (Read Only)\nAfter set ADEN (LPADC_ADCR[0]) to 1 the ADPRDY will set to 1 within one PCLK2 clock period. Then ADC macro can start convet.\nThe chip also support ALDO when chip want to do A/D conversion under chip power level is.." "0,1"
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rbitfld.long 0x10 16. "OVERRUNF,Overrun Flag (Read Only)\nIf any one of OVERRUN (ADDRx[16]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and the FIFO is overrun this flag will be set to 1." "0,1"
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rbitfld.long 0x10 8. "VALIDF,Data Valid Flag (Read Only)\nIf any one of VALID (ADDRx[17]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and any conversion result is valid this flag will be set to 1." "0,1"
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rbitfld.long 0x10 7. "BUSY,BUSY/IDLE (Read Only)\nThis bit is a mirror of ADST bit in ADCR register." "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
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bitfld.long 0x10 2. "CMPF1,Compare Flag 1\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register this bit is set to 1; it is cleared by writing 1 to it" "0: Conversion result in ADDR does not meet ADCMPR1..,1: Conversion result in ADDR meets ADCMPR1 setting"
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bitfld.long 0x10 1. "CMPF0,Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it." "0: Conversion result in ADDR does not meet ADCMPR0..,1: Conversion result in ADDR meets ADCMPR0 setting"
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bitfld.long 0x10 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.\nThe ADF bit is set to 1 at the following three conditions:\nWhen A/D conversion ends in Single mode.\nWhen A/D conversion ends.." "0,1"
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rgroup.long 0x94++0x7
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line.long 0x0 "LPADC_ADSR1,ADC Status Register1"
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hexmask.long 0x0 0.--31. 1. "VALID,Data Valid Flag (Read Only)\nVALID[31 30 29 28 26 25 24 23:0] are the mirror of the VALID bits in ADDR31[17] ADDR30[17] ADDR29[17] ADDR28[17] ADDR26[17] ADDR25[17] ADDR24[17] ADDR23[17]~ ADDR0[17]. The other bits are reserved.\nNote:.."
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line.long 0x4 "LPADC_ADSR2,ADC Status Register2"
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hexmask.long 0x4 0.--31. 1. "OVERRUN,Overrun Flag (Read Only)\nOVERRUN[31 30 29 28 26 25 24 23:0] are the mirror of the OVERRUN bit in ADDR31[16] ADDR30[16] ADDR29[16] ADDR28[16] ADDR26[16] ADDR25[16] ADDR24[16] ADDR23[16] ~ ADDR0[16]. The other bits are reserved."
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group.long 0xA0++0x7
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line.long 0x0 "LPADC_ESMPCTL,ADC Extend Sample Time Control Register"
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hexmask.long.word 0x0 0.--13. 1. "EXTSMPT,ADC Sampling Time Extend \nWhen A/D conversion at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
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line.long 0x4 "LPADC_CFDCTL,ADC Channel Floating Detect Control Register"
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bitfld.long 0x4 8. "FDETCHEN,Floating Detect Channel Enable Bit" "0: Floating Detect Channel Disabled,1: Floating Detect Channel Enabled"
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bitfld.long 0x4 1. "DISCHEN,Discharge Enable Bit\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enabled." "0: Channel discharge Disabled,1: Channel discharge Enabled"
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bitfld.long 0x4 0. "PRECHEN,Precharge Enable Bit\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enabled." "0: Channel precharge Disabled,1: Channel precharge Enabled"
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rgroup.long 0x100++0x3
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line.long 0x0 "LPADC_ADPDMA,ADC LPPDMA Current Transfer Data Register"
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hexmask.long.tbyte 0x0 0.--17. 1. "CURDAT,ADC LPPDMA Current Transfer Data Register (Read Only)\nWhen LPPDMA transfers data reading the register can monitor the current LPPDMA transfer data.\nCurrent LPPDMA transfer data could be the content of ADDR0 ~ ADDR23 ADDR24 ADDR25 ADDR26 .."
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group.long 0x180++0x7
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line.long 0x0 "LPADC_ADCAL,ADC Calibration Mode Register"
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bitfld.long 0x0 1. "CALIE,Calibration Interrupt Enable Bit\nIf calibration function is enabled and the calibration is finished CALIF bit will be asserted in the meanwhile if CALIE bit is set to 1 a calibration interrupt request is generated." "0: Calibration function Interrupt Disabled,1: Calibration function Interrupt Enabled"
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bitfld.long 0x0 0. "CALEN,Calibration Function Enable Bit\nNote: If chip is powered off calibration function should be executed again." "0: Calibration function Disabled,?"
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line.long 0x4 "LPADC_ADCALSTS,ADC Calibration Status Register"
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bitfld.long 0x4 0. "CALIF,Calibration Finish Interrupt Flag\nIf calibration is finished this flag will be set to 1. It is cleared by writing 1 to it." "0,1"
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group.long 0x800++0x3
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line.long 0x0 "LPADC_AUTOCTL,ADC Auto Operation Control Register"
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bitfld.long 0x0 31. "AUTOEN,Automatic Operation Mode Enable Bit" "0: LPADC automatic operation Disabled,1: LPADC automatic operation Enabled"
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bitfld.long 0x0 10. "CMP1WKEN,Automatic Operation Mode Comparator 1 Wake-up Enable Bit" "0: LPADC automatic operation comparator 1 wake-up..,1: LPADC automatic operation comparator 1 wake-up.."
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bitfld.long 0x0 9. "CMP0WKEN,Automatic Operation Mode Comparator 0 Wake-up Enable Bit" "0: LPADC automatic operation comparator 0 wake-up..,1: LPADC automatic operation comparator 0 wake-up.."
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bitfld.long 0x0 8. "ADWKEN,Automatic Operation Mode Conversion End Wake-up Enable Bit" "0: LPADC automatic operation conversion end wake-up..,1: LPADC automatic operation conversion end wake-up.."
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bitfld.long 0x0 4. "TRIGEN,Automatic Operation Trigger Enable Bit\nWhen automatic operation mode is enabled the LPADC will start working if LPADC is triggered by a event sent from the trigger source selected by TRIGSEL[3:0] after this bit is set to 1." "0: LPADC Automatic Operation Trigger Disabled,1: LPADC Automatic Operation Trigger Enabled"
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hexmask.long.byte 0x0 0.--3. 1. "TRIGSEL,Automatic Operation Trigger Source Select\nNote: TRIGSEL cannot be changed when TRIGEN is 1."
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wgroup.long 0x804++0x3
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line.long 0x0 "LPADC_AUTOSTRG,ADC Auto Operation Software Trigger Register"
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bitfld.long 0x0 0. "SWTRIG,Automatic Operation Software Trigger Bit\nWrite 1 to this bit will trigger LPADC start automatic operation.\nNote: This bit will be auto cleared by hardware." "0,1"
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group.long 0x810++0x3
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line.long 0x0 "LPADC_AUTOSTS,ADC Auto Operation Status Register"
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bitfld.long 0x0 2. "CMP1WKF,Automatic Operation Compare 1 Wake-up Flag Bit\nWhen automatic operation mode is enabled and the conversion result monitor comparator 0 is match setting criteria this flag will be set. If CMP0WKEN is also set to 1 the chip will be woken.." "0,1"
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bitfld.long 0x0 1. "CMP0WKF,Automatic Operation Compare 0 Wake-up Flag Bit\nWhen automatic operation mode is enabled and the conversion result monitor comparator 1 matches setting criteria this flag will be set. If CMP1WKEN is also set to 1 the chip will be woken.." "0,1"
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bitfld.long 0x0 0. "ADWKF,Automatic Operation Conversion End Wake-up Flag Bit\nWhen automatic operation mode is enabled and the conversion is finished this flag will be set. If WKEN is also set to 1 the chip will be woken up.\nNote: Software can write 1 to clear this bit." "0,1"
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group.long 0xFEC++0x3
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line.long 0x0 "LPADC_ALDOCTL,ADC ALDO Control Register"
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bitfld.long 0x0 23. "IGENEN,ALDO Enable under IGEN Enable Bit\nNote: When ALDO enable under IGEN enable the ALDO stable time is shorter." "0: ALDO enable under IGEN Disabled,1: ALDO enable under IGEN Enabled"
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bitfld.long 0x0 16.--18. "STBSEL,ALDO Stable Count Select Bits\nIf IGENEN (ALDOCTL[23]) is 0 the ALDO stable count is as follows." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8. "ALDOEN,ALDO Enable Bit\nNote 1: After ADEN (LPADC_ADCR[0]) is enabled the ALDOEN cannot be changed.\nNote 2: ALDO can be enabled only when the chip runs at power level 3 (PL3) or NPD2/4 or NPD0/1/3 with power level 3. When the chip runs at power level 1.." "0: ALDO Disabled,1: After ADEN"
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tree.end
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tree "LPGPIO (Low Power General Purpose I/O)"
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base ad:0x4003A000
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group.long 0x0++0x7
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line.long 0x0 "LPGPIO_MODE,LPIOn Mode Control"
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bitfld.long 0x0 31. "LPPDMA_EN,LPPDMA Enable Bit\nThis bit is used to enable LPPDMA to access LPGPIO when chip is in NPD0/1/2/3/4." "0: LPPDMA cannot access LPGPIO when chip is in..,1: LPPDMA can access LPGPIO when chip is in.."
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bitfld.long 0x0 7. "MODE7,LPIOn I/O Pin Mode Control\nDetermine each I/O mode of LPIOn pins." "0: LPIOn is in Input mode,1: LPIOn is in Push-pull Output mode"
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bitfld.long 0x0 6. "MODE6,LPIOn I/O Pin Mode Control\nDetermine each I/O mode of LPIOn pins." "0: LPIOn is in Input mode,1: LPIOn is in Push-pull Output mode"
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bitfld.long 0x0 5. "MODE5,LPIOn I/O Pin Mode Control\nDetermine each I/O mode of LPIOn pins." "0: LPIOn is in Input mode,1: LPIOn is in Push-pull Output mode"
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bitfld.long 0x0 4. "MODE4,LPIOn I/O Pin Mode Control\nDetermine each I/O mode of LPIOn pins." "0: LPIOn is in Input mode,1: LPIOn is in Push-pull Output mode"
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bitfld.long 0x0 3. "MODE3,LPIOn I/O Pin Mode Control\nDetermine each I/O mode of LPIOn pins." "0: LPIOn is in Input mode,1: LPIOn is in Push-pull Output mode"
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bitfld.long 0x0 2. "MODE2,LPIOn I/O Pin Mode Control\nDetermine each I/O mode of LPIOn pins." "0: LPIOn is in Input mode,1: LPIOn is in Push-pull Output mode"
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bitfld.long 0x0 1. "MODE1,LPIOn I/O Pin Mode Control\nDetermine each I/O mode of LPIOn pins." "0: LPIOn is in Input mode,1: LPIOn is in Push-pull Output mode"
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bitfld.long 0x0 0. "MODE0,LPIOn I/O Pin Mode Control\nDetermine each I/O mode of LPIOn pins." "0: LPIOn is in Input mode,1: LPIOn is in Push-pull Output mode"
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line.long 0x4 "LPGPIO_DOUT,LPIOn Data Output Value"
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bitfld.long 0x4 7. "DOUT7,LPIOn Output Value\nEach of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode." "0: LPIOn will drive Low if the LPIOn pin is..,1: LPIOn will drive High if the LPIOn pin is.."
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bitfld.long 0x4 6. "DOUT6,LPIOn Output Value\nEach of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode." "0: LPIOn will drive Low if the LPIOn pin is..,1: LPIOn will drive High if the LPIOn pin is.."
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bitfld.long 0x4 5. "DOUT5,LPIOn Output Value\nEach of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode." "0: LPIOn will drive Low if the LPIOn pin is..,1: LPIOn will drive High if the LPIOn pin is.."
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bitfld.long 0x4 4. "DOUT4,LPIOn Output Value\nEach of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode." "0: LPIOn will drive Low if the LPIOn pin is..,1: LPIOn will drive High if the LPIOn pin is.."
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bitfld.long 0x4 3. "DOUT3,LPIOn Output Value\nEach of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode." "0: LPIOn will drive Low if the LPIOn pin is..,1: LPIOn will drive High if the LPIOn pin is.."
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bitfld.long 0x4 2. "DOUT2,LPIOn Output Value\nEach of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode." "0: LPIOn will drive Low if the LPIOn pin is..,1: LPIOn will drive High if the LPIOn pin is.."
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bitfld.long 0x4 1. "DOUT1,LPIOn Output Value\nEach of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode." "0: LPIOn will drive Low if the LPIOn pin is..,1: LPIOn will drive High if the LPIOn pin is.."
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bitfld.long 0x4 0. "DOUT0,LPIOn Output Value\nEach of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode." "0: LPIOn will drive Low if the LPIOn pin is..,1: LPIOn will drive High if the LPIOn pin is.."
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rgroup.long 0x8++0x3
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line.long 0x0 "LPGPIO_PIN,LPIOn Pin Value"
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bitfld.long 0x0 7. "PIN7,LPIOn Pin Value\nEach bit of the register reflects the actual status of the respective Pn pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low." "0,1"
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bitfld.long 0x0 6. "PIN6,LPIOn Pin Value\nEach bit of the register reflects the actual status of the respective Pn pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low." "0,1"
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bitfld.long 0x0 5. "PIN5,LPIOn Pin Value\nEach bit of the register reflects the actual status of the respective Pn pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low." "0,1"
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bitfld.long 0x0 4. "PIN4,LPIOn Pin Value\nEach bit of the register reflects the actual status of the respective Pn pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low." "0,1"
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bitfld.long 0x0 3. "PIN3,LPIOn Pin Value\nEach bit of the register reflects the actual status of the respective Pn pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low." "0,1"
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bitfld.long 0x0 2. "PIN2,LPIOn Pin Value\nEach bit of the register reflects the actual status of the respective Pn pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low." "0,1"
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bitfld.long 0x0 1. "PIN1,LPIOn Pin Value\nEach bit of the register reflects the actual status of the respective Pn pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low." "0,1"
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bitfld.long 0x0 0. "PIN0,LPIOn Pin Value\nEach bit of the register reflects the actual status of the respective Pn pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low." "0,1"
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wgroup.long 0xC++0x7
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line.long 0x0 "LPGPIO_DSRST,LPIOn Data Output Set and Reset Control"
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bitfld.long 0x0 23. "DRESET7,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n].." "0: No action,1: This bit field is write only"
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bitfld.long 0x0 22. "DRESET6,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n].." "0: No action,1: This bit field is write only"
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bitfld.long 0x0 21. "DRESET5,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n].." "0: No action,1: This bit field is write only"
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bitfld.long 0x0 20. "DRESET4,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n].." "0: No action,1: This bit field is write only"
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bitfld.long 0x0 19. "DRESET3,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n].." "0: No action,1: This bit field is write only"
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bitfld.long 0x0 18. "DRESET2,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n].." "0: No action,1: This bit field is write only"
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newline
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bitfld.long 0x0 17. "DRESET1,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n].." "0: No action,1: This bit field is write only"
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bitfld.long 0x0 16. "DRESET0,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n].." "0: No action,1: This bit field is write only"
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newline
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bitfld.long 0x0 7. "DSET7,LPIOn Data Ouput Set Control (Write Only)\nWriting 1 to each bit can set LPIOn pin output data to 1.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n] has.." "0: No action,1: This bit field is write only"
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bitfld.long 0x0 6. "DSET6,LPIOn Data Ouput Set Control (Write Only)\nWriting 1 to each bit can set LPIOn pin output data to 1.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n] has.." "0: No action,1: This bit field is write only"
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bitfld.long 0x0 5. "DSET5,LPIOn Data Ouput Set Control (Write Only)\nWriting 1 to each bit can set LPIOn pin output data to 1.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n] has.." "0: No action,1: This bit field is write only"
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bitfld.long 0x0 4. "DSET4,LPIOn Data Ouput Set Control (Write Only)\nWriting 1 to each bit can set LPIOn pin output data to 1.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n] has.." "0: No action,1: This bit field is write only"
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newline
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bitfld.long 0x0 3. "DSET3,LPIOn Data Ouput Set Control (Write Only)\nWriting 1 to each bit can set LPIOn pin output data to 1.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n] has.." "0: No action,1: This bit field is write only"
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bitfld.long 0x0 2. "DSET2,LPIOn Data Ouput Set Control (Write Only)\nWriting 1 to each bit can set LPIOn pin output data to 1.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n] has.." "0: No action,1: This bit field is write only"
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newline
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bitfld.long 0x0 1. "DSET1,LPIOn Data Ouput Set Control (Write Only)\nWriting 1 to each bit can set LPIOn pin output data to 1.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n] has.." "0: No action,1: This bit field is write only"
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bitfld.long 0x0 0. "DSET0,LPIOn Data Ouput Set Control (Write Only)\nWriting 1 to each bit can set LPIOn pin output data to 1.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : If DRESET[n] and DSET[n] are both set DSET[n] has.." "0: No action,1: This bit field is write only"
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line.long 0x4 "LPGPIO_DRST,LPIOn Data Output Reset Control"
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bitfld.long 0x4 7. "DRESET7,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : Writing 1 to DRESET[n] will make DOUT[n].." "0: No action,1: This bit field is write only"
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bitfld.long 0x4 6. "DRESET6,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : Writing 1 to DRESET[n] will make DOUT[n].." "0: No action,1: This bit field is write only"
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newline
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bitfld.long 0x4 5. "DRESET5,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : Writing 1 to DRESET[n] will make DOUT[n].." "0: No action,1: This bit field is write only"
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bitfld.long 0x4 4. "DRESET4,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : Writing 1 to DRESET[n] will make DOUT[n].." "0: No action,1: This bit field is write only"
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newline
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bitfld.long 0x4 3. "DRESET3,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : Writing 1 to DRESET[n] will make DOUT[n].." "0: No action,1: This bit field is write only"
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bitfld.long 0x4 2. "DRESET2,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : Writing 1 to DRESET[n] will make DOUT[n].." "0: No action,1: This bit field is write only"
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newline
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bitfld.long 0x4 1. "DRESET1,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : Writing 1 to DRESET[n] will make DOUT[n].." "0: No action,1: This bit field is write only"
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bitfld.long 0x4 0. "DRESET0,LPIOn Data Ouput Reset Control (Write Only)\nWriting 1 to each bit can reset LPIOn pin output data to 0.\nNote 1 : This bit field is write only and reading this field will respond with 0.\nNote 2 : Writing 1 to DRESET[n] will make DOUT[n].." "0: No action,1: This bit field is write only"
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tree.end
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tree "LPI2C (Low Power Inter-Integrated Circuit)"
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base ad:0x400E2000
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group.long 0x0++0xB
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line.long 0x0 "LPI2C_CTL0,LPI2C Control Register 0"
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bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: LPI2C interrupt Disabled,1: LPI2C interrupt Enabled"
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bitfld.long 0x0 6. "LPI2CEN,LPI2C Controller Enable Bit" "0: LPI2C controller Disabled,1: LPI2C controller Enabled"
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newline
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bitfld.long 0x0 5. "STA,LPI2C START Control\nSetting STA to logic 1 to enter Master mode the LPI2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,LPI2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then LPI2C will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
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bitfld.long 0x0 3. "SI,LPI2C Interrupt Flag\nWhen a new LPI2C state is present in the LPI2C_STATUS0 register the SI flag is set by hardware. If bit INTEN (LPI2C_CTL0 [7]) is set the LPI2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
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line.long 0x4 "LPI2C_ADDR0,LPI2C Slave Address Register0"
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hexmask.long.byte 0x4 1.--7. 1. "ADDR,LPI2C Address \nThe content of this register is irrelevant when LPI2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The LPI2C hardware will react if either of the address is.."
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bitfld.long 0x4 0. "GC,General Call Function" "0: General Call function Disabled,1: General Call function Enabled"
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line.long 0x8 "LPI2C_DAT,LPI2C Data Register"
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hexmask.long.byte 0x8 0.--7. 1. "DAT,LPI2C Data \nBit [7:0] is located with the 8-bit transferred/received data of LPI2C serial port."
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rgroup.long 0xC++0x3
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line.long 0x0 "LPI2C_STATUS0,LPI2C Status Register 0"
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hexmask.long.byte 0x0 0.--7. 1. "STATUS,LPI2C Status"
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group.long 0x10++0x23
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line.long 0x0 "LPI2C_CLKDIV,LPI2C Clock Divided Register"
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hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width. If the pulse width is narrower than the setting((3+N)*PCLK) it will be ignored.\nNote: Filter width Min :3*PCLK Max : 18*PCLK"
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hexmask.long.word 0x0 0.--9. 1. "DIVIDER,LPI2C Clock Divider\nNote: The minimum value of DIVIDER is 4."
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line.long 0x4 "LPI2C_TOCTL,LPI2C Time-out Control Register"
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bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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newline
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when LPI2C time-out happened and it can interrupt CPU if LPI2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "LPI2C_ADDR1,LPI2C Slave Address Register1"
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hexmask.long.byte 0x8 1.--7. 1. "ADDR,LPI2C Address \nThe content of this register is irrelevant when LPI2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The LPI2C hardware will react if either of the address is.."
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bitfld.long 0x8 0. "GC,General Call Function" "0: General Call function Disabled,1: General Call function Enabled"
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line.long 0xC "LPI2C_ADDR2,LPI2C Slave Address Register2"
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hexmask.long.byte 0xC 1.--7. 1. "ADDR,LPI2C Address \nThe content of this register is irrelevant when LPI2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The LPI2C hardware will react if either of the address is.."
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bitfld.long 0xC 0. "GC,General Call Function" "0: General Call function Disabled,1: General Call function Enabled"
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line.long 0x10 "LPI2C_ADDR3,LPI2C Slave Address Register3"
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hexmask.long.byte 0x10 1.--7. 1. "ADDR,LPI2C Address \nThe content of this register is irrelevant when LPI2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The LPI2C hardware will react if either of the address is.."
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bitfld.long 0x10 0. "GC,General Call Function" "0: General Call function Disabled,1: General Call function Enabled"
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line.long 0x14 "LPI2C_ADDRMSK0,LPI2C Slave Address Mask Register0"
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hexmask.long.byte 0x14 1.--7. 1. "ADDRMSK,LPI2C Address Mask\nLPI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is.."
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line.long 0x18 "LPI2C_ADDRMSK1,LPI2C Slave Address Mask Register1"
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hexmask.long.byte 0x18 1.--7. 1. "ADDRMSK,LPI2C Address Mask\nLPI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is.."
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line.long 0x1C "LPI2C_ADDRMSK2,LPI2C Slave Address Mask Register2"
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hexmask.long.byte 0x1C 1.--7. 1. "ADDRMSK,LPI2C Address Mask\nLPI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is.."
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line.long 0x20 "LPI2C_ADDRMSK3,LPI2C Slave Address Mask Register3"
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hexmask.long.byte 0x20 1.--7. 1. "ADDRMSK,LPI2C Address Mask\nLPI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is.."
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group.long 0x3C++0x13
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line.long 0x0 "LPI2C_WKCTL,LPI2C Wake-up Control Register"
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bitfld.long 0x0 7. "NHDBUSEN,LPI2C No Hold BUS Enable Bit\nNote: LPI2C could respond when WKIF event is not clear it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear user must reset LPI2C and execute the original.." "0: LPI2C hold bus after wake-up,1: LPI2C didn't hold bus after wake-up"
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bitfld.long 0x0 0. "WKEN,LPI2C Wake-up Enable Bit\nNote: This is for slave address match wakeup." "0: LPI2C wake-up function Disabled,1: LPI2C wake-up function Enabled"
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line.long 0x4 "LPI2C_WKSTS,LPI2C Wake-up Status Register"
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bitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit cannot release WKIF. Software can write 1 to clear this bit." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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newline
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bitfld.long 0x4 0. "WKIF,LPI2C Wake-up Flag\nWhen chip is woken up from Power-down mode by LPI2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "LPI2C_CTL1,LPI2C Control Register 1"
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bitfld.long 0x8 10. "SWITCHEN,SCL And SDA Pin Switch Enable Bit\nNote: Original pin configuration table is shown in Basic Configuration chapter." "0: LPI2C use original pin configuration,1: LPI2C switch SCL and SDA pin configuration"
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bitfld.long 0x8 8. "PDMASTR,LPPDMA Stretch Bit" "0: LPI2C send STOP automatically after LPPDMA..,1: LPI2C SCL bus is stretched by hardware after.."
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newline
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bitfld.long 0x8 2. "PDMARST,LPPDMA Reset" "0: No effect,1: Reset the LPI2C request to LPPDMA"
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bitfld.long 0x8 1. "RXPDMAEN,LPPDMA Receive Channel Available" "0: Receive LPPDMA function Disabled,1: Receive LPPDMA function Enabled"
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newline
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bitfld.long 0x8 0. "TXPDMAEN,LPPDMA Transmit Channel Available" "0: Transmit LPPDMA function Disabled,1: Transmit LPPDMA function Enabled"
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line.long 0xC "LPI2C_STATUS1,LPI2C Status Register 1"
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rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
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bitfld.long 0xC 3. "ADMAT3,LPI2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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newline
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bitfld.long 0xC 2. "ADMAT2,LPI2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 1. "ADMAT1,LPI2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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newline
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bitfld.long 0xC 0. "ADMAT0,LPI2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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line.long 0x10 "LPI2C_TMCTL,LPI2C Timing Configure Control Register"
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hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
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hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
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group.long 0x70++0xB
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line.long 0x0 "LPI2C_AUTOCTL,LPI2C Automatic Operation Control Register"
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bitfld.long 0x0 31. "SWTRG,Auto-operation Mode Software Trigger Bit\nNote: TGSRCSEL(LPI2C_AUTOCTL[3:0]) need to be set to 0x8 first" "0: No operation,1: Software trigger auto-operattion"
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bitfld.long 0x0 8.--10. "AUTOMODE,Auto-operation Mode Select" "0: No auto-operation,1: Auto TXPDMA transfer mode,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 7. "NACKWKEN,Receive Slave NACK Wakeup Enable bit" "0: Stop after receiving NACK,1: Wakeup after receiving NACK"
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bitfld.long 0x0 6. "RXWKEN,RX Transfer Count Match Wakeup Enable bit" "0: Power off after RX transfer count matches RXCNT,1: Wakeup after RX transfer count matches RXCNT"
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newline
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bitfld.long 0x0 5. "TXWKEN,TX Transfer Count Match Wakeup Enable bit" "0: Power off after TX transfer count matches TXCNT,1: Wakeup after TX transfer count matches TXCNT"
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bitfld.long 0x0 4. "TRGEN,Trigger Source Enable bit" "0: LPIC trigger source disable,1: LPIC trigger source enable"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "TGSRCSEL,Low Power Auto-operation Trigger Source Select"
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line.long 0x4 "LPI2C_AUTOSTS,LPI2C Automatic Operation Status Register"
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bitfld.long 0x4 31. "BUSY,Busy Flag\nWhen chip is woken up and this bit is set to 1 it means that there are one or more requests from trigger source during transfer. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 24. "AOFINISH,Automatic Operation Finish Flag\nAOFINISH is set when finishing one round of auto operation but it will not issue interrupt. Software can write 1 to clear this bit." "0,1"
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newline
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bitfld.long 0x4 10. "ERRORIF,ERROR Interrupt Flag\nWhen LPI2C receiving NACK from slave running into bus error or arbitration lost this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 9. "RXFINISH,Automatic Operation RX Finish Flag" "0,1"
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newline
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bitfld.long 0x4 8. "TXFINISH,Automatic Operation TX Finish Flag" "0,1"
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bitfld.long 0x4 2. "ERRORWKF,Error Condition Wakeup Flag\nWhen chip is woken up from Power-down mode by LPI2C receiving NACK from slave running into bus error or arbitration lost this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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newline
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bitfld.long 0x4 1. "RXWKF,RX Transfer Count Match Wakeup Flag\nWhen chip is woken up from Power-down mode by LPI2C RX transfer count match this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 0. "TXWKF,TX Transfer Count Match Wakeup Flag\nWhen chip is woken up from Power-down mode by LPI2C TX transfer count match this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "LPI2C_AUTOCNT,LPI2C Automatic Operation Transfer Count Register"
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hexmask.long.byte 0x8 16.--23. 1. "RXCNT,RX Transfer Count\nBit [23:16] is set for RXPDMA and Random Read transfer mode. RXCNT represents the required number of the transfer the real transfer count is RXCNT + 1. The maximum transfer count is 255 + 1."
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hexmask.long.byte 0x8 0.--7. 1. "TXCNT,TX Transfer Count\nBit [7:0] is set for TXPDMA and Random Read transfer mode. TXCNT represents the required number of the transfer the real transfer count is TXCNT + 1. The maximum transfer count is 255 + 1."
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tree.end
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tree "LPPDMA (Low Power PDMA Controller)"
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base ad:0x40039000
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group.long 0x0++0x3
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line.long 0x0 "LPPDMAx_DSCT0_CTL,Descriptor Table Control Register of LPPDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of LPPDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: LPPDMA transfer source address (LPPDMA_DSCTn_SA) and LPPDMA transfer destination address (LPPDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (LPPDMA_TDSTS[3:0]) when LPPDMA finishes transfer task.\nNote: This function only for.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,LPPDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check LPPDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x10++0x3
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line.long 0x0 "LPPDMAx_DSCT1_CTL,Descriptor Table Control Register of LPPDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of LPPDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: LPPDMA transfer source address (LPPDMA_DSCTn_SA) and LPPDMA transfer destination address (LPPDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (LPPDMA_TDSTS[3:0]) when LPPDMA finishes transfer task.\nNote: This function only for.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,LPPDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check LPPDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x20++0x3
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line.long 0x0 "LPPDMAx_DSCT2_CTL,Descriptor Table Control Register of LPPDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of LPPDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: LPPDMA transfer source address (LPPDMA_DSCTn_SA) and LPPDMA transfer destination address (LPPDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (LPPDMA_TDSTS[3:0]) when LPPDMA finishes transfer task.\nNote: This function only for.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,LPPDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check LPPDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x30++0x3
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line.long 0x0 "LPPDMAx_DSCT3_CTL,Descriptor Table Control Register of LPPDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of LPPDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: LPPDMA transfer source address (LPPDMA_DSCTn_SA) and LPPDMA transfer destination address (LPPDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (LPPDMA_TDSTS[3:0]) when LPPDMA finishes transfer task.\nNote: This function only for.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,LPPDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check LPPDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x4++0x3
|
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line.long 0x0 "LPPDMAx_DSCT0_SA,Source Address Register of LPPDMA Channel n"
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hexmask.long 0x0 0.--31. 1. "SA,LPPDMA Transfer Source Address\nThis field indicates a 32-bit source address of LPPDMA."
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group.long 0x14++0x3
|
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line.long 0x0 "LPPDMAx_DSCT1_SA,Source Address Register of LPPDMA Channel n"
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hexmask.long 0x0 0.--31. 1. "SA,LPPDMA Transfer Source Address\nThis field indicates a 32-bit source address of LPPDMA."
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group.long 0x24++0x3
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line.long 0x0 "LPPDMAx_DSCT2_SA,Source Address Register of LPPDMA Channel n"
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hexmask.long 0x0 0.--31. 1. "SA,LPPDMA Transfer Source Address\nThis field indicates a 32-bit source address of LPPDMA."
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group.long 0x34++0x3
|
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line.long 0x0 "LPPDMAx_DSCT3_SA,Source Address Register of LPPDMA Channel n"
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hexmask.long 0x0 0.--31. 1. "SA,LPPDMA Transfer Source Address\nThis field indicates a 32-bit source address of LPPDMA."
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group.long 0x8++0x3
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line.long 0x0 "LPPDMAx_DSCT0_DA,Destination Address Register of LPPDMA Channel n"
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hexmask.long 0x0 0.--31. 1. "DA,LPPDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of LPPDMA."
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group.long 0x18++0x3
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line.long 0x0 "LPPDMAx_DSCT1_DA,Destination Address Register of LPPDMA Channel n"
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hexmask.long 0x0 0.--31. 1. "DA,LPPDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of LPPDMA."
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group.long 0x28++0x3
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line.long 0x0 "LPPDMAx_DSCT2_DA,Destination Address Register of LPPDMA Channel n"
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hexmask.long 0x0 0.--31. 1. "DA,LPPDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of LPPDMA."
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group.long 0x38++0x3
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line.long 0x0 "LPPDMAx_DSCT3_DA,Destination Address Register of LPPDMA Channel n"
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hexmask.long 0x0 0.--31. 1. "DA,LPPDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of LPPDMA."
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group.long 0xC++0x3
|
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line.long 0x0 "LPPDMAx_DSCT0_NEXT,Next Scatter-gather Descriptor Table Offset Address of LPPDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "EXENEXT,LPPDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
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hexmask.long.word 0x0 0.--15. 1. "NEXT,LPPDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2800_0000 (LPPDMA_SCATBA) and the next descriptor table is start.."
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group.long 0x1C++0x3
|
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line.long 0x0 "LPPDMAx_DSCT1_NEXT,Next Scatter-gather Descriptor Table Offset Address of LPPDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "EXENEXT,LPPDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
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hexmask.long.word 0x0 0.--15. 1. "NEXT,LPPDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2800_0000 (LPPDMA_SCATBA) and the next descriptor table is start.."
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group.long 0x2C++0x3
|
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line.long 0x0 "LPPDMAx_DSCT2_NEXT,Next Scatter-gather Descriptor Table Offset Address of LPPDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "EXENEXT,LPPDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
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hexmask.long.word 0x0 0.--15. 1. "NEXT,LPPDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2800_0000 (LPPDMA_SCATBA) and the next descriptor table is start.."
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group.long 0x3C++0x3
|
|
line.long 0x0 "LPPDMAx_DSCT3_NEXT,Next Scatter-gather Descriptor Table Offset Address of LPPDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,LPPDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
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hexmask.long.word 0x0 0.--15. 1. "NEXT,LPPDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2800_0000 (LPPDMA_SCATBA) and the next descriptor table is start.."
|
|
rgroup.long 0x40++0xF
|
|
line.long 0x0 "LPPDMAx_CURSCAT0,Current Scatter-gather Descriptor Table Address of LPPDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "CURADDR,LPPDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of LPPDMA.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description address."
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|
line.long 0x4 "LPPDMAx_CURSCAT1,Current Scatter-gather Descriptor Table Address of LPPDMA Channel n"
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hexmask.long 0x4 0.--31. 1. "CURADDR,LPPDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of LPPDMA.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description address."
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line.long 0x8 "LPPDMAx_CURSCAT2,Current Scatter-gather Descriptor Table Address of LPPDMA Channel n"
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hexmask.long 0x8 0.--31. 1. "CURADDR,LPPDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of LPPDMA.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description address."
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line.long 0xC "LPPDMAx_CURSCAT3,Current Scatter-gather Descriptor Table Address of LPPDMA Channel n"
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hexmask.long 0xC 0.--31. 1. "CURADDR,LPPDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of LPPDMA.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description address."
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group.long 0x400++0x3
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line.long 0x0 "LPPDMAx_CHCTL,LPPDMA Channel Control Register"
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bitfld.long 0x0 3. "CHEN3,LPPDMA Channel Enable Bits\nSet this bit to 1 to enable LPPDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of LPPDMA_PAUSE or LPPDMA_CHRST register will also clear this bit." "0: LPPDMA channel [n] Disabled,1: LPPDMA channel [n] Enabled"
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bitfld.long 0x0 2. "CHEN2,LPPDMA Channel Enable Bits\nSet this bit to 1 to enable LPPDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of LPPDMA_PAUSE or LPPDMA_CHRST register will also clear this bit." "0: LPPDMA channel [n] Disabled,1: LPPDMA channel [n] Enabled"
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bitfld.long 0x0 1. "CHEN1,LPPDMA Channel Enable Bits\nSet this bit to 1 to enable LPPDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of LPPDMA_PAUSE or LPPDMA_CHRST register will also clear this bit." "0: LPPDMA channel [n] Disabled,1: LPPDMA channel [n] Enabled"
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bitfld.long 0x0 0. "CHEN0,LPPDMA Channel Enable Bits\nSet this bit to 1 to enable LPPDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of LPPDMA_PAUSE or LPPDMA_CHRST register will also clear this bit." "0: LPPDMA channel [n] Disabled,1: LPPDMA channel [n] Enabled"
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wgroup.long 0x404++0x7
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line.long 0x0 "LPPDMAx_PAUSE,LPPDMA Transfer Pause Control Register"
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bitfld.long 0x0 3. "PAUSE3,LPPDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause LPPDMA channel n transfer"
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bitfld.long 0x0 2. "PAUSE2,LPPDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause LPPDMA channel n transfer"
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bitfld.long 0x0 1. "PAUSE1,LPPDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause LPPDMA channel n transfer"
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bitfld.long 0x0 0. "PAUSE0,LPPDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause LPPDMA channel n transfer"
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line.long 0x4 "LPPDMAx_SWREQ,LPPDMA Software Request Register"
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bitfld.long 0x4 3. "SWREQ3,LPPDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to LPPDMA [n].\nNote 1: User can read LPPDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read LPPDMAx_TRGSTS register to know.."
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bitfld.long 0x4 2. "SWREQ2,LPPDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to LPPDMA [n].\nNote 1: User can read LPPDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read LPPDMAx_TRGSTS register to know.."
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bitfld.long 0x4 1. "SWREQ1,LPPDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to LPPDMA [n].\nNote 1: User can read LPPDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read LPPDMAx_TRGSTS register to know.."
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bitfld.long 0x4 0. "SWREQ0,LPPDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to LPPDMA [n].\nNote 1: User can read LPPDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read LPPDMAx_TRGSTS register to know.."
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rgroup.long 0x40C++0x3
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line.long 0x0 "LPPDMAx_TRGSTS,LPPDMA Channel Request Status Register"
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bitfld.long 0x0 3. "REQSTS3,LPPDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When LPPDMA finishes channel transfer this bit will be cleared automatically. \nNote: If user.." "0: LPPDMA Channel n has no request,1: LPPDMA Channel n has a request"
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bitfld.long 0x0 2. "REQSTS2,LPPDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When LPPDMA finishes channel transfer this bit will be cleared automatically. \nNote: If user.." "0: LPPDMA Channel n has no request,1: LPPDMA Channel n has a request"
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bitfld.long 0x0 1. "REQSTS1,LPPDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When LPPDMA finishes channel transfer this bit will be cleared automatically. \nNote: If user.." "0: LPPDMA Channel n has no request,1: LPPDMA Channel n has a request"
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bitfld.long 0x0 0. "REQSTS0,LPPDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When LPPDMA finishes channel transfer this bit will be cleared automatically. \nNote: If user.." "0: LPPDMA Channel n has no request,1: LPPDMA Channel n has a request"
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group.long 0x410++0x3
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line.long 0x0 "LPPDMAx_PRISET,LPPDMA Fixed Priority Setting Register"
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bitfld.long 0x0 3. "FPRISET3,LPPDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use LPPDMA_PRICLR register." "0: No effect.\nCorresponding LPPDMA channel is..,1: Set LPPDMA channel [n] to fixed priority.."
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bitfld.long 0x0 2. "FPRISET2,LPPDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use LPPDMA_PRICLR register." "0: No effect.\nCorresponding LPPDMA channel is..,1: Set LPPDMA channel [n] to fixed priority.."
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bitfld.long 0x0 1. "FPRISET1,LPPDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use LPPDMA_PRICLR register." "0: No effect.\nCorresponding LPPDMA channel is..,1: Set LPPDMA channel [n] to fixed priority.."
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bitfld.long 0x0 0. "FPRISET0,LPPDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use LPPDMA_PRICLR register." "0: No effect.\nCorresponding LPPDMA channel is..,1: Set LPPDMA channel [n] to fixed priority.."
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wgroup.long 0x414++0x3
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line.long 0x0 "LPPDMAx_PRICLR,LPPDMA Fixed Priority Clear Register"
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bitfld.long 0x0 3. "FPRICLR3,LPPDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read LPPDMA_PRISET register to know the channel priority." "0: No effect,1: Clear LPPDMA channel [n] fixed priority setting"
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bitfld.long 0x0 2. "FPRICLR2,LPPDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read LPPDMA_PRISET register to know the channel priority." "0: No effect,1: Clear LPPDMA channel [n] fixed priority setting"
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bitfld.long 0x0 1. "FPRICLR1,LPPDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read LPPDMA_PRISET register to know the channel priority." "0: No effect,1: Clear LPPDMA channel [n] fixed priority setting"
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bitfld.long 0x0 0. "FPRICLR0,LPPDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read LPPDMA_PRISET register to know the channel priority." "0: No effect,1: Clear LPPDMA channel [n] fixed priority setting"
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group.long 0x418++0x13
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line.long 0x0 "LPPDMAx_INTEN,LPPDMA Interrupt Enable Register"
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bitfld.long 0x0 3. "INTEN3,LPPDMA Interrupt Enable Bits\nThis field is used to enable LPPDMA channel[n] interrupt.\nNote: The interrupt flag is abort transfer done and align." "0: LPPDMA channel n interrupt Disabled,1: LPPDMA channel n interrupt Enabled"
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bitfld.long 0x0 2. "INTEN2,LPPDMA Interrupt Enable Bits\nThis field is used to enable LPPDMA channel[n] interrupt.\nNote: The interrupt flag is abort transfer done and align." "0: LPPDMA channel n interrupt Disabled,1: LPPDMA channel n interrupt Enabled"
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bitfld.long 0x0 1. "INTEN1,LPPDMA Interrupt Enable Bits\nThis field is used to enable LPPDMA channel[n] interrupt.\nNote: The interrupt flag is abort transfer done and align." "0: LPPDMA channel n interrupt Disabled,1: LPPDMA channel n interrupt Enabled"
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bitfld.long 0x0 0. "INTEN0,LPPDMA Interrupt Enable Bits\nThis field is used to enable LPPDMA channel[n] interrupt.\nNote: The interrupt flag is abort transfer done and align." "0: LPPDMA channel n interrupt Disabled,1: LPPDMA channel n interrupt Enabled"
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line.long 0x4 "LPPDMAx_INTSTS,LPPDMA Interrupt Status Register"
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bitfld.long 0x4 3. "WKF,Wake Up Flag" "0: LPPDMA no wake up event,1: LPPDMA wake up event happened"
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rbitfld.long 0x4 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: LPPDMA channel source address and destination..,1: LPPDMA channel source address or destination.."
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rbitfld.long 0x4 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that LPPDMA controller has finished transmission; User can read LPPDMA_TDSTS register to indicate which channel finished transfer." "0: Not finished yet,1: LPPDMA channel has finished transmission"
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rbitfld.long 0x4 0. "ABTIF,LPPDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that LPPDMA has target abort error; Software can read LPPDMA_ABTSTS register to find which channel has target abort error." "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
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line.long 0x8 "LPPDMAx_ABTSTS,LPPDMA Channel Read/Write Target Abort Flag Register"
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bitfld.long 0x8 3. "ABTIF3,LPPDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which LPPDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 2. "ABTIF2,LPPDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which LPPDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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newline
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bitfld.long 0x8 1. "ABTIF1,LPPDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which LPPDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 0. "ABTIF0,LPPDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which LPPDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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line.long 0xC "LPPDMAx_TDSTS,LPPDMA Channel Transfer Done Flag Register"
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bitfld.long 0xC 3. "TDIF3,Transfer Done Flag\nThis bit indicates whether LPPDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: LPPDMA channel transfer has not finished,1: LPPDMA channel has finished transmission"
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bitfld.long 0xC 2. "TDIF2,Transfer Done Flag\nThis bit indicates whether LPPDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: LPPDMA channel transfer has not finished,1: LPPDMA channel has finished transmission"
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bitfld.long 0xC 1. "TDIF1,Transfer Done Flag\nThis bit indicates whether LPPDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: LPPDMA channel transfer has not finished,1: LPPDMA channel has finished transmission"
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bitfld.long 0xC 0. "TDIF0,Transfer Done Flag\nThis bit indicates whether LPPDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: LPPDMA channel transfer has not finished,1: LPPDMA channel has finished transmission"
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line.long 0x10 "LPPDMAx_ALIGN,LPPDMA Transfer Alignment Status Register"
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bitfld.long 0x10 3. "ALIGN3,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: LPPDMA channel source address and destination..,1: LPPDMA channel source address or destination.."
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bitfld.long 0x10 2. "ALIGN2,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: LPPDMA channel source address and destination..,1: LPPDMA channel source address or destination.."
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newline
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bitfld.long 0x10 1. "ALIGN1,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: LPPDMA channel source address and destination..,1: LPPDMA channel source address or destination.."
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bitfld.long 0x10 0. "ALIGN0,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: LPPDMA channel source address and destination..,1: LPPDMA channel source address or destination.."
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rgroup.long 0x42C++0x3
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line.long 0x0 "LPPDMAx_TACTSTS,LPPDMA Transfer Active Flag Register"
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bitfld.long 0x0 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which LPPDMA channel is in active." "0: LPPDMA channel is finished,1: LPPDMA channel is active"
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bitfld.long 0x0 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which LPPDMA channel is in active." "0: LPPDMA channel is finished,1: LPPDMA channel is active"
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newline
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bitfld.long 0x0 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which LPPDMA channel is in active." "0: LPPDMA channel is finished,1: LPPDMA channel is active"
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bitfld.long 0x0 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which LPPDMA channel is in active." "0: LPPDMA channel is finished,1: LPPDMA channel is active"
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group.long 0x43C++0x3
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line.long 0x0 "LPPDMAx_SCATBA,LPPDMA Scatter-gather Descriptor Table Base Address Register"
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hexmask.long.word 0x0 16.--31. 1. "SCATBA,LPPDMA Scatter-gather Descriptor Table Address\nIn Scatter-gather mode this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-gather mode."
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group.long 0x460++0x3
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line.long 0x0 "LPPDMAx_CHRST,LPPDMA Channel Reset Register"
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bitfld.long 0x0 3. "CH3RST,LPPDMA Channel n Reset Control\nNote: After LPPDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 2. "CH2RST,LPPDMA Channel n Reset Control\nNote: After LPPDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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newline
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bitfld.long 0x0 1. "CH1RST,LPPDMA Channel n Reset Control\nNote: After LPPDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 0. "CH0RST,LPPDMA Channel n Reset Control\nNote: After LPPDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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group.long 0x480++0x3
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line.long 0x0 "LPPDMAx_REQSEL0_3,LPPDMA Request Source Select Register 0"
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hexmask.long.byte 0x0 24.--30. 1. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to LPPDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 16.--22. 1. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to LPPDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 8.--14. 1. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to LPPDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 0.--6. 1. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to LPPDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral cannot be assigned to two channels at the same time.\nNote 2:.."
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tree.end
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tree "LPSCC (Low Power System and Clock Control)"
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base ad:0x40038000
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group.long 0x4++0x3
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line.long 0x0 "LPSCC_IPRST0,Peripheral Reset Control Register 0"
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bitfld.long 0x0 27. "OPARST,OP Amplifier Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: OPA controller normal operation,1: OPA controller reset"
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bitfld.long 0x0 24. "LPADC0RST,LPADC0 Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LPADC0 controller normal operation,1: LPADC0 controller reset"
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newline
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bitfld.long 0x0 23. "TTMR1RST,TTMR1 Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: TTMR1 controller normal operation,1: TTMR1 controller reset"
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bitfld.long 0x0 22. "TTMR0RST,TTMR0 Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: TTMR0 controller normal operation,1: TTMR0 controller reset"
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newline
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bitfld.long 0x0 21. "LPTMR1RST,LPTMR1 Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LPTMR1 controller normal operation,1: LPTMR1 controller reset"
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bitfld.long 0x0 20. "LPTMR0RST,LPTMR0 Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LPTMR0 controller normal operation,1: LPTMR0 controller reset"
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bitfld.long 0x0 19. "LPUART0RST,LPUART0 Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LPUART0 controller normal operation,1: LPUART0 controller reset"
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bitfld.long 0x0 18. "LPI2C0RST,LPI2C0 Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LPI2C0 controller normal operation,1: LPI2C0 controller reset"
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bitfld.long 0x0 17. "LPSPI0RST,LPSPI0 Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LPSPI0 controller normal operation,1: LPSPI0 controller reset"
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bitfld.long 0x0 16. "WDTRST,WDT Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: WDT controller normal operation,1: WDT controller reset"
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newline
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bitfld.long 0x0 2. "LPSRAMRST,LPSRAM Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LPSRAM controller normal operation,1: LPSRAM controller reset"
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bitfld.long 0x0 1. "LPGPIORST,LPGPIO Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LPGPIO controller normal operation,1: LPGPIO controller reset"
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bitfld.long 0x0 0. "LPPDMA0RST,LPPDMA0 Controller Reset\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LPPDMA0 controller normal operation,1: LPPDMA0 controller reset"
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group.long 0x40++0x7
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line.long 0x0 "LPSCC_CLKEN0,Peripheral Clock Enable Control Register 0"
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bitfld.long 0x0 27. "OPACKEN,OP Amplifier Clock Enable Bit" "0: OPA clock Disabled,1: OPA clock Enabled"
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bitfld.long 0x0 24. "LPADC0CKEN,LPADC0 Clock Enable Bit" "0: LPADC0 clock Disabled,1: LPADC0 clock Enabled"
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newline
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bitfld.long 0x0 23. "TTMR1CKEN,TTMR1 Clock Enable Bit" "0: TTMR1 clock Disabled,1: TTMR1 clock Enabled"
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bitfld.long 0x0 22. "TTMR0CKEN,TTMR0 Clock Enable Bit" "0: TTMR0 clock Disabled,1: TTMR0 clock Enabled"
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newline
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bitfld.long 0x0 21. "LPTMR1CKEN,LPTMR1 Clock Enable Bit" "0: LPTMR1 clock Disabled,1: LPTMR1 clock Enabled"
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bitfld.long 0x0 20. "LPTMR0CKEN,LPTMR0 Clock Enable Bit" "0: LPTMR0 clock Disabled,1: LPTMR0 clock Enabled"
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newline
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bitfld.long 0x0 19. "LPUART0CKEN,LPUART0 Clock Enable Bit" "0: LPUART0 clock Disabled,1: LPUART0 clock Enabled"
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bitfld.long 0x0 18. "LPI2C0CKEN,LPI2C0 Clock Enable Bit" "0: LPI2C0 clock Disabled,1: LPI2C0 clock Enabled"
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newline
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bitfld.long 0x0 17. "LPSPI0CKEN,LPSPI0 Clock Enable Bit" "0: LPSPI0 clock Disabled,1: LPSPI0 clock Enabled"
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bitfld.long 0x0 16. "WDTCKEN,WDT Clock Enable Bit" "0: WDT clock Disabled,1: WDT clock Enabled"
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newline
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bitfld.long 0x0 2. "LPSRAMCKEN,LPSRAM Clock Enable Bit" "0: LPSRAM clock Disabled,1: LPSRAM clock Enabled"
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bitfld.long 0x0 1. "LPGPIOCKEN,LPGPIO Clock Enable Bit" "0: LPGPIO clock Disabled,1: LPGPIO clock Enabled"
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newline
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bitfld.long 0x0 0. "LPPDMA0CKEN,LPPDMA0 Clock Enable Bit" "0: LPPDMA0 clock Disabled,1: LPPDMA0 clock Enabled"
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line.long 0x4 "LPSCC_CLKKEEP0,Peripheral Clock Keep Control Register 0"
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bitfld.long 0x4 27. "OPAKEEP,OP Amplifier Clock Keep Bit" "0: OPA clock Disabled when entering NPD0~5/SPD0~2..,1: OPA clock Enabled when entering NPD0~5/SPD0~2 mode"
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bitfld.long 0x4 24. "LPADC0KEEP,LPADC0 Clock Keep Bit" "0: LPADC0 clock Disabled when entering..,1: LPADC0 clock Enabled when entering NPD0~5/SPD0~2.."
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newline
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bitfld.long 0x4 23. "TTMR1KEEP,TTMR1 Clock Keep Bit" "0: TTMR1 clock Disabled when entering NPD0~5/SPD0~2..,1: TTMR1 clock Enabled when entering NPD0~5/SPD0~2.."
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bitfld.long 0x4 22. "TTMR0KEEP,TTMR0 Clock Keep Bit" "0: TTMR0 clock Disabled when entering NPD0~5/SPD0~2..,1: TTMR0 clock Enabled when entering NPD0~5/SPD0~2.."
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bitfld.long 0x4 21. "LPTMR1KEEP,LPTMR1 Clock Keep Bit" "0: LPTMR1 clock Disabled when entering..,1: LPTMR1 clock Enabled when entering NPD0~5/SPD0~2.."
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bitfld.long 0x4 20. "LPTMR0KEEP,LPTMR0 Clock Keep Bit" "0: LPTMR0 clock Disabled when entering..,1: LPTMR0 clock Enabled when entering NPD0~5/SPD0~2.."
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bitfld.long 0x4 19. "LPUART0KEEP,LPUART0 Clock Keep Bit" "0: LPUART0 clock Disabled when entering..,1: LPUART0 clock Enabled when entering.."
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bitfld.long 0x4 18. "LPI2C0KEEP,LPI2C0 Clock Keep Bit" "0: LPI2C0 clock Disabled when entering..,1: LPI2C0 clock Enabled when entering NPD0~5/SPD0~2.."
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bitfld.long 0x4 17. "LPSPI0KEEP,LPSPI0 Clock Keep Bit" "0: LPSPI0 clock Disabled when entering..,1: LPSPI0 clock Enabled when entering NPD0~5/SPD0~2.."
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bitfld.long 0x4 16. "WDTKEEP,WDT Clock Keep Bit" "0: WDT clock Disabled when entering NPD0~5/SPD0~2..,1: WDT clock Enabled when entering NPD0~5/SPD0~2 mode"
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bitfld.long 0x4 2. "LPSRAMKEEP,LPSRAM Clock Keep Bit" "0: LPSRAM clock Disabled when entering..,1: LPSRAM clock Enabled when entering NPD0~5/SPD0~2.."
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bitfld.long 0x4 1. "LPGPIOKEEP,LPGPIO Clock Keep Bit" "0: LPGPIO clock Disabled when entering..,1: LPGPIO clock Enabled when entering NPD0~5/SPD0~2.."
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bitfld.long 0x4 0. "LPPDMA0KEEP,LPPDMA0 Clock Keep Bit" "0: LPPDMA0 clock Disabled when entering..,1: LPPDMA0 clock Enabled when entering.."
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group.long 0x50++0x3
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line.long 0x0 "LPSCC_CLKSEL0,Peripheral Clock Source Select Control Register 0"
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bitfld.long 0x0 24.--25. "WDTSEL,WDT Clock Source Selection\nNote: The WDTSEL cannot be changed when WDT is operating. User should make WDT disable before changing WDTSEL and reset WDT after changing WDTSEL.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from 32 kHz internal low speed RC..,1: Clock source from 32.768 kHz external low speed..,?,?"
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bitfld.long 0x0 16.--17. "LPADC0SEL,LPADC0 Clock Source Selection\nNote: The LPADC0SEL cannot be changed when LPADC0 is operating. User should make LPADC0 disable before changing LPADC0SEL and reset LPADC0 after changing LPADC0SEL." "0: Clock source from 12 MHz internal high speed RC..,1: Clock source from 1~24 MHz internal middle speed..,?,?"
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bitfld.long 0x0 12.--14. "LPTMR1SEL,LPTMR1 Clock Source Selection\nNote: The LPTMR1SEL cannot be changed when LPTMR1 is operating. User should make LPTMR1 disable before changing LPTMR1SEL and reset LPTMR1 after changing LPTMR1SEL." "0: Clock source from 12 MHz internal high speed RC..,1: Clock source from 1~24 MHz internal middle speed..,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "LPTMR0SEL,LPTMR0 Clock Source Selection\nNote: The LPTMR0SEL cannot be changed when LPTMR0 is operating. User should make LPTMR0 disable before changing LPTMR0SEL and reset LPTMR0 after changing LPTMR0SEL." "0: Clock source from 12 MHz internal high speed RC..,1: Clock source from 1~24 MHz internal middle speed..,?,?,?,?,?,?"
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bitfld.long 0x0 6.--7. "TTMR1SEL,TTMR1 Clock Source Selection\nNote: The TTMR1SEL cannot be changed when TTMR1 is operating. User should make TTMR1 disable before changing TTMR1SEL and reset TTMR1 after changing TTMR1SEL." "0: Clock source from 12 MHz internal high speed RC..,1: Clock source from 1~24 MHz internal middle speed..,?,?"
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bitfld.long 0x0 4.--5. "TTMR0SEL,TTMR0 Clock Source Selection\nNote: The TTMR0SEL cannot be changed when TTMR0 is operating. User should make TTMR0 disable before changing TTMR0SEL and reset TTMR0 after changing TTMR0SEL." "0: Clock source from 12 MHz internal high speed RC..,1: Clock source from 1~24 MHz internal middle speed..,?,?"
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bitfld.long 0x0 2.--3. "LPSPI0SEL,LPSPI0 Clock Source Selection\nNote: The LPSPI0SEL cannot be changed when LPSPI0 is operating. User should make LPSPI0 disable before changing LPSPI0SEL and reset LPSPI0 after changing LPSPI0SEL." "0: Clock source from 12 MHz internal high speed RC..,1: Clock source from 1~24 MHz internal middle speed..,?,?"
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bitfld.long 0x0 0.--1. "LPUART0SEL,LPUART0 Clock Source Selection\nNote: The LPUART0SEL cannot be changed when LPUART0 is operating. User should make LPUART0 disable before changing LPUART0SEL and reset LPUART0 after changing LPUART0SEL." "0: Clock source from 12 MHz internal high speed RC..,1: Clock source from 1~24 MHz internal middle speed..,?,?"
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group.long 0x60++0x3
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line.long 0x0 "LPSCC_CLKDIV0,Peripheral Clock Divider Number Register 0"
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hexmask.long.byte 0x0 16.--19. 1. "LPADC0DIV,LPADC0 Clock Divide Number from LPADC0 Clock Source"
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hexmask.long.byte 0x0 8.--11. 1. "LPUART0DIV,LPUART0 Clock Divide Number from LPUART0 Clock Source"
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bitfld.long 0x0 4.--6. "APB2DIV,APB2 Clock Divider\nAPB2 clock can be divided from HCLK1." "0: PCLK2 frequency is HCLK1,1: PCLK2 frequency is 1/2 HCLK1,?,?,?,?,?,?"
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hexmask.long.byte 0x0 0.--3. 1. "HCLK1DIV,HCLK1 Clock Divide Number from HCLK1 Clock Source"
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group.long 0x80++0x3
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line.long 0x0 "LPSCC_CLKMCTL,Clock Monitor Control Register"
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bitfld.long 0x0 25. "AOCMEN2,Auto-operation Clock Monitor Enable 2\nNote: When crystal is connected to chip DO NOT set this bit or may cause chip damage by I/O conflict." "0: No auto-operation clock monitor function,1: PF.2 will output AOCM0 (controlled by CLKM0SEL.."
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bitfld.long 0x0 24. "AOCMEN1,Auto-operation Clock Monitor Enable 1\nNote: When ICE is connected to chip DO NOT set this bit or may cause chip damage by I/O conflict" "0: No auto-operation clock monitor function,1: PF.0 will output AOCM0 (controlled by CLKM0SEL.."
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bitfld.long 0x0 8.--9. "CLKM1SEL,Clock Monitor 1 Source Select\nThe CLKM1 output high means clock source is enabled else clock source is disabled" "0: Clock monitor source is HCLK1,1: Clock monitor source is HIRC12M,?,?"
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bitfld.long 0x0 0.--1. "CLKM0SEL,Clock Monitor 0 Source Select\nThe CLKM0 output high means clock source is enabled else clock source is disabled" "0: Clock monitor source is HCLK1,1: Clock monitor source is HIRC12M,?,?"
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group.long 0xA0++0x3
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line.long 0x0 "LPSCC_SRAMCTL,Low Power SRAM Control Register"
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bitfld.long 0x0 5. "LPSRAMDRL,LPSRAM low power Retention at idle Enabled" "0: LPSRAM retention at idle only (default),1: LPSRAM retention at idle with low power mode"
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bitfld.long 0x0 4. "LPSRAMDR,LPSRAM Dynamic Retention Enable Bit\nNote 1: If this bit is 1 LPSRAM will be auto changed to active mode when LPPDMA accesses LPSRAM.\nNote 2: This bit does not work if LSRETSEL(CLK_PMUCTL[16]) is 0 when chip in NPD3/NPD4/NPD5 mode." "0: LPSRAM dynamic retention function is disabled.,1: If this bit is 1"
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bitfld.long 0x0 0. "LPSRAMEN,Force LPSRAM Enable Bit" "0: LPSRAM is controlled by..,1: Force LPSRAM to active mode when chip is in.."
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group.long 0x100++0x3
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line.long 0x0 "LPSCC_IOHCTL,I/O Hold Control Register"
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bitfld.long 0x0 0. "SCHDIS,I/O Schmitt-Trigger Disable Bit\nWhen chip enter NPD3/NPD4/NPD5 the I/O will be hold and the input mode is default at Schmitt-Trigger mode. Setting this bit can change all I/O input mode to TTL mode." "0: I/O hold with Schmitt-Trigger iput mode,1: I/O hold with TTL input mode"
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tree.end
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tree "LPSPI (Low Power Serial Peripheral Interface)"
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base ad:0x400E1000
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group.long 0x0++0x17
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line.long 0x0 "LPSPI_CTL,SPI Control Register"
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bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. \nNote: This bit is.." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (LPSPI_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 4 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore .."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "LPSPI_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
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line.long 0x8 "LPSPI_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode the LPSPI controller can work with 3-wire interface including LPSPI_CLK LPSPI_MISO and LPSPI_MOSI pins.\nNote: This bit is for Slave Mode only." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit\nNote: This bit is for Master Mode only." "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (LPSPI_SS)." "0: The slave selection signal LPSPI_SS is active low,1: The slave selection signal LPSPI_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control\nIf AUTOSS bit is cleared to 0 \nNote: This bit is for Master Mode only." "0: set the LPSPI_SS line to inactive state.\nKeep..,1: set the LPSPI_SS line to active state.\nLPSPI_SS.."
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line.long 0xC "LPSPI_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the LPSPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
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line.long 0x10 "LPSPI_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error\nNote: This bit is for Slave Mode only." "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (LPSPI_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: When TX underflow event occurs LPSPI_MISO pin state will be determined by this setting even.." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "LPSPI_STATUS,SPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of LPSPI controller." "0: LPSPI controller Disabled,1: LPSPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (LPSPI_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: LPSPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications this SPI busy flag should be used with other status registers in LPSPI_STATUS such as TXCNT RXCNT TXTHIF TXFULL TXEMPTY RXTHIF RXFULL RXEMPTY and UNITIF. Therefore the SPI transfer done events.." "0: LPSPI controller is in idle state,1: LPSPI controller is in busy state"
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rgroup.long 0x18++0x3
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line.long 0x0 "LPSPI_STATUS2,SPI Status2 Register"
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hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX data\nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (LPSPI_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode.\nThis status register.."
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wgroup.long 0x20++0x3
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line.long 0x0 "LPSPI_TX,SPI Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (LPSPI_CTL[12:8]) in SPI mode.\nIn SPI mode if DWIDTH is set to.."
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rgroup.long 0x30++0x3
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line.long 0x0 "LPSPI_RX,SPI Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (LPSPI_STATUS[8]) is not set to 1 the receive FIFO buffers can be accessed.."
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group.long 0x50++0x7
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line.long 0x0 "LPSPI_AUTOCTL,LPSPI Automatic Operation Control Register"
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hexmask.long.byte 0x0 16.--23. 1. "TCNT,Auomatic Operation RX Transfer Count\nIn Auomatic Operation Master mode TCNT represents the required number of RX data received from external SPI slave device while in RX Phase. The maximum transfer count is 255."
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bitfld.long 0x0 10. "CNTWKEN,TCNT Count Match Wake Up Enable Bit" "0: TCNT count match wake-up function disabled,1: TCNT count match wake-up function enabled"
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bitfld.long 0x0 9. "SWTRIG,Software Trigger (Write Only)\nAfter AUTOEN set to 1 software can manually trigger the Automatic Operation Master mode by writing 1 to this bit." "0,1"
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bitfld.long 0x0 8. "AUTOEN,Automatic Operation Mode Enable Bit" "0: Automatic operation master mode disabled,1: Automatic operation master mode enabled"
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bitfld.long 0x0 7. "SSWKEN,Slave Select Wake Up Enable Bit\nIn Slave mode the CPU will be woken up by SS falling or rising edge in NPDx mode after this bit is set to 1." "0: LPSPI SS wake-up function disabled,1: LPSPI SS wake-up function enabled"
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bitfld.long 0x0 6. "FULLRXEN,Full RX Data Acception Enable Bit\nIn Auomatic Operation Master mode and LPSPI operates in full-duplex mode the RX data will be saved from RX buffer by LPPDMA while in TX Phase after this bit is set to 1." "0,1"
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bitfld.long 0x0 5. "CNTIEN,TCNT Count Match Interrupt Enable" "0: TCNT count match interrupt disabled,1: TCNT count match interrupt enabled"
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bitfld.long 0x0 4. "TRIGEN,Automatic Operation Trigger Enable Bit\nIn Auomatic Operation Master mode the automatic operation of LPSPI will be triggered by an event sent from the trigger source selected by TRIGSEL[3:0] after this bit is set to 1." "0: LPSPI Automatic Operation Trigger disabled,1: LPSPI Automatic Operation Trigger enabled"
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hexmask.long.byte 0x0 0.--3. 1. "TRIGSEL,Automatic Operation Trigger Source Select"
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line.long 0x4 "LPSPI_AUTOSTS,LPSPI Automatic Operation Status Register"
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bitfld.long 0x4 3. "CNTWKF,TCNT Count Match Wake Up Flag\nWhen chip is woken up due to the received data count matching the setting value of TCNT this bit will be set to 1.\nSoftware can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 2. "AOBUSY,Automatic Operation Busy Flag\nWhen there were one or more requests from trigger sources during auto operation this bit will be set to 1. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 1. "SSWKF,Slave Select Wake Up Flag\nIn Slave mode when chip is woken up from NPDx mode by LPSPI this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 0. "CNTIF,TCNT Count Match Interrupt Flag\nWhen the received data count matchs the setting value of TCNT this bit will be set to 1." "0: The received data count is less than the setting..,1: The received data count is equal than the.."
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tree.end
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tree "LPTMR (Low Power Timer)"
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base ad:0x400E4000
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group.long 0x0++0xF
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line.long 0x0 "LPTMR0_CTL,LPTMR0 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Low Power Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * LPTMR_CLK period to become active user can read ACTSTS (LPTMRx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Low Power Timer Interrupt Enable Bit\nNote: If this bit is enabled when the low power timer time-out interrupt flag TIF is set to 1 the low power timer interrupt signal is generated and inform to CPU." "0: Low Power Timer time-out interrupt Disabled,1: Low Power Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Low Power Timer Counting Mode Select" "0: The low power timer controller is operated in..,1: The low power timer controller is operated in..,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Low Power Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (LPTMRx_INTSTS[0]) is 1 and INTEN (LPTMRx_CTL[29]) is enabled the low power timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from LPTMRx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to LPTMRx (Low Power Timer..,1: Toggle mode output to LPTMRx_EXT (Low Power.."
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 16. "PDCLKEN,Power-down Engine Clock Enable" "0: Disable engine clock in power-down mode,1: Enable engine clock in power-down mode"
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bitfld.long 0x0 15. "FUNCSEL,Function Selection" "0: Low Power Timer controller is used as timer..,1: Low Power Timer controller is used as PWM function"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "LPTMR0_CMP,LPTMR0 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Low Power Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (LPTMRx_INTSTS[0] Low Power Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or.."
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line.long 0x8 "LPTMR0_INTSTS,LPTMR0 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Low Power Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Low Power Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Low Power Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Low Power Timer while 24-bit timer up counter CNT (LPTMRx_CNT[23:0]) value reaches to CMPDAT (LPTMRx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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line.long 0xC "LPTMR0_CNT,LPTMR0 Data Register"
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rbitfld.long 0xC 31. "RSTACT,Low Power Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register low power timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit.." "0: Reset operation is done,1: Reset operation triggered by writing LPTMRx_CNT.."
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hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Low Power Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (LPTMRx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (LPTMRx_CTL[24]) is 1 user can read.."
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rgroup.long 0x10++0x3
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line.long 0x0 "LPTMR0_CAP,LPTMR0 Capture Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Low Power Timer Capture Data Register\nWhen CAPEN (LPTMRx_EXTCTL[3]) bit is set CAPFUNCS (LPTMRx_EXTCTL[4]) bit is 0 and a transition on LPTMRx_EXT pin matched the CAPEDGE (LPTMRx_EXTCTL[14:12]) setting CAPIF (LPTMRx_EINTSTS[0]) will set to 1.."
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group.long 0x14++0xB
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line.long 0x0 "LPTMR0_EXTCTL,LPTMR0 External Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Low Power Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (LPTMRx_EXTCTL[10:8]) and CAPSRC (LPTMRx_CTL[22]) to select capture source."
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bitfld.long 0x0 16.--18. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external..,?,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Low Power Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (LPTMRx_CNT[23:0]) will be reset to 0 and first CAPDAT (LPTMRx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (LPTMRx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (LPTMRx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Low Power Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of LPTMRx pin is detected with de-bounce circuit." "0: LPTMRx (x= 0~1) pin de-bounce Disabled,1: LPTMRx (x= 0~1) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Low Power Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of LPTMRx_EXT pin or ACMP output is detected with de-bounce circuit." "0: LPTMRx_EXT (x= 0~1) pin de-bounce or ACMP output..,1: LPTMRx_EXT (x= 0~1) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Low Power Timer External Capture Interrupt Enable Bit" "0: LPTMRx_EXT (x= 0~1) pin ACMP internal clock or..,1: LPTMRx_EXT (x= 0~1) pin ACMP internal clock or.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Low Power Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (LPTMRx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 0. "CNTPHASE,Low Power Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "LPTMR0_EINTSTS,LPTMR0 External Interrupt Status Register"
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rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
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bitfld.long 0x4 0. "CAPIF,Low Power Timer External Capture Interrupt Flag\nThis bit indicates the low power timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition.." "0: LPTMRx_EXT (x= 0~1) pin ACMP internal clock or..,1: LPTMRx_EXT (x= 0~1) pin ACMP internal clock or.."
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line.long 0x8 "LPTMR0_TRGCTL,LPTMR0 Trigger Control Register"
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bitfld.long 0x8 4. "TRGLPPDMA,Trigger LPPDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered LPPDMA transfer." "0: Low Power Timer interrupt trigger LPPDMA Disabled,1: Low Power Timer interrupt trigger LPPDMA Enabled"
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bitfld.long 0x8 1. "TRGEN,Trigger Low power IPs Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can trigger Low Power IPs." "0: Low Power Timer interrupt trigger Low Power IPs..,1: Low Power Timer interrupt trigger Low Power IPs.."
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is from timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x24++0x3
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line.long 0x0 "LPTMR0_CAPNF,LPTMR0 Capture Input Noise Filter Register"
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bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is ECLKx,1: Noise filter clock is ECLKx/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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group.long 0x40++0x13
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line.long 0x0 "LPTMR0_PWMCTL,LPTMR0 PWM Control Register"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 12. "PWMINTWKEN,PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode PWMINTWKEN can determine whether chip wake-up occurs or not." "0: PWM interrupt wake-up Disabled,1: PWM interrupt wake-up Enabled"
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bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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line.long 0x4 "LPTMR0_PWMCLKPSC,LPTMR0 PWM Counter Clock Pre-scale Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0 then there is no scaling in PWM counter clock source."
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line.long 0x8 "LPTMR0_PWMCNTCLR,LPTMR0 PWM Clear Counter Register"
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bitfld.long 0x8 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x0000 in up count.."
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line.long 0xC "LPTMR0_PWMPERIOD,LPTMR0 PWM Period Register"
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hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn up count type:"
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line.long 0x10 "LPTMR0_PWMCMPDAT,LPTMR0 PWM Comparator Register"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger EADC PDMA and DAC start conversion."
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rgroup.long 0x54++0x3
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line.long 0x0 "LPTMR0_PWMCNT,LPTMR0 PWM Counter Register"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter."
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group.long 0x58++0x17
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line.long 0x0 "LPTMR0_PWMPOLCTL,LPTMR0 PWM Pin Output Polar Control Register"
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bitfld.long 0x0 0. "PINV,PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Set POSEL (LPTMRx_PWMPOCTL[8]) to select LPTMRx or LPTMRx_EXT as PWMx output pin." "0: PWMx_OUT pin polar inverse Disabled,1: PWMx_OUT polar inverse Enabled"
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line.long 0x4 "LPTMR0_PWMPOCTL,LPTMR0 PWM Pin Output Control Register"
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bitfld.long 0x4 8. "POSEL,PWM Output Pin Select" "0: PWMx_OUT pin is LPTMRx,1: PWMx_OUT pin is LPTMRx_EXT"
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bitfld.long 0x4 0. "POEN,PWMx Output Pin Enable Bit\nNote: Set POSEL (LPTMRx_PWMPOCTL[8]) to select LPTMRx or LPTMRx_EXT as PWMx output pin." "0: PWMx_OUT pin at tri-state mode,1: PWMx_OUT pin in output mode"
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line.long 0x8 "LPTMR0_PWMINTEN0,LPTMR0 PWM Interrupt Enable Register 0"
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bitfld.long 0x8 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x8 1. "PIEN,PWM Period Point Interrupt Enable Bit" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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line.long 0xC "LPTMR0_PWMINTSTS0,LPTMR0 PWM Interrupt Status Register 0"
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bitfld.long 0xC 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when LPTMRx_PWM counter in up count direction and reaches CMP.\nNote: If CMP equal to PERIOD there is no CMPUIF flag in up count type. Note 2: This bit is cleared by writing 1 to it." "?,?"
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bitfld.long 0xC 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when LPTMRx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it." "0,1"
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line.long 0x10 "LPTMR0_PWMTRGCTL,LPTMR0 PWM Trigger Control Register"
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bitfld.long 0x10 9. "PWMTRGLPPDMA,PWM Counter Event Trigger LPPDMA Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger LPPDMA conversion.\nNote: Set TRGSEL (LPTMRx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.\nNote: TRGEN (LPTMRx_PWMTRGCTL[2]) is.." "0: PWM trigger LPPDMA Disabled,1: PWM trigger LPPDMA Enabled"
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bitfld.long 0x10 2. "TRGEN,Trigger Low power IPs Enable Bit\nf this bit is set to 1 each timer time-out event or capture event can trigger Low Power IP." "0: Low Power Timer PWM counter event trigger Low..,1: Low Power Timer PWM counter event trigger Low.."
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bitfld.long 0x10 0.--1. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at period point (PIF),1: Trigger conversion at compare up count point..,?,?"
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line.long 0x14 "LPTMR0_PWMSTATUS,LPTMR0 PWM Status Register"
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bitfld.long 0x14 8. "PWMINTWKF,PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM interrupt wake-up has not occurred,1: PWM interrupt wake-up has occurred"
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bitfld.long 0x14 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it." "0: The PWM counter value never reached its maximum..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0x70++0x7
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line.long 0x0 "LPTMR0_PWMPBUF,LPTMR0 PWM Period Buffer Register"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register."
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line.long 0x4 "LPTMR0_PWMCMPBUF,LPTMR0 PWM Comparator Buffer Register"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register."
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group.long 0xA8++0xF
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line.long 0x0 "LPTMR0_PWMIFA,LPTMR0 PWM Interrupt Flag Accumulator Register"
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bitfld.long 0x0 31. "IFAEN,PWM Interrupt Flag Accumulator Enable Bit" "0: PWM interrupt flag accumulator function Disabled,1: PWM interrupt flag accumulator function Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM Interrupt Flag Accumulator Source Select" "?,1: Accumulate at each PWM period point,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM Accumulator Stop Mode Enable Bit" "0: PWM interrupt accumulator event to stop counting..,1: PWM interrupt accumulator event to stop counting.."
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hexmask.long.word 0x0 0.--15. 1. "IFACNT,PWM Interrupt Flag Accumulator Counter\nThis field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. \nPWM accumulator flag (IFAIF) will be set in every.."
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line.long 0x4 "LPTMR0_PWMAINTSTS,LPTMR0 PWM Accumulator Interrupt Flag Register"
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bitfld.long 0x4 0. "IFAIF,PWM Interrupt Flag Accumulator Interrupt Flag\nThis bit is set by hardware when the accumulator value reaches (IFACNT+1)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: If APDMAEN (LPTMRx_PWMAPDMACTL[0]) is set this bit will be auto.." "?,1: This bit is cleared by writing 1 to it"
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line.long 0x8 "LPTMR0_PWMAINTEN,LPTMR0 PWM Accumulator Interrupt Enable Register"
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bitfld.long 0x8 0. "IFAIEN,PWM Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag Accumulator interrupt Disabled,1: Interrupt Flag Accumulator interrupt Enabled"
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line.long 0xC "LPTMR0_PWMAPDMACTL,LPTMR0 PWM Accumulator LPPDMA Control Register"
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bitfld.long 0xC 0. "APDMAEN,PWM Accumulator LPPDMA Enable Bit" "0: PWM interrupt accumulator event to trigger..,1: PWM interrupt accumulator event to trigger.."
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group.long 0x100++0xF
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line.long 0x0 "LPTMR1_CTL,LPTMR1 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Low Power Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * LPTMR_CLK period to become active user can read ACTSTS (LPTMRx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Low Power Timer Interrupt Enable Bit\nNote: If this bit is enabled when the low power timer time-out interrupt flag TIF is set to 1 the low power timer interrupt signal is generated and inform to CPU." "0: Low Power Timer time-out interrupt Disabled,1: Low Power Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Low Power Timer Counting Mode Select" "0: The low power timer controller is operated in..,1: The low power timer controller is operated in..,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Low Power Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (LPTMRx_INTSTS[0]) is 1 and INTEN (LPTMRx_CTL[29]) is enabled the low power timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from LPTMRx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to LPTMRx (Low Power Timer..,1: Toggle mode output to LPTMRx_EXT (Low Power.."
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 16. "PDCLKEN,Power-down Engine Clock Enable" "0: Disable engine clock in power-down mode,1: Enable engine clock in power-down mode"
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bitfld.long 0x0 15. "FUNCSEL,Function Selection" "0: Low Power Timer controller is used as timer..,1: Low Power Timer controller is used as PWM function"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "LPTMR1_CMP,LPTMR1 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Low Power Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (LPTMRx_INTSTS[0] Low Power Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or.."
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line.long 0x8 "LPTMR1_INTSTS,LPTMR1 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Low Power Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Low Power Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Low Power Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Low Power Timer while 24-bit timer up counter CNT (LPTMRx_CNT[23:0]) value reaches to CMPDAT (LPTMRx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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line.long 0xC "LPTMR1_CNT,LPTMR1 Data Register"
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rbitfld.long 0xC 31. "RSTACT,Low Power Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register low power timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit.." "0: Reset operation is done,1: Reset operation triggered by writing LPTMRx_CNT.."
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hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Low Power Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (LPTMRx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (LPTMRx_CTL[24]) is 1 user can read.."
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rgroup.long 0x110++0x3
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line.long 0x0 "LPTMR1_CAP,LPTMR1 Capture Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Low Power Timer Capture Data Register\nWhen CAPEN (LPTMRx_EXTCTL[3]) bit is set CAPFUNCS (LPTMRx_EXTCTL[4]) bit is 0 and a transition on LPTMRx_EXT pin matched the CAPEDGE (LPTMRx_EXTCTL[14:12]) setting CAPIF (LPTMRx_EINTSTS[0]) will set to 1.."
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group.long 0x114++0xB
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line.long 0x0 "LPTMR1_EXTCTL,LPTMR1 External Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Low Power Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (LPTMRx_EXTCTL[10:8]) and CAPSRC (LPTMRx_CTL[22]) to select capture source."
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bitfld.long 0x0 16.--18. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external..,?,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Low Power Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (LPTMRx_CNT[23:0]) will be reset to 0 and first CAPDAT (LPTMRx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (LPTMRx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (LPTMRx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Low Power Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of LPTMRx pin is detected with de-bounce circuit." "0: LPTMRx (x= 0~1) pin de-bounce Disabled,1: LPTMRx (x= 0~1) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Low Power Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of LPTMRx_EXT pin or ACMP output is detected with de-bounce circuit." "0: LPTMRx_EXT (x= 0~1) pin de-bounce or ACMP output..,1: LPTMRx_EXT (x= 0~1) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Low Power Timer External Capture Interrupt Enable Bit" "0: LPTMRx_EXT (x= 0~1) pin ACMP internal clock or..,1: LPTMRx_EXT (x= 0~1) pin ACMP internal clock or.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Low Power Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (LPTMRx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 0. "CNTPHASE,Low Power Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "LPTMR1_EINTSTS,LPTMR1 External Interrupt Status Register"
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rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
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bitfld.long 0x4 0. "CAPIF,Low Power Timer External Capture Interrupt Flag\nThis bit indicates the low power timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition.." "0: LPTMRx_EXT (x= 0~1) pin ACMP internal clock or..,1: LPTMRx_EXT (x= 0~1) pin ACMP internal clock or.."
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line.long 0x8 "LPTMR1_TRGCTL,LPTMR1 Trigger Control Register"
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bitfld.long 0x8 4. "TRGLPPDMA,Trigger LPPDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered LPPDMA transfer." "0: Low Power Timer interrupt trigger LPPDMA Disabled,1: Low Power Timer interrupt trigger LPPDMA Enabled"
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bitfld.long 0x8 1. "TRGEN,Trigger Low power IPs Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can trigger Low Power IPs." "0: Low Power Timer interrupt trigger Low Power IPs..,1: Low Power Timer interrupt trigger Low Power IPs.."
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is from timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x124++0x3
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line.long 0x0 "LPTMR1_CAPNF,LPTMR1 Capture Input Noise Filter Register"
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bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is ECLKx,1: Noise filter clock is ECLKx/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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group.long 0x140++0x13
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line.long 0x0 "LPTMR1_PWMCTL,LPTMR1 PWM Control Register"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 12. "PWMINTWKEN,PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode PWMINTWKEN can determine whether chip wake-up occurs or not." "0: PWM interrupt wake-up Disabled,1: PWM interrupt wake-up Enabled"
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bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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line.long 0x4 "LPTMR1_PWMCLKPSC,LPTMR1 PWM Counter Clock Pre-scale Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0 then there is no scaling in PWM counter clock source."
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line.long 0x8 "LPTMR1_PWMCNTCLR,LPTMR1 PWM Clear Counter Register"
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bitfld.long 0x8 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x0000 in up count.."
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line.long 0xC "LPTMR1_PWMPERIOD,LPTMR1 PWM Period Register"
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hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn up count type:"
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line.long 0x10 "LPTMR1_PWMCMPDAT,LPTMR1 PWM Comparator Register"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger EADC PDMA and DAC start conversion."
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rgroup.long 0x154++0x3
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line.long 0x0 "LPTMR1_PWMCNT,LPTMR1 PWM Counter Register"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter."
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group.long 0x158++0x17
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line.long 0x0 "LPTMR1_PWMPOLCTL,LPTMR1 PWM Pin Output Polar Control Register"
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bitfld.long 0x0 0. "PINV,PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Set POSEL (LPTMRx_PWMPOCTL[8]) to select LPTMRx or LPTMRx_EXT as PWMx output pin." "0: PWMx_OUT pin polar inverse Disabled,1: PWMx_OUT polar inverse Enabled"
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line.long 0x4 "LPTMR1_PWMPOCTL,LPTMR1 PWM Pin Output Control Register"
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bitfld.long 0x4 8. "POSEL,PWM Output Pin Select" "0: PWMx_OUT pin is LPTMRx,1: PWMx_OUT pin is LPTMRx_EXT"
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bitfld.long 0x4 0. "POEN,PWMx Output Pin Enable Bit\nNote: Set POSEL (LPTMRx_PWMPOCTL[8]) to select LPTMRx or LPTMRx_EXT as PWMx output pin." "0: PWMx_OUT pin at tri-state mode,1: PWMx_OUT pin in output mode"
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line.long 0x8 "LPTMR1_PWMINTEN0,LPTMR1 PWM Interrupt Enable Register 0"
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bitfld.long 0x8 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x8 1. "PIEN,PWM Period Point Interrupt Enable Bit" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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line.long 0xC "LPTMR1_PWMINTSTS0,LPTMR1 PWM Interrupt Status Register 0"
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bitfld.long 0xC 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when LPTMRx_PWM counter in up count direction and reaches CMP.\nNote: If CMP equal to PERIOD there is no CMPUIF flag in up count type. Note 2: This bit is cleared by writing 1 to it." "?,?"
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bitfld.long 0xC 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when LPTMRx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it." "0,1"
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line.long 0x10 "LPTMR1_PWMTRGCTL,LPTMR1 PWM Trigger Control Register"
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bitfld.long 0x10 9. "PWMTRGLPPDMA,PWM Counter Event Trigger LPPDMA Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger LPPDMA conversion.\nNote: Set TRGSEL (LPTMRx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.\nNote: TRGEN (LPTMRx_PWMTRGCTL[2]) is.." "0: PWM trigger LPPDMA Disabled,1: PWM trigger LPPDMA Enabled"
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bitfld.long 0x10 2. "TRGEN,Trigger Low power IPs Enable Bit\nf this bit is set to 1 each timer time-out event or capture event can trigger Low Power IP." "0: Low Power Timer PWM counter event trigger Low..,1: Low Power Timer PWM counter event trigger Low.."
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bitfld.long 0x10 0.--1. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at period point (PIF),1: Trigger conversion at compare up count point..,?,?"
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line.long 0x14 "LPTMR1_PWMSTATUS,LPTMR1 PWM Status Register"
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bitfld.long 0x14 8. "PWMINTWKF,PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM interrupt wake-up has not occurred,1: PWM interrupt wake-up has occurred"
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bitfld.long 0x14 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it." "0: The PWM counter value never reached its maximum..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0x170++0x7
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line.long 0x0 "LPTMR1_PWMPBUF,LPTMR1 PWM Period Buffer Register"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register."
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line.long 0x4 "LPTMR1_PWMCMPBUF,LPTMR1 PWM Comparator Buffer Register"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register."
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group.long 0x1A8++0xF
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line.long 0x0 "LPTMR1_PWMIFA,LPTMR1 PWM Interrupt Flag Accumulator Register"
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bitfld.long 0x0 31. "IFAEN,PWM Interrupt Flag Accumulator Enable Bit" "0: PWM interrupt flag accumulator function Disabled,1: PWM interrupt flag accumulator function Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM Interrupt Flag Accumulator Source Select" "?,1: Accumulate at each PWM period point,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM Accumulator Stop Mode Enable Bit" "0: PWM interrupt accumulator event to stop counting..,1: PWM interrupt accumulator event to stop counting.."
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hexmask.long.word 0x0 0.--15. 1. "IFACNT,PWM Interrupt Flag Accumulator Counter\nThis field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. \nPWM accumulator flag (IFAIF) will be set in every.."
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line.long 0x4 "LPTMR1_PWMAINTSTS,LPTMR1 PWM Accumulator Interrupt Flag Register"
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bitfld.long 0x4 0. "IFAIF,PWM Interrupt Flag Accumulator Interrupt Flag\nThis bit is set by hardware when the accumulator value reaches (IFACNT+1)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: If APDMAEN (LPTMRx_PWMAPDMACTL[0]) is set this bit will be auto.." "?,1: This bit is cleared by writing 1 to it"
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line.long 0x8 "LPTMR1_PWMAINTEN,LPTMR1 PWM Accumulator Interrupt Enable Register"
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bitfld.long 0x8 0. "IFAIEN,PWM Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag Accumulator interrupt Disabled,1: Interrupt Flag Accumulator interrupt Enabled"
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line.long 0xC "LPTMR1_PWMAPDMACTL,LPTMR1 PWM Accumulator LPPDMA Control Register"
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bitfld.long 0xC 0. "APDMAEN,PWM Accumulator LPPDMA Enable Bit" "0: PWM interrupt accumulator event to trigger..,1: PWM interrupt accumulator event to trigger.."
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tree.end
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tree "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)"
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base ad:0x400E0000
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group.long 0x0++0x27
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line.long 0x0 "LPUART_DAT,LPUART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO. If PBE (LPUART_LINE[3]) and PSS (LPUART_LINE[7]) are set the LPUART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The LPUART controller will send out the data stored in transmitter FIFO top location through the LPUART_TXD.\nRead.."
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line.long 0x4 "LPUART_INTEN,LPUART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (LPUART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (LPUART_INTSTS[30]) will be generated when TXENDIF (LPUART_INTSTS[22]) is set (TX FIFO (LPUART_DAT) is empty and the STOP.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(LPUART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(LPUART_INTSTS[16]) is set.\nNote:.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX LPPDMA Enable Bit\nThis bit can enable or disable RX LPPDMA service.\nNote: If RLSIEN (LPUART_INTEN[2]) is enabled and HWRLSINT (LPUART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by.." "0: RX LPPDMA Disabled,1: RX LPPDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX LPPDMA Enable Bit\nNote: If RLSIEN (LPUART_INTEN[2]) is enabled and HWRLSINT (LPUART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(LPUART_FIFOSTS[6]) Frame.." "0: TX LPPDMA Disabled,1: TX LPPDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the LPUART will send data to external device if nCTS input assert (LPUART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (LPUART_FIFO[19:16]) the LPUART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "LPUART_FIFO,LPUART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (LPUART_ALTCTL[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (LPUART_INTSTS[0]) will be set (if RDAIEN (LPUART_INTEN[0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (LPUART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 LPUART peripheral clock cycles.\nNote 2: Before setting.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (LPUART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 LPUART peripheral clock cycles.\nNote 2: Before setting.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "LPUART_LINE,LPUART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (LPUART_FUNCSEL[3]) should be set then waited for TXRXACT (LPUART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (LPUART_FUNCSEL[3]) to activate LPUART.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (LPUART_FUNCSEL[3]) should be set then waited for TXRXACT (LPUART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (LPUART_FUNCSEL[3]) to activate LPUART.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (LPUART_LINE[3]) is set.\nNote 2: If PSS is 0 the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (LPUART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (LPUART_LINE[3]) and EPE (LPUART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0. If PBE (LPUART_LINE[3]) is 1 and EPE (LPUART_LINE[4]) is 0 then the PARITY bit is transmitted and.." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (LPUART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets LPUART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "LPUART_MODEM,LPUART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 013 and Figure 014 for LPUART function mode.\nNote 2: Refer to Figure 015 and Figure 016 for RS-485 function mode.\nNote 3: Before.." "0: nRTS pin output is high level active,1: Refer to Figure 013 and Figure 014 for LPUART.."
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
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line.long 0x14 "LPUART_MODEMSTS,LPUART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (LPUART_FUNCSEL[3]) should be set then waited for TXRXACT (LPUART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when LPUART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (LPUART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "LPUART_FIFOSTS,LPUART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (LPUART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The LPUART controller cannot transmit or receive.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (LPUART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (LPUART_DAT) is full an additional write to LPUART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into LPUART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when LPUART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When LPUART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (LPUART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (LPUART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x1C "LPUART_INTSTS,LPUART Interrupt Status Register"
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rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (LPUART_INTEN[18]) and ABRIF (LPUART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (LPUART_INTEN[22]) and TXENDIF(LPUART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,LPPDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (LPUART_INTEN[5]) and HWBUFEIF (LPUART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in LPPDMA..,1: Buffer error interrupt is generated in LPPDMA mode"
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rbitfld.long 0x1C 28. "HWTOINT,LPPDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (LPUART_INTEN[4]) and HWTOIF(LPUART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in LPPDMA..,1: RX time-out interrupt is generated in LPPDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,LPPDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (LPUART_INTEN[3]) and HWMODIF(LPUART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in LPPDMA mode,1: Modem interrupt is generated in LPPDMA mode"
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rbitfld.long 0x1C 26. "HWRLSINT,LPPDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (LPUART_INTEN[2]) and HWRLSIF(LPUART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in LPPDMA mode,1: RLS interrupt is generated in LPPDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (LPUART_INTEN[16]) and SWBEIF (LPUART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (LPUART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (LPUART_FIFOSTS[28]) is set). If TXENDIEN (LPUART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,LPPDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (LPUART_FIFOSTS[24]) or RXOVIF (LPUART_FIFOSTS[0]) is set). When BUFERRIF (LPUART_INTSTS[5]) is set the transfer maybe is not correct." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in.."
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bitfld.long 0x1C 20. "HWTOIF,LPPDMA Mode RX Time-out Interrupt Flag\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (LPUART_TOUT[7:0]). If RXTOIEN (LPUART_INTEN[4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x1C 19. "HWMODIF,LPPDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (LPUART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (LPUART_MODEMSTS[0])." "0: No Modem interrupt flag is generated in LPPDMA..,1: Modem interrupt flag is generated in LPPDMA mode"
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rbitfld.long 0x1C 18. "HWRLSIF,LPPDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (LPUART_FIFOSTS[6]) FEF (LPUART_FIFOSTS[5]) and PEF (LPUART_FIFOSTS[4]) is.." "0: No RLS interrupt flag is generated in LPPDMA mode,1: RLS interrupt flag is generated in LPPDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to LPUART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (LPUART_FUNCSEL[2:0]) is select LPUART.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
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rbitfld.long 0x1C 14. "WKINT,LPUART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (LPUART_INTEN[6]) and WKIF (LPUART_INTSTS[6]) are both set to 1." "0: No LPUART wake-up interrupt is generated,1: LPUART wake-up interrupt is generated"
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rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(LPUART_INTEN[5]) and BUFERRIF(LPUART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (LPUART_INTEN[4]) and RXTOIF(LPUART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(LPUART_INTEN[3]) and MODEMIF(LPUART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated."
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (LPUART_INTEN[2]) and RLSIF(LPUART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (LPUART_INTEN[1]) and THREIF(LPUART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (LPUART_INTEN[0]) and RDAIF (LPUART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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rbitfld.long 0x1C 6. "WKIF,LPUART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (LPUART_WKSTS[4]) RS485WKF (LPUART_WKSTS[3]) RFRTWKF (LPUART_WKSTS[2]) DATWKF (LPUART_WKSTS[1]) or CTSWKF(LPUART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of.." "0: No LPUART wake-up interrupt flag is generated,1: LPUART wake-up interrupt flag is generated"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (LPUART_FIFOSTS[24]) or RXOVIF (LPUART_FIFOSTS[0]) is set). When BUFERRIF (LPUART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (LPUART_TOUT[7:0]). If RXTOIEN (LPUART_INTEN[4]) is enabled the RX time-out interrupt will.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(LPUART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(LPUART_FIFOSTS[6]) FEF(LPUART_FIFOSTS[5]) and PEF(LPUART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (LPUART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(LPUART_INTSTS[0]) will be set. If RDAIEN (LPUART_INTEN[0]) is enabled the RDA interrupt will be generated.\nNote: This bit.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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line.long 0x20 "LPUART_TOUT,LPUART Time-out Register"
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bitfld.long 0x20 31. "BITOMEN,Bus Idle Time-out Mode Enable Bit\nIf BITOMEN (LPUART_TOUT[31]) is enabled the reset conditions of the time-out counter and RXTOIF (LPUART_INTSTS[4]) will be changed to detect the bus idle.\nWhen BITOMEN (LPUART_TOUT[31]) is disabled the.." "0: Bus idle time-out mode Disabled,1: Bus idle time-out mode Enabled"
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hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
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hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x24 "LPUART_BAUD,LPUART Baud Rate Divider Register"
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bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. LPUART provides three baud rate calculation modes. This bit combines with BAUDM0 (LPUART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. LPUART provides three baud rate calculation modes. This bit combines with BAUDM1 (LPUART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 04."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 04."
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group.long 0x2C++0x7
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line.long 0x0 "LPUART_ALTCTL,LPUART Alternate Control/Status Register"
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hexmask.long.byte 0x0 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0x0 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x0 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x0 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(LPUART_INTEN[18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x0 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x0 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x0 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x0 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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line.long 0x4 "LPUART_FUNCSEL,LPUART Function Select Register"
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bitfld.long 0x4 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
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bitfld.long 0x4 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x4 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x4 0.--2. "FUNCSEL,Function Select" "0: LPUART function,?,?,?,?,?,?,?"
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group.long 0x3C++0x13
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line.long 0x0 "LPUART_BRCOMP,LPUART Baud Rate Compensation Register"
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bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (LPUART_DAT[7:0]) and BRCOM[8] is used to define PARITY (LPUART_DAT[8])."
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line.long 0x4 "LPUART_WKCTL,LPUART Wake-up Control Register"
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bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
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bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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newline
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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newline
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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line.long 0x8 "LPUART_WKSTS,LPUART Wake-up Status Register"
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bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\nNote 1: If WKTOUTEN (LPUART_WKCTL[4]) is enabled the Received Data FIFO reached.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (LPUART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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|
newline
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (LPUART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (LPUART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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newline
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (LPUART_WKCTL[0]) is enabled the nCTS wake-up cause this bit set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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|
line.long 0xC "LPUART_DWKCOMP,LPUART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by LPUART_CLK do the LPUART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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|
line.long 0x10 "LPUART_RS485DD,LPUART RS485 Transceiver Deactivate Delay Register"
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hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by LPUART_CLK do the LPUART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX.."
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|
group.long 0x58++0x7
|
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line.long 0x0 "LPUART_AUTOCTL,LPUART Automatic Operation Control Register"
|
|
bitfld.long 0x0 31. "AOEN,Automatic Operation Enable Bit" "0: Automatic Operation Disabled,1: Automatic Operation Enabled"
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bitfld.long 0x0 9. "SWTRIG,Software Trigger (Write Only)\nAfter AOEN (LPUART_AUTOCTL[31]) is set to 1 software can manually trigger the automatic TX operation by writing 1 to this bit." "0,1"
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newline
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bitfld.long 0x0 8. "WKAOTOEN,Bus Idle Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Bus Idle Time-out Wake-up will wake-up system from Power-down mode if WKAOTOEN (LPUART_AUTOCTL[8]) is set to '1'.\nNote 2: When WKAOTOEN (LPUART_AUTOCTL[8]) is.." "0: Bus Idle Time-out Wake-up system function Disabled,1: When the system is in Power-down mode"
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|
bitfld.long 0x0 5. "CKAWOEN,Automatic Operation Clock Always-on Enable Bit" "0: Automatic Operation Clock Always-on Disabled,1: Automatic Operation Clock Always-on Enabled"
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newline
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bitfld.long 0x0 4. "TRIGEN,Automatic Operation Trigger Enable Bit\nWhen TRIGEN (LPUART_AUTOCTL[4]) is set to '1' the automatic TX operation of LPUART will be triggered by an event sent from the trigger source selected by TRIGSEL[3:0]." "0: LPUART Automatic Operation Trigger disabled,1: LPUART Automatic Operation Trigger enabled"
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|
hexmask.long.byte 0x0 0.--3. 1. "TRIGSEL,Automatic Operation Trigger Source Select"
|
|
line.long 0x4 "LPUART_AUTOSTS,LPUART Automatic Operation Status Register"
|
|
bitfld.long 0x4 0. "AOTOWKF,Bus Idle Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Bus Idle Time-out Wake-up\nNote 1: When RXPDMAEN (LPUART_INTEN[15]) or TXPDMAEN (LPUART_INTEN[14]) is enabled this bit is the shadow bit of HWTOIF.." "0: There is no Bus Idle Time-out Wake-up event,1: When RXPDMAEN"
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tree.end
|
|
tree "NMI (Non-Maskable Interrupt)"
|
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base ad:0x40000300
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "NMIEN,NMI Source Interrupt Enable Register"
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bitfld.long 0x0 15. "UART1_INT,UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART1 NMI source Disabled,1: UART1 NMI source Enabled"
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bitfld.long 0x0 14. "UART0_INT,UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled"
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newline
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bitfld.long 0x0 13. "EINT5,External Interrupt From INT5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT5 pin NMI source..,1: External interrupt from INT5 pin NMI source.."
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bitfld.long 0x0 12. "EINT4,External Interrupt From INT4 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT4 pin NMI source..,1: External interrupt from INT4 pin NMI source.."
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newline
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bitfld.long 0x0 11. "EINT3,External Interrupt From INT3 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT3 pin NMI source..,1: External interrupt from INT3 pin NMI source.."
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|
bitfld.long 0x0 10. "EINT2,External Interrupt From INT2 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT2 pin NMI source..,1: External interrupt from INT2 pin NMI source.."
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|
newline
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bitfld.long 0x0 9. "EINT1,External Interrupt From INT1 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT1 pin NMI source..,1: External interrupt from INT1 pin NMI source.."
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|
bitfld.long 0x0 8. "EINT0,External Interrupt From INT0 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT0 pin NMI source..,1: External interrupt from INT0 pin NMI source.."
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newline
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bitfld.long 0x0 7. "TAMPER_INT,TAMPER_INT NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Backup register tamper detected interrupt.NMI..,1: Backup register tamper detected interrupt.NMI.."
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|
bitfld.long 0x0 6. "RTC_INT,RTC NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: RTC NMI source Disabled,1: RTC NMI source Enabled"
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|
newline
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bitfld.long 0x0 4. "CLKFAIL,Clock Fail Detected NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock fail detected interrupt NMI source Disabled,1: Clock fail detected interrupt NMI source Enabled"
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bitfld.long 0x0 3. "SRAM_PERR,SRAM ParityCheck Error NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: SRAM parity check error NMI source Disabled,1: SRAM parity check error NMI source Enabled"
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newline
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bitfld.long 0x0 2. "PWRWU_INT,Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled"
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|
bitfld.long 0x0 1. "IRC_INT,IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: IRC TRIM NMI source Disabled,1: IRC TRIM NMI source Enabled"
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|
newline
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bitfld.long 0x0 0. "BODOUT,BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: BOD NMI source Disabled,1: BOD NMI source Enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "NMISTS,NMI Source Interrupt Status Register"
|
|
bitfld.long 0x0 15. "UART1_INT,UART1 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
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|
bitfld.long 0x0 14. "UART0_INT,UART0 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
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newline
|
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bitfld.long 0x0 13. "EINT5,External Interrupt From INT5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT5 interrupt is..,1: External Interrupt from INT5 interrupt is asserted"
|
|
bitfld.long 0x0 12. "EINT4,External Interrupt From INT4 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT4 interrupt is..,1: External Interrupt from INT4 interrupt is asserted"
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|
newline
|
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bitfld.long 0x0 11. "EINT3,External Interrupt From INT3 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT3 interrupt is..,1: External Interrupt from INT3 interrupt is asserted"
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bitfld.long 0x0 10. "EINT2,External Interrupt From INT2 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT2 interrupt is..,1: External Interrupt from INT2 interrupt is asserted"
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newline
|
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bitfld.long 0x0 9. "EINT1,External Interrupt From INT1 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT1 interrupt is..,1: External Interrupt from INT1 interrupt is asserted"
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bitfld.long 0x0 8. "EINT0,External Interrupt From INT0 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT0 interrupt is..,1: External Interrupt from INT0 interrupt is asserted"
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newline
|
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bitfld.long 0x0 7. "TAMPER_INT,TAMPER_INT Interrupt Flag (Read Only)" "0: Backup register tamper detected interrupt is..,1: Backup register tamper detected interrupt is.."
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bitfld.long 0x0 6. "RTC_INT,RTC Interrupt Flag (Read Only)" "0: RTC interrupt is deasserted,1: RTC interrupt is asserted"
|
|
newline
|
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bitfld.long 0x0 4. "CLKFAIL,Clock Fail Detected Interrupt Flag (Read Only)" "0: Clock fail detected interrupt is deasserted,1: Clock fail detected interrupt is asserted"
|
|
bitfld.long 0x0 3. "SRAM_PERR,SRAM ParityCheck Error Interrupt Flag (Read Only)" "0: SRAM parity check error interrupt is deasserted,1: SRAM parity check error interrupt is asserted"
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|
newline
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bitfld.long 0x0 2. "PWRWU_INT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted"
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bitfld.long 0x0 1. "IRC_INT,IRC TRIM Interrupt Flag (Read Only)" "0: HIRC TRIM interrupt is deasserted,1: HIRC TRIM interrupt is asserted"
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newline
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bitfld.long 0x0 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted"
|
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tree.end
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
base ad:0xE000E100
|
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group.long 0x0++0x13
|
|
line.long 0x0 "NVIC_ISER0,IRQ0 ~ IRQ143 Set-enable Control Register"
|
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hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER4 registers enable interrupts and show which interrupts are enabled\nWrite Operation:"
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line.long 0x4 "NVIC_ISER1,IRQ0 ~ IRQ143 Set-enable Control Register"
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hexmask.long 0x4 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER4 registers enable interrupts and show which interrupts are enabled\nWrite Operation:"
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line.long 0x8 "NVIC_ISER2,IRQ0 ~ IRQ143 Set-enable Control Register"
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hexmask.long 0x8 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER4 registers enable interrupts and show which interrupts are enabled\nWrite Operation:"
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line.long 0xC "NVIC_ISER3,IRQ0 ~ IRQ143 Set-enable Control Register"
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hexmask.long 0xC 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER4 registers enable interrupts and show which interrupts are enabled\nWrite Operation:"
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line.long 0x10 "NVIC_ISER4,IRQ0 ~ IRQ143 Set-enable Control Register"
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hexmask.long 0x10 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER4 registers enable interrupts and show which interrupts are enabled\nWrite Operation:"
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group.long 0x80++0x13
|
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line.long 0x0 "NVIC_ICER0,IRQ0 ~ IRQ143 Clear-enable Control Register"
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hexmask.long 0x0 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER4 registers disable interrupts and show which interrupts are enabled.\nWrite Operation:"
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line.long 0x4 "NVIC_ICER1,IRQ0 ~ IRQ143 Clear-enable Control Register"
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hexmask.long 0x4 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER4 registers disable interrupts and show which interrupts are enabled.\nWrite Operation:"
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line.long 0x8 "NVIC_ICER2,IRQ0 ~ IRQ143 Clear-enable Control Register"
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hexmask.long 0x8 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER4 registers disable interrupts and show which interrupts are enabled.\nWrite Operation:"
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line.long 0xC "NVIC_ICER3,IRQ0 ~ IRQ143 Clear-enable Control Register"
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hexmask.long 0xC 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER4 registers disable interrupts and show which interrupts are enabled.\nWrite Operation:"
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line.long 0x10 "NVIC_ICER4,IRQ0 ~ IRQ143 Clear-enable Control Register"
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hexmask.long 0x10 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER4 registers disable interrupts and show which interrupts are enabled.\nWrite Operation:"
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group.long 0x100++0x13
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line.long 0x0 "NVIC_ISPR0,IRQ0 ~ IRQ143 Set-pending Control Register"
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hexmask.long 0x0 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR4 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation:"
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line.long 0x4 "NVIC_ISPR1,IRQ0 ~ IRQ143 Set-pending Control Register"
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hexmask.long 0x4 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR4 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation:"
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line.long 0x8 "NVIC_ISPR2,IRQ0 ~ IRQ143 Set-pending Control Register"
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hexmask.long 0x8 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR4 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation:"
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line.long 0xC "NVIC_ISPR3,IRQ0 ~ IRQ143 Set-pending Control Register"
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hexmask.long 0xC 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR4 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation:"
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line.long 0x10 "NVIC_ISPR4,IRQ0 ~ IRQ143 Set-pending Control Register"
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hexmask.long 0x10 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR4 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation:"
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group.long 0x180++0x13
|
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line.long 0x0 "NVIC_ICPR0,IRQ0 ~ IRQ143 Clear-pending Control Register"
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hexmask.long 0x0 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR4 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation:"
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line.long 0x4 "NVIC_ICPR1,IRQ0 ~ IRQ143 Clear-pending Control Register"
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hexmask.long 0x4 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR4 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation:"
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line.long 0x8 "NVIC_ICPR2,IRQ0 ~ IRQ143 Clear-pending Control Register"
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hexmask.long 0x8 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR4 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation:"
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line.long 0xC "NVIC_ICPR3,IRQ0 ~ IRQ143 Clear-pending Control Register"
|
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hexmask.long 0xC 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR4 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation:"
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line.long 0x10 "NVIC_ICPR4,IRQ0 ~ IRQ143 Clear-pending Control Register"
|
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hexmask.long 0x10 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR4 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation:"
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group.long 0x200++0x13
|
|
line.long 0x0 "NVIC_IABR0,IRQ0 ~ IRQ143 Active Bit Register"
|
|
hexmask.long 0x0 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR4 registers indicate which interrupts are active."
|
|
line.long 0x4 "NVIC_IABR1,IRQ0 ~ IRQ143 Active Bit Register"
|
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hexmask.long 0x4 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR4 registers indicate which interrupts are active."
|
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line.long 0x8 "NVIC_IABR2,IRQ0 ~ IRQ143 Active Bit Register"
|
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hexmask.long 0x8 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR4 registers indicate which interrupts are active."
|
|
line.long 0xC "NVIC_IABR3,IRQ0 ~ IRQ143 Active Bit Register"
|
|
hexmask.long 0xC 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR4 registers indicate which interrupts are active."
|
|
line.long 0x10 "NVIC_IABR4,IRQ0 ~ IRQ143 Active Bit Register"
|
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hexmask.long 0x10 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR4 registers indicate which interrupts are active."
|
|
group.long 0x300++0x8F
|
|
line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ143 Priority Control Register"
|
|
bitfld.long 0x0 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
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bitfld.long 0x0 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x4 "NVIC_IPR1,IRQ0 ~ IRQ143 Priority Control Register"
|
|
bitfld.long 0x4 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x8 "NVIC_IPR2,IRQ0 ~ IRQ143 Priority Control Register"
|
|
bitfld.long 0x8 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0xC "NVIC_IPR3,IRQ0 ~ IRQ143 Priority Control Register"
|
|
bitfld.long 0xC 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x10 "NVIC_IPR4,IRQ0 ~ IRQ143 Priority Control Register"
|
|
bitfld.long 0x10 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x10 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x10 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x10 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x14 "NVIC_IPR5,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x14 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x14 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x14 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x14 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x18 "NVIC_IPR6,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x18 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x18 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x18 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x18 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x1C "NVIC_IPR7,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x1C 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x1C 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x1C 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x1C 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x20 "NVIC_IPR8,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x20 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x20 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x20 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x20 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x24 "NVIC_IPR9,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x24 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x24 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x24 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x24 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x28 "NVIC_IPR10,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x28 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x28 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x28 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x28 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x2C "NVIC_IPR11,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x2C 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x2C 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x2C 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x2C 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x30 "NVIC_IPR12,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x30 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x30 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x30 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x30 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x34 "NVIC_IPR13,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x34 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x34 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x34 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x34 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x38 "NVIC_IPR14,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x38 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x38 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x38 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x38 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x3C "NVIC_IPR15,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x3C 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x3C 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x3C 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x3C 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x40 "NVIC_IPR16,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x40 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x40 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x40 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x40 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x44 "NVIC_IPR17,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x44 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x44 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x44 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x44 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x48 "NVIC_IPR18,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x48 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x48 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x48 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x48 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x4C "NVIC_IPR19,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x4C 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x4C 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x4C 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x4C 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x50 "NVIC_IPR20,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x50 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x50 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x50 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x50 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x54 "NVIC_IPR21,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x54 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x54 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x54 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x54 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x58 "NVIC_IPR22,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x58 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x58 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x58 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x58 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x5C "NVIC_IPR23,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x5C 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x5C 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x5C 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x5C 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x60 "NVIC_IPR24,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x60 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x60 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x60 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x60 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x64 "NVIC_IPR25,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x64 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x64 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x64 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x64 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x68 "NVIC_IPR26,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x68 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x68 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x68 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x68 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x6C "NVIC_IPR27,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x6C 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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|
bitfld.long 0x6C 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x6C 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x6C 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x70 "NVIC_IPR28,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x70 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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|
bitfld.long 0x70 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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|
bitfld.long 0x70 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x70 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
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line.long 0x74 "NVIC_IPR29,IRQ0 ~ IRQ143 Priority Control Register"
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|
bitfld.long 0x74 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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|
bitfld.long 0x74 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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|
bitfld.long 0x74 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x74 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x78 "NVIC_IPR30,IRQ0 ~ IRQ143 Priority Control Register"
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|
bitfld.long 0x78 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x78 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x78 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x78 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x7C "NVIC_IPR31,IRQ0 ~ IRQ143 Priority Control Register"
|
|
bitfld.long 0x7C 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x7C 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x7C 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x7C 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x80 "NVIC_IPR32,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x80 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x80 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x80 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x80 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x84 "NVIC_IPR33,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x84 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x84 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x84 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x84 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x88 "NVIC_IPR34,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x88 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x88 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x88 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x88 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x8C "NVIC_IPR35,IRQ0 ~ IRQ143 Priority Control Register"
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bitfld.long 0x8C 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x8C 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x8C 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x8C 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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group.long 0xE00++0x3
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line.long 0x0 "STIR,Software Trigger Interrupt Registers"
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hexmask.long.word 0x0 0.--8. 1. "INTID,Interrupt ID\nWrite to the STIR To Generate An Interrupt from Software\nWhen the USERSETMPEND bit in the SCR is set to 1 unprivileged software can access the STIR\nInterrupt ID of the interrupt to trigger in the range 0-63. For example a value.."
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tree.end
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tree "OPA (Operational Amplifier)"
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base ad:0x40046000
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group.long 0x0++0xF
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line.long 0x0 "OPA_CTL,OP Amplifier Control Register"
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bitfld.long 0x0 14. "OPDOWKE2,OP Amplifier 2 Schmitt Trigger Digital Output Wake-up Enable Bit\nNote: If OPDOWKE2 is set to 1 and the OP amplifier 2 Schmitt trigger non-inverting buffer digital output changes state in Power-down mode an OPA wake-up is generated." "0: OP amplifier 2 digital output wake-up function..,1: OP amplifier 2 digital output wake-up function.."
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bitfld.long 0x0 13. "OPDOWKE1,OP Amplifier 1 Schmitt Trigger Digital Output Wake-up Enable Bit\nNote: If OPDOWKE1 is set to 1 and the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state in Power-down mode an OPA wake-up is generated." "0: OP amplifier 1 digital output wake-up function..,1: OP amplifier 1 digital output wake-up function.."
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bitfld.long 0x0 12. "OPDOWKE0,OP Amplifier 0 Schmitt Trigger Digital Output Wake-up Enable Bit\nNote: If OPDOWKE0 is set to 1 and the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state in Power-down mode an OPA wake-up is generated." "0: OP amplifier 0 digital output wake-up function..,1: OP amplifier 0 digital output wake-up function.."
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bitfld.long 0x0 10. "OPDOIEN2,OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Enable Bit\nNote: The OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt trigger non-inverting buffer digital output changes state in the meanwhile if OPDOIEN2.." "0: OP amplifier 2 digital output interrupt function..,1: OP amplifier 2 digital output interrupt function.."
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bitfld.long 0x0 9. "OPDOIEN1,OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit\nNote: The OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state in the meanwhile if OPDOIEN1.." "0: OP amplifier 1 digital output interrupt function..,1: OP amplifier 1 digital output interrupt function.."
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bitfld.long 0x0 8. "OPDOIEN0,OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit\nNote: The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state in the meanwhile if OPDOIEN0.." "0: OP amplifier 0 digital output interrupt function..,1: OP amplifier 0 digital output interrupt function.."
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bitfld.long 0x0 6. "OPDOEN2,OP Amplifier 2 Schmitt Trigger Non-inverting Buffer Enable Bit" "0: OP amplifier 2 schmitt trigger non-invert buffer..,1: OP amplifier 2 schmitt trigger non-invert buffer.."
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bitfld.long 0x0 5. "OPDOEN1,OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit" "0: OP amplifier 1 schmitt trigger non-invert buffer..,1: OP amplifier 1 schmitt trigger non-invert buffer.."
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bitfld.long 0x0 4. "OPDOEN0,OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit" "0: OP amplifier 0 schmitt trigger non-invert buffer..,1: OP amplifier 0 schmitt trigger non-invert buffer.."
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bitfld.long 0x0 2. "OPEN2,OP Amplifier 2 Enable Bit\nNote: OP amplifier 2 output needs wait stable 20μs after OPEN2 is set." "0: OP amplifier 2 Disabled,1: OP amplifier 2 Enabled"
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newline
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bitfld.long 0x0 1. "OPEN1,OP Amplifier 1 Enable Bit\nNote: OP amplifier 1 output needs wait stable 20μs after OPEN1 is set." "0: OP amplifier 1 Disabled,1: OP amplifier 1 Enabled"
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bitfld.long 0x0 0. "OPEN0,OP Amplifier 0 Enable Bit\nNote: OP amplifier 0 output needs wait stable 20μs after OPEN0 is set." "0: OP amplifier 0 Disabled,1: OP amplifier 0 Enabled"
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line.long 0x4 "OPA_MODE0,OP Amplifier Mode Control Register0"
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bitfld.long 0x4 24.--25. "SWSEL,OP Amplifier 0 Resistor End Switch Selection" "0: Input channel from OPA0 negative channel 0..,1: Input channel connected to AVSS is enabled,?,?"
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bitfld.long 0x4 23. "LMODE,Low Power Mode Enable Bit" "0: OPA operated in normal mode,1: OPA operated in low power mode"
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bitfld.long 0x4 20. "OUTOE,OP Amplifier 0 Output Enable Bit" "0: OP Amplifier 0 Output floating,1: OP Amplifier 0 Output to PAD"
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bitfld.long 0x4 16.--18. "GAIN,OP Amplifier 0 Gain Control" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x4 8.--11. 1. "NEGCHEN,OP Amplifier 0 Negative Input Channel Enable Bit\nNote 1: OPA_int_OUT means the input from OPA1 internal output\nNote 2: For example if NEGCHEN is selected as 0011 OPA0_N0 and OPA0_N1 are both enabled."
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hexmask.long.byte 0x4 0.--3. 1. "POSCHEN,OP Amplifier 0 Positvie Input Channel Enable Bit\nNote 1: OPA1_int_OUT means the input from OPA1 internal output\nNote 2: For example if POSCHEN is selected as 00011 PGA0_P0 and PGA0_P1 are both enabled."
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line.long 0x8 "OPA_MODE1,OP Amplifier Mode Control Register1"
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bitfld.long 0x8 24.--25. "SWSEL,OP Amplifier Resistor End Switch Selection" "0: Input channel from OPA1 negative channel 0..,1: Input channel connected to AVSS is enabled,?,?"
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bitfld.long 0x8 23. "LMODE,Low Power Mode Enable Bit" "0: OPA operated in normal mode,1: OPA operated in low power mode"
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newline
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bitfld.long 0x8 20. "OUTOE,OP Amplifier 1 Output Enable Bit" "0: OP Amplifier 1 Output floating,1: OP Amplifier 1 Output to PAD"
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bitfld.long 0x8 16.--18. "GAIN,OP Amplifier 1 Gain Control" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x8 8.--11. 1. "NEGCHEN,OP Amplifier 1 Negative Input Channel Enable Bit\nNote 1: OPA0_int_OUT means the input from OPA0 internal output\nNote 2: For example if NEGCHEN is selected as 0011 PGA1_N0 and PGA1_N1 are both enabled."
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hexmask.long.byte 0x8 0.--3. 1. "POSCHEN,OP Amplifier 1 Positvie Input Channel Enable Bit\nNote 1: OPA0_int_OUT means the input from OPA0 internal output\nNote 2: For example if POSCHEN is selected as 00011 PGA1_P0 and PGA1_P1 are both enabled."
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line.long 0xC "OPA_MODE2,OP Amplifier Mode Control Register2"
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bitfld.long 0xC 24.--25. "SWSEL,OP Amplifier Resistor End Switch Selection" "0: Input channel from OPA2 negative channel 0..,1: Input channel connected to AVSS is enabled,?,?"
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bitfld.long 0xC 23. "LMODE,Low Power Mode Enable Bit" "0: OPA operated in normal mode,1: OPA operated in low power mode"
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newline
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bitfld.long 0xC 20. "OUTOE,OP Amplifier 2 Output Enable Bit" "0: OP Amplifier 2 Output floating,1: OP Amplifier 2 Output to PAD"
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bitfld.long 0xC 16.--18. "GAIN,OP Amplifier 2 Gain Control" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0xC 8.--11. 1. "NEGCHEN,OP Amplifier 2 Negative Input Channel Enable Bit\nNote 1: OPA1_int_OUT means the input from OPA1 internal output\nNote 2: For example if NEGCHEN is selected as 0011 PGA2_N0 and PGA2_N1 are both enabled."
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hexmask.long.byte 0xC 0.--4. 1. "POSCHEN,OP Amplifier 2 Positvie Input Channel Enable Bit\nNote 1: OPA1_int_OUT means the input from OPA1 internal output\nNote 2: For example if POSCHEN is selected as 00011 PGA2_P0 and PGA2_P1 are both enabled."
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group.long 0x20++0x7
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line.long 0x0 "OPA_STATUS,OP Amplifier Status Register"
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bitfld.long 0x0 10. "OPDOWKF2,OP Amplifier 2 Schmitt Trigger Digital Output Wake-Up Flag\nOPDOWKF2 wake-up flag is set by hardware whenever OPDOWKE2 is set to 1 and the OP amplifier 2 Schmitt trigger non-inverting buffer digital output changes state in chip Power-down.." "0,1"
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bitfld.long 0x0 9. "OPDOWKF1,OP Amplifier 1 Schmitt Trigger Digital Output Wake-Up Flag\nOPDOWKF1 wake-up flag is set by hardware whenever OPDOWKE1 is set to 1 and the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state in chip Power-down mode." "0,1"
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bitfld.long 0x0 8. "OPDOWKF0,OP Amplifier 0 Schmitt Trigger Digital Output Wake-Up Flag\nOPDOWKF0 wake-up flag is set by hardware whenever OPDOWKE0 is set to 1 and the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state in chip Power-down.." "0,1"
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bitfld.long 0x0 6. "OPDOIF2,OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Flag\nIf chip is not in Power-down mode OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt trigger non-inverting buffer digital output changes state. If chip is.." "0,1"
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bitfld.long 0x0 5. "OPDOIF1,OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag\nIf chip is not in Power-down mode OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state. If chip is.." "0,1"
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bitfld.long 0x0 4. "OPDOIF0,OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag\nIf chip is not in Power-down mode OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state. If chip is.." "0,1"
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newline
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bitfld.long 0x0 2. "OPDO2,OP Amplifier 2 Digital Output" "0,1"
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bitfld.long 0x0 1. "OPDO1,OP Amplifier 1 Digital Output" "0,1"
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newline
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bitfld.long 0x0 0. "OPDO0,OP Amplifier 0 Digital Output" "0,1"
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line.long 0x4 "OPA_CALCTL,OP Amplifier Calibration Control Register"
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bitfld.long 0x4 26. "TRIMOPT2,OPA2 Calibration Trim Option" "0: Calibration trim from NMOS to PMOS,1: Calibration trim from PMOS to NMOS"
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bitfld.long 0x4 25. "TRIMOPT1,OPA1 Calibration Trim Option" "0: Calibration trim from NMOS to PMOS,1: Calibration trim from PMOS to NMOS"
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newline
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bitfld.long 0x4 24. "TRIMOPT0,OPA0 Calibration Trim Option" "0: Calibration trim from NMOS to PMOS,1: Calibration trim from PMOS to NMOS"
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bitfld.long 0x4 18. "CALRVS2,OPA2 Calibration Reference Voltage Selection" "0: VREF is,1: VREF from high vcm to low vcm"
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newline
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bitfld.long 0x4 17. "CALRVS1,OPA1 Calibration Reference Voltage Selection" "0: VREF is,1: VREF from high vcm to low vcm"
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bitfld.long 0x4 16. "CALRVS0,OPA0 Calibration Reference Voltage Selection" "0: VREF is,1: VREF from high vcm to low vcm"
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newline
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bitfld.long 0x4 8.--9. "CALCLK2,OP Amplifier 2 Calibration Clock Rate Selection" "0: 1 kHz,1: Reserved.,?,?"
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bitfld.long 0x4 6.--7. "CALCLK1,OP Amplifier 1 Calibration Clock Rate Selection" "0: 1 kHz,1: Reserved.,?,?"
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newline
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bitfld.long 0x4 4.--5. "CALCLK0,OP Amplifier 0 Calibration Clock Rate Selection" "0: 1 kHz,1: Reserved.,?,?"
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bitfld.long 0x4 2. "CALTRG2,OP Amplifier 2 Calibration Trigger Bit\nNote 1: Before this bit is enabled OPEN2 should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will auto clear this bit when calibration is finished." "0: Calibration is stopped,1: Before this bit is enabled"
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newline
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bitfld.long 0x4 1. "CALTRG1,OP Amplifier 1 Calibration Trigger Bit\nNote 1: Before this bit is enabled OPEN1 should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will auto clear this bit when calibration is finished." "0: Calibration is stopped,1: Before this bit is enabled"
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bitfld.long 0x4 0. "CALTRG0,OP Amplifier 0 Calibration Trigger Bit\nNote 1: Before this bit is enabled OPEN0 should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote 2: Hardware will auto clear this bit when calibration is finished." "0: Calibration is stopped,1: Before this bit is enabled"
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rgroup.long 0x28++0x3
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line.long 0x0 "OPA_CALST,OP Amplifier Calibration Status Register"
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bitfld.long 0x0 10. "CALPS2,OP Amplifier 2 Calibration Result Status for PMOS" "0: Pass,1: Fail"
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bitfld.long 0x0 9. "CALNS2,OP Amplifier 2 Calibration Result Status for NMOS" "0: Pass,1: Fail"
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newline
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bitfld.long 0x0 8. "DONE2,OP Amplifier 2 Calibration Done Status" "0: Calibrating,1: Calibration Done"
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bitfld.long 0x0 6. "CALPS1,OP Amplifier 1 Calibration Result Status for PMOS" "0: Pass,1: Fail"
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newline
|
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bitfld.long 0x0 5. "CALNS1,OP Amplifier 1 Calibration Result Status for NMOS" "0: Pass,1: Fail"
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bitfld.long 0x0 4. "DONE1,OP Amplifier 1 Calibration Done Status" "0: Calibrating,1: Calibration Done"
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newline
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bitfld.long 0x0 2. "CALPS0,OP Amplifier 0 Calibration Result Status for PMOS" "0: Pass,1: Fail"
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bitfld.long 0x0 1. "CALNS0,OP Amplifier 0 Calibration Result Status for NMOS" "0: Pass,1: Fail"
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newline
|
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bitfld.long 0x0 0. "DONE0,OP Amplifier 0 Calibration Done Status" "0: Calibrating,1: Calibration Done"
|
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tree.end
|
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tree "OTG (USB On-The-Go)"
|
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base ad:0x4004D000
|
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group.long 0x0++0xF
|
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line.long 0x0 "OTG_CTL,OTG Control Register"
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bitfld.long 0x0 5. "WKEN,OTG ID Pin Wake-up Enable Bit" "0: OTG ID pin status change wake-up function Disabled,1: OTG ID pin status change wake-up function Enabled"
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bitfld.long 0x0 4. "OTGEN,OTG Function Enable Bit\nUser needs to set this bit to enable OTG function while the USB frame configured as OTG device. When the USB frame is not configured as OTG device this bit must be low." "0: OTG function Disabled,1: OTG function Enabled"
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newline
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bitfld.long 0x0 2. "HNPREQEN,OTG HNP Request Enable Bit\nWhen the USB frame acts as A-device set this bit when A-device allows to process HNP protocolA-device changes role from Host to Peripheral. This bit will be cleared when OTG state changes from a_suspend to.." "0: HNP request Disabled,1: HNP request Enabled (A-device can change role.."
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bitfld.long 0x0 1. "BUSREQ,OTG Bus Request\nIf OTG A-device wants to do data transfers via USB bus setting this bit will drive VBUS high to detect USB device connection. If user won't use the bus any more clearing this bit will drop VBUS to save power. This bit will be.." "0: Not launch VBUS in OTG A-device or not request..,1: Launch VBUS in OTG A-device or request SRP in.."
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newline
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bitfld.long 0x0 0. "VBUSDROP,Drop VBUS Control\nIf user application running on this OTG A-device wants to conserve power set this bit to drop VBUS. BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device." "0: Not drop the VBUS,1: Drop the VBUS"
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line.long 0x4 "OTG_PHYCTL,OTG PHY Control Register"
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bitfld.long 0x4 5. "VBSTSPOL,Off-chip USB VBUS Power Switch Status Polarity\nThe polarity of off-chip USB VBUS power switch valid signal depends on the selected component. A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch. Set this.." "0: The polarity of off-chip USB VBUS power switch..,1: The polarity of off-chip USB VBUS power switch.."
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bitfld.long 0x4 4. "VBENPOL,Off-chip USB VBUS Power Switch Enable Polarity\nThe OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need. A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.\nThe polarity of enabling.." "0: The off-chip USB VBUS power switch enable is..,1: The off-chip USB VBUS power switch enable is.."
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newline
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bitfld.long 0x4 1. "IDDETEN,ID Detection Enable Bit" "0: Detect ID pin status Disabled,1: Detect ID pin status Enabled"
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bitfld.long 0x4 0. "OTGPHYEN,OTG PHY Enable Bit\nWhen the USB frame is configured as either OTG device or ID dependent user needs to set this bit before using OTG function. If device is configured as neither OTG device nor ID dependent this bit is 'don't care'." "0: OTG PHY Disabled,1: OTG PHY Enabled"
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line.long 0x8 "OTG_INTEN,OTG Interrupt Enable Register"
|
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bitfld.long 0x8 13. "SRPDETIEN,SRP Detected Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 11. "SECHGIEN,SESSEND Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x8 10. "VBCHGIEN,VBUSVLD Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 9. "AVLDCHGIEN,A-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x8 8. "BVLDCHGIEN,B-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 7. "HOSTIEN,Act As Host Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a host an interrupt will be asserted." "0: This device as a host interrupt Disabled,1: This device as a host interrupt Enabled"
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newline
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bitfld.long 0x8 6. "PDEVIEN,Act As Peripheral Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a peripheral an interrupt will be asserted." "0: This device as a peripheral interrupt Disabled,1: This device as a peripheral interrupt Enabled"
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bitfld.long 0x8 5. "IDCHGIEN,IDSTS Changed Interrupt Enable Bit\nIf this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high an interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x8 4. "GOIDLEIEN,OTG Device Going to IDLE State Interrupt Enable Bit\nNote: Going to idle state means going to a_idle or b_idle state. Please refer to A-device state diagram and B-device state diagram in OTG specification." "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x8 3. "HNPFIEN,HNP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x8 2. "SRPFIEN,SRP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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|
bitfld.long 0x8 1. "VBEIEN,VBUS Error Interrupt Enable Bit\nNote: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification." "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x8 0. "ROLECHGIEN,Role Changed Interrupt Enable Bit\nNote: Role is Host or Peripheral." "0: Interrupt Disabled,1: Interrupt Enabled"
|
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line.long 0xC "OTG_INTSTS,OTG Interrupt Status Register"
|
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bitfld.long 0xC 13. "SRPDETIF,SRP Detected Interrupt Status\nNote: Write 1 to clear this status." "0: SRP not detected,1: SRP detected"
|
|
bitfld.long 0xC 11. "SECHGIF,SESSEND State Change Interrupt Status\nNote: Write 1 to clear this flag." "0: SESSEND (OTG_STATUS[2]) not toggled,1: SESSEND (OTG_STATUS[2]) from high to low or from.."
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newline
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bitfld.long 0xC 10. "VBCHGIF,VBUSVLD State Change Interrupt Status\nNote: Write 1 to clear this status." "0: VBUSVLD (OTG_STATUS[5]) not toggled,1: VBUSVLD (OTG_STATUS[5]) from high to low or from.."
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bitfld.long 0xC 9. "AVLDCHGIF,A-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status." "0: AVLD (OTG_STATUS[4]) not toggled,1: AVLD (OTG_STATUS[4]) from high to low or low to.."
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newline
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bitfld.long 0xC 8. "BVLDCHGIF,B-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status." "0: BVLD (OTG_STATUS[3]) not toggled,1: BVLD (OTG_STATUS[3]) from high to low or low to.."
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bitfld.long 0xC 7. "HOSTIF,Act As Host Interrupt Status\nNote: Write 1 to clear this flag." "0: This device does not act as a host,1: This device acts as a host"
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newline
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bitfld.long 0xC 6. "PDEVIF,Act As Peripheral Interrupt Status\nNote: Write 1 to clear this flag." "0: This device does not act as a peripheral,1: This device acts as a peripheral"
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bitfld.long 0xC 5. "IDCHGIF,ID State Change Interrupt Status\nNote: Write 1 to clear this flag." "0: IDSTS (OTG_STATUS[1]) not toggled,1: IDSTS (OTG_STATUS[1]) from high to low or from.."
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newline
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bitfld.long 0xC 4. "GOIDLEIF,OTG Device Goes to IDLE Interrupt Status\nFlag is set if the OTG device transfers from non-idle state to idle state. The OTG device will be neither a host nor a peripheral.\nNote 1: Going to idle state means going to a_idle or b_idle state." "0: OTG device does not go back to idle state..,1: Going to idle state means going to a_idle or.."
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bitfld.long 0xC 3. "HNPFIF,HNP Fail Interrupt Status\nWhen A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state this bit will be set when A-device does not connect after specified interval expires. \nNote: Write 1 to clear this.." "0: A-device connects to B-device before specified..,1: A-device does not connect to B-device before.."
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newline
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bitfld.long 0xC 2. "SRPFIF,SRP Fail Interrupt Status\nAfter initiating SRP an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum defined in OTG specification. This flag is set when the OTG B-device does not get VBUS high after this.." "0: OTG B-device gets VBUS high before this interval,1: OTG B-device does not get VBUS high before this.."
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bitfld.long 0xC 1. "VBEIF,VBUS Error Interrupt Status\nThis bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. \nNote: Write 1 to clear this flag and recover from.." "0: OTG A-device drives VBUS over threshold voltage..,1: OTG A-device cannot drive VBUS over threshold.."
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newline
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bitfld.long 0xC 0. "ROLECHGIF,OTG Role Change Interrupt Status\nThis flag is set when the role of an OTG device changed from a host to a peripheral or changed from a peripheral to a host while USB_ID pin status does not change.\nNote: Write 1 to clear this flag." "0: OTG device role not changed,1: OTG device role changed"
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rgroup.long 0x10++0x3
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line.long 0x0 "OTG_STATUS,OTG Status Register"
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bitfld.long 0x0 7. "ASHOST,As Host Status\nWhen OTG acts as Host this bit is set." "0: OTG not as Host,1: OTG as Host"
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bitfld.long 0x0 6. "ASPERI,As Peripheral Status\nWhen OTG acts as peripheral this bit is set." "0: OTG not as peripheral,1: OTG as peripheral"
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newline
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bitfld.long 0x0 5. "VBUSVLD,VBUS Valid Status\nWhen VBUS is larger than 4.7V this bit will be set to 1." "0: VBUS is not valid,1: VBUS is valid"
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bitfld.long 0x0 4. "AVLD,A-Device Session Valid Status" "0: A-device session is not valid,1: A-device session is valid"
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newline
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bitfld.long 0x0 3. "BVLD,B-device Session Valid Status" "0: B-device session is not valid,1: B-device session is valid"
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bitfld.long 0x0 2. "SESSEND,Session End Status\nWhen VBUS voltage is lower than 0.4V this bit will be set to 1. Session end means no meaningful power on VBUS." "0: Session is not end,1: Session is end"
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newline
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bitfld.long 0x0 1. "IDSTS,USB_ID Pin State of Mini-/Micro-Plug" "0: Mini-A/Micro-A plug is attached,1: Mini-B/Micro-B plug is attached"
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bitfld.long 0x0 0. "OVERCUR,Overcurrent Condition\nThe voltage on VBUS cannot reach a minimum VBUS valid threshold 4.4V minimum within a maximum time of 100ms after OTG A-device drives VBUS high." "0: OTG A-device drives VBUS successfully,1: OTG A-device cannot drives VBUS high in this.."
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tree.end
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tree "PDMA (Peripheral Direct Memory Access)"
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base ad:0x40008000
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group.long 0x0++0x3
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line.long 0x0 "PDMAx_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x10++0x3
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line.long 0x0 "PDMAx_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x20++0x3
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line.long 0x0 "PDMAx_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x30++0x3
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line.long 0x0 "PDMAx_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x40++0x3
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line.long 0x0 "PDMAx_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x50++0x3
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line.long 0x0 "PDMAx_DSCT5_CTL,Descriptor Table Control Register of PDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x60++0x3
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line.long 0x0 "PDMAx_DSCT6_CTL,Descriptor Table Control Register of PDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x70++0x3
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line.long 0x0 "PDMAx_DSCT7_CTL,Descriptor Table Control Register of PDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x80++0x3
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line.long 0x0 "PDMAx_DSCT8_CTL,Descriptor Table Control Register of PDMA Channel n"
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hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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newline
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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newline
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x90++0x3
|
|
line.long 0x0 "PDMAx_DSCT9_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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|
newline
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|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
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|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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|
group.long 0xA0++0x3
|
|
line.long 0x0 "PDMAx_DSCT10_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
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|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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|
group.long 0xB0++0x3
|
|
line.long 0x0 "PDMAx_DSCT11_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "PDMAx_DSCT12_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "PDMAx_DSCT13_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0xE0++0x3
|
|
line.long 0x0 "PDMAx_DSCT14_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "PDMAx_DSCT15_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: PDMA transfer source address (PDMA_DSCTn_SA) and PDMA transfer destination address (PDMA_DSCTn_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is 1 it will not generates TDIFn (PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check PDMA_INTSTS[1] to make sure the current task is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "PDMAx_DSCT0_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "PDMAx_DSCT1_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "PDMAx_DSCT2_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "PDMAx_DSCT3_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "PDMAx_DSCT4_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "PDMAx_DSCT5_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "PDMAx_DSCT6_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "PDMAx_DSCT7_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "PDMAx_DSCT8_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "PDMAx_DSCT9_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0xA4++0x3
|
|
line.long 0x0 "PDMAx_DSCT10_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "PDMAx_DSCT11_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "PDMAx_DSCT12_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0xD4++0x3
|
|
line.long 0x0 "PDMAx_DSCT13_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "PDMAx_DSCT14_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0xF4++0x3
|
|
line.long 0x0 "PDMAx_DSCT15_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PDMAx_DSCT0_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PDMAx_DSCT1_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PDMAx_DSCT2_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PDMAx_DSCT3_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PDMAx_DSCT4_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PDMAx_DSCT5_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PDMAx_DSCT6_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PDMAx_DSCT7_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PDMAx_DSCT8_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PDMAx_DSCT9_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0xA8++0x3
|
|
line.long 0x0 "PDMAx_DSCT10_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "PDMAx_DSCT11_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "PDMAx_DSCT12_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "PDMAx_DSCT13_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "PDMAx_DSCT14_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "PDMAx_DSCT15_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PDMAx_DSCT0_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "PDMAx_DSCT1_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "PDMAx_DSCT2_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "PDMAx_DSCT3_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "PDMAx_DSCT4_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "PDMAx_DSCT5_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PDMAx_DSCT6_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "PDMAx_DSCT7_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "PDMAx_DSCT8_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "PDMAx_DSCT9_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0xAC++0x3
|
|
line.long 0x0 "PDMAx_DSCT10_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0xBC++0x3
|
|
line.long 0x0 "PDMAx_DSCT11_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0xCC++0x3
|
|
line.long 0x0 "PDMAx_DSCT12_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0xDC++0x3
|
|
line.long 0x0 "PDMAx_DSCT13_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0xEC++0x3
|
|
line.long 0x0 "PDMAx_DSCT14_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "PDMAx_DSCT15_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the next descriptor table is start.."
|
|
rgroup.long 0x100++0x3F
|
|
line.long 0x0 "PDMAx_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x4 "PDMAx_CURSCAT1,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x4 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x8 "PDMAx_CURSCAT2,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x8 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0xC "PDMAx_CURSCAT3,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0xC 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x10 "PDMAx_CURSCAT4,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x10 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x14 "PDMAx_CURSCAT5,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x14 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x18 "PDMAx_CURSCAT6,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x18 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x1C "PDMAx_CURSCAT7,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x1C 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x20 "PDMAx_CURSCAT8,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x20 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x24 "PDMAx_CURSCAT9,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x24 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x28 "PDMAx_CURSCAT10,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x28 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x2C "PDMAx_CURSCAT11,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x2C 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x30 "PDMAx_CURSCAT12,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x30 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x34 "PDMAx_CURSCAT13,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x34 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x38 "PDMAx_CURSCAT14,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x38 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
line.long 0x3C "PDMAx_CURSCAT15,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x3C 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description.."
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "PDMAx_CHCTL,PDMA Channel Control Register"
|
|
bitfld.long 0x0 15. "CHEN15,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 14. "CHEN14,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "CHEN13,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 12. "CHEN12,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "CHEN11,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 10. "CHEN10,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "CHEN9,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 8. "CHEN8,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "CHEN7,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 6. "CHEN6,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CHEN5,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 4. "CHEN4,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "CHEN3,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 2. "CHEN2,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "CHEN1,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 0. "CHEN0,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
wgroup.long 0x404++0x7
|
|
line.long 0x0 "PDMAx_PAUSE,PDMA Transfer Pause Control Register"
|
|
bitfld.long 0x0 15. "PAUSE15,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 14. "PAUSE14,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x0 13. "PAUSE13,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 12. "PAUSE12,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x0 11. "PAUSE11,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 10. "PAUSE10,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x0 9. "PAUSE9,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 8. "PAUSE8,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x0 7. "PAUSE7,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 6. "PAUSE6,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x0 5. "PAUSE5,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 4. "PAUSE4,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "PAUSE3,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 2. "PAUSE2,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x0 1. "PAUSE1,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 0. "PAUSE0,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
line.long 0x4 "PDMAx_SWREQ,PDMA Software Request Register"
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bitfld.long 0x4 15. "SWREQ15,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 14. "SWREQ14,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 13. "SWREQ13,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 12. "SWREQ12,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 11. "SWREQ11,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 10. "SWREQ10,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 9. "SWREQ9,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 8. "SWREQ8,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 7. "SWREQ7,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 6. "SWREQ6,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 5. "SWREQ5,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 4. "SWREQ4,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 3. "SWREQ3,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 2. "SWREQ2,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 1. "SWREQ1,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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bitfld.long 0x4 0. "SWREQ0,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMAx_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral.." "0: No effect,1: User can read PDMAx_TRGSTS register to know.."
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rgroup.long 0x40C++0x3
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line.long 0x0 "PDMAx_TRGSTS,PDMA Channel Request Status Register"
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bitfld.long 0x0 15. "REQSTS15,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 14. "REQSTS14,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 13. "REQSTS13,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 12. "REQSTS12,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 11. "REQSTS11,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 10. "REQSTS10,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 9. "REQSTS9,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 8. "REQSTS8,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 7. "REQSTS7,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 6. "REQSTS6,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 5. "REQSTS5,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 4. "REQSTS4,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 3. "REQSTS3,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 2. "REQSTS2,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 1. "REQSTS1,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x0 0. "REQSTS0,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. \nNote:.." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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group.long 0x410++0x3
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line.long 0x0 "PDMAx_PRISET,PDMA Fixed Priority Setting Register"
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bitfld.long 0x0 15. "FPRISET15,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 14. "FPRISET14,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 13. "FPRISET13,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 12. "FPRISET12,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 11. "FPRISET11,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 10. "FPRISET10,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 9. "FPRISET9,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 8. "FPRISET8,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 7. "FPRISET7,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 6. "FPRISET6,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 5. "FPRISET5,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 4. "FPRISET4,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 3. "FPRISET3,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 2. "FPRISET2,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 1. "FPRISET1,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x0 0. "FPRISET0,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register." "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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wgroup.long 0x414++0x3
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line.long 0x0 "PDMAx_PRICLR,PDMA Fixed Priority Clear Register"
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bitfld.long 0x0 15. "FPRICLR15,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 14. "FPRICLR14,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 13. "FPRICLR13,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 12. "FPRICLR12,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 11. "FPRICLR11,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 10. "FPRICLR10,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 9. "FPRICLR9,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 8. "FPRICLR8,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 7. "FPRICLR7,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 6. "FPRICLR6,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 5. "FPRICLR5,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 4. "FPRICLR4,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 3. "FPRICLR3,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 2. "FPRICLR2,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 1. "FPRICLR1,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 0. "FPRICLR0,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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group.long 0x418++0x13
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line.long 0x0 "PDMAx_INTEN,PDMA Interrupt Enable Register"
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bitfld.long 0x0 15. "INTEN15,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 14. "INTEN14,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 13. "INTEN13,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 12. "INTEN12,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 11. "INTEN11,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 10. "INTEN10,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 9. "INTEN9,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 8. "INTEN8,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 7. "INTEN7,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 6. "INTEN6,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 5. "INTEN5,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 4. "INTEN4,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 3. "INTEN3,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 2. "INTEN2,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 1. "INTEN1,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 0. "INTEN0,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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line.long 0x4 "PDMAx_INTSTS,PDMA Interrupt Status Register"
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bitfld.long 0x4 9. "REQTOF1,Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC1(PDMA_TOC0_1[31:16]).\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: User can.." "0: No request time-out,1: Please disable time-out function before clearing.."
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bitfld.long 0x4 8. "REQTOF0,Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by TOC0(PDMA_TOC0_1[15:0].\nNote 1: Please disable time-out function before clearing this bit.\nNote 2: User can.." "0: No request time-out,1: Please disable time-out function before clearing.."
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rbitfld.long 0x4 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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rbitfld.long 0x4 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer." "0: Not finished yet,1: PDMA channel has finished transmission"
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rbitfld.long 0x4 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error." "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
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line.long 0x8 "PDMAx_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
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bitfld.long 0x8 15. "ABTIF15,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 14. "ABTIF14,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 13. "ABTIF13,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 12. "ABTIF12,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 11. "ABTIF11,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 10. "ABTIF10,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this.." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 9. "ABTIF9,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 8. "ABTIF8,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 7. "ABTIF7,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 6. "ABTIF6,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 5. "ABTIF5,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 4. "ABTIF4,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 3. "ABTIF3,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 2. "ABTIF2,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 1. "ABTIF1,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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bitfld.long 0x8 0. "ABTIF0,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error. \nNote 1: If channel n target abort REQSRCn should set0 to disable peripheral request.\nNote 2: User can write 1 to clear this bit." "0: No AHB bus ERROR response received when channel..,1: If channel n target abort"
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line.long 0xC "PDMAx_TDSTS,PDMA Channel Transfer Done Flag Register"
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bitfld.long 0xC 15. "TDIF15,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 14. "TDIF14,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 13. "TDIF13,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 12. "TDIF12,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 11. "TDIF11,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 10. "TDIF10,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 9. "TDIF9,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 8. "TDIF8,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 7. "TDIF7,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 6. "TDIF6,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 5. "TDIF5,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 4. "TDIF4,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 3. "TDIF3,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 2. "TDIF2,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 1. "TDIF1,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 0. "TDIF0,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not. \nNote: User can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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line.long 0x10 "PDMAx_ALIGN,PDMA Transfer Alignment Status Register"
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bitfld.long 0x10 15. "ALIGN15,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 14. "ALIGN14,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 13. "ALIGN13,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 12. "ALIGN12,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 11. "ALIGN11,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 10. "ALIGN10,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 9. "ALIGN9,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 8. "ALIGN8,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 7. "ALIGN7,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 6. "ALIGN6,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 5. "ALIGN5,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 4. "ALIGN4,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 3. "ALIGN3,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 2. "ALIGN2,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 1. "ALIGN1,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x10 0. "ALIGN0,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting. \nNote: User can write 1 to clear these bits." "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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rgroup.long 0x42C++0x3
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line.long 0x0 "PDMAx_TACTSTS,PDMA Transfer Active Flag Register"
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bitfld.long 0x0 15. "TXACTF15,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 14. "TXACTF14,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 13. "TXACTF13,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 12. "TXACTF12,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 11. "TXACTF11,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 10. "TXACTF10,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 9. "TXACTF9,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 8. "TXACTF8,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 7. "TXACTF7,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 6. "TXACTF6,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 5. "TXACTF5,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 4. "TXACTF4,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x0 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active." "0: PDMA channel is finished,1: PDMA channel is active"
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group.long 0x430++0x13
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line.long 0x0 "PDMAx_TOUTPSC,PDMA Time-out Prescaler Register(CH0 to CH1)"
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bitfld.long 0x0 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,?,?,?,?,?,?"
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line.long 0x4 "PDMAx_TOUTEN,PDMA Time-out Enable Register"
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bitfld.long 0x4 1. "TOUTEN1,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 0. "TOUTEN0,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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line.long 0x8 "PDMAx_TOUTIEN,PDMA Time-out Interrupt Enable Register"
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bitfld.long 0x8 1. "TOUTIEN1,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 0. "TOUTIEN0,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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line.long 0xC "PDMAx_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
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hexmask.long.word 0xC 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address\nIn Scatter-gather mode this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-gather mode."
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line.long 0x10 "PDMAx_TOC,PDMA Time-out Counter Ch0 and Ch1 Register"
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hexmask.long.word 0x10 16.--31. 1. "TOC1,Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[6:4]) clock. The example of time-out period can refer TOC0 bit description."
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hexmask.long.word 0x10 0.--15. 1. "TOC0,Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock."
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group.long 0x460++0x3
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line.long 0x0 "PDMAx_CHRST,PDMA Channel Reset Register"
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bitfld.long 0x0 15. "CH15RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 14. "CH14RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 13. "CH13RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 12. "CH12RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 11. "CH11RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 10. "CH10RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 9. "CH9RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 8. "CH8RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 7. "CH7RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 6. "CH6RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 5. "CH5RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 4. "CH4RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 3. "CH3RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 2. "CH2RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 1. "CH1RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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bitfld.long 0x0 0. "CH0RST,PDMA Channel n Reset Control\nNote: After PDMA current request transfer is complete this bit will be cleared automatically." "0: Corresponding channel n is not reset,1: Corresponding channel n is reset"
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group.long 0x480++0xF
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line.long 0x0 "PDMAx_REQSEL0_3,PDMA Request Source Select Register 0"
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hexmask.long.byte 0x0 24.--30. 1. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 16.--22. 1. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 8.--14. 1. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 0.--6. 1. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral cannot be assigned to two channels at the same time.\nNote 2: This.."
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line.long 0x4 "PDMAx_REQSEL4_7,PDMA Request Source Select Register 1"
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hexmask.long.byte 0x4 24.--30. 1. "REQSRC7,Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x4 16.--22. 1. "REQSRC6,Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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newline
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hexmask.long.byte 0x4 8.--14. 1. "REQSRC5,Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x4 0.--6. 1. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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line.long 0x8 "PDMAx_REQSEL8_11,PDMA Request Source Select Register 2"
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hexmask.long.byte 0x8 24.--30. 1. "REQSRC11,Channel 11 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 11. User can configure the peripheral setting by REQSRC11. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x8 16.--22. 1. "REQSRC10,Channel 10 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 10. User can configure the peripheral setting by REQSRC10. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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newline
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hexmask.long.byte 0x8 8.--14. 1. "REQSRC9,Channel 9 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 9. User can configure the peripheral setting by REQSRC9. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x8 0.--6. 1. "REQSRC8,Channel 8 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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line.long 0xC "PDMAx_REQSEL12_15,PDMA Request Source Select Register 3"
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hexmask.long.byte 0xC 24.--30. 1. "REQSRC15,Channel 15 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 15. User can configure the peripheral setting by REQSRC15. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0xC 16.--22. 1. "REQSRC14,Channel 14 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 14. User can configure the peripheral setting by REQSRC14. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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newline
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hexmask.long.byte 0xC 8.--14. 1. "REQSRC13,Channel 13 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 13. User can configure the peripheral setting by REQSRC13. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0xC 0.--6. 1. "REQSRC12,Channel 12 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 12. User can configure the peripheral setting by REQSRC12. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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tree.end
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tree "PWM (PWM Generator and Capture Timer)"
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base ad:0x0
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tree "PWM0"
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base ad:0x4005C000
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group.long 0x0++0x7
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line.long 0x0 "PWM_CTL0,PWM Control Register 0"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disable,1: ICE debug mode counter halt Enable"
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bitfld.long 0x0 16. "IMMLDENn,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x0 0. "CTRLDn,Center Load Enable Bits\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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line.long 0x4 "PWM_CTL1,PWM Control Register 1"
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bitfld.long 0x4 24.--26. "OUTMODEn,PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode,?,?,?,?,?,?"
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bitfld.long 0x4 8.--9. "CNTTYPE4,PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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newline
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bitfld.long 0x4 4.--5. "CNTTYPE2,PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 0.--1. "CNTTYPE0,PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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group.long 0x10++0x17
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line.long 0x0 "PWM_CLKSRC,PWM Clock Source Register"
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bitfld.long 0x0 16.--18. "ECLKSRC4,PWM_CH45 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "ECLKSRC2,PWM_CH23 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 0.--2. "ECLKSRC0,PWM_CH01 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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line.long 0x4 "PWM_CLKPSC0_1,PWM Clock Prescale Register 0/1"
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hexmask.long.word 0x4 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0x8 "PWM_CLKPSC2_3,PWM Clock Prescale Register 2/3"
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hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0xC "PWM_CLKPSC4_5,PWM Clock Prescale Register 4/5"
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hexmask.long.word 0xC 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0x10 "PWM_CNTEN,PWM Counter Enable Register"
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bitfld.long 0x10 4. "CNTEN4,PWM Counter Enable Bit 4" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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bitfld.long 0x10 2. "CNTEN2,PWM Counter Enable Bit 2" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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newline
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bitfld.long 0x10 0. "CNTEN0,PWM Counter Enable Bit 0" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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line.long 0x14 "PWM_CNTCLR,PWM Clear Counter Register"
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bitfld.long 0x14 4. "CNTCLR4,Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
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bitfld.long 0x14 2. "CNTCLR2,Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
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newline
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bitfld.long 0x14 0. "CNTCLR0,Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
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group.long 0x30++0x3
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line.long 0x0 "PWM_PERIOD0,PWM Period Register 0"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x38++0x3
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line.long 0x0 "PWM_PERIOD2,PWM Period Register 2"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x40++0x3
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line.long 0x0 "PWM_PERIOD4,PWM Period Register 4"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x50++0x17
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line.long 0x0 "PWM_CMPDAT0,PWM Comparator Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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line.long 0x4 "PWM_CMPDAT1,PWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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line.long 0x8 "PWM_CMPDAT2,PWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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line.long 0xC "PWM_CMPDAT3,PWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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line.long 0x10 "PWM_CMPDAT4,PWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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line.long 0x14 "PWM_CMPDAT5,PWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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group.long 0x70++0xB
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line.long 0x0 "PWM_DTCTL0_1,PWM Dead-time Control Register 0/1"
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bitfld.long 0x0 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x0 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of pin pair are complementary without any delay.\nNote: This.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x0 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x4 "PWM_DTCTL2_3,PWM Dead-time Control Register 2/3"
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bitfld.long 0x4 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x4 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of pin pair are complementary without any delay.\nNote: This.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x4 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x8 "PWM_DTCTL4_5,PWM Dead-time Control Register 4/5"
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bitfld.long 0x8 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x8 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of pin pair are complementary without any delay.\nNote: This.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x8 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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rgroup.long 0x90++0x3
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line.long 0x0 "PWM_CNT0,PWM Counter Register 0"
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bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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rgroup.long 0x98++0x3
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line.long 0x0 "PWM_CNT2,PWM Counter Register 2"
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bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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rgroup.long 0xA0++0x3
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line.long 0x0 "PWM_CNT4,PWM Counter Register 4"
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bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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group.long 0xB0++0x2B
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line.long 0x0 "PWM_WGCTL0,PWM Generation Register 0"
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bitfld.long 0x0 26.--27. "PRDPCTL5,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 24.--25. "PRDPCTL4,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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newline
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bitfld.long 0x0 22.--23. "PRDPCTL3,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 20.--21. "PRDPCTL2,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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newline
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bitfld.long 0x0 18.--19. "PRDPCTL1,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 16.--17. "PRDPCTL0,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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newline
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bitfld.long 0x0 10.--11. "ZPCTL5,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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bitfld.long 0x0 8.--9. "ZPCTL4,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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newline
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bitfld.long 0x0 6.--7. "ZPCTL3,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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bitfld.long 0x0 4.--5. "ZPCTL2,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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newline
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bitfld.long 0x0 2.--3. "ZPCTL1,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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bitfld.long 0x0 0.--1. "ZPCTL0,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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line.long 0x4 "PWM_WGCTL1,PWM Generation Register 1"
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bitfld.long 0x4 26.--27. "CMPDCTL5,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 24.--25. "CMPDCTL4,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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newline
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bitfld.long 0x4 22.--23. "CMPDCTL3,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 20.--21. "CMPDCTL2,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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newline
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bitfld.long 0x4 18.--19. "CMPDCTL1,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 16.--17. "CMPDCTL0,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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newline
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bitfld.long 0x4 10.--11. "CMPUCTL5,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 8.--9. "CMPUCTL4,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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newline
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bitfld.long 0x4 6.--7. "CMPUCTL3,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 4.--5. "CMPUCTL2,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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newline
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bitfld.long 0x4 2.--3. "CMPUCTL1,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 0.--1. "CMPUCTL0,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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line.long 0x8 "PWM_MSKEN,PWM Mask Enable Register"
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bitfld.long 0x8 5. "MSKEN5,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 4. "MSKEN4,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 2. "MSKEN2,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 0. "MSKEN0,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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line.long 0xC "PWM_MSK,PWM Mask Data Register"
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bitfld.long 0xC 5. "MSKDAT5,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 4. "MSKDAT4,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 3. "MSKDAT3,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 2. "MSKDAT2,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 1. "MSKDAT1,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 0. "MSKDAT0,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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line.long 0x10 "PWM_BNF,PWM Brake Noise Filter Register"
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bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select\nFor PWM0 setting:" "0: Brake 1 pin source come from PWM0_BRAKE1.\nBrake..,1: Brake 1 pin source come from PWM1_BRAKE1.\nBrake.."
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bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select\nFor PWM0 setting:" "0: Brake 0 pin source come from PWM0_BRAKE0.\nBrake..,1: Brake 0 pin source come from PWM1_BRAKE0.\nBrake.."
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bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: The state of pin PWMx_BRAKE1 is passed to the..,1: The inversed state of pin PWMx_BRAKE1 is passed.."
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bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 9.--11. "BRK1FSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 8. "BRK1NFEN,PWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled"
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bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: The state of pin PWMx_BRAKE0 is passed to the..,1: The inversed state of pin PWMx_BRAKE10 is passed.."
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bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 1.--3. "BRK0FSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "BRK0NFEN,PWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled"
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line.long 0x14 "PWM_FAILBRK,PWM System Fail Brake Control Register"
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bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x14 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by CSS detection Disabled,1: Brake Function triggered by CSS detection Enabled"
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line.long 0x18 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0/1"
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bitfld.long 0x18 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x18 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x18 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x18 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x18 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect or edge-detect..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x18 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect or edge-detect..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x18 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x18 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x18 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x18 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x18 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x18 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x18 6. "VBSNEBEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x18 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x18 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x18 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x18 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x18 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x1C "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2/3"
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bitfld.long 0x1C 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x1C 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x1C 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x1C 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x1C 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect or edge-detect..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x1C 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect or edge-detect..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x1C 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x1C 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x1C 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x1C 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x1C 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x1C 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x1C 6. "VBSNEBEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x1C 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x1C 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x1C 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x20 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4/5"
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bitfld.long 0x20 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x20 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x20 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x20 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x20 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect or edge-detect..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x20 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect or edge-detect..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x20 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x20 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x20 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x20 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x20 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x20 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x20 6. "VBSNEBEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x20 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x20 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x20 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x20 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x20 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x24 "PWM_POLCTL,PWM Pin Polar Inverse Register"
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bitfld.long 0x24 5. "PINV5,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 4. "PINV4,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 3. "PINV3,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 2. "PINV2,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 1. "PINV1,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 0. "PINV0,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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line.long 0x28 "PWM_POEN,PWM Output Enable Register"
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bitfld.long 0x28 5. "POEN5,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 4. "POEN4,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 3. "POEN3,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 2. "POEN2,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 1. "POEN1,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 0. "POEN0,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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wgroup.long 0xDC++0x3
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line.long 0x0 "PWM_SWBRK,PWM Software Brake Control Register"
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bitfld.long 0x0 10. "BRKLTRG4,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 9. "BRKLTRG2,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 8. "BRKLTRG0,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 2. "BRKETRG4,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 1. "BRKETRG2,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 0. "BRKETRG0,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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group.long 0xE0++0xF
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line.long 0x0 "PWM_INTEN0,PWM Interrupt Enable Register 0"
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bitfld.long 0x0 29. "CMPDIEN5,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 28. "CMPDIEN4,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 26. "CMPDIEN2,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 24. "CMPDIEN0,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 20. "CMPUIEN4,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 18. "CMPUIEN2,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 16. "CMPUIEN0,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 12. "PIEN4,PWM Period Point Interrupt Enable Bit 4\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 10. "PIEN2,PWM Period Point Interrupt Enable Bit 2\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 8. "PIEN0,PWM Period Point Interrupt Enable Bit 0\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 4. "ZIEN4,PWM Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 2. "ZIEN2,PWM Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 0. "ZIEN0,PWM Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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line.long 0x4 "PWM_INTEN1,PWM Interrupt Enable Register 1"
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bitfld.long 0x4 10. "BRKLIEN4_5,PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x4 9. "BRKLIEN2_3,PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x4 8. "BRKLIEN0_1,PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x4 2. "BRKEIEN4_5,PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled"
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bitfld.long 0x4 1. "BRKEIEN2_3,PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled"
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bitfld.long 0x4 0. "BRKEIEN0_1,PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled"
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line.long 0x8 "PWM_INTSTS0,PWM Interrupt Flag Register 0"
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bitfld.long 0x8 29. "CMPDIF5,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 28. "CMPDIF4,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 27. "CMPDIF3,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 26. "CMPDIF2,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 25. "CMPDIF1,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 24. "CMPDIF0,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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hexmask.long.byte 0x8 16.--21. 1. "CMPUIFn,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 .."
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bitfld.long 0x8 12. "PIF4,PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 10. "PIF2,PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 8. "PIF0,PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 4. "ZIF4,PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 2. "ZIF2,PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 0. "ZIF0,PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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line.long 0xC "PWM_INTSTS1,PWM Interrupt Flag Register 1"
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rbitfld.long 0xC 29. "BRKLSTS5,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 28. "BRKLSTS4,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 27. "BRKLSTS3,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 26. "BRKLSTS2,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 25. "BRKLSTS1,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 24. "BRKLSTS0,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 21. "BRKESTS5,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 20. "BRKESTS4,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 19. "BRKESTS3,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 18. "BRKESTS2,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 17. "BRKESTS1,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 16. "BRKESTS0,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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bitfld.long 0xC 13. "BRKLIF5,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 12. "BRKLIF4,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 11. "BRKLIF3,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 10. "BRKLIF2,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 9. "BRKLIF1,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 8. "BRKLIF0,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 5. "BRKEIF5,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 4. "BRKEIF4,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 3. "BRKEIF3,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 2. "BRKEIF2,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 1. "BRKEIF1,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 0. "BRKEIF0,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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group.long 0xF4++0xB
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line.long 0x0 "PWM_DACTRGEN,PWM Trigger DAC Enable Register"
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bitfld.long 0x0 29. "CDTRGEN5,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 28. "CDTRGEN4,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 27. "CDTRGEN3,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 26. "CDTRGEN2,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 25. "CDTRGEN1,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 24. "CDTRGEN0,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 21. "CUTRGEN5,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 20. "CUTRGEN4,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 19. "CUTRGEN3,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 18. "CUTRGEN2,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 17. "CUTRGEN1,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 16. "CUTRGEN0,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 12. "PTE4,PWM Period Point Trigger DAC Enable Bit 4\nPWM can trigger DAC to start action when PWM counter counts up to (PERIODn+1) if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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bitfld.long 0x0 10. "PTE2,PWM Period Point Trigger DAC Enable Bit 2\nPWM can trigger DAC to start action when PWM counter counts up to (PERIODn+1) if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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bitfld.long 0x0 8. "PTE0,PWM Period Point Trigger DAC Enable Bit 0\nPWM can trigger DAC to start action when PWM counter counts up to (PERIODn+1) if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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bitfld.long 0x0 4. "ZTE4,PWM Zero Point Trigger DAC Enable Bit 4\nPWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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bitfld.long 0x0 2. "ZTE2,PWM Zero Point Trigger DAC Enable Bit 2\nPWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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bitfld.long 0x0 0. "ZTE0,PWM Zero Point Trigger DAC Enable Bit 0\nPWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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line.long 0x4 "PWM_EADCTS0,PWM Trigger EADC Source Select Register 0"
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bitfld.long 0x4 31. "TRGEN3,PWM_CH3 Trigger EADC Enable Bit" "0: PWM_CH3 Trigger EADC function Disabled,1: PWM_CH3 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 24.--27. 1. "TRGSEL3,PWM_CH3 Trigger EADC Source Select"
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bitfld.long 0x4 23. "TRGEN2,PWM_CH2 Trigger EADC Enable Bit" "0: PWM_CH2 Trigger EADC function Disabled,1: PWM_CH2 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 16.--19. 1. "TRGSEL2,PWM_CH2 Trigger EADC Source Select"
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bitfld.long 0x4 15. "TRGEN1,PWM_CH1 Trigger EADC Enable Bit" "0: PWM_CH1 Trigger EADC function Disabled,1: PWM_CH1 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 8.--11. 1. "TRGSEL1,PWM_CH1 Trigger EADC Source Select"
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bitfld.long 0x4 7. "TRGEN0,PWM_CH0 Trigger EADC Enable Bit" "0: PWM_CH0 Trigger EADC function Disabled,1: PWM_CH0 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 0.--3. 1. "TRGSEL0,PWM_CH0 Trigger EADC Source Select"
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line.long 0x8 "PWM_EADCTS1,PWM Trigger EADC Source Select Register 1"
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bitfld.long 0x8 15. "TRGEN5,PWM_CH5 Trigger EADC Enable Bit" "0: PWM_CH5 Trigger EADC function Disabled,1: PWM_CH5 Trigger EADC function Enabled"
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hexmask.long.byte 0x8 8.--11. 1. "TRGSEL5,PWM_CH5 Trigger EADC Source Select"
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bitfld.long 0x8 7. "TRGEN4,PWM_CH4 Trigger EADC Enable Bit" "0: PWM_CH4 Trigger EADC function Disabled,1: PWM_CH4 Trigger EADC function Enabled"
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hexmask.long.byte 0x8 0.--3. 1. "TRGSEL4,PWM_CH4 Trigger EADC Source Select"
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group.long 0x110++0x3
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line.long 0x0 "PWM_SSCTL,PWM Synchronous Start Control Register"
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bitfld.long 0x0 8.--9. "SSRC,PWM Synchronous Start Source Select Bits" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,?,?"
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bitfld.long 0x0 4. "SSEN4,PWM Synchronous Start Function Enable Bit 4\nWhen synchronous start function is enabled the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x0 2. "SSEN2,PWM Synchronous Start Function Enable Bit 2\nWhen synchronous start function is enabled the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x0 0. "SSEN0,PWM Synchronous Start Function Enable Bit 0\nWhen synchronous start function is enabled the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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wgroup.long 0x114++0x3
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line.long 0x0 "PWM_SSTRG,PWM Synchronous Start Trigger Register"
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bitfld.long 0x0 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only)\nPWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time." "0,1"
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group.long 0x120++0x3
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line.long 0x0 "PWM_STATUS,PWM Status Register"
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bitfld.long 0x0 24. "DACTRGF,DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No DAC start of conversion trigger event has..,1: A DAC start of conversion trigger event has.."
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bitfld.long 0x0 23. "LPADCTRG,LPADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no LPADC start of conversion trigger..,1: An LPADC start of conversion trigger event has.."
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bitfld.long 0x0 21. "EADCTRG5,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 20. "EADCTRG4,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 19. "EADCTRG3,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 18. "EADCTRG2,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 17. "EADCTRG1,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 16. "EADCTRG0,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 4. "CNTMAX4,Time-base Counter 4 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x0 2. "CNTMAX2,Time-base Counter 2 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
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bitfld.long 0x0 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
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group.long 0x130++0x3
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line.long 0x0 "PWM_IFA0,PWM Interrupt Flag Accumulator Register 0"
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bitfld.long 0x0 31. "IFAEN,PWM_CHn Interrupt Flag Accumulator Enable Bits" "0: PWM_CHn interrupt flag accumulator Disabled,1: PWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM_CHn Interrupt Flag Accumulator Source Select" "0: PWM_CHn zero point,1: PWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM_CHn Accumulator Stop Mode Enable Bits" "0: PWM_CHn Stop Mode Disable,1: PWM_CHn Stop Mode Enable"
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hexmask.long.byte 0x0 0.--7. 1. "IFACNT,PWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of PWM_CHn period occurs to set bit IFAIFn to request the PWM period interrupt. PWM flag will be set in every IFACNT[15:0] times of PWM period."
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group.long 0x138++0x3
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line.long 0x0 "PWM_IFA2,PWM Interrupt Flag Accumulator Register 2"
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bitfld.long 0x0 31. "IFAEN,PWM_CHn Interrupt Flag Accumulator Enable Bits" "0: PWM_CHn interrupt flag accumulator Disabled,1: PWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM_CHn Interrupt Flag Accumulator Source Select" "0: PWM_CHn zero point,1: PWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM_CHn Accumulator Stop Mode Enable Bits" "0: PWM_CHn Stop Mode Disable,1: PWM_CHn Stop Mode Enable"
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hexmask.long.byte 0x0 0.--7. 1. "IFACNT,PWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of PWM_CHn period occurs to set bit IFAIFn to request the PWM period interrupt. PWM flag will be set in every IFACNT[15:0] times of PWM period."
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group.long 0x140++0x3
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line.long 0x0 "PWM_IFA4,PWM Interrupt Flag Accumulator Register 4"
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bitfld.long 0x0 31. "IFAEN,PWM_CHn Interrupt Flag Accumulator Enable Bits" "0: PWM_CHn interrupt flag accumulator Disabled,1: PWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM_CHn Interrupt Flag Accumulator Source Select" "0: PWM_CHn zero point,1: PWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM_CHn Accumulator Stop Mode Enable Bits" "0: PWM_CHn Stop Mode Disable,1: PWM_CHn Stop Mode Enable"
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hexmask.long.byte 0x0 0.--7. 1. "IFACNT,PWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of PWM_CHn period occurs to set bit IFAIFn to request the PWM period interrupt. PWM flag will be set in every IFACNT[15:0] times of PWM period."
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group.long 0x150++0xB
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line.long 0x0 "PWM_AINTSTS,PWM Accumulator Interrupt Flag Register"
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bitfld.long 0x0 4. "IFAIF4,PWM_CH4 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in PWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 2. "IFAIF2,PWM_CH2 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in PWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 0. "IFAIF0,PWM_CH0 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in PWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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line.long 0x4 "PWM_AINTEN,PWM Accumulator Interrupt Enable Register"
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bitfld.long 0x4 4. "IFAIEN4,PWM_CH4 Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 2. "IFAIEN2,PWM_CH2 Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 0. "IFAIEN0,PWM_CH0 Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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line.long 0x8 "PWM_APDMACTL,PWM Accumulator PDMA Control Register"
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bitfld.long 0x8 5. "APDMAEN5,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 4. "APDMAEN4,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 3. "APDMAEN3,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 2. "APDMAEN2,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 1. "APDMAEN1,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 0. "APDMAEN0,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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group.long 0x200++0x7
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line.long 0x0 "PWM_CAPINEN,PWM Capture Input Enable Register"
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bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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line.long 0x4 "PWM_CAPCTL,PWM Capture Control Register"
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bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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rgroup.long 0x208++0x33
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line.long 0x0 "PWM_CAPSTS,PWM Capture Status Register"
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bitfld.long 0x0 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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newline
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bitfld.long 0x0 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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newline
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bitfld.long 0x0 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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line.long 0x4 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x8 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0xC "PWM_RCAPDAT1,PWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x10 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0x14 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x18 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2"
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hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0x1C "PWM_RCAPDAT3,PWM Rising Capture Data Register 3"
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hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x20 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3"
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hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0x24 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4"
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hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x28 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4"
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hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0x2C "PWM_RCAPDAT5,PWM Rising Capture Data Register 5"
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hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x30 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5"
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hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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group.long 0x23C++0x3
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line.long 0x0 "PWM_PDMACTL,PWM PDMA Control Register"
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bitfld.long 0x0 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel4,1: Channel5"
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bitfld.long 0x0 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid." "0: PWM_FCAPDAT4/5 is the first captured data to..,1: PWM_RCAPDAT4/5 is the first captured data to.."
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newline
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bitfld.long 0x0 17.--18. "CAPMOD4_5,Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Reserved.,1: PWM_RCAPDAT4/5,?,?"
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bitfld.long 0x0 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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newline
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bitfld.long 0x0 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel2,1: Channel3"
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bitfld.long 0x0 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid." "0: PWM_FCAPDAT2/3 is the first captured data to..,1: PWM_RCAPDAT2/3 is the first captured data to.."
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newline
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bitfld.long 0x0 9.--10. "CAPMOD2_3,Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Reserved.,1: PWM_RCAPDAT2/3,?,?"
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bitfld.long 0x0 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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newline
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bitfld.long 0x0 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel0,1: Channel1"
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bitfld.long 0x0 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid." "0: PWM_FCAPDAT0/1 is the first captured data to..,1: PWM_RCAPDAT0/1 is the first captured data to.."
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newline
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bitfld.long 0x0 1.--2. "CAPMOD0_1,Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Reserved.,1: PWM_RCAPDAT0/1,?,?"
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bitfld.long 0x0 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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rgroup.long 0x240++0xB
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line.long 0x0 "PWM_PDMACAP0_1,PWM Capture Channel 01 PDMA Register"
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hexmask.long.word 0x0 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid."
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line.long 0x4 "PWM_PDMACAP2_3,PWM Capture Channel 23 PDMA Register"
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hexmask.long.word 0x4 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid."
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line.long 0x8 "PWM_PDMACAP4_5,PWM Capture Channel 45 PDMA Register"
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hexmask.long.word 0x8 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid."
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group.long 0x250++0x23
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line.long 0x0 "PWM_CAPIEN,PWM Capture Interrupt Enable Register"
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bitfld.long 0x0 13. "CAPFIEN5,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 12. "CAPFIEN4,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 11. "CAPFIEN3,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 10. "CAPFIEN2,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 9. "CAPFIEN1,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 8. "CAPFIEN0,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 5. "CAPRIEN5,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 4. "CAPRIEN4,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 3. "CAPRIEN3,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 2. "CAPRIEN2,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 1. "CAPRIEN1,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 0. "CAPRIEN0,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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line.long 0x4 "PWM_CAPIF,PWM Capture Interrupt Flag Register"
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bitfld.long 0x4 13. "CFLIF5,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 12. "CFLIF4,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 11. "CFLIF3,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 10. "CFLIF2,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 9. "CFLIF1,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 8. "CFLIF0,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 5. "CRLIF5,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 4. "CRLIF4,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 3. "CRLIF3,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 2. "CRLIF2,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 1. "CRLIF1,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 0. "CRLIF0,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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line.long 0x8 "PWM_CAPNF0,PWM Capture Input Noise Filter Register 0"
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bitfld.long 0x8 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x8 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0xC "PWM_CAPNF1,PWM Capture Input Noise Filter Register 1"
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bitfld.long 0xC 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0xC 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x10 "PWM_CAPNF2,PWM Capture Input Noise Filter Register 2"
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bitfld.long 0x10 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x10 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x14 "PWM_CAPNF3,PWM Capture Input Noise Filter Register 3"
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bitfld.long 0x14 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x14 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x18 "PWM_CAPNF4,PWM Capture Input Noise Filter Register 4"
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bitfld.long 0x18 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x18 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x1C "PWM_CAPNF5,PWM Capture Input Noise Filter Register 5"
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bitfld.long 0x1C 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x1C 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x20 "PWM_EXTETCTL0,PWM External Event Trigger Control Register 0"
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hexmask.long.byte 0x20 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x20 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x20 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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group.long 0x278++0x3
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line.long 0x0 "PWM_EXTETCTL2,PWM External Event Trigger Control Register 2"
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hexmask.long.byte 0x0 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x0 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x0 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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group.long 0x280++0x3
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line.long 0x0 "PWM_EXTETCTL4,PWM External Event Trigger Control Register 4"
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hexmask.long.byte 0x0 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x0 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
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bitfld.long 0x0 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
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group.long 0x288++0x7
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line.long 0x0 "PWM_SWEOFCTL,PWM Software Event Output Force Control Register"
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bitfld.long 0x0 10.--11. "OUTACTS5,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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bitfld.long 0x0 8.--9. "OUTACTS4,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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newline
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bitfld.long 0x0 6.--7. "OUTACTS3,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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bitfld.long 0x0 4.--5. "OUTACTS2,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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newline
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bitfld.long 0x0 2.--3. "OUTACTS1,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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bitfld.long 0x0 0.--1. "OUTACTS0,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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line.long 0x4 "PWM_SWEOFTRG,PWM Software Event Output Force Trigger Register"
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bitfld.long 0x4 5. "SWETRG5,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x4 4. "SWETRG4,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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newline
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bitfld.long 0x4 3. "SWETRG3,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x4 2. "SWETRG2,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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newline
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bitfld.long 0x4 1. "SWETRG1,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x4 0. "SWETRG0,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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rgroup.long 0x304++0x3
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line.long 0x0 "PWM_PBUF0,PWM PERIOD0 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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rgroup.long 0x30C++0x3
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line.long 0x0 "PWM_PBUF2,PWM PERIOD2 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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rgroup.long 0x314++0x3
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line.long 0x0 "PWM_PBUF4,PWM PERIOD4 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
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rgroup.long 0x31C++0x17
|
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line.long 0x0 "PWM_CMPBUF0,PWM CMPDAT0 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x4 "PWM_CMPBUF1,PWM CMPDAT1 Buffer"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x8 "PWM_CMPBUF2,PWM CMPDAT2 Buffer"
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hexmask.long.word 0x8 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0xC "PWM_CMPBUF3,PWM CMPDAT3 Buffer"
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hexmask.long.word 0xC 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x10 "PWM_CMPBUF4,PWM CMPDAT4 Buffer"
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hexmask.long.word 0x10 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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line.long 0x14 "PWM_CMPBUF5,PWM CMPDAT5 Buffer"
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hexmask.long.word 0x14 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
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rgroup.long 0x368++0x3
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line.long 0x0 "PWM_IFACNT0,PWM Interrupt Flag Accumulator Counter 0"
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hexmask.long.word 0x0 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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rgroup.long 0x370++0x3
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line.long 0x0 "PWM_IFACNT2,PWM Interrupt Flag Accumulator Counter 2"
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hexmask.long.word 0x0 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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rgroup.long 0x378++0x3
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line.long 0x0 "PWM_IFACNT4,PWM Interrupt Flag Accumulator Counter 4"
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hexmask.long.word 0x0 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
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tree.end
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tree "PWM1"
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base ad:0x4005D000
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group.long 0x0++0x7
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line.long 0x0 "PWM_CTL0,PWM Control Register 0"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disable,1: ICE debug mode counter halt Enable"
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bitfld.long 0x0 16. "IMMLDENn,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x0 0. "CTRLDn,Center Load Enable Bits\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
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line.long 0x4 "PWM_CTL1,PWM Control Register 1"
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bitfld.long 0x4 24.--26. "OUTMODEn,PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode,?,?,?,?,?,?"
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bitfld.long 0x4 8.--9. "CNTTYPE4,PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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newline
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bitfld.long 0x4 4.--5. "CNTTYPE2,PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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bitfld.long 0x4 0.--1. "CNTTYPE0,PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
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group.long 0x10++0x17
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line.long 0x0 "PWM_CLKSRC,PWM Clock Source Register"
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bitfld.long 0x0 16.--18. "ECLKSRC4,PWM_CH45 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "ECLKSRC2,PWM_CH23 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 0.--2. "ECLKSRC0,PWM_CH01 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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line.long 0x4 "PWM_CLKPSC0_1,PWM Clock Prescale Register 0/1"
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hexmask.long.word 0x4 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0x8 "PWM_CLKPSC2_3,PWM Clock Prescale Register 2/3"
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hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0xC "PWM_CLKPSC4_5,PWM Clock Prescale Register 4/5"
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hexmask.long.word 0xC 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0x10 "PWM_CNTEN,PWM Counter Enable Register"
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bitfld.long 0x10 4. "CNTEN4,PWM Counter Enable Bit 4" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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bitfld.long 0x10 2. "CNTEN2,PWM Counter Enable Bit 2" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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newline
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bitfld.long 0x10 0. "CNTEN0,PWM Counter Enable Bit 0" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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line.long 0x14 "PWM_CNTCLR,PWM Clear Counter Register"
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bitfld.long 0x14 4. "CNTCLR4,Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
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bitfld.long 0x14 2. "CNTCLR2,Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
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newline
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bitfld.long 0x14 0. "CNTCLR0,Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
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group.long 0x30++0x3
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line.long 0x0 "PWM_PERIOD0,PWM Period Register 0"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x38++0x3
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line.long 0x0 "PWM_PERIOD2,PWM Period Register 2"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x40++0x3
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line.long 0x0 "PWM_PERIOD4,PWM Period Register 4"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x50++0x17
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line.long 0x0 "PWM_CMPDAT0,PWM Comparator Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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line.long 0x4 "PWM_CMPDAT1,PWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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line.long 0x8 "PWM_CMPDAT2,PWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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line.long 0xC "PWM_CMPDAT3,PWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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line.long 0x10 "PWM_CMPDAT4,PWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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line.long 0x14 "PWM_CMPDAT5,PWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNT to generate PWM waveform interrupt and trigger EADC/LPADC/DAC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4.."
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group.long 0x70++0xB
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line.long 0x0 "PWM_DTCTL0_1,PWM Dead-time Control Register 0/1"
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bitfld.long 0x0 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x0 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of pin pair are complementary without any delay.\nNote: This.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x0 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x4 "PWM_DTCTL2_3,PWM Dead-time Control Register 2/3"
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bitfld.long 0x4 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x4 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of pin pair are complementary without any delay.\nNote: This.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x4 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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line.long 0x8 "PWM_DTCTL4_5,PWM Dead-time Control Register 4/5"
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bitfld.long 0x8 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x8 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs of pin pair are complementary without any delay.\nNote: This.." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x8 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
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rgroup.long 0x90++0x3
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line.long 0x0 "PWM_CNT0,PWM Counter Register 0"
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bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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rgroup.long 0x98++0x3
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line.long 0x0 "PWM_CNT2,PWM Counter Register 2"
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bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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rgroup.long 0xA0++0x3
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line.long 0x0 "PWM_CNT4,PWM Counter Register 4"
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bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter."
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group.long 0xB0++0x2B
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line.long 0x0 "PWM_WGCTL0,PWM Generation Register 0"
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bitfld.long 0x0 26.--27. "PRDPCTL5,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 24.--25. "PRDPCTL4,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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newline
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bitfld.long 0x0 22.--23. "PRDPCTL3,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 20.--21. "PRDPCTL2,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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newline
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bitfld.long 0x0 18.--19. "PRDPCTL1,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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bitfld.long 0x0 16.--17. "PRDPCTL0,PWM Period/Center Point Control\nNote 1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote 2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM can control output level when PWM counter..,2: This bit is center point control when PWM..,?"
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newline
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bitfld.long 0x0 10.--11. "ZPCTL5,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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bitfld.long 0x0 8.--9. "ZPCTL4,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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newline
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bitfld.long 0x0 6.--7. "ZPCTL3,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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bitfld.long 0x0 4.--5. "ZPCTL2,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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newline
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bitfld.long 0x0 2.--3. "ZPCTL1,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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bitfld.long 0x0 0.--1. "ZPCTL0,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
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line.long 0x4 "PWM_WGCTL1,PWM Generation Register 1"
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bitfld.long 0x4 26.--27. "CMPDCTL5,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 24.--25. "CMPDCTL4,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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newline
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bitfld.long 0x4 22.--23. "CMPDCTL3,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 20.--21. "CMPDCTL2,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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newline
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bitfld.long 0x4 18.--19. "CMPDCTL1,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 16.--17. "CMPDCTL0,PWM Compare Down Point Control\nNote 1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote 2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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newline
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bitfld.long 0x4 10.--11. "CMPUCTL5,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 8.--9. "CMPUCTL4,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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newline
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bitfld.long 0x4 6.--7. "CMPUCTL3,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 4.--5. "CMPUCTL2,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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newline
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bitfld.long 0x4 2.--3. "CMPUCTL1,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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bitfld.long 0x4 0.--1. "CMPUCTL0,PWM Compare Up Point Control\nNote 1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote 2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM can control output level when PWM counter..,2: In complementary mode,?"
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line.long 0x8 "PWM_MSKEN,PWM Mask Enable Register"
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bitfld.long 0x8 5. "MSKEN5,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 4. "MSKEN4,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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newline
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bitfld.long 0x8 3. "MSKEN3,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 2. "MSKEN2,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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newline
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bitfld.long 0x8 1. "MSKEN1,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 0. "MSKEN0,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
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line.long 0xC "PWM_MSK,PWM Mask Data Register"
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bitfld.long 0xC 5. "MSKDAT5,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 4. "MSKDAT4,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 3. "MSKDAT3,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 2. "MSKDAT2,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 1. "MSKDAT1,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0xC 0. "MSKDAT0,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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line.long 0x10 "PWM_BNF,PWM Brake Noise Filter Register"
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bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select\nFor PWM0 setting:" "0: Brake 1 pin source come from PWM0_BRAKE1.\nBrake..,1: Brake 1 pin source come from PWM1_BRAKE1.\nBrake.."
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bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select\nFor PWM0 setting:" "0: Brake 0 pin source come from PWM0_BRAKE0.\nBrake..,1: Brake 0 pin source come from PWM1_BRAKE0.\nBrake.."
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bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: The state of pin PWMx_BRAKE1 is passed to the..,1: The inversed state of pin PWMx_BRAKE1 is passed.."
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bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 9.--11. "BRK1FSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 8. "BRK1NFEN,PWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled"
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bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: The state of pin PWMx_BRAKE0 is passed to the..,1: The inversed state of pin PWMx_BRAKE10 is passed.."
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bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 1.--3. "BRK0FSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "BRK0NFEN,PWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled"
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line.long 0x14 "PWM_FAILBRK,PWM System Fail Brake Control Register"
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bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x14 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by CSS detection Disabled,1: Brake Function triggered by CSS detection Enabled"
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line.long 0x18 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0/1"
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bitfld.long 0x18 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x18 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x18 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x18 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x18 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect or edge-detect..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x18 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect or edge-detect..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x18 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x18 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x18 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x18 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x18 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x18 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x18 6. "VBSNEBEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x18 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x18 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x18 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x18 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x18 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x1C "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2/3"
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bitfld.long 0x1C 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x1C 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x1C 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x1C 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x1C 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect or edge-detect..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x1C 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect or edge-detect..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x1C 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x1C 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x1C 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x1C 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x1C 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x1C 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x1C 6. "VBSNEBEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x1C 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x1C 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x1C 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x20 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4/5"
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bitfld.long 0x20 31. "VBSRLBEN,UTCPD0 VBUS Source Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as level-detect brake..,1: UTCPD0 VBUS source disable as level-detect brake.."
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bitfld.long 0x20 28. "EADC0LBEN,Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as level-detect brake source Disabled,1: EADC0RM as level-detect brake source Enabled"
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bitfld.long 0x20 23. "VBSREBEN,UTCPD0 VBUS Source Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS source disable as edge-detect brake..,1: UTCPD0 VBUS source disable as edge-detect brake.."
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bitfld.long 0x20 20. "EADC0EBEN,Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: EADC0RM as edge-detect brake source Disabled,1: EADC0RM as edge-detect brake source Enabled"
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bitfld.long 0x20 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect or edge-detect..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x20 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect or edge-detect..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x20 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x20 14. "VBSNLBEN,UTCPD0 VBUS Sink Disable As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as level-detect brake..,1: UTCPD0 VBUS sink disable as level-detect brake.."
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bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x20 10. "CPO2LBEN,Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as level-detect brake source Disabled,1: ACMP2_O as level-detect brake source Enabled"
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bitfld.long 0x20 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x20 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x20 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x20 6. "VBSNEBEN,UTCPD0 VBUS Sink Disable As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer toSYS_REGLCTL register." "0: UTCPD0 VBUS sink disable as edge-detect brake..,1: UTCPD0 VBUS sink disable as edge-detect brake.."
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bitfld.long 0x20 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x20 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x20 2. "CPO2EBEN,Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP2_O as edge-detect brake source Disabled,1: ACMP2_O as edge-detect brake source Enabled"
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bitfld.long 0x20 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x20 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer toSYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x24 "PWM_POLCTL,PWM Pin Polar Inverse Register"
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bitfld.long 0x24 5. "PINV5,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 4. "PINV4,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 3. "PINV3,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 2. "PINV2,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 1. "PINV1,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x24 0. "PINV0,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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line.long 0x28 "PWM_POEN,PWM Output Enable Register"
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bitfld.long 0x28 5. "POEN5,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 4. "POEN4,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 3. "POEN3,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 2. "POEN2,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 1. "POEN1,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x28 0. "POEN0,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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wgroup.long 0xDC++0x3
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line.long 0x0 "PWM_SWBRK,PWM Software Brake Control Register"
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bitfld.long 0x0 10. "BRKLTRG4,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 9. "BRKLTRG2,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 8. "BRKLTRG0,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 2. "BRKETRG4,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 1. "BRKETRG2,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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bitfld.long 0x0 0. "BRKETRG0,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
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group.long 0xE0++0xF
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line.long 0x0 "PWM_INTEN0,PWM Interrupt Enable Register 0"
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bitfld.long 0x0 29. "CMPDIEN5,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 28. "CMPDIEN4,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 26. "CMPDIEN2,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 24. "CMPDIEN0,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 20. "CMPUIEN4,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 18. "CMPUIEN2,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 16. "CMPUIEN0,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 12. "PIEN4,PWM Period Point Interrupt Enable Bit 4\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 10. "PIEN2,PWM Period Point Interrupt Enable Bit 2\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 8. "PIEN0,PWM Period Point Interrupt Enable Bit 0\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 4. "ZIEN4,PWM Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 2. "ZIEN2,PWM Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x0 0. "ZIEN0,PWM Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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line.long 0x4 "PWM_INTEN1,PWM Interrupt Enable Register 1"
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bitfld.long 0x4 10. "BRKLIEN4_5,PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x4 9. "BRKLIEN2_3,PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x4 8. "BRKLIEN0_1,PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x4 2. "BRKEIEN4_5,PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled"
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bitfld.long 0x4 1. "BRKEIEN2_3,PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled"
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bitfld.long 0x4 0. "BRKEIEN0_1,PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled"
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line.long 0x8 "PWM_INTSTS0,PWM Interrupt Flag Register 0"
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bitfld.long 0x8 29. "CMPDIF5,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 28. "CMPDIF4,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 27. "CMPDIF3,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 26. "CMPDIF2,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 25. "CMPDIF1,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x8 24. "CMPDIF0,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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hexmask.long.byte 0x8 16.--21. 1. "CMPUIFn,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 .."
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bitfld.long 0x8 12. "PIF4,PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 10. "PIF2,PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 8. "PIF0,PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 4. "ZIF4,PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 2. "ZIF2,PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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bitfld.long 0x8 0. "ZIF0,PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
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line.long 0xC "PWM_INTSTS1,PWM Interrupt Flag Register 1"
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rbitfld.long 0xC 29. "BRKLSTS5,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 28. "BRKLSTS4,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 27. "BRKLSTS3,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 26. "BRKLSTS2,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 25. "BRKLSTS1,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 24. "BRKLSTS0,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
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rbitfld.long 0xC 21. "BRKESTS5,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 20. "BRKESTS4,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 19. "BRKESTS3,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 18. "BRKESTS2,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 17. "BRKESTS1,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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rbitfld.long 0xC 16. "BRKESTS0,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
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bitfld.long 0xC 13. "BRKLIF5,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 12. "BRKLIF4,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 11. "BRKLIF3,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 10. "BRKLIF2,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 9. "BRKLIF1,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 8. "BRKLIF0,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0xC 5. "BRKEIF5,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 4. "BRKEIF4,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 3. "BRKEIF3,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 2. "BRKEIF2,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 1. "BRKEIF1,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0xC 0. "BRKEIF0,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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group.long 0xF4++0xB
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line.long 0x0 "PWM_DACTRGEN,PWM Trigger DAC Enable Register"
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bitfld.long 0x0 29. "CDTRGEN5,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 28. "CDTRGEN4,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 27. "CDTRGEN3,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 26. "CDTRGEN2,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 25. "CDTRGEN1,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 24. "CDTRGEN0,PWM Compare Down Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter down count to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in up counter type.\nNote 2: In.." "0: PWM Compare Down count point trigger DAC..,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 21. "CUTRGEN5,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 20. "CUTRGEN4,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 19. "CUTRGEN3,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 18. "CUTRGEN2,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 17. "CUTRGEN1,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 16. "CUTRGEN0,PWM Compare Up Count Point Trigger DAC Enable Bits\nPWM can trigger DAC to start action when PWM counter counts up to CMP if this bit is set to1.\nNote 1: This bit should keep at 0 when PWM counter operating in down counter type.\nNote 2: In.." "0: PWM Compare Up point trigger DAC function Disabled,1: This bit should keep at 0 when PWM counter.."
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bitfld.long 0x0 12. "PTE4,PWM Period Point Trigger DAC Enable Bit 4\nPWM can trigger DAC to start action when PWM counter counts up to (PERIODn+1) if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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bitfld.long 0x0 10. "PTE2,PWM Period Point Trigger DAC Enable Bit 2\nPWM can trigger DAC to start action when PWM counter counts up to (PERIODn+1) if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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bitfld.long 0x0 8. "PTE0,PWM Period Point Trigger DAC Enable Bit 0\nPWM can trigger DAC to start action when PWM counter counts up to (PERIODn+1) if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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bitfld.long 0x0 4. "ZTE4,PWM Zero Point Trigger DAC Enable Bit 4\nPWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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bitfld.long 0x0 2. "ZTE2,PWM Zero Point Trigger DAC Enable Bit 2\nPWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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bitfld.long 0x0 0. "ZTE0,PWM Zero Point Trigger DAC Enable Bit 0\nPWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1." "0: PWM period point trigger DAC function Disabled,1: PWM period point trigger DAC function Enabled"
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line.long 0x4 "PWM_EADCTS0,PWM Trigger EADC Source Select Register 0"
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bitfld.long 0x4 31. "TRGEN3,PWM_CH3 Trigger EADC Enable Bit" "0: PWM_CH3 Trigger EADC function Disabled,1: PWM_CH3 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 24.--27. 1. "TRGSEL3,PWM_CH3 Trigger EADC Source Select"
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bitfld.long 0x4 23. "TRGEN2,PWM_CH2 Trigger EADC Enable Bit" "0: PWM_CH2 Trigger EADC function Disabled,1: PWM_CH2 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 16.--19. 1. "TRGSEL2,PWM_CH2 Trigger EADC Source Select"
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bitfld.long 0x4 15. "TRGEN1,PWM_CH1 Trigger EADC Enable Bit" "0: PWM_CH1 Trigger EADC function Disabled,1: PWM_CH1 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 8.--11. 1. "TRGSEL1,PWM_CH1 Trigger EADC Source Select"
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bitfld.long 0x4 7. "TRGEN0,PWM_CH0 Trigger EADC Enable Bit" "0: PWM_CH0 Trigger EADC function Disabled,1: PWM_CH0 Trigger EADC function Enabled"
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hexmask.long.byte 0x4 0.--3. 1. "TRGSEL0,PWM_CH0 Trigger EADC Source Select"
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line.long 0x8 "PWM_EADCTS1,PWM Trigger EADC Source Select Register 1"
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bitfld.long 0x8 15. "TRGEN5,PWM_CH5 Trigger EADC Enable Bit" "0: PWM_CH5 Trigger EADC function Disabled,1: PWM_CH5 Trigger EADC function Enabled"
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hexmask.long.byte 0x8 8.--11. 1. "TRGSEL5,PWM_CH5 Trigger EADC Source Select"
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bitfld.long 0x8 7. "TRGEN4,PWM_CH4 Trigger EADC Enable Bit" "0: PWM_CH4 Trigger EADC function Disabled,1: PWM_CH4 Trigger EADC function Enabled"
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hexmask.long.byte 0x8 0.--3. 1. "TRGSEL4,PWM_CH4 Trigger EADC Source Select"
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group.long 0x110++0x3
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line.long 0x0 "PWM_SSCTL,PWM Synchronous Start Control Register"
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bitfld.long 0x0 8.--9. "SSRC,PWM Synchronous Start Source Select Bits" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,?,?"
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bitfld.long 0x0 4. "SSEN4,PWM Synchronous Start Function Enable Bit 4\nWhen synchronous start function is enabled the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x0 2. "SSEN2,PWM Synchronous Start Function Enable Bit 2\nWhen synchronous start function is enabled the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x0 0. "SSEN0,PWM Synchronous Start Function Enable Bit 0\nWhen synchronous start function is enabled the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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wgroup.long 0x114++0x3
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line.long 0x0 "PWM_SSTRG,PWM Synchronous Start Trigger Register"
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bitfld.long 0x0 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only)\nPWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time." "0,1"
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group.long 0x120++0x3
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line.long 0x0 "PWM_STATUS,PWM Status Register"
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bitfld.long 0x0 24. "DACTRGF,DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1." "0: No DAC start of conversion trigger event has..,1: A DAC start of conversion trigger event has.."
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bitfld.long 0x0 23. "LPADCTRG,LPADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no LPADC start of conversion trigger..,1: An LPADC start of conversion trigger event has.."
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bitfld.long 0x0 21. "EADCTRG5,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 20. "EADCTRG4,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 19. "EADCTRG3,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 18. "EADCTRG2,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 17. "EADCTRG1,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 16. "EADCTRG0,EADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no EADC start of conversion trigger..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x0 4. "CNTMAX4,Time-base Counter 4 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
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bitfld.long 0x0 2. "CNTMAX2,Time-base Counter 2 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
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bitfld.long 0x0 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
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group.long 0x130++0x3
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line.long 0x0 "PWM_IFA0,PWM Interrupt Flag Accumulator Register 0"
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bitfld.long 0x0 31. "IFAEN,PWM_CHn Interrupt Flag Accumulator Enable Bits" "0: PWM_CHn interrupt flag accumulator Disabled,1: PWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM_CHn Interrupt Flag Accumulator Source Select" "0: PWM_CHn zero point,1: PWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM_CHn Accumulator Stop Mode Enable Bits" "0: PWM_CHn Stop Mode Disable,1: PWM_CHn Stop Mode Enable"
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hexmask.long.byte 0x0 0.--7. 1. "IFACNT,PWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of PWM_CHn period occurs to set bit IFAIFn to request the PWM period interrupt. PWM flag will be set in every IFACNT[15:0] times of PWM period."
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group.long 0x138++0x3
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line.long 0x0 "PWM_IFA2,PWM Interrupt Flag Accumulator Register 2"
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bitfld.long 0x0 31. "IFAEN,PWM_CHn Interrupt Flag Accumulator Enable Bits" "0: PWM_CHn interrupt flag accumulator Disabled,1: PWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM_CHn Interrupt Flag Accumulator Source Select" "0: PWM_CHn zero point,1: PWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM_CHn Accumulator Stop Mode Enable Bits" "0: PWM_CHn Stop Mode Disable,1: PWM_CHn Stop Mode Enable"
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hexmask.long.byte 0x0 0.--7. 1. "IFACNT,PWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of PWM_CHn period occurs to set bit IFAIFn to request the PWM period interrupt. PWM flag will be set in every IFACNT[15:0] times of PWM period."
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group.long 0x140++0x3
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line.long 0x0 "PWM_IFA4,PWM Interrupt Flag Accumulator Register 4"
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bitfld.long 0x0 31. "IFAEN,PWM_CHn Interrupt Flag Accumulator Enable Bits" "0: PWM_CHn interrupt flag accumulator Disabled,1: PWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM_CHn Interrupt Flag Accumulator Source Select" "0: PWM_CHn zero point,1: PWM_CHn period in channel n,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM_CHn Accumulator Stop Mode Enable Bits" "0: PWM_CHn Stop Mode Disable,1: PWM_CHn Stop Mode Enable"
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hexmask.long.byte 0x0 0.--7. 1. "IFACNT,PWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of PWM_CHn period occurs to set bit IFAIFn to request the PWM period interrupt. PWM flag will be set in every IFACNT[15:0] times of PWM period."
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group.long 0x150++0xB
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line.long 0x0 "PWM_AINTSTS,PWM Accumulator Interrupt Flag Register"
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bitfld.long 0x0 4. "IFAIF4,PWM_CH4 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in PWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 2. "IFAIF2,PWM_CH2 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in PWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x0 0. "IFAIF0,PWM_CH0 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in PWM_IFAn register software can clear this bit by writing 1 to it." "0,1"
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line.long 0x4 "PWM_AINTEN,PWM Accumulator Interrupt Enable Register"
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bitfld.long 0x4 4. "IFAIEN4,PWM_CH4 Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 2. "IFAIEN2,PWM_CH2 Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x4 0. "IFAIEN0,PWM_CH0 Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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line.long 0x8 "PWM_APDMACTL,PWM Accumulator PDMA Control Register"
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bitfld.long 0x8 5. "APDMAEN5,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 4. "APDMAEN4,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 3. "APDMAEN3,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 2. "APDMAEN2,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 1. "APDMAEN1,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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bitfld.long 0x8 0. "APDMAEN0,Channel n Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the channel.."
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group.long 0x200++0x7
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line.long 0x0 "PWM_CAPINEN,PWM Capture Input Enable Register"
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bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
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line.long 0x4 "PWM_CAPCTL,PWM Capture Control Register"
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bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
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rgroup.long 0x208++0x33
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line.long 0x0 "PWM_CAPSTS,PWM Capture Status Register"
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bitfld.long 0x0 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
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bitfld.long 0x0 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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bitfld.long 0x0 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
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line.long 0x4 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x8 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0xC "PWM_RCAPDAT1,PWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x10 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0x14 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x18 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2"
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|
hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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|
line.long 0x1C "PWM_RCAPDAT3,PWM Rising Capture Data Register 3"
|
|
hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
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|
line.long 0x20 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3"
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hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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|
line.long 0x24 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x28 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4"
|
|
hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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|
line.long 0x2C "PWM_RCAPDAT5,PWM Rising Capture Data Register 5"
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|
hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x30 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5"
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|
hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
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|
group.long 0x23C++0x3
|
|
line.long 0x0 "PWM_PDMACTL,PWM PDMA Control Register"
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|
bitfld.long 0x0 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel4,1: Channel5"
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bitfld.long 0x0 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid." "0: PWM_FCAPDAT4/5 is the first captured data to..,1: PWM_RCAPDAT4/5 is the first captured data to.."
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newline
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bitfld.long 0x0 17.--18. "CAPMOD4_5,Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Reserved.,1: PWM_RCAPDAT4/5,?,?"
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bitfld.long 0x0 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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newline
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bitfld.long 0x0 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel2,1: Channel3"
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bitfld.long 0x0 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid." "0: PWM_FCAPDAT2/3 is the first captured data to..,1: PWM_RCAPDAT2/3 is the first captured data to.."
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newline
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bitfld.long 0x0 9.--10. "CAPMOD2_3,Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Reserved.,1: PWM_RCAPDAT2/3,?,?"
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bitfld.long 0x0 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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newline
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bitfld.long 0x0 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel0,1: Channel1"
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bitfld.long 0x0 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid." "0: PWM_FCAPDAT0/1 is the first captured data to..,1: PWM_RCAPDAT0/1 is the first captured data to.."
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newline
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bitfld.long 0x0 1.--2. "CAPMOD0_1,Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid." "0: Reserved.,1: PWM_RCAPDAT0/1,?,?"
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bitfld.long 0x0 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid." "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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|
rgroup.long 0x240++0xB
|
|
line.long 0x0 "PWM_PDMACAP0_1,PWM Capture Channel 01 PDMA Register"
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|
hexmask.long.word 0x0 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid."
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line.long 0x4 "PWM_PDMACAP2_3,PWM Capture Channel 23 PDMA Register"
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hexmask.long.word 0x4 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid."
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line.long 0x8 "PWM_PDMACAP4_5,PWM Capture Channel 45 PDMA Register"
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hexmask.long.word 0x8 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid."
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|
group.long 0x250++0x23
|
|
line.long 0x0 "PWM_CAPIEN,PWM Capture Interrupt Enable Register"
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|
bitfld.long 0x0 13. "CAPFIEN5,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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|
bitfld.long 0x0 12. "CAPFIEN4,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 11. "CAPFIEN3,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 10. "CAPFIEN2,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 9. "CAPFIEN1,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x0 8. "CAPFIEN0,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 5. "CAPRIEN5,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 4. "CAPRIEN4,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 3. "CAPRIEN3,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x0 2. "CAPRIEN2,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x0 1. "CAPRIEN1,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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|
bitfld.long 0x0 0. "CAPRIEN0,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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line.long 0x4 "PWM_CAPIF,PWM Capture Interrupt Flag Register"
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bitfld.long 0x4 13. "CFLIF5,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 12. "CFLIF4,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 11. "CFLIF3,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 10. "CFLIF2,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 9. "CFLIF1,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 8. "CFLIF0,PWM Capture Falling Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 5. "CRLIF5,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 4. "CRLIF4,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 3. "CRLIF3,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 2. "CRLIF2,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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newline
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bitfld.long 0x4 1. "CRLIF1,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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bitfld.long 0x4 0. "CRLIF0,PWM Capture Rising Latch Interrupt Flag\nNote 1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote 2: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: When Capture with PDMA operating"
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line.long 0x8 "PWM_CAPNF0,PWM Capture Input Noise Filter Register 0"
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bitfld.long 0x8 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x8 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0xC "PWM_CAPNF1,PWM Capture Input Noise Filter Register 1"
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bitfld.long 0xC 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0xC 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x10 "PWM_CAPNF2,PWM Capture Input Noise Filter Register 2"
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bitfld.long 0x10 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x10 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x14 "PWM_CAPNF3,PWM Capture Input Noise Filter Register 3"
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bitfld.long 0x14 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x14 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x18 "PWM_CAPNF4,PWM Capture Input Noise Filter Register 4"
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bitfld.long 0x18 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
|
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bitfld.long 0x18 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x1C "PWM_CAPNF5,PWM Capture Input Noise Filter Register 5"
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bitfld.long 0x1C 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThe register bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Filter clock = PCLK,1: Filter clock = PCLK/2,?,?,?,?,?,?"
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newline
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bitfld.long 0x1C 0. "CAPNFEN,Capture Noise Filter Enable Bit" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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line.long 0x20 "PWM_EXTETCTL0,PWM External Event Trigger Control Register 0"
|
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hexmask.long.byte 0x20 8.--11. 1. "EXTTRGS,External Trigger Selection"
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bitfld.long 0x20 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
|
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bitfld.long 0x20 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
|
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group.long 0x278++0x3
|
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line.long 0x0 "PWM_EXTETCTL2,PWM External Event Trigger Control Register 2"
|
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hexmask.long.byte 0x0 8.--11. 1. "EXTTRGS,External Trigger Selection"
|
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bitfld.long 0x0 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
|
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bitfld.long 0x0 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
|
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group.long 0x280++0x3
|
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line.long 0x0 "PWM_EXTETCTL4,PWM External Event Trigger Control Register 4"
|
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hexmask.long.byte 0x0 8.--11. 1. "EXTTRGS,External Trigger Selection"
|
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bitfld.long 0x0 4.--5. "CNTACTS,Counter Action Selection" "0: Counter reset,1: Counter start,?,?"
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newline
|
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bitfld.long 0x0 0. "EXTETEN,External Event Trigger Enable Bit" "0: External Event Trigger function Disabled,1: External Event Trigger function Enabled"
|
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group.long 0x288++0x7
|
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line.long 0x0 "PWM_SWEOFCTL,PWM Software Event Output Force Control Register"
|
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bitfld.long 0x0 10.--11. "OUTACTS5,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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bitfld.long 0x0 8.--9. "OUTACTS4,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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newline
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bitfld.long 0x0 6.--7. "OUTACTS3,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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bitfld.long 0x0 4.--5. "OUTACTS2,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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newline
|
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bitfld.long 0x0 2.--3. "OUTACTS1,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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bitfld.long 0x0 0.--1. "OUTACTS0,Output Action Selection" "0: Do nothing,1: PWM output Low,?,?"
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line.long 0x4 "PWM_SWEOFTRG,PWM Software Event Output Force Trigger Register"
|
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bitfld.long 0x4 5. "SWETRG5,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x4 4. "SWETRG4,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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newline
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bitfld.long 0x4 3. "SWETRG3,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x4 2. "SWETRG2,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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newline
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bitfld.long 0x4 1. "SWETRG1,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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bitfld.long 0x4 0. "SWETRG0,Software Event Trigger\nWrite 1 to this bit will change PWM output status according to OUTACTSn in PWMx_SWEOFCTL setting.\nNote: This bit will auto cleared by hardware." "0,1"
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rgroup.long 0x304++0x3
|
|
line.long 0x0 "PWM_PBUF0,PWM PERIOD0 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
|
|
rgroup.long 0x30C++0x3
|
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line.long 0x0 "PWM_PBUF2,PWM PERIOD2 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
|
|
rgroup.long 0x314++0x3
|
|
line.long 0x0 "PWM_PBUF4,PWM PERIOD4 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
|
|
rgroup.long 0x31C++0x17
|
|
line.long 0x0 "PWM_CMPBUF0,PWM CMPDAT0 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x4 "PWM_CMPBUF1,PWM CMPDAT1 Buffer"
|
|
hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x8 "PWM_CMPBUF2,PWM CMPDAT2 Buffer"
|
|
hexmask.long.word 0x8 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0xC "PWM_CMPBUF3,PWM CMPDAT3 Buffer"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x10 "PWM_CMPBUF4,PWM CMPDAT4 Buffer"
|
|
hexmask.long.word 0x10 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x14 "PWM_CMPBUF5,PWM CMPDAT5 Buffer"
|
|
hexmask.long.word 0x14 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
rgroup.long 0x368++0x3
|
|
line.long 0x0 "PWM_IFACNT0,PWM Interrupt Flag Accumulator Counter 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
|
|
rgroup.long 0x370++0x3
|
|
line.long 0x0 "PWM_IFACNT2,PWM Interrupt Flag Accumulator Counter 2"
|
|
hexmask.long.word 0x0 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
|
|
rgroup.long 0x378++0x3
|
|
line.long 0x0 "PWM_IFACNT4,PWM Interrupt Flag Accumulator Counter 4"
|
|
hexmask.long.word 0x0 0.--15. 1. "ACUCNT,Accumulator Counter (Read Only)\nThis value indicates how many interrupt are accumulated when using interrupt flag accumulator function."
|
|
tree.end
|
|
tree.end
|
|
tree "QSPI (Quad Serial Peripheral Interface)"
|
|
base ad:0x40060000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "QSPIx_CTL,QSPI Control Register"
|
|
bitfld.long 0x0 23. "TXDTREN,Transmit Double Transfer Rate Mode Enable Bit \nNote: QSPI Master mode supports TXDTR mode and QSPI Slave mode does not support this mode." "0: TX DTR (Transmit Double Transfer Rate) mode..,1: TX DTR (Transmit Double Transfer Rate) mode.."
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bitfld.long 0x0 22. "QUADIOEN,Quad I/O Mode Enable Bit" "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
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bitfld.long 0x0 21. "DUALIOEN,Dual I/O Mode Enable Bit" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: QSPI data is input direction,1: QSPI data is output direction"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: QSPI unit transfer interrupt Disabled,1: QSPI unit transfer interrupt Enabled"
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bitfld.long 0x0 16. "TWOBIT,2-bit Transfer Mode Enable Bit\nNote: When 2-bit Transfer mode is enabled the first serial transmitted bit data is from the first FIFO buffer data and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as.." "0: 2-bit Transfer mode Disabled,1: 2-bit Transfer mode Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode QSPI Master will generate QSPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x0 14. "HALFDPX,QSPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for QSPI transfer. The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: QSPI operates in full-duplex transfer,1: QSPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the QSPIx TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 8 bits and can up to 32 bits."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: QSPI bus clock is idle low,1: QSPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge\nNote: In TX DTR mode TXNEG equals to CLKPOL (QSPIx_CTL[3])." "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,QSPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "QSPIx_CLKDIV,QSPI Clock Divider Register"
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hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the QSPI bus clock of QSPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
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line.long 0x8 "QSPIx_SSCTL,QSPI Slave Select Control Register"
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hexmask.long.word 0x8 16.--31. 1. "SLVTOCNT,Slave Mode Time-out Period\nIn Slave mode these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0 it indicates the.."
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 6. "SLVTORST,Slave Mode Time-out Reset Control" "0: When Slave mode time-out event occurs the TX and..,1: When Slave mode time-out event occurs the TX and.."
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bitfld.long 0x8 5. "SLVTOIEN,Slave Mode Time-out Interrupt Enable Bit" "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode the QSPI controller can work with 3-wire interface including QSPIx_CLK QSPIx_MISO and QSPIx_MOSI pins." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled.."
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (QSPIx_SS)." "0: The slave selection signal QSPIx_SS is active low,1: The slave selection signal QSPIx_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control\nIf AUTOSS bit is cleared to 0 \nNote: Master Only." "0: Set the QSPIx_SS line to inactive state.\nKeep..,1: Set the QSPIx_SS line to active state.\nQSPIx_SS.."
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line.long 0xC "QSPIx_PDMACTL,QSPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the QSPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In QSPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In QSPI Master mode with full duplex transfer"
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line.long 0x10 "QSPIx_FIFOCTL,QSPI FIFO Control Register"
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bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error\nNote: Slave mode Only." "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (QSPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: When TX underflow event occurs QSPIx_MISO pin state will be determined by this setting even.." "0: The QSPI data out is kept 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in QSPI Slave mode this bit can be used to make QSPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "QSPIx_STATUS,QSPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,QSPI Enable Status (Read Only)\nNote: The QSPI peripheral clock is asynchronous with the system clock. In order to make sure the QSPI control logic is disabled this bit indicates the real status of QSPI controller." "0: QSPI controller Disabled,1: QSPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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bitfld.long 0x14 5. "SLVTOIF,Slave Time-out Interrupt Flag \nWhen the slave select is active and the value of SLVTOCNT is not 0 if the bus clock is detected the slave time-out counter in QSPI controller logic will be started. When the value of time-out counter is greater.." "0: Slave time-out is not active,1: Slave time-out is active"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (QSPIx_SSCTL[2]) is set 0 and the SSLINE is 1 the QSPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: QSPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications this QSPI busy flag should be used with other status registers in QSPIx_STATUS such as TXCNT RXCNT TXTHIF TXFULL TXEMPTY RXTHIF RXFULL RXEMPTY and UNITIF. Therefore the QSPI transfer done.." "0: QSPI controller is in idle state,1: QSPI controller is in busy state"
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rgroup.long 0x18++0x3
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line.long 0x0 "QSPIx_STATUS2,QSPI Status2 Register"
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hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX data\nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happened in QSPI slave mode.\nThis status.."
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wgroup.long 0x20++0x3
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line.long 0x0 "QSPIx_TX,QSPI Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode.\nIn QSPI mode if DWIDTH is set to.."
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rgroup.long 0x30++0x3
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line.long 0x0 "QSPIx_RX,QSPI Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 8-level FIFO buffers in this controller. The data receive register holds the data received from QSPI data input pin. If the RXEMPTY (QSPIx_STATUS[8) is not set to 1 the receive FIFO buffers can be accessed.."
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tree.end
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tree "RMC (RRAM Memory Controller)"
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base ad:0x4000C000
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group.long 0x0++0x13
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line.long 0x0 "RMC_ISPCTL,ISP Control Register"
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bitfld.long 0x0 24. "INTEN,Secure ISP INT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. Before using INT user needs to clear the INTFLAG(RMC_ISPSTS[24]) make sure INT happen at correct time." "0: ISP INT Disabled,1: ISP INT Enabled"
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bitfld.long 0x0 8. "MPEN,Word Line Program Function Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Word line program function is disabled,1: Word line program function is enabled"
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN.." "0,1"
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bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LDROM cannot be updated,1: LDROM can be updated"
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bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CONFIG cannot be updated,1: CONFIG can be updated"
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bitfld.long 0x0 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in APROM"
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bitfld.long 0x0 1. "BS,Boot Select (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Boot from APROM,1: Boot from LDROM"
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bitfld.long 0x0 0. "ISPEN,ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ISP function Disabled,1: ISP function Enabled"
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line.long 0x4 "RMC_ISPADDR,ISP Address Register"
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hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address\nThe M2L31 series is equipped with embedded RRAM. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation.\nFor CRC32 Checksum Calculation command this field is the RRAM starting address for checksum calculation 4 Kbytes alignment is.."
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line.long 0x8 "RMC_ISPDAT,ISP Data Register"
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hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation."
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line.long 0xC "RMC_ISPCMD,ISP Command Register"
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hexmask.long.byte 0xC 0.--6. 1. "CMD,ISP Command\nISP command table is shown below:\nThe other commands are invalid."
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line.long 0x10 "RMC_ISPTRG,ISP Trigger Control Register"
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bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ISP operation is finished,1: ISP is progressed"
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rgroup.long 0x14++0x3
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line.long 0x0 "RMC_DFBA,Data RRAM Base Address"
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hexmask.long 0x0 0.--31. 1. "DFBA,Data RRAM Base Address (Read Only)\nThis register indicates Data RRAM start address.\nThe Data RRAM is shared with APROM. the content of this register is loaded from CONFIG1"
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group.long 0x18++0x3
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line.long 0x0 "RMC_FTCTL,RRAM Access Time Control Register"
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bitfld.long 0x0 9. "CACHEINV,RRAM Cache Invalidation (Write Protect)\nNote 1: Write 1 to start cache invalidation. The value will be changed to 0 once the process finishes.\nNote 2: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: RRAM Cache Invalidation finished (default),1: Write 1 to start cache invalidation"
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group.long 0x40++0x3
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line.long 0x0 "RMC_ISPSTS,ISP Status Register"
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bitfld.long 0x0 30. "FBS,Flash Bank Selection\nThis bit indicate which bank is selected to boot." "0: Booting from Bank0,1: Booting from Bank1"
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bitfld.long 0x0 25. "SCFF,Secure Conceal Fail Flag (Write Protect)\nNote 1: This bit is set by hardware if any ISP command accesses secure region when secure conceal function is active.\nNote 2: This bit needs to be cleared by writing 1 to it." "0: ISP did not access secure conceal region,1: This bit is set by hardware if any ISP command.."
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bitfld.long 0x0 24. "INTFLAG,ISP Interrupt Flag\nNote: This function needs to be enabled by RMC_ISPCTRL[24]." "0: ISP Not Finished,1: ISP done or ISPFF set"
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hexmask.long.word 0x0 9.--23. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the RRAM memory address {VECMAP[14:0] 9'h000} ~ {VECMAP[14:0] 9'h1FF}"
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bitfld.long 0x0 7. "ALLONE,RRAM All-one Verification Flag \nThis bit is set by hardware if all of RRAM bits are 1 and clear if RRAM bits are not all 1 after 'Run RRAM All-One Verification' complete; this bit also can be clear by writing 1" "0: All of RRAM bits are 1 after 'Run RRAM All-One..,1: RRAM bits are not all 1 after 'Run RRAM All-One.."
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (RMC_ISPCTL[6]) it needs to be cleared by writing 1 to RMC_ISPCTL[6] or RMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\nAPROM.." "0,1"
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rbitfld.long 0x0 2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened." "0: LDROM with IAP mode,1: APROM with IAP mode"
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rbitfld.long 0x0 0. "ISPBUSY,ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(RMC_ISPTRG[0])." "0: ISP operation is finished,1: ISP is progressed"
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group.long 0x4C++0x3
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line.long 0x0 "RMC_CYCCTL,RRAM Access Cycle Control Register"
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hexmask.long.byte 0x0 0.--3. 1. "CYCLE,RRAM Access Cycle Control (Write Protect)\nCHIP power level is PL1:\nNote: This bit is write protected. Refer to the SYS_REGLCTL register."
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rgroup.long 0xD0++0x13
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line.long 0x0 "RMC_XOMR0STS,XOM Region 0 Status Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "BASE,XOM Region 0 Base Address \nBASE is the base address of XOM Region 0 must be page-aligned.."
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hexmask.long.byte 0x0 0.--7. 1. "SIZE,XOM Region 0 Size \nSIZE is the page number of XOM Region 0 must be page-aligned.."
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line.long 0x4 "RMC_XOMR1STS,XOM Region 1 Status Register"
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hexmask.long.tbyte 0x4 8.--31. 1. "BASE,XOM Region 1 Base Address \nBASE is the base address of XOM Region 1 must be page-aligned.."
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hexmask.long.byte 0x4 0.--7. 1. "SIZE,XOM Region 1 Size\nSIZE is the page number of XOM Region 1 must be page-aligned.."
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line.long 0x8 "RMC_XOMR2STS,XOM Region 2 Status Register"
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hexmask.long.tbyte 0x8 8.--31. 1. "BASE,XOM Region 2 Base Address\nBASE is the base address of XOM Region 2 must be page-aligned.."
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hexmask.long.byte 0x8 0.--7. 1. "SIZE,XOM Region 2 Size \nSIZE is the page number of XOM Region 2 must be page-aligned.."
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line.long 0xC "RMC_XOMR3STS,XOM Region 3 Status Register"
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hexmask.long.tbyte 0xC 8.--31. 1. "BASE,XOM Region 3 Base Address \nBASE is the base address of XOM Region 3 must be page-aligned."
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hexmask.long.byte 0xC 0.--7. 1. "SIZE,XOM Region 3 Size \nSIZE is the page number of XOM Region 3 must be page-aligned."
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line.long 0x10 "RMC_XOMSTS,XOM Status Register"
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bitfld.long 0x10 4. "XOMPEF,XOM Page Erase Function Fail\nXOM page erase function status. If XOMPEF is set to 1 user needs to erase XOM region again." "0: Sucess,1: Fail"
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bitfld.long 0x10 3. "XOMR3ON,XOM Region 3 On\nXOM Region 3 active status." "0: No active,1: XOM region 3 is active"
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newline
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bitfld.long 0x10 2. "XOMR2ON,XOM Region 2 On\nXOM Region 2 active status." "0: No active,1: XOM region 2 is active"
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bitfld.long 0x10 1. "XOMR1ON,XOM Region 1 On\nXOM Region 1 active status." "0: No active,1: XOM region 1 is active"
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newline
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bitfld.long 0x10 0. "XOMR0ON,XOM Region 0 On\nXOM Region 0 active status." "0: No active,1: XOM region 0 is active"
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group.long 0x110++0xF
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line.long 0x0 "RMC_APWPROT0,APROM Write Protect Register0"
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bitfld.long 0x0 31. "APPROEN31,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 30. "APPROEN30,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 29. "APPROEN29,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 28. "APPROEN28,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 27. "APPROEN27,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 26. "APPROEN26,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 25. "APPROEN25,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 24. "APPROEN24,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 23. "APPROEN23,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 22. "APPROEN22,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 21. "APPROEN21,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 20. "APPROEN20,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 19. "APPROEN19,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 18. "APPROEN18,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 17. "APPROEN17,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 16. "APPROEN16,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 15. "APPROEN15,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 14. "APPROEN14,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 13. "APPROEN13,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 12. "APPROEN12,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 11. "APPROEN11,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 10. "APPROEN10,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 9. "APPROEN9,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 8. "APPROEN8,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 7. "APPROEN7,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 6. "APPROEN6,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 5. "APPROEN5,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 4. "APPROEN4,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 3. "APPROEN3,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 2. "APPROEN2,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x0 1. "APPROEN1,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x0 0. "APPROEN0,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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line.long 0x4 "RMC_APWPROT1,APROM Write Protect Register1"
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bitfld.long 0x4 31. "APPROEN63,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 30. "APPROEN62,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 29. "APPROEN61,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 28. "APPROEN60,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 27. "APPROEN59,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 26. "APPROEN58,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 25. "APPROEN57,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 24. "APPROEN56,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 23. "APPROEN55,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 22. "APPROEN54,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 21. "APPROEN53,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 20. "APPROEN52,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 19. "APPROEN51,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 18. "APPROEN50,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 17. "APPROEN49,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 16. "APPROEN48,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 15. "APPROEN47,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 14. "APPROEN46,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 13. "APPROEN45,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 12. "APPROEN44,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 11. "APPROEN43,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 10. "APPROEN42,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 9. "APPROEN41,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 8. "APPROEN40,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 7. "APPROEN39,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 6. "APPROEN38,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 5. "APPROEN37,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 4. "APPROEN36,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 3. "APPROEN35,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 2. "APPROEN34,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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newline
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bitfld.long 0x4 1. "APPROEN33,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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bitfld.long 0x4 0. "APPROEN32,APROM Protect enable\nThis bit indicates which APROM region is protected.\nNote: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000)" "0: APROM region n is not protected,1: APROM region n is protected"
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line.long 0x8 "RMC_APWPKEEP,APROM Write Protect Keep Register"
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hexmask.long.word 0x8 16.--31. 1. "APWPKEEP1,APROM Write Protect Keep 1"
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hexmask.long.word 0x8 0.--15. 1. "APWPKEEP0,APROM Write Protect Keep 0"
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line.long 0xC "RMC_SCACT,APROM Secure Conceal Active Register"
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bitfld.long 0xC 0. "SCACT,Secure Conceal Function Active\nNote: Secure conceal function active will base on this bit and setting of CONFIG6 is all 0.\nNote: After SCACT is set to 1 the secure conceal function is active and cannot be disabled by software. Thus reading.." "0: Secure conceal function inactive,1: Secure conceal function active"
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tree.end
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tree "RTC (Real-Time Clock)"
|
|
base ad:0x40041000
|
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group.long 0x0++0x3
|
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line.long 0x0 "RTC_INIT,RTC Initiation Register"
|
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hexmask.long 0x0 1.--31. 1. "INIT,RTC Initiation (Write Only)\nWhen RTC block is powered on RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state. Once the INIT is written as 0xa5eb1357 the RTC will be in un-reset state.."
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rbitfld.long 0x0 0. "ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state"
|
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group.long 0x8++0x1B
|
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line.long 0x0 "RTC_FREQADJ,RTC Frequency Compensation Register"
|
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rbitfld.long 0x0 31. "FCRBUSY,Frequency Compensation Register Write Operation Busy (Read Only)\nNote: This bit is only used when DCOMPEN (RTC_CLKFMT[16]) enabled." "0: The new register write operation is acceptable,1: The last write operation is in progress and new.."
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hexmask.long.byte 0x0 8.--12. 1. "INTEGER,Integer Part"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "FRACTION,Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number."
|
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line.long 0x4 "RTC_TIME,RTC Time Loading Register"
|
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hexmask.long.byte 0x4 24.--30. 1. "HZCNT,Index of sub-second counter (0x00~0x7F)"
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bitfld.long 0x4 20.--21. "TENHR,10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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newline
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hexmask.long.byte 0x4 16.--19. 1. "HR,1-Hour Time Digit (0~9)"
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bitfld.long 0x4 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x4 8.--11. 1. "MIN,1-Min Time Digit (0~9)"
|
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bitfld.long 0x4 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x4 0.--3. 1. "SEC,1-Sec Time Digit (0~9)"
|
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line.long 0x8 "RTC_CAL,RTC Calendar Loading Register"
|
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hexmask.long.byte 0x8 20.--23. 1. "TENYEAR,10-Year Calendar Digit (0~9)"
|
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hexmask.long.byte 0x8 16.--19. 1. "YEAR,1-Year Calendar Digit (0~9)"
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newline
|
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bitfld.long 0x8 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
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hexmask.long.byte 0x8 8.--11. 1. "MON,1-Month Calendar Digit (0~9)"
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newline
|
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bitfld.long 0x8 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
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hexmask.long.byte 0x8 0.--3. 1. "DAY,1-Day Calendar Digit (0~9)"
|
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line.long 0xC "RTC_CLKFMT,RTC Time Scale Selection Register"
|
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bitfld.long 0xC 16. "DCOMPEN,Dynamic Compensation Enable Bit" "0: Dynamic Compensation Disabled,1: Dynamic Compensation Enabled"
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bitfld.long 0xC 8. "HZCNTEN,Sub-second Counter Enable Bit" "0: HZCNT disabled in RTC_TIME and RTC_TALM,1: HZCNT enabled in RTC_TIME and RTC_TALM"
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bitfld.long 0xC 0. "_24HEN,24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected"
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line.long 0x10 "RTC_WEEKDAY,RTC Day of the Week Register"
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bitfld.long 0x10 0.--2. "WEEKDAY,Day of the Week Register" "0: Sunday,1: Monday,?,?,?,?,?,?"
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line.long 0x14 "RTC_TALM,RTC Time Alarm Register"
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hexmask.long.byte 0x14 24.--30. 1. "HZCNT,Index of sub-second counter (0x00~0x7F)"
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bitfld.long 0x14 20.--21. "TENHR,10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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hexmask.long.byte 0x14 16.--19. 1. "HR,1-Hour Time Digit of Alarm Setting (0~9)"
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bitfld.long 0x14 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x14 8.--11. 1. "MIN,1-Min Time Digit of Alarm Setting (0~9)"
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bitfld.long 0x14 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x14 0.--3. 1. "SEC,1-Sec Time Digit of Alarm Setting (0~9)"
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line.long 0x18 "RTC_CALM,RTC Calendar Alarm Register"
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hexmask.long.byte 0x18 20.--23. 1. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)"
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hexmask.long.byte 0x18 16.--19. 1. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)"
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bitfld.long 0x18 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
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hexmask.long.byte 0x18 8.--11. 1. "MON,1-Month Calendar Digit of Alarm Setting (0~9)"
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bitfld.long 0x18 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
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hexmask.long.byte 0x18 0.--3. 1. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)"
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rgroup.long 0x24++0x3
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line.long 0x0 "RTC_LEAPYEAR,RTC Leap Year Indicator Register"
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bitfld.long 0x0 0. "LEAPYEAR,Leap Year Indication (Read Only)" "0: This year is not a leap year,1: This year is leap year"
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group.long 0x28++0x2B
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line.long 0x0 "RTC_INTEN,RTC Interrupt Enable Register"
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bitfld.long 0x0 10. "TAMP2IEN,Tamper 2 Interrupt Enable Bit\nSet TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated." "0: Tamper 2 interrupt Disabled,1: Tamper 2 interrupt Enabled"
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bitfld.long 0x0 9. "TAMP1IEN,Tamper 1 Interrupt Enable Bit\nSet TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated." "0: Tamper 1 interrupt Disabled,1: Tamper 1 interrupt Enabled"
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bitfld.long 0x0 8. "TAMP0IEN,Tamper 0 Interrupt Enable Bit\nSet TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated." "0: Tamper 0 interrupt Disabled,1: Tamper 0 interrupt Enabled"
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bitfld.long 0x0 1. "TICKIEN,Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated." "0: RTC Time Tick interrupt Disabled,1: RTC Time Tick interrupt Enabled"
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bitfld.long 0x0 0. "ALMIEN,Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated." "0: RTC Alarm interrupt Disabled,1: RTC Alarm interrupt Enabled"
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line.long 0x4 "RTC_INTSTS,RTC Interrupt Status Register"
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bitfld.long 0x4 10. "TAMP2IF,Tamper 2 Interrupt Flag\nThis bit is set when TAMPER2 detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will generate again when Tamper setting condition is not restoration.\nNote.." "0: No Tamper 2 interrupt flag is generated,1: Write 1 to clear this bit"
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bitfld.long 0x4 9. "TAMP1IF,Tamper 1 Interrupt Flag\nThis bit is set when TAMPER1 detected level non-equal TAMP1LV (RTC_TAMPCTL[13]).\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will generate again when Tamper setting condition is not restoration.\nNote.." "0: No Tamper 1 interrupt flag is generated,1: Write 1 to clear this bit"
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bitfld.long 0x4 8. "TAMP0IF,Tamper 0 Interrupt Flag\nThis bit is set when TAMPER0 detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will generate again when Tamper setting condition is not restoration.\nNote.." "0: No Tamper 0 interrupt flag is generated,1: Write 1 to clear this bit"
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bitfld.long 0x4 1. "TICKIF,RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit." "0: Tick condition did not occur,1: Tick condition occurred"
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bitfld.long 0x4 0. "ALMIF,RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit." "0: Alarm condition is not matched,1: Alarm condition is matched"
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line.long 0x8 "RTC_TICK,RTC Time Tick Register"
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bitfld.long 0x8 0.--2. "TICK,Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request." "0: Time tick is 1 second,1: Time tick is 1/2 second,?,?,?,?,?,?"
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line.long 0xC "RTC_TAMSK,RTC Time Alarm Mask Register"
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bitfld.long 0xC 5. "MTENHR,Mask 10-Hour Time Digit of Alarm Setting (0~2)" "0,1"
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bitfld.long 0xC 4. "MHR,Mask 1-Hour Time Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0xC 3. "MTENMIN,Mask 10-Min Time Digit of Alarm Setting (0~5)" "0,1"
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bitfld.long 0xC 2. "MMIN,Mask 1-Min Time Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0xC 1. "MTENSEC,Mask 10-Sec Time Digit of Alarm Setting (0~5)" "0,1"
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bitfld.long 0xC 0. "MSEC,Mask 1-Sec Time Digit of Alarm Setting (0~9)" "0,1"
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line.long 0x10 "RTC_CAMSK,RTC Calendar Alarm Mask Register"
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bitfld.long 0x10 5. "MTENYEAR,Mask 10-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x10 4. "MYEAR,Mask 1-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x10 3. "MTENMON,Mask 10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
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bitfld.long 0x10 2. "MMON,Mask 1-Month Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x10 1. "MTENDAY,Mask 10-Day Calendar Digit of Alarm Setting (0~3)" "0,1"
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bitfld.long 0x10 0. "MDAY,Mask 1-Day Calendar Digit of Alarm Setting (0~9)" "0,1"
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line.long 0x14 "RTC_SPRCTL,RTC Spare Functional Control Register"
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bitfld.long 0x14 5. "SPRCSTS,SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~ RTC_SPR4 content is cleared when specify tamper event is detected.\nNote 1: Write 1 to clear this bit.\nNote 2: This bit keeps 1 when RTC_INTSTS[10:8] is not equal to 0." "0: Spare register content is not cleared,1: Write 1 to clear this bit"
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bitfld.long 0x14 2. "SPRRWEN,Spare Register Enable Bit\nNote: When spare register is disabled RTC_SPR0 ~ RTC_SPR4 cannot be accessed." "0: Spare register Disabled,1: Spare register Enabled"
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line.long 0x18 "RTC_SPR0,RTC Spare Register 0"
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hexmask.long 0x18 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions a tamper pin event is detected or after RRAM mass operation."
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line.long 0x1C "RTC_SPR1,RTC Spare Register 1"
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hexmask.long 0x1C 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions a tamper pin event is detected or after RRAM mass operation."
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line.long 0x20 "RTC_SPR2,RTC Spare Register 2"
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hexmask.long 0x20 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions a tamper pin event is detected or after RRAM mass operation."
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line.long 0x24 "RTC_SPR3,RTC Spare Register 3"
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hexmask.long 0x24 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions a tamper pin event is detected or after RRAM mass operation."
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line.long 0x28 "RTC_SPR4,RTC Spare Register 4"
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hexmask.long 0x28 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions a tamper pin event is detected or after RRAM mass operation."
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group.long 0x100++0xB
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line.long 0x0 "RTC_LXTCTL,RTC 32.768 kHz Oscillator Control Register"
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bitfld.long 0x0 8. "IOCTLSEL,I/O Pin Backup Control Selection\nWhen low speed 32 kHz oscillator is disabled or TAMPxEN is disabled PF.4 pin (X32_OUT pin) PF.5 pin (X32_IN pin) or PF.6~8 pin (TAMPERx pin) can be used as GPIO function. User can program IOCTLSEL to decide.." "0: PF.4~11 pin I/O function is controlled by GPIO..,1: PF.4~11 pin I/O function is controlled by VBAT.."
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bitfld.long 0x0 7. "RTCCKSEL,RTC Clock Source Selection" "0: Clock source from external low speed crystal..,1: Clock source from internal low speed RC.."
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hexmask.long.byte 0x0 1.--4. 1. "GAIN,Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption."
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line.long 0x4 "RTC_GPIOCTL0,RTC GPIO Control 0 Register"
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bitfld.long 0x4 28.--29. "PUSEL3,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.7 I/O pull-up or pull-down.\nNote: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.7 pull-up and pull-down Disabled,1: PF.7 pull-up Enabled,?,?"
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bitfld.long 0x4 27. "DINOFF3,I/O Pin Digital Input Path Disable Bit" "0: PF.7 digital input path Enabled,1: PF.7 digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DOUT3,I/O Output Data" "0: PF.7 output low,1: PF.7 output high"
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bitfld.long 0x4 24.--25. "OPMODE3,I/O Operation Mode" "0: PF.7 is input only mode,1: PF.7 is output push pull mode,?,?"
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bitfld.long 0x4 20.--21. "PUSEL2,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.6 I/O Pull-up or Pull-down.\nNote: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.6 pull-up and pull-down Disabled,1: PF.6 pull-up Enabled,?,?"
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bitfld.long 0x4 19. "DINOFF2,I/O Pin Digital Input Path Disable Bit" "0: PF.6 digital input path Enabled,1: PF.6 digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DOUT2,I/O Output Data" "0: PF.6 output low,1: PF.6 output high"
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bitfld.long 0x4 16.--17. "OPMODE2,I/O Operation Mode" "0: PF.6 is input only mode,1: PF.6 is output push pull mode,?,?"
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bitfld.long 0x4 12.--13. "PUSEL1,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.5 I/O pull-up or pull-down.\nNote: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.5 pull-up and pull-down Disabled,1: PF.5 pull-up Enabled,?,?"
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bitfld.long 0x4 11. "DINOFF1,I/O Pin Digital Input Path Disable Bit" "0: PF.5 digital input path Enabled,1: PF.5 digital input path Disabled (digital input.."
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bitfld.long 0x4 10. "DOUT1,I/O Output Data" "0: PF.5 output low,1: PF.5 output high"
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bitfld.long 0x4 8.--9. "OPMODE1,I/O Operation Mode" "0: PF.5 is input only mode,1: PF.5 is output push pull mode,?,?"
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bitfld.long 0x4 4.--5. "PUSEL0,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.4 I/O pull-up or pull-down.\nNote: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.4 pull-up and pull-down Disabled,1: PF.4 pull-up Enabled,?,?"
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bitfld.long 0x4 3. "DINOFF0,I/O Pin Digital Input Path Disable Bit" "0: PF.4 digital input path Enabled,1: PF.4 digital input path Disabled (digital input.."
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bitfld.long 0x4 2. "DOUT0,I/O Output Data" "0: PF.4 output low,1: PF.4 output high"
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bitfld.long 0x4 0.--1. "OPMODE0,I/O Operation Mode" "0: PF.4 is input only mode,1: PF.4 is output push pull mode,?,?"
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line.long 0x8 "RTC_GPIOCTL1,RTC GPIO Control 1 Register"
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bitfld.long 0x8 28.--29. "PUSEL7,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.11 I/O pull-up or pull-down.\nNote: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid.." "0: PF.11 pull-up and pull-down Disabled,1: PF.11 pull-up Enabled,?,?"
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bitfld.long 0x8 27. "DINOFF7,I/O Pin Digital Input Path Disable Bit" "0: PF.11 digital input path Enabled,1: PF.11 digital input path Disabled (digital input.."
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bitfld.long 0x8 26. "DOUT7,I/O Output Data" "0: PF.11 output low,1: PF.11 output high"
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bitfld.long 0x8 24.--25. "OPMODE7,I/O Operation Mode" "0: PF.11 is input only mode,1: PF.11 is output push pull mode,?,?"
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bitfld.long 0x8 20.--21. "PUSEL6,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.10 I/O pull-up or pull-down.\nNote: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid.." "0: PF.10 pull-up and pull-down Disabled,1: PF.10 pull-up Enabled,?,?"
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bitfld.long 0x8 19. "DINOFF6,I/O Pin Digital Input Path Disable Bit" "0: PF.10 digital input path Enabled,1: PF.10 digital input path Disabled (digital input.."
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bitfld.long 0x8 18. "DOUT6,I/O Output Data" "0: PF.10 output low,1: PF.10 output high"
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bitfld.long 0x8 16.--17. "OPMODE6,I/O Operation Mode" "0: PF.10 is input only mode,1: PF.10 is output push pull mode,?,?"
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bitfld.long 0x8 12.--13. "PUSEL5,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.9 I/O pull-up or pull-down.\nNote: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.9 pull-up and pull-down Disabled,1: PF.9 pull-up Enabled,?,?"
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bitfld.long 0x8 11. "DINOFF5,I/O Pin Digital Input Path Disable Bit" "0: PF.9 digital input path Enabled,1: PF.9 digital input path Disabled (digital input.."
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bitfld.long 0x8 10. "DOUT5,I/O Output Data" "0: PF.9 output low,1: PF.9 output high"
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bitfld.long 0x8 8.--9. "OPMODE5,I/O Operation Mode" "0: PF.9 is input only mode,1: PF.9 is output push pull mode,?,?"
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bitfld.long 0x8 4.--5. "PUSEL4,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.8 I/O pull-up or pull-down.\nNote: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when.." "0: PF.8 pull-up and pull-down Disabled,1: PF.8 pull-up Enabled,?,?"
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bitfld.long 0x8 3. "DINOFF4,I/O Pin Digital Input Path Disable Bit" "0: PF.8 digital input path Enabled,1: PF.8 digital input path Disabled (digital input.."
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bitfld.long 0x8 2. "DOUT4,I/O Output Data" "0: PF.8 output low,1: PF.8 output high"
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bitfld.long 0x8 0.--1. "OPMODE4,I/O Operation Mode" "0: PF.8 is input only mode,1: PF.8 is output push pull mode,?,?"
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group.long 0x110++0x3
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line.long 0x0 "RTC_DSTCTL,RTC Daylight Saving Time Control Register"
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bitfld.long 0x0 2. "DSBAK,Daylight Saving Back" "0: Daylight Saving Change is not performed,1: Daylight Saving Change is performed"
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bitfld.long 0x0 1. "SUBHR,Subtract 1 Hour" "0: No effect,1: Indicates RTC hour digit has been subtracted one.."
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bitfld.long 0x0 0. "ADDHR,Add 1 Hour" "0: No effect,1: Indicates RTC hour digit has been added one hour.."
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group.long 0x120++0x3
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line.long 0x0 "RTC_TAMPCTL,RTC Tamper Pin Control Register"
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bitfld.long 0x0 18. "TAMP2DEN,Tamper 2 De-bounce Enable Bit" "0: Tamper 2 de-bounce Disabled,1: Tamper 2 de-bounce Enabled tamper detection pin.."
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bitfld.long 0x0 17. "TAMP2LV,Tamper 2 Level\nThis bit depends on level attribute of tamper pin for static tamper detection." "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x0 16. "TAMP2EN,Tamper 2 Detect Enable Bit\nNote: The detection reference clock is RTC counter clock. Tamper detector need to sync 2 ~ 3 RTC counter clock." "0: Tamper 2 detect Disabled,1: Tamper 2 detect Enabled"
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bitfld.long 0x0 14. "TAMP1DEN,Tamper 1 De-bounce Enable Bit" "0: Tamper 1 de-bounce Disabled,1: Tamper 1 de-bounce Enabled tamper detection pin.."
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bitfld.long 0x0 13. "TAMP1LV,Tamper 1 Level\nThis bit depends on level attribute of tamper pin for static tamper detection." "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x0 12. "TAMP1EN,Tamper 1 Detect Enable Bit\nNote: The detection reference clock is RTC counter clock. Tamper detector needs to sync 2 ~ 3 RTC counter clock." "0: Tamper 1 detect Disabled,1: Tamper 1 detect Enabled"
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bitfld.long 0x0 10. "TAMP0DEN,Tamper 0 De-bounce Enable Bit" "0: Tamper 0 de-bounce Disabled,1: Tamper 0 de-bounce Enabled tamper detection pin.."
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bitfld.long 0x0 9. "TAMP0LV,Tamper 0 Level\nThis bit depends on level attribute of tamper pin for static tamper detection." "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x0 8. "TAMP0EN,Tamper0 Detect Enable Bit\nNote: The detection reference clock is RTC counter clock. Tamper detector needs to sync 2 ~ 3 RTC counter clock." "0: Tamper 0 detect Disabled,1: Tamper 0 detect Enabled"
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rgroup.long 0x130++0x7
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line.long 0x0 "RTC_TAMPTIME,RTC Tamper Time Register"
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hexmask.long.byte 0x0 24.--30. 1. "HZCNT,Index of sub-second counter (0x00~0x7F)"
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bitfld.long 0x0 20.--21. "TENHR,10-Hour Time Digit of TAMPER Time (0~2)Note: 24-hour time scale only ." "0,1,2,3"
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hexmask.long.byte 0x0 16.--19. 1. "HR,1-Hour Time Digit of TAMPER Time (0~9)"
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bitfld.long 0x0 12.--14. "TENMIN,10-Min Time Digit of TAMPER Time (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 8.--11. 1. "MIN,1-Min Time Digit of TAMPER Time (0~9)"
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bitfld.long 0x0 4.--6. "TENSEC,10-Sec Time Digit of TAMPER Time (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 0.--3. 1. "SEC,1-Sec Time Digit of TAMPER Time (0~9)"
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line.long 0x4 "RTC_TAMPCAL,RTC Tamper Calendar Register"
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hexmask.long.byte 0x4 20.--23. 1. "TENYEAR,10-Year Calendar Digit of TAMPER Calendar (0~9)"
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hexmask.long.byte 0x4 16.--19. 1. "YEAR,1-Year Calendar Digit of TAMPER Calendar (0~9)"
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bitfld.long 0x4 12. "TENMON,10-Month Calendar Digit of TAMPER Calendar (0~1)" "0,1"
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hexmask.long.byte 0x4 8.--11. 1. "MON,1-Month Calendar Digit of TAMPER Calendar (0~9)"
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bitfld.long 0x4 4.--5. "TENDAY,10-Day Calendar Digit of TAMPER Calendar (0~3)" "0,1,2,3"
|
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hexmask.long.byte 0x4 0.--3. 1. "DAY,1-Day Calendar Digit of TAMPER Calendar (0~9)"
|
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tree.end
|
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tree "SCS (System Controller Space)"
|
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base ad:0xE000E000
|
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group.long 0x10++0xB
|
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line.long 0x0 "SYST_CTL,SysTick Control and Status Register"
|
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bitfld.long 0x0 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register." "0,1"
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bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
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bitfld.long 0x0 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
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bitfld.long 0x0 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
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line.long 0x4 "SYST_LOAD,SysTick Reload Value Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0."
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line.long 0x8 "SYST_VAL,SysTick Current Value Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-Write Protect. The register is write-clear. A software write of any value will clear the.."
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group.long 0xD04++0x3
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line.long 0x0 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x0 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0." "0: No effect.\nNMI exception is not pending,1: Change NMI exception state to pending.\nNMI.."
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bitfld.long 0x0 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending." "0: No effect.\nPendSV exception is not pending,1: Change PendSV exception state to.."
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bitfld.long 0x0 27. "PENDSVRTC_CAL,PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDSV bit you must 'write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL' at the same time." "0: No effect,1: Remove the pending state from the PendSV exception"
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bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation:" "0: No effect.\nSysTick exception is not pending,1: Change SysTick exception state to.."
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bitfld.long 0x0 25. "PENDSTRTC_CAL,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDST bit you must 'write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL' at the same time." "0: No effect,1: Remove the pending state from the SysTick.."
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rbitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state." "0,1"
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rbitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending"
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hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Number of the Highest Pended Exception\nIndicate the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers but not any effect of the.."
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bitfld.long 0x0 11. "RETTOBASE,Preempted Active Exceptions Indicator\nIndicate whether There are Preempted Active Exceptions" "0: there are preempted active exceptions to execute,1: there are no active exceptions or the.."
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hexmask.long.byte 0x0 0.--6. 1. "VECTACTIVE,Number of the Current Active Exception"
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group.long 0xD0C++0x7
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line.long 0x0 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x0 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register this field should be 0x05FA otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of.."
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bitfld.long 0x0 15. "ENDIANNESS,Data Endianness" "0: Little-endian,1: Big-endian"
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bitfld.long 0x0 8.--10. "PRIGROUP,Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority " "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 2. "SYSRESETREQ,System Reset Request\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence." "0,1"
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bitfld.long 0x0 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's.." "0,1"
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bitfld.long 0x0 0. "VECTRESET,Reserved." "0,1"
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line.long 0x4 "SCR,System Control Register"
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bitfld.long 0x4 4. "SEVONPEND,Send Event on Pending\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE. If the processor is not waiting for an event the event is registered and affects the next WFE.\nThe processor also wakes.." "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
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bitfld.long 0x4 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode." "0: Sleep,1: Deep sleep"
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bitfld.long 0x4 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application." "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR.."
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group.long 0xD18++0xB
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line.long 0x0 "SHPR1,System Handler Priority Register 1"
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hexmask.long.byte 0x0 20.--23. 1. "PRI_6,Priority of system handler 6 UsageFault"
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hexmask.long.byte 0x0 12.--15. 1. "PRI_5,Priority of system handler 5 BusFault"
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hexmask.long.byte 0x0 4.--7. 1. "PRI_4,Priority of system handler 4 MemManage"
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line.long 0x4 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x4 28.--31. 1. "PRI_11,Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority."
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line.long 0x8 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x8 28.--31. 1. "PRI_15,Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority."
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hexmask.long.byte 0x8 20.--23. 1. "PRI_14,Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority."
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tree.end
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tree "SPI (Serial Peripheral Interface)"
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base ad:0x0
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tree "SPI0"
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base ad:0x40061000
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group.long 0x0++0x17
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line.long 0x0 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 4 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore .."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
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line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode the SPI controller can work with 3-wire interface including SPIx_CLK SPIx_MISO and SPIx_MOSI pins.\nNote: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled.."
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control\nIf AUTOSS bit is cleared to 0 " "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active state.\nSPIx_SS.."
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line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
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line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error" "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: This bit should be set as 0 in I2S mode.\nNote 3: When TX underflow event occurs SPIx_MISO.." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "SPIx_STATUS,SPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT RXCNT TXTHIF TXFULL TXEMPTY RXTHIF RXFULL RXEMPTY and UNITIF. Therefore the SPI transfer done events.." "0: SPI controller is in idle state,1: SPI controller is in busy state"
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rgroup.long 0x18++0x3
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line.long 0x0 "SPIx_STATUS2,SPI Status2 Register"
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hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX data \nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode.\nThis status register.."
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wgroup.long 0x20++0x3
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line.long 0x0 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.."
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rgroup.long 0x30++0x3
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line.long 0x0 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1 the receive FIFO.."
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group.long 0x60++0xB
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line.long 0x0 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x0 31. "SLVERRIEN,Bit Number Error Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit number error event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode\nI2S can operate as master or slave. For Master mode I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and.." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit\nNote 1: If enabling this bit I2Sx_BCLK will start to output in Master mode.\nNote 2: Before changing the configurations of SPIx_I2SCTL SPIx_I2SCLK and SPIx_FIFOCTL registers user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: If enabling this bit"
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line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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bitfld.long 0x4 25. "I2SSLAVE,I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode\nUser sets I2SSLAVE to set frequency of peripheral clock of I2S Master mode and I2S Slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.\nI2SSLAVE needs to set before I2SEN.." "0: The frequency of peripheral clock is set to I2S..,1: The frequency of peripheral clock is set to I2S.."
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bitfld.long 0x4 24. "I2SMODE,I2S Clock Divider Number Selection for I2S Mode and SPI Mode\nUser sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.\nUser needs to set I2SMODE before.." "0: The frequency of peripheral clock is set to SPI..,1: The frequency of peripheral clock is set to I2S.."
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hexmask.long.word 0x4 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock fBCLK is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source which is defined in.."
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hexmask.long.byte 0x4 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The frequency of master clock fMCLK is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock.."
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line.long 0x8 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x8 22. "SLVERRIF,Bit Number Error Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it." "0: No bit number error event occurred,1: Bit number error event occurred"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled this bit indicates the real status of SPI/I2S control logic for user." "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
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tree.end
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tree "SPI1"
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base ad:0x40062000
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group.long 0x0++0x17
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line.long 0x0 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 4 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore .."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
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line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode the SPI controller can work with 3-wire interface including SPIx_CLK SPIx_MISO and SPIx_MOSI pins.\nNote: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled.."
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control\nIf AUTOSS bit is cleared to 0 " "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active state.\nSPIx_SS.."
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line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
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line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error" "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: This bit should be set as 0 in I2S mode.\nNote 3: When TX underflow event occurs SPIx_MISO.." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "SPIx_STATUS,SPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT RXCNT TXTHIF TXFULL TXEMPTY RXTHIF RXFULL RXEMPTY and UNITIF. Therefore the SPI transfer done events.." "0: SPI controller is in idle state,1: SPI controller is in busy state"
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rgroup.long 0x18++0x3
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line.long 0x0 "SPIx_STATUS2,SPI Status2 Register"
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hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX data \nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode.\nThis status register.."
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wgroup.long 0x20++0x3
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line.long 0x0 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.."
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rgroup.long 0x30++0x3
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line.long 0x0 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1 the receive FIFO.."
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group.long 0x60++0xB
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line.long 0x0 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x0 31. "SLVERRIEN,Bit Number Error Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit number error event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode\nI2S can operate as master or slave. For Master mode I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and.." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit\nNote 1: If enabling this bit I2Sx_BCLK will start to output in Master mode.\nNote 2: Before changing the configurations of SPIx_I2SCTL SPIx_I2SCLK and SPIx_FIFOCTL registers user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: If enabling this bit"
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line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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bitfld.long 0x4 25. "I2SSLAVE,I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode\nUser sets I2SSLAVE to set frequency of peripheral clock of I2S Master mode and I2S Slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.\nI2SSLAVE needs to set before I2SEN.." "0: The frequency of peripheral clock is set to I2S..,1: The frequency of peripheral clock is set to I2S.."
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bitfld.long 0x4 24. "I2SMODE,I2S Clock Divider Number Selection for I2S Mode and SPI Mode\nUser sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.\nUser needs to set I2SMODE before.." "0: The frequency of peripheral clock is set to SPI..,1: The frequency of peripheral clock is set to I2S.."
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hexmask.long.word 0x4 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock fBCLK is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source which is defined in.."
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hexmask.long.byte 0x4 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The frequency of master clock fMCLK is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock.."
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line.long 0x8 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x8 22. "SLVERRIF,Bit Number Error Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it." "0: No bit number error event occurred,1: Bit number error event occurred"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled this bit indicates the real status of SPI/I2S control logic for user." "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
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tree.end
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tree "SPI2"
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base ad:0x40063000
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group.long 0x0++0x17
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line.long 0x0 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 4 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore .."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
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line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode the SPI controller can work with 3-wire interface including SPIx_CLK SPIx_MISO and SPIx_MOSI pins.\nNote: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled.."
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control\nIf AUTOSS bit is cleared to 0 " "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active state.\nSPIx_SS.."
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line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
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line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error" "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: This bit should be set as 0 in I2S mode.\nNote 3: When TX underflow event occurs SPIx_MISO.." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "SPIx_STATUS,SPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT RXCNT TXTHIF TXFULL TXEMPTY RXTHIF RXFULL RXEMPTY and UNITIF. Therefore the SPI transfer done events.." "0: SPI controller is in idle state,1: SPI controller is in busy state"
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rgroup.long 0x18++0x3
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line.long 0x0 "SPIx_STATUS2,SPI Status2 Register"
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hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX data \nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode.\nThis status register.."
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wgroup.long 0x20++0x3
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line.long 0x0 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.."
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rgroup.long 0x30++0x3
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line.long 0x0 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1 the receive FIFO.."
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group.long 0x60++0xB
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line.long 0x0 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x0 31. "SLVERRIEN,Bit Number Error Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit number error event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode\nI2S can operate as master or slave. For Master mode I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and.." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit\nNote 1: If enabling this bit I2Sx_BCLK will start to output in Master mode.\nNote 2: Before changing the configurations of SPIx_I2SCTL SPIx_I2SCLK and SPIx_FIFOCTL registers user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: If enabling this bit"
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line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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bitfld.long 0x4 25. "I2SSLAVE,I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode\nUser sets I2SSLAVE to set frequency of peripheral clock of I2S Master mode and I2S Slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.\nI2SSLAVE needs to set before I2SEN.." "0: The frequency of peripheral clock is set to I2S..,1: The frequency of peripheral clock is set to I2S.."
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bitfld.long 0x4 24. "I2SMODE,I2S Clock Divider Number Selection for I2S Mode and SPI Mode\nUser sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.\nUser needs to set I2SMODE before.." "0: The frequency of peripheral clock is set to SPI..,1: The frequency of peripheral clock is set to I2S.."
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hexmask.long.word 0x4 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock fBCLK is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source which is defined in.."
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hexmask.long.byte 0x4 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The frequency of master clock fMCLK is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock.."
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line.long 0x8 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x8 22. "SLVERRIF,Bit Number Error Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it." "0: No bit number error event occurred,1: Bit number error event occurred"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled this bit indicates the real status of SPI/I2S control logic for user." "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
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tree.end
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tree "SPI3"
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base ad:0x40064000
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group.long 0x0++0x17
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line.long 0x0 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x0 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit\nThis bit field is only available in Master mode. In receive-only mode SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 4 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore .."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.\nNote: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x4 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral.."
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line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode the SPI controller can work with 3-wire interface including SPIx_CLK SPIx_MISO and SPIx_MOSI pins.\nNote: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled.."
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control\nIf AUTOSS bit is cleared to 0 " "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active state.\nSPIx_SS.."
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line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote 1: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
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line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 4~16.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 10. "SLVBERX,RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error" "0: Uncompleted RX data will be dropped from RX FIFO..,1: Uncompleted RX data will be written into RX FIFO.."
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: This bit should be set as 0 in I2S mode.\nNote 3: When TX underflow event occurs SPIx_MISO.." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is no any.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "SPIx_STATUS,SPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)\nNote: By applications this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT RXCNT TXTHIF TXFULL TXEMPTY RXTHIF RXFULL RXEMPTY and UNITIF. Therefore the SPI transfer done events.." "0: SPI controller is in idle state,1: SPI controller is in busy state"
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rgroup.long 0x18++0x3
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line.long 0x0 "SPIx_STATUS2,SPI Status2 Register"
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hexmask.long.byte 0x0 24.--29. 1. "SLVBENUM,Effective Bit Number of Uncompleted RX data \nThis status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode.\nThis status register.."
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wgroup.long 0x20++0x3
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line.long 0x0 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.."
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rgroup.long 0x30++0x3
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line.long 0x0 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1 the receive FIFO.."
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group.long 0x60++0xB
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line.long 0x0 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x0 31. "SLVERRIEN,Bit Number Error Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit number error event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode\nI2S can operate as master or slave. For Master mode I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and.." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit\nNote 1: If enabling this bit I2Sx_BCLK will start to output in Master mode.\nNote 2: Before changing the configurations of SPIx_I2SCTL SPIx_I2SCLK and SPIx_FIFOCTL registers user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: If enabling this bit"
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line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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bitfld.long 0x4 25. "I2SSLAVE,I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode\nUser sets I2SSLAVE to set frequency of peripheral clock of I2S Master mode and I2S Slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.\nI2SSLAVE needs to set before I2SEN.." "0: The frequency of peripheral clock is set to I2S..,1: The frequency of peripheral clock is set to I2S.."
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bitfld.long 0x4 24. "I2SMODE,I2S Clock Divider Number Selection for I2S Mode and SPI Mode\nUser sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.\nUser needs to set I2SMODE before.." "0: The frequency of peripheral clock is set to SPI..,1: The frequency of peripheral clock is set to I2S.."
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hexmask.long.word 0x4 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock fBCLK is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source which is defined in.."
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hexmask.long.byte 0x4 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The frequency of master clock fMCLK is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock.."
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line.long 0x8 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x8 22. "SLVERRIF,Bit Number Error Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it." "0: No bit number error event occurred,1: Bit number error event occurred"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled this bit indicates the real status of SPI/I2S control logic for user." "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
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tree.end
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tree.end
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tree "SYS (System Control Registers)"
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base ad:0x40000000
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rgroup.long 0x0++0x3
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line.long 0x0 "SYS_PDID,Part Device Identification Number Register"
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hexmask.long 0x0 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used."
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group.long 0x4++0xF
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line.long 0x0 "SYS_RSTSTS,System Reset Status Register"
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bitfld.long 0x0 8. "CPULKRF,CPU Lockup Reset Flag\nNote 1: Write 1 to clear this bit to 0.\nNote 2: When CPU lockup happened under ICE is connected this flag will set to 1 but chip will not reset." "0: No reset from CPU lockup happened,1: Write 1 to clear this bit to 0"
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bitfld.long 0x0 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M23 core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0." "0: No reset from CPU,1: The Cortex-M23 core and FMC are reset by.."
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bitfld.long 0x0 6. "HRESETRF,HRESET Reset Flag\nThe HRESET reset flag is set by the 'Reset Signal' from the HRESET.\nNote: Write 1 to clear this bit to 0." "0: No reset from HRESET,1: Reset from HRESET"
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bitfld.long 0x0 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M23 core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from Cortex-M23,1: The Cortex-M23 had issued the reset signal to.."
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bitfld.long 0x0 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.."
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bitfld.long 0x0 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
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bitfld.long 0x0 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote 1: Write 1 to clear this bit to 0.\nNote 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit.." "0: No reset from watchdog timer or window watchdog..,1: Write 1 to clear this bit to 0"
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bitfld.long 0x0 1. "PINRF,NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.."
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bitfld.long 0x0 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued the.."
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line.long 0x4 "SYS_IPRST0,Peripheral Reset Control Register 0"
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bitfld.long 0x4 21. "CANFD1RST,CANFD1 Controller Reset\nSetting this bit to 1 will generate a reset signal to the CANFD1 controller. User needs to set this bit to 0 to release from the reset state." "0: CANFD1 controller normal operation,1: CANFD1 controller reset"
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bitfld.long 0x4 20. "CANFD0RST,CANFD0 Controller Reset\nSetting this bit to 1 will generate a reset signal to the CANFD0 controller. User needs to set this bit to 0 to release from the reset state." "0: CANFD0 controller normal operation,1: CANFD0 controller reset"
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bitfld.long 0x4 12. "CRPTRST,CRYPTO Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRYPTO controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: CRYPTO controller normal operation,1: CRYPTO controller reset"
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bitfld.long 0x4 7. "CRCRST,CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the.." "0: CRC calculation controller normal operation,1: CRC calculation controller reset"
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bitfld.long 0x4 4. "USBHRST,USBH Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the USBH. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: USBH controller normal operation,1: USBH controller reset"
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bitfld.long 0x4 3. "EBIRST,EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: EBI controller normal operation,1: EBI controller reset"
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bitfld.long 0x4 2. "PDMA0RST,PDMA0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA0. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PDMA0 controller normal operation,1: PDMA0 controller reset"
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bitfld.long 0x4 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to.." "0: Processor core normal operation,1: Processor core one-shot reset"
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bitfld.long 0x4 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the.." "0: Chip normal operation,1: Chip one-shot reset"
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line.long 0x8 "SYS_IPRST1,Peripheral Reset Control Register 1"
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bitfld.long 0x8 31. "TRNGRST,TRNG Controller Reset" "0: TRNG controller normal operation,1: TRNG controller reset"
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bitfld.long 0x8 28. "EADC0RST,EADC0 Controller Reset" "0: EADC0 controller normal operation,1: EADC0 controller reset"
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bitfld.long 0x8 27. "USBDRST,USBD Controller Reset" "0: USBD controller normal operation,1: USBD controller reset"
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bitfld.long 0x8 26. "OTGRST,OTG Controller Reset" "0: OTG controller normal operation,1: OTG controller reset"
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bitfld.long 0x8 23. "UART7RST,UART7 Controller Reset" "0: UART7 controller normal operation,1: UART7 controller reset"
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bitfld.long 0x8 22. "UART6RST,UART6 Controller Reset" "0: UART6 controller normal operation,1: UART6 controller reset"
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bitfld.long 0x8 21. "UART5RST,UART5 Controller Reset" "0: UART5 controller normal operation,1: UART5 controller reset"
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bitfld.long 0x8 20. "UART4RST,UART4 Controller Reset" "0: UART4 controller normal operation,1: UART4 controller reset"
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bitfld.long 0x8 19. "UART3RST,UART3 Controller Reset" "0: UART3 controller normal operation,1: UART3 controller reset"
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bitfld.long 0x8 18. "UART2RST,UART2 Controller Reset" "0: UART2 controller normal operation,1: UART2 controller reset"
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bitfld.long 0x8 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
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bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
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bitfld.long 0x8 15. "SPI2RST,SPI2 Controller Reset" "0: SPI2 controller normal operation,1: SPI2 controller reset"
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bitfld.long 0x8 14. "SPI1RST,SPI1 Controller Reset" "0: SPI1 controller normal operation,1: SPI1 controller reset"
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bitfld.long 0x8 13. "SPI0RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset"
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bitfld.long 0x8 12. "QSPI0RST,Qual SPI0 Controller Reset" "0: Qual SPI0 controller normal operation,1: Qual SPI0 controller reset"
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bitfld.long 0x8 11. "I2C3RST,I2C3 Controller Reset" "0: I2C3 controller normal operation,1: I2C3 controller reset"
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bitfld.long 0x8 10. "I2C2RST,I2C2 Controller Reset" "0: I2C2 controller normal operation,1: I2C2 controller reset.`"
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bitfld.long 0x8 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset"
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bitfld.long 0x8 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x8 7. "ACMP01RST,ACMP01 Controller Reset" "0: ACMP01 controller normal operation,1: ACMP01 controller reset"
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bitfld.long 0x8 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
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bitfld.long 0x8 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
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bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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bitfld.long 0x8 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
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line.long 0xC "SYS_IPRST2,Peripheral Reset Control Register 2"
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bitfld.long 0xC 27. "ECAP1RST,ECAP1 Controller Reset" "0: ECAP1 controller normal operation,1: ECAP1 controller reset"
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bitfld.long 0xC 26. "ECAP0RST,ECAP0 Controller Reset" "0: ECAP0 controller normal operation,1: ECAP0 controller reset"
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bitfld.long 0xC 25. "TKRST,TK Controller Reset" "0: TK controller normal operation,1: TK controller reset"
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bitfld.long 0xC 23. "EQEI1RST,EQEI1 Controller Reset" "0: EQEI1 controller normal operation,1: EQEI1 controller reset"
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bitfld.long 0xC 22. "EQEI0RST,EQEI0 Controller Reset" "0: EQEI0 controller normal operation,1: EQEI0 controller reset"
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bitfld.long 0xC 17. "EPWM1RST,EPWM1 Controller Reset" "0: EPWM1 controller normal operation,1: EPWM1 controller reset"
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bitfld.long 0xC 16. "EPWM0RST,EPWM0 Controller Reset" "0: EPWM0 controller normal operation,1: EPWM0 controller reset"
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bitfld.long 0xC 12. "DACRST,DAC Controller Reset" "0: DAC controller normal operation,1: DAC controller reset"
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bitfld.long 0xC 11. "WWDTRST,WWDT Controller Reset" "0: WWDT controller normal operation,1: WWDT controller reset"
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bitfld.long 0xC 9. "USCI1RST,USCI1 Controller Reset" "0: USCI1 controller normal operation,1: USCI1 controller reset"
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bitfld.long 0xC 8. "USCI0RST,USCI0 Controller Reset" "0: USCI0 controller normal operation,1: USCI0 controller reset"
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bitfld.long 0xC 6. "SPI3RST,SPI3 Controller Reset" "0: SPI3 controller normal operation,1: SPI3 controller reset"
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group.long 0x18++0xB
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line.long 0x0 "SYS_BODCTL,Brown-out Detector Control Register"
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hexmask.long.byte 0x0 16.--19. 1. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV ({1'b1 CONFIG0 [23:21]}).\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
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rbitfld.long 0x0 15. "LVRRDY,LVR Enable Ready Flag (Read Only)" "0: LVR disabled and not ready,1: LVR enabled and ready"
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bitfld.long 0x0 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\nNote 1: These bits are write protected. Refer to the SYS_REGLCTL register.\nNote 2: In NPD3/NPD4/NPD5/SPD0~2 mode LVR output is sampled by RC10K clock." "0: Without de-glitch function,1: These bits are write protected,2: In NPD3/NPD4/NPD5/SPD0~2 mode,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote 1: These bits are write protected. Refer to the SYS_REGLCTL register.\nNote 2: In NPD3/NPD4/NPD5/SPD0~2 mode BOD output is sampled by RC10K clock." "0: BOD output is sampled by RC10K clock,1: These bits are write protected,2: In NPD3/NPD4/NPD5/SPD0~2 mode,?,?,?,?,?"
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bitfld.long 0x0 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote 1: After enabling the bit the LVR function will be active with.." "0: Low Voltage Reset function Disabled,1: After enabling the bit"
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bitfld.long 0x0 6. "BODOUT,Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0 BOD function disabled this bit always responds 0000." "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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bitfld.long 0x0 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\nNote 1: The BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote 2: This bit is write protected. Refer to the.." "0: BOD operate in normal mode (default),1: The BOD consumes about 100uA in normal mode"
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bitfld.long 0x0 4. "BODIF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0." "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the AVDD is.."
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bitfld.long 0x0 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit.\nNote 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is.." "0: Brown-out 'INTERRUPT' function Enabled,1: While the Brown-out Detector function is enabled"
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bitfld.long 0x0 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
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line.long 0x4 "SYS_IVSCTL,Internal Voltage Source Control Register"
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bitfld.long 0x4 7. "ADCCSEL,ADC Controller Select Bit\nThis bit is used to select ADC controller." "0: EADC0 controlled is active,1: LPADC0 controller is active"
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bitfld.long 0x4 4. "VTEMPSEL,Temperature Sensor Slope Select Bit\nThis bit is used to select temperature sensor slope trend." "0: Temperature sensor negative temperature..,1: Temperature sensor positive temperature.."
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bitfld.long 0x4 2. "AVDDDIV4EN,AVDD divide 4 Enable Bit\nThis bit is used to enable/disable AVDD divide 4 function.\nNote: After this bit is set to 1 the value of AVDD divide 4 output voltage can be obtained from ADC conversion result" "0: AVDD divide 4 function Disabled (default),1: AVDD divide 4 function Enabled"
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bitfld.long 0x4 1. "VBATUGEN,VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1 the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result" "0: VBAT unity gain buffer function Disabled (default),1: VBAT unity gain buffer function Enabled"
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bitfld.long 0x4 0. "VTEMPEN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function." "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
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line.long 0x8 "SYS_IPRST3,Peripheral Reset Control Register 3"
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bitfld.long 0x8 15. "UTCPD0RST,UTCPD0 Controller Reset" "0: UTCPD0 controller normal operation,1: UTCPD0 controller reset"
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bitfld.long 0x8 9. "PWM1RST,PWM1 Controller Reset" "0: PWM1 controller normal operation,1: PWM1 controller reset"
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bitfld.long 0x8 8. "PWM0RST,PWM0 Controller Reset" "0: PWM0 controller normal operation,1: PWM0 controller reset"
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bitfld.long 0x8 7. "ACMP2RST,ACMP2 Controller Reset" "0: ACMP2 controller normal operation,1: ACMP2 controller reset"
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group.long 0x28++0xB
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line.long 0x0 "SYS_VREFCTL,VREF Control Register"
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bitfld.long 0x0 24. "VBGFEN,Chip Internal Voltage Band-gap Force Enable Bit (Write Only)" "0: Chip internal voltage band-gap controlled by..,1: Chip internal voltage band-gap force enable"
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bitfld.long 0x0 6.--7. "PRELOAD_SEL,Pre-load Timing Selection (Write Protect)" "0: pre-load time is 60us for 0.1uF Capacitor,1: pre-load time is 310us for 1uF Capacitor,?,?"
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hexmask.long.byte 0x0 0.--4. 1. "VREFCTL,VREF Control Bits (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register."
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line.long 0x4 "SYS_USBPHY,USB PHY Control Register"
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bitfld.long 0x4 8. "USBEN,USB PHY Enable Bit\nThis bit is used to enable/disable USB PHY." "0: USB PHY Disabled,1: USB PHY Enabled"
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bitfld.long 0x4 2. "SBO,Note: This bit must always be kept 1 If set to 0 the result is unpredictable" "0,1"
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bitfld.long 0x4 0.--1. "USBROLE,USB Role Option (Write Protect)\nThese two bits are used to select the role of USB.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Standard USB Device mode,1: Standard USB Host mode,?,?"
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line.long 0x8 "SYS_UTCPDCTL,UTCPD Control Register"
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bitfld.long 0x8 12. "UDVBDETS,UDC11 VBUS Detect Source Select\nNote: Before use UDC11 function UDVBDETS should be set and cannot change during UDC11 operating." "0: UDC11 VBUS detect source from OTGPHY,1: UDC11 VBUS detect source from VBDETSW0"
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bitfld.long 0x8 8.--10. "PD0VBDSS,UTCPD0 VBUS Detect Source Select\nUTCPD0 controller need a VBUS detect result to note if VBUS is connected. For SPD0~2/NPD3/NPD4/NPD5 usage ACMP can be another voltage detect method to detect VBUS pulg in or out. This bit field is used to.." "0: UTCPD0 VBUS detect source from UTCPD0 PHY,1: UTCPD0 VBUS detect source from ACMP0 output,?,?,?,?,?,?"
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bitfld.long 0x8 1. "POREN0,UTCPD0 Power-on Enable Bit\nNote: user should set POREN0 to 1 after IOMODE is setting down." "0: UTCPD0 PHY in reset mode,1: UTCPD0 PHY in normal mode"
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bitfld.long 0x8 0. "IOMODE,UTCPD0 as I/O mode\nThis bit is used to define UTCPD0 CCx and CCDBx function" "0: Pin as UTCPD0 CCx and CCDBx function,1: Pin as general I/O function"
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group.long 0x80++0x1F
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line.long 0x0 "SYS_GPA_MFOS,GPIOA Multiple Function Output Select Register"
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bitfld.long 0x0 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x0 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x0 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x0 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x0 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x0 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x0 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x0 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x0 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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line.long 0x4 "SYS_GPB_MFOS,GPIOB Multiple Function Output Select Register"
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bitfld.long 0x4 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x4 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x4 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x4 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x4 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x4 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x4 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x4 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x4 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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line.long 0x8 "SYS_GPC_MFOS,GPIOC Multiple Function Output Select Register"
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bitfld.long 0x8 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x8 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x8 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x8 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x8 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x8 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x8 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x8 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x8 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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line.long 0xC "SYS_GPD_MFOS,GPIOD Multiple Function Output Select Register"
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bitfld.long 0xC 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0xC 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0xC 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0xC 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0xC 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0xC 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0xC 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0xC 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0xC 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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line.long 0x10 "SYS_GPE_MFOS,GPIOE Multiple Function Output Select Register"
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bitfld.long 0x10 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x10 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x10 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x10 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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newline
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bitfld.long 0x10 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x10 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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line.long 0x14 "SYS_GPF_MFOS,GPIOF Multiple Function Output Select Register"
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bitfld.long 0x14 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x14 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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line.long 0x18 "SYS_GPG_MFOS,GPIOG Multiple Function Output Select Register"
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bitfld.long 0x18 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x18 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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line.long 0x1C "SYS_GPH_MFOS,GPIOH Multiple Function Output Select Register"
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bitfld.long 0x1C 15. "MFOS15,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 14. "MFOS14,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 13. "MFOS13,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 12. "MFOS12,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 11. "MFOS11,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 10. "MFOS10,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 9. "MFOS9,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 8. "MFOS8,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 7. "MFOS7,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 6. "MFOS6,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 5. "MFOS5,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 4. "MFOS4,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 3. "MFOS3,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 2. "MFOS2,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 1. "MFOS1,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x1C 0. "MFOS0,GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin\nNote: For more information about Px.n please refer to the 'PIN CONFIGURATION' chapter." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0xB0++0xB
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line.long 0x0 "SYS_MIRCTCTL,MIRC1M Trim Control Register"
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hexmask.long.byte 0x0 16.--20. 1. "BOUNDARY,Boundary Selection\nFill the boundary range from 0x1 to 0x31 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_MIRCTRIMCTL[9]) is enabled."
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bitfld.long 0x0 10. "REFCKSEL,Reference Clock Selection\nNote: MIRC trim reference clock is 20 kHz in test mode." "0: MIRC trim reference clock is from LXT (32.768 kHz),1: Reserved."
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bitfld.long 0x0 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled"
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bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked.\nOnce the MIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?"
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bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
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bitfld.long 0x0 2.--3. "ACCURSEL,Trim Accuracy Selection\nThis field indicates the target frequency accuracy of 1 MHz internal high speed RC oscillator (MIRC) auto trim." "0: Accuracy is +-0.25% deviation within all..,1: Accuracy is +-0.50% deviation within all..,?,?"
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bitfld.long 0x0 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 1 MHz internal high speed RC oscillator (MIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable MIRC auto trim function,1: Enable MIRC auto trim function and trim MIRC to..,?,?"
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line.long 0x4 "SYS_MIRCTIEN,MIRC1M Trim Interrupt Enable Register"
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bitfld.long 0x4 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_MIRCTISTS[2]) is set during auto trim operation an interrupt will.." "0: Disable CLKERRIF(SYS_MIRCTISTS[2]) status to..,1: Enable CLKERRIF(SYS_MIRCTISTS[2]) status to.."
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bitfld.long 0x4 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_MIRCTCTL[1:0]).\nIf this bit.." "0: Disable TFAILIF(SYS_MIRCTISTS[1]) status to..,1: Enable TFAILIF(SYS_MIRCTISTS[1]) status to.."
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line.long 0x8 "SYS_MIRCTISTS,MIRC1M Trim Interrupt Status Register"
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bitfld.long 0x8 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set if there occurs the over boundary condition this flag will be set.\nNote 1: Write 1 to clear this flag." "0: Over boundary coundition did not occur,1: Write 1 to clear this flag"
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bitfld.long 0x8 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 1 MHz internal high speed RC oscillator (MIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_MIRCTCTL[1:0]) will.." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.."
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bitfld.long 0x8 0. "FREQLOCK,MIRC Frequency Lock Status\nThis bit indicates the MIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically if the frequency is lock and the RC_TRIM is.." "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
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group.long 0xC0++0x7
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line.long 0x0 "SYS_SRAM_INTCTL,System SRAM Interrupt Enable Control Register"
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bitfld.long 0x0 0. "PERRIEN,SRAM Parity Check Error Interrupt Enable Bit" "0: SRAM parity check error interrupt Disabled,1: SRAM parity check error interrupt Enabled"
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line.long 0x4 "SYS_SRAM_STATUS,System SRAM Parity Error Status Register"
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bitfld.long 0x4 0. "PERRIF,SRAM Parity Check Error Flag\nThis bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0." "0: No System SRAM parity error,1: System SRAM parity error occur"
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rgroup.long 0xC8++0x3
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line.long 0x0 "SYS_SRAM_ERRADDR,System SRAM Parity Check Error Address Register"
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hexmask.long 0x0 0.--31. 1. "ERRADDR,System SRAM Parity Error Address\nThis register shows system SRAM parity error byte address."
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group.long 0xD0++0x3
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line.long 0x0 "SYS_SRAM_BISTCTL,System SRAM BIST Test Control Register"
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bitfld.long 0x0 11. "LPSRBIST,Low Power SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for LPSRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: system LPSRAM BIST Disabled,1: system LPSRAM BIST Enabled"
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bitfld.long 0x0 4. "USBBIST,USB BIST Enable Bit (Write Protect)\nThis bit enables BIST test for USB RAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: system USB BIST Disabled,1: system USB BIST Enabled"
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bitfld.long 0x0 3. "CANFDBIST,CANFDx BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CANFDx RAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: system CANFDx BIST Disabled,1: system CANFDx BIST Enabled"
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bitfld.long 0x0 2. "CRBIST,CACHE BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CACHE RAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: system CACHE BIST Disabled,1: system CACHE BIST Enabled"
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bitfld.long 0x0 1. "SRBIST1,SRAM Bank1 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM bank1.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: system SRAM bank1 BIST Disabled,1: system SRAM bank1 BIST Enabled"
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bitfld.long 0x0 0. "SRBIST0,SRAM Bank0 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM bank0.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: system SRAM bank0 BIST Disabled,1: system SRAM bank0 BIST Enabled"
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rgroup.long 0xD4++0x3
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line.long 0x0 "SYS_SRAM_BISTSTS,System SRAM BIST Test Status Register"
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bitfld.long 0x0 27. "LPSRBEND,Low Power SRAM BIST Test Finish" "0: LPSRAM BIST is active,1: LPSRAM BIST test finish"
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bitfld.long 0x0 20. "USBBEND,USB SRAM BIST Test Finish" "0: USB SRAM BIST is active,1: USB SRAM BIST test finish"
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newline
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bitfld.long 0x0 19. "CANBEND,CAN SRAM BIST Test Finish" "0: CAN SRAM BIST is active,1: CAN SRAM BIST test finish"
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bitfld.long 0x0 18. "CRBEND,CACHE SRAM BIST Test Finish" "0: System CACHE RAM BIST is active,1: System CACHE RAM BIST test finish"
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bitfld.long 0x0 17. "SRBEND1,2nd SRAM BIST Test Finish" "0: 2nd system SRAM BIST is active,1: 2nd system SRAM BIST finish"
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bitfld.long 0x0 16. "SRBEND0,1st SRAM BIST Test Finish" "0: 1st system SRAM BIST active,1: 1st system SRAM BIST finish"
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newline
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bitfld.long 0x0 11. "LPSRBEF,Low Power SRAM BIST Fail Flag" "0: LPSRAM BIST test pass,1: LPSRAM BIST test fail"
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bitfld.long 0x0 4. "USBBEF,USB SRAM BIST Fail Flag" "0: USB SRAM BIST test pass,1: USB SRAM BIST test fail"
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newline
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bitfld.long 0x0 3. "CANBEF,CAN SRAM BIST Fail Flag" "0: CAN SRAM BIST test pass,1: CAN SRAM BIST test fail"
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bitfld.long 0x0 2. "CRBISTEF,CACHE SRAM BIST Fail Flag" "0: System CACHE RAM BIST test pass,1: System CACHE RAM BIST test fail"
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newline
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bitfld.long 0x0 1. "SRBISTEF1,2nd System SRAM BIST Fail Flag" "0: 2nd system SRAM BIST test pass,1: 2nd system SRAM BIST test fail"
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bitfld.long 0x0 0. "SRBISTEF0,1st System SRAM BIST Fail Flag" "0: 1st system SRAM BIST test pass,1: 1st system SRAM BIST test fail"
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group.long 0xDC++0x3
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line.long 0x0 "SYS_SRAMPC0,SRAM Power Mode Control Register 0"
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rbitfld.long 0x0 31. "PCBUSY,Power Changing Busy Flag (Read Only)\nThis bit indicate SRAM power changing." "0: SRAM power change finish,1: SRAM power changing"
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bitfld.long 0x0 24.--26. "SRAM6PM,SRAM Group 6 Power Mode Select (Write Protect)\nThis field can control SRAM group 6 in bank2 (8k) power mode for range 0x2800_0000 - 0x2800_1FFF." "0: Normal mode,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 20.--22. "SRAM5PM,SRAM Group 5 Power Mode Select (Write Protect)\nThis field can control SRAM group 5 in bank1 (64k) power mode for range 0x2001_A000 - 0x2002_9FFF.\nNote 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal.." "0: Normal mode,?,?,3: Only support from normal mode to each Power-down..,4: Power saving priority first,?,?,?"
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bitfld.long 0x0 16.--18. "SRAM4PM,SRAM Group 4 Power Mode Select (Write Protect)\nThis field can control SRAM group 4 in bank1 (32k) power mode for range 0x2001_2000 - 0x2001_9FFF.\nNote 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal.." "0: Normal mode,?,?,3: Only support from normal mode to each Power-down..,4: Power saving priority first,?,?,?"
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bitfld.long 0x0 12.--14. "SRAM3PM,SRAM Group 3 Power Mode Select (Write Protect)\nThis field can control SRAM group 3 in bank1 (32k) power mode for range 0x2000_A000 - 0x2001_1FFF.\nNote 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal.." "0: Normal mode,?,?,3: Only support from normal mode to each Power-down..,4: Power saving priority first,?,?,?"
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bitfld.long 0x0 8.--10. "SRAM2PM,SRAM Group 2 Power Mode Select (Write Protect)\nThis field can control SRAM group2 in bank0 (16k) power mode for range 0x2000_6000 - 0x2000_9FFF.\nNote 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal.." "0: Normal mode,?,?,3: Only support from normal mode to each Power-down..,4: Power saving priority first,?,?,?"
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newline
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bitfld.long 0x0 4.--6. "SRAM1PM,SRAM Group 1 Power Mode Select (Write Protect)\nThis field can control SRAM group1 in bank0 (16k) power mode for range 0x2000_2000 - 0x2000_5FFF.\nNote 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal.." "0: Normal mode,?,?,3: Only support from normal mode to each Power-down..,4: Power saving priority first,?,?,?"
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bitfld.long 0x0 0.--2. "SRAM0PM,SRAM Group 0 Power Mode Select (Write Protect)\nThis field can control SRAM group0 in bank0 (8k) power mode for range 0x2000_0000 - 0x2000_1FFF.\nNote 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal.." "0: Normal mode,?,?,3: Only support from normal mode to each Power-down..,4: Power saving priority first,?,?,?"
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group.long 0xE4++0x1F
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line.long 0x0 "SYS_HIRCTCTL,HIRC48M Trim Control Register"
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hexmask.long.byte 0x0 16.--20. 1. "BOUNDARY,Boundary Selection\nFill the boundary range from 0x1 to 0x31 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enabled."
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bitfld.long 0x0 10. "REFCKSEL,Reference Clock Selection\nNote: HIRC trim reference clock is 20 kHz in test mode." "0: HIRC trim reference clock is from LXT (32.768 kHz),1: HIRC trim reference clock is from internal USB.."
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bitfld.long 0x0 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled"
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bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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newline
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bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?"
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bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
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bitfld.long 0x0 2.--3. "ACCURSEL,Trim Accuracy Selection\nThis field indicates the target frequency accuracy of 48 MHz internal high speed RC oscillator (HIRC) auto trim." "0: Accuracy is +-0.25% deviation within all..,1: Accuracy is +-0.50% deviation within all..,?,?"
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bitfld.long 0x0 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC to..,?,?"
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line.long 0x4 "SYS_HIRCTIEN,HIRC48M Trim Interrupt Enable Register"
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bitfld.long 0x4 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation an interrupt will be.." "0: Disable CLKERRIF(SYS_IRCTISTS[2]) status to..,1: Enable CLKERRIF(SYS_IRCTISTS[2]) status to.."
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bitfld.long 0x4 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).\nIf this bit.." "0: Disable TFAILIF(SYS_IRCTISTS[1]) status to..,1: Enable TFAILIF(SYS_IRCTISTS[1]) status to.."
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line.long 0x8 "SYS_HIRCTISTS,HIRC48M Trim Interrupt Status Register"
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bitfld.long 0x8 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set if there occurs the over boundary condition this flag will be set.\nNote: Write 1 to clear this flag." "0: Over boundary coundition did not occur,1: Over boundary coundition occurred"
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bitfld.long 0x8 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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newline
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bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will.." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.."
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bitfld.long 0x8 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically if the frequency is lock and the RC_TRIM is.." "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
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line.long 0xC "SYS_IRCTCTL,HIRC Trim Control Register"
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hexmask.long.byte 0xC 16.--20. 1. "BOUNDARY,Boundary Selection\nFill the boundary range from 0x1 to 0x31 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enabled."
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bitfld.long 0xC 10. "REFCKSEL,Reference Clock Selection\nNote: HIRC trim reference clock is 20 kHz in test mode." "0: HIRC trim reference clock is from LXT (32.768 kHz),1: HIRC trim reference clock is from internal USB.."
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newline
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bitfld.long 0xC 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled"
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bitfld.long 0xC 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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newline
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bitfld.long 0xC 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?"
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bitfld.long 0xC 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
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newline
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bitfld.long 0xC 2.--3. "ACCURSEL,Trim Accuracy Selection\nThis field indicates the target frequency accuracy of 12 MHz internal high speed RC oscillator (IRC) auto trim." "0: Accuracy is +-0.25% deviation within all..,1: Accuracy is +-0.50% deviation within all..,?,?"
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bitfld.long 0xC 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC to..,?,?"
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line.long 0x10 "SYS_IRCTIEN,HIRC Trim Interrupt Enable Register"
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bitfld.long 0x10 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation an interrupt will be.." "0: Disable CLKERRIF(SYS_IRCTISTS[2]) status to..,1: Enable CLKERRIF(SYS_IRCTISTS[2]) status to.."
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bitfld.long 0x10 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).\nIf this bit.." "0: Disable TFAILIF(SYS_IRCTISTS[1]) status to..,1: Enable TFAILIF(SYS_IRCTISTS[1]) status to.."
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line.long 0x14 "SYS_IRCTISTS,HIRC Trim Interrupt Status Register"
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bitfld.long 0x14 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set if there occurs the over boundary condition this flag will be set.\nNote: Write 1 to clear this flag." "0: Over boundary coundition did not occur,1: Over boundary coundition occurred"
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bitfld.long 0x14 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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newline
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bitfld.long 0x14 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will.." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.."
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bitfld.long 0x14 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically if the frequency is lock and the RC_TRIM is.." "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
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line.long 0x18 "SYS_RAMPGCTL,RRAM Power Gating Contol Register"
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rbitfld.long 0x18 6. "RRAMBUSY1,RRAM Bank1 Busy Flag(Read Only)" "0: RRAM bank1 in stand by mode,1: RRAM bank1 is busy"
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rbitfld.long 0x18 5. "RRAMPGDN1,RRAM Bank1 Power Gating Done Flag(Read Only)" "0: RRAM bank1 power switch is openoing,1: RRAM bank1 power gating done"
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newline
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bitfld.long 0x18 4. "RRAMPGEN1,RRAM Bank1 Power Gating Enable Bit" "0: RRAM bank1 power gating disabled,1: RRAM bank1 power gating enabled"
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rbitfld.long 0x18 2. "RRAMBUSY0,RRAM Bank0 Busy Flag (Read Only)" "0: RRAM bank0 in stand by mode,1: RRAM bank0 is busy"
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newline
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rbitfld.long 0x18 1. "RRAMPGDN0,RRAM Bank0 Power Gating Done Flag(Read Only)" "0: RRAM bank0 power switch is openoing,1: RRAM bank0 power gating done"
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bitfld.long 0x18 0. "RRAMPGEN0,RRAM Bank0 Power Gating Enable Bit" "0: RRAM bank0 power gating disabled,1: RRAM bank0 power gating enabled"
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line.long 0x1C "SYS_REGLCTL,Register Lock Control Register"
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hexmask.long.byte 0x1C 0.--7. 1. "REGLCTL,Register Lock Control Code\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is completed the.."
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group.long 0x1EC++0x3
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line.long 0x0 "SYS_PORDISAN,Analog POR Disable Control Register"
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hexmask.long.word 0x0 0.--15. 1. "POROFFAN,Power-on Reset Enable Bit (Write Protect)\nAfter powered on User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.\nThe analog POR circuit will be active again when this field is set to another value or.."
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rgroup.long 0x1F4++0x3
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line.long 0x0 "SYS_CSERVER,Chip Series Version Register"
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hexmask.long.byte 0x0 0.--7. 1. "VERSION,Chip Series Version\nThese bits indicate the series version of chip."
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group.long 0x1F8++0x3
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line.long 0x0 "SYS_PLCTL,Power Level Control Register"
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bitfld.long 0x0 3. "PLKEEP,Power Level keep for wakeup(Write Protect)" "0: Power level back to default PL1 when SPD0~2 wakeup,1: Power level back to normal run voltage when.."
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bitfld.long 0x0 0.--2. "PLSEL,Power Level Select (Write Protect)\nThese bits indicate the status of power level.\nNote : Write ignore when wtire reserved setting.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "?,1: Power level is PL1,?,?,?,?,?,?"
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rgroup.long 0x1FC++0x3
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line.long 0x0 "SYS_PLSTS,Power Level Status Register"
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bitfld.long 0x0 8.--10. "PLSTATUS,Power Level Status (Read Only)\nThis bit indicates the status of power level." "?,1: Power level is PL1,?,?,?,?,?,?"
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bitfld.long 0x0 0. "PLCBUSY,Power Level Change Busy Bit (Read Only)\nThis bit is set by hardware when power level is changing. After power level change is completed this bit will be cleared automatically by hardware." "0: Core voltage change is completed,1: Core voltage change is ongoing"
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group.long 0x310++0x3
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line.long 0x0 "SYS_INIVTOR,Initial VTOR Control Register"
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hexmask.long.tbyte 0x0 10.--31. 1. "INIVTOR,Initial VTOR Control Register\nThis is the register to set the address of vector table after CPU reseted or chip waked up from SPD0~2 mode.\nThe value will be loaded to Vector Table Offset Register which is at the address 0xE000ED08 when CPU.."
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group.long 0x500++0x5B
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line.long 0x0 "SYS_GPA_MFP0,GPIOA Multiple Function Control Register 0"
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hexmask.long.byte 0x0 24.--28. 1. "PA3MFP,PA.3 Multi-function Pin Selection"
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hexmask.long.byte 0x0 16.--20. 1. "PA2MFP,PA.2 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x0 8.--12. 1. "PA1MFP,PA.1 Multi-function Pin Selection"
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hexmask.long.byte 0x0 0.--4. 1. "PA0MFP,PA.0 Multi-function Pin Selection"
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line.long 0x4 "SYS_GPA_MFP1,GPIOA Multiple Function Control Register 1"
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hexmask.long.byte 0x4 24.--28. 1. "PA7MFP,PA.7 Multi-function Pin Selection"
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hexmask.long.byte 0x4 16.--20. 1. "PA6MFP,PA.6 Multi-function Pin Selection"
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hexmask.long.byte 0x4 8.--12. 1. "PA5MFP,PA.5 Multi-function Pin Selection"
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hexmask.long.byte 0x4 0.--4. 1. "PA4MFP,PA.4 Multi-function Pin Selection"
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line.long 0x8 "SYS_GPA_MFP2,GPIOA Multiple Function Control Register 2"
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hexmask.long.byte 0x8 24.--28. 1. "PA11MFP,PA.11 Multi-function Pin Selection"
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hexmask.long.byte 0x8 16.--20. 1. "PA10MFP,PA.10 Multi-function Pin Selection"
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hexmask.long.byte 0x8 8.--12. 1. "PA9MFP,PA.9 Multi-function Pin Selection"
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hexmask.long.byte 0x8 0.--4. 1. "PA8MFP,PA.8 Multi-function Pin Selection"
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line.long 0xC "SYS_GPA_MFP3,GPIOA Multiple Function Control Register 3"
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hexmask.long.byte 0xC 24.--28. 1. "PA15MFP,PA.15 Multi-function Pin Selection"
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hexmask.long.byte 0xC 16.--20. 1. "PA14MFP,PA.14 Multi-function Pin Selection"
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hexmask.long.byte 0xC 8.--12. 1. "PA13MFP,PA.13 Multi-function Pin Selection"
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hexmask.long.byte 0xC 0.--4. 1. "PA12MFP,PA.12 Multi-function Pin Selection"
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line.long 0x10 "SYS_GPB_MFP0,GPIOB Multiple Function Control Register 0"
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hexmask.long.byte 0x10 24.--28. 1. "PB3MFP,PB.3 Multi-function Pin Selection"
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hexmask.long.byte 0x10 16.--20. 1. "PB2MFP,PB.2 Multi-function Pin Selection"
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hexmask.long.byte 0x10 8.--12. 1. "PB1MFP,PB.1 Multi-function Pin Selection"
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hexmask.long.byte 0x10 0.--4. 1. "PB0MFP,PB.0 Multi-function Pin Selection"
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line.long 0x14 "SYS_GPB_MFP1,GPIOB Multiple Function Control Register 1"
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hexmask.long.byte 0x14 24.--28. 1. "PB7MFP,PB.7 Multi-function Pin Selection"
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hexmask.long.byte 0x14 16.--20. 1. "PB6MFP,PB.6 Multi-function Pin Selection"
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hexmask.long.byte 0x14 8.--12. 1. "PB5MFP,PB.5 Multi-function Pin Selection"
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hexmask.long.byte 0x14 0.--4. 1. "PB4MFP,PB.4 Multi-function Pin Selection"
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line.long 0x18 "SYS_GPB_MFP2,GPIOB Multiple Function Control Register 2"
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hexmask.long.byte 0x18 24.--28. 1. "PB11MFP,PB.11 Multi-function Pin Selection"
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hexmask.long.byte 0x18 16.--20. 1. "PB10MFP,PB.10 Multi-function Pin Selection"
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hexmask.long.byte 0x18 8.--12. 1. "PB9MFP,PB.9 Multi-function Pin Selection"
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hexmask.long.byte 0x18 0.--4. 1. "PB8MFP,PB.8 Multi-function Pin Selection"
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line.long 0x1C "SYS_GPB_MFP3,GPIOB Multiple Function Control Register 3"
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hexmask.long.byte 0x1C 24.--28. 1. "PB15MFP,PB.15 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 16.--20. 1. "PB14MFP,PB.14 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 8.--12. 1. "PB13MFP,PB.13 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 0.--4. 1. "PB12MFP,PB.12 Multi-function Pin Selection"
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line.long 0x20 "SYS_GPC_MFP0,GPIOC Multiple Function Control Register 0"
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hexmask.long.byte 0x20 24.--28. 1. "PC3MFP,PC.3 Multi-function Pin Selection"
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hexmask.long.byte 0x20 16.--20. 1. "PC2MFP,PC.2 Multi-function Pin Selection"
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hexmask.long.byte 0x20 8.--12. 1. "PC1MFP,PC.1 Multi-function Pin Selection"
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hexmask.long.byte 0x20 0.--4. 1. "PC0MFP,PC.0 Multi-function Pin Selection"
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line.long 0x24 "SYS_GPC_MFP1,GPIOC Multiple Function Control Register 1"
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hexmask.long.byte 0x24 24.--28. 1. "PC7MFP,PC.7 Multi-function Pin Selection"
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hexmask.long.byte 0x24 16.--20. 1. "PC6MFP,PC.6 Multi-function Pin Selection"
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hexmask.long.byte 0x24 8.--12. 1. "PC5MFP,PC.5 Multi-function Pin Selection"
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hexmask.long.byte 0x24 0.--4. 1. "PC4MFP,PC.4 Multi-function Pin Selection"
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line.long 0x28 "SYS_GPC_MFP2,GPIOC Multiple Function Control Register 2"
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hexmask.long.byte 0x28 24.--28. 1. "PC11MFP,PC.11 Multi-function Pin Selection"
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hexmask.long.byte 0x28 16.--20. 1. "PC10MFP,PC.10 Multi-function Pin Selection"
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hexmask.long.byte 0x28 8.--12. 1. "PC9MFP,PC.9 Multi-function Pin Selection"
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hexmask.long.byte 0x28 0.--4. 1. "PC8MFP,PC.8 Multi-function Pin Selection"
|
|
line.long 0x2C "SYS_GPC_MFP3,GPIOC Multiple Function Control Register 3"
|
|
hexmask.long.byte 0x2C 16.--20. 1. "PC14MFP,PC.14 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "PC13MFP,PC.13 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0x2C 0.--4. 1. "PC12MFP,PC.12 Multi-function Pin Selection"
|
|
line.long 0x30 "SYS_GPD_MFP0,GPIOD Multiple Function Control Register 0"
|
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hexmask.long.byte 0x30 24.--28. 1. "PD3MFP,PD.3 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x30 16.--20. 1. "PD2MFP,PD.2 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0x30 8.--12. 1. "PD1MFP,PD.1 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x30 0.--4. 1. "PD0MFP,PD.0 Multi-function Pin Selection"
|
|
line.long 0x34 "SYS_GPD_MFP1,GPIOD Multiple Function Control Register 1"
|
|
hexmask.long.byte 0x34 24.--28. 1. "PD7MFP,PD.7 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x34 16.--20. 1. "PD6MFP,PD.6 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0x34 8.--12. 1. "PD5MFP,PD.5 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x34 0.--4. 1. "PD4MFP,PD.4 Multi-function Pin Selection"
|
|
line.long 0x38 "SYS_GPD_MFP2,GPIOD Multiple Function Control Register 2"
|
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hexmask.long.byte 0x38 24.--28. 1. "PD11MFP,PD.11 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x38 16.--20. 1. "PD10MFP,PD.10 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0x38 8.--12. 1. "PD9MFP,PD.9 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x38 0.--4. 1. "PD8MFP,PD.8 Multi-function Pin Selection"
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line.long 0x3C "SYS_GPD_MFP3,GPIOD Multiple Function Control Register 3"
|
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hexmask.long.byte 0x3C 24.--28. 1. "PD15MFP,PD.15 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "PD14MFP,PD.14 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0x3C 8.--12. 1. "PD13MFP,PD.13 Multi-function Pin Selection"
|
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hexmask.long.byte 0x3C 0.--4. 1. "PD12MFP,PD.12 Multi-function Pin Selection"
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line.long 0x40 "SYS_GPE_MFP0,GPIOE Multiple Function Control Register 0"
|
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hexmask.long.byte 0x40 24.--28. 1. "PE3MFP,PE.3 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x40 16.--20. 1. "PE2MFP,PE.2 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0x40 8.--12. 1. "PE1MFP,PE.1 Multi-function Pin Selection"
|
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hexmask.long.byte 0x40 0.--4. 1. "PE0MFP,PE.0 Multi-function Pin Selection"
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line.long 0x44 "SYS_GPE_MFP1,GPIOE Multiple Function Control Register 1"
|
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hexmask.long.byte 0x44 24.--28. 1. "PE7MFP,PE.7 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x44 16.--20. 1. "PE6MFP,PE.6 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0x44 8.--12. 1. "PE5MFP,PE.5 Multi-function Pin Selection"
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hexmask.long.byte 0x44 0.--4. 1. "PE4MFP,PE.4 Multi-function Pin Selection"
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line.long 0x48 "SYS_GPE_MFP2,GPIOE Multiple Function Control Register 2"
|
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hexmask.long.byte 0x48 24.--28. 1. "PE11MFP,PE.11 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x48 16.--20. 1. "PE10MFP,PE.10 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0x48 8.--12. 1. "PE9MFP,PE.9 Multi-function Pin Selection"
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hexmask.long.byte 0x48 0.--4. 1. "PE8MFP,PE.8 Multi-function Pin Selection"
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line.long 0x4C "SYS_GPE_MFP3,GPIOE Multiple Function Control Register 3"
|
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hexmask.long.byte 0x4C 24.--28. 1. "PE15MFP,PE.15 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x4C 16.--20. 1. "PE14MFP,PE.14 Multi-function Pin Selection"
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|
newline
|
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hexmask.long.byte 0x4C 8.--12. 1. "PE13MFP,PE.13 Multi-function Pin Selection"
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hexmask.long.byte 0x4C 0.--4. 1. "PE12MFP,PE.12 Multi-function Pin Selection"
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line.long 0x50 "SYS_GPF_MFP0,GPIOF Multiple Function Control Register 0"
|
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hexmask.long.byte 0x50 24.--28. 1. "PF3MFP,PF.3 Multi-function Pin Selection"
|
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hexmask.long.byte 0x50 16.--20. 1. "PF2MFP,PF.2 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x50 8.--12. 1. "PF1MFP,PF.1 Multi-function Pin Selection"
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hexmask.long.byte 0x50 0.--4. 1. "PF0MFP,PF.0 Multi-function Pin Selection"
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line.long 0x54 "SYS_GPF_MFP1,GPIOF Multiple Function Control Register 1"
|
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hexmask.long.byte 0x54 24.--28. 1. "PF7MFP,PF.7 Multi-function Pin Selection"
|
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hexmask.long.byte 0x54 16.--20. 1. "PF6MFP,PF.6 Multi-function Pin Selection"
|
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newline
|
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hexmask.long.byte 0x54 8.--12. 1. "PF5MFP,PF.5 Multi-function Pin Selection"
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hexmask.long.byte 0x54 0.--4. 1. "PF4MFP,PF.4 Multi-function Pin Selection"
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line.long 0x58 "SYS_GPF_MFP2,GPIOF Multiple Function Control Register 2"
|
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hexmask.long.byte 0x58 24.--28. 1. "PF11MFP,PF.11 Multi-function Pin Selection"
|
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hexmask.long.byte 0x58 16.--20. 1. "PF10MFP,PF.10 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x58 8.--12. 1. "PF9MFP,PF.9 Multi-function Pin Selection"
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hexmask.long.byte 0x58 0.--4. 1. "PF8MFP,PF.8 Multi-function Pin Selection"
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group.long 0x560++0xF
|
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line.long 0x0 "SYS_GPG_MFP0,GPIOG Multiple Function Control Register 0"
|
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hexmask.long.byte 0x0 24.--28. 1. "PG3MFP,PG.3 Multi-function Pin Selection"
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hexmask.long.byte 0x0 16.--20. 1. "PG2MFP,PG.2 Multi-function Pin Selection"
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|
line.long 0x4 "SYS_GPG_MFP1,GPIOG Multiple Function Control Register 1"
|
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hexmask.long.byte 0x4 0.--4. 1. "PG4MFP,PG.4 Multi-function Pin Selection"
|
|
line.long 0x8 "SYS_GPG_MFP2,GPIOG Multiple Function Control Register 2"
|
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hexmask.long.byte 0x8 24.--28. 1. "PG11MFP,PG.11 Multi-function Pin Selection"
|
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hexmask.long.byte 0x8 16.--20. 1. "PG10MFP,PG.10 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x8 8.--12. 1. "PG9MFP,PG.9 Multi-function Pin Selection"
|
|
line.long 0xC "SYS_GPG_MFP3,GPIOG Multiple Function Control Register 3"
|
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hexmask.long.byte 0xC 24.--28. 1. "PG15MFP,PG.15 Multi-function Pin Selection"
|
|
hexmask.long.byte 0xC 16.--20. 1. "PG14MFP,PG.14 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0xC 8.--12. 1. "PG13MFP,PG.13 Multi-function Pin Selection"
|
|
hexmask.long.byte 0xC 0.--4. 1. "PG12MFP,PG.12 Multi-function Pin Selection"
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group.long 0x574++0x7
|
|
line.long 0x0 "SYS_GPH_MFP1,GPIOH Multiple Function Control Register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PH7MFP,PH.7 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PH6MFP,PH.6 Multi-function Pin Selection"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "PH5MFP,PH.5 Multi-function Pin Selection"
|
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hexmask.long.byte 0x0 0.--4. 1. "PH4MFP,PH.4 Multi-function Pin Selection"
|
|
line.long 0x4 "SYS_GPH_MFP2,GPIOH Multiple Function Control Register 2"
|
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hexmask.long.byte 0x4 24.--28. 1. "PH11MFP,PH.11 Multi-function Pin Selection"
|
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hexmask.long.byte 0x4 16.--20. 1. "PH10MFP,PH.10 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0x4 8.--12. 1. "PH9MFP,PH.9 Multi-function Pin Selection"
|
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hexmask.long.byte 0x4 0.--4. 1. "PH8MFP,PH.8 Multi-function Pin Selection"
|
|
tree.end
|
|
tree "TIMER (Timer Controller)"
|
|
base ad:0x0
|
|
tree "TMR01"
|
|
base ad:0x40050000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TIMER0_CTL,Timer0 Control Register"
|
|
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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|
newline
|
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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newline
|
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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newline
|
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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|
bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
|
|
newline
|
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bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
|
|
bitfld.long 0x0 15. "FUNCSEL,Function Selection" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
|
|
line.long 0x4 "TIMER0_CMP,Timer0 Comparator Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
|
|
line.long 0x8 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
|
|
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
|
|
line.long 0xC "TIMER0_CNT,Timer0 Data Register"
|
|
rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TIMER0_CAP,Timer0 Capture Data Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
|
|
group.long 0x14++0xB
|
|
line.long 0x0 "TIMER0_EXTCTL,Timer0 External Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
|
|
bitfld.long 0x0 16.--18. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Event Counter input source is from internal USB..,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
|
|
bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
|
|
bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
|
|
newline
|
|
bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
|
|
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
|
|
bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
|
|
line.long 0x4 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
|
|
rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
|
|
bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
|
|
line.long 0x8 "TIMER0_TRGCTL,Timer0 Trigger Control Register"
|
|
bitfld.long 0x8 8. "TRGTK,Trigger Touch-key Scan Enable Bit\nIf this bit is set to 1 timer time-out interrupt can trigger Touck-Key start scan." "0: Timer time-out interrupt signal trigger..,1: Timer time-out interrupt signal trigger.."
|
|
bitfld.long 0x8 5. "TRGLPADC,Trigger LPADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered LPADC transfer." "0: Timer interrupt trigger LPADC Disabled,1: Timer interrupt trigger LPADC Enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
|
|
bitfld.long 0x8 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
|
|
newline
|
|
bitfld.long 0x8 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
|
|
bitfld.long 0x8 1. "TRGPWM,Trigger PWM/EPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM/EPWM counter clock source." "0: Timer interrupt trigger PWM/EPWM Disabled,1: Timer interrupt trigger PWM/EPWM Enabled"
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|
newline
|
|
bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIMER0_CAPNF,Timer0 Capture Input Noise Filter Register"
|
|
bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is ECLKx,1: Noise filter clock is ECLKx/2,?,?,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
|
|
group.long 0x40++0x13
|
|
line.long 0x0 "TIMER0_PWMCTL,Timer0 PWM Control Register"
|
|
bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
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|
bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "PWMINTWKEN,PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode PWMINTWKEN can determine whether chip wake-up occurs or not." "0: PWM interrupt wake-up Disabled,1: PWM interrupt wake-up Enabled"
|
|
bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
|
|
newline
|
|
bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
|
|
line.long 0x4 "TIMER0_PWMCLKPSC,Timer0 PWM Counter Clock Pre-scale Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0 then there is no scaling in PWM counter clock source."
|
|
line.long 0x8 "TIMER0_PWMCNTCLR,Timer0 PWM Clear Counter Register"
|
|
bitfld.long 0x8 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x0000 in up count.."
|
|
line.long 0xC "TIMER0_PWMPERIOD,Timer0 PWM Period Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn up count type:"
|
|
line.long 0x10 "TIMER0_PWMCMPDAT,Timer0 PWM Comparator Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger EADC LPADC PDMA and DAC start conversion."
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "TIMER0_PWMCNT,Timer0 PWM Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter."
|
|
group.long 0x58++0x17
|
|
line.long 0x0 "TIMER0_PWMPOLCTL,Timer0 PWM Pin Output Polar Control Register"
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bitfld.long 0x0 0. "PINV,PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin." "0: PWMx_OUT pin polar inverse Disabled,1: PWMx_OUT polar inverse Enabled"
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line.long 0x4 "TIMER0_PWMPOCTL,Timer0 PWM Pin Output Control Register"
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bitfld.long 0x4 8. "POSEL,PWM Output Pin Select" "0: PWMx_OUT pin is TMx,1: PWMx_OUT pin is TMx_EXT"
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bitfld.long 0x4 0. "POEN,PWMx Output Pin Enable Bit\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin." "0: PWMx_OUT pin at tri-state mode,1: PWMx_OUT pin in output mode"
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line.long 0x8 "TIMER0_PWMINTEN0,Timer0 PWM Interrupt Enable Register 0"
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bitfld.long 0x8 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x8 1. "PIEN,PWM Period Point Interrupt Enable Bit" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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line.long 0xC "TIMER0_PWMINTSTS0,Timer0 PWM Interrupt Status Register 0"
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bitfld.long 0xC 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote: If CMP equal to PERIOD there is no CMPUIF flag in up count type. Note 2: This bit is cleared by writing 1 to it." "?,?"
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bitfld.long 0xC 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it." "0,1"
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line.long 0x10 "TIMER0_PWMTRGCTL,Timer0 PWM Trigger Control Register"
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bitfld.long 0x10 10. "PWMTRGLPADC,PWM Counter Event Trigger LPADC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger LPADC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger LPADC Disabled,1: PWM trigger LPADC Enabled"
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bitfld.long 0x10 9. "PWMTRGPDMA,PWM Counter Event Trigger PDMA Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger PDMA conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger PDMA Disabled,1: PWM trigger PDMA Enabled"
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bitfld.long 0x10 8. "PWMTRGDAC,PWM Counter Event Trigger DAC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger DAC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger DAC Disabled,1: PWM trigger DAC Enabled"
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bitfld.long 0x10 7. "PWMTRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM counter event trigger EADC conversion Disabled,1: PWM counter event trigger EADC conversion Enabled"
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bitfld.long 0x10 0.--1. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at period point (PIF),1: Trigger conversion at compare up count point..,?,?"
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line.long 0x14 "TIMER0_PWMSTATUS,Timer0 PWM Status Register"
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bitfld.long 0x14 19. "LPADCTRGF,Trigger LPADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger LPADC start conversion..,1: PWM counter event trigger LPADC start conversion.."
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bitfld.long 0x14 18. "PDMATRGF,Trigger PDMA Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger PDMA start conversion..,1: PWM counter event trigger PDMA start conversion.."
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bitfld.long 0x14 17. "DACTRGF,Trigger DAC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger DAC start conversion..,1: PWM counter event trigger DAC start conversion.."
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bitfld.long 0x14 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger EADC start conversion..,1: PWM counter event trigger EADC start conversion.."
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bitfld.long 0x14 8. "PWMINTWKF,PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM interrupt wake-up has not occurred,1: PWM interrupt wake-up has occurred"
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bitfld.long 0x14 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it." "0: The PWM counter value never reached its maximum..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0x70++0x7
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line.long 0x0 "TIMER0_PWMPBUF,Timer0 PWM Period Buffer Register"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register."
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line.long 0x4 "TIMER0_PWMCMPBUF,Timer0 PWM Comparator Buffer Register"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register."
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group.long 0xA8++0xF
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line.long 0x0 "TIMER0_PWMIFA,Timer0 PWM Interrupt Flag Accumulator Register"
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bitfld.long 0x0 31. "IFAEN,PWM Interrupt Flag Accumulator Enable Bit" "0: PWM interrupt flag accumulator function Disabled,1: PWM interrupt flag accumulator function Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM Interrupt Flag Accumulator Source Select" "?,1: Accumulate at each PWM period point,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM Accumulator Stop Mode Enable Bit" "0: PWM interrupt accumulator event to stop counting..,1: PWM interrupt accumulator event to stop counting.."
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hexmask.long.word 0x0 0.--15. 1. "IFACNT,PWM Interrupt Flag Accumulator Counter\nThis field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. \nPWM accumulator flag (IFAIF) will be set in every.."
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line.long 0x4 "TIMER0_PWMAINTSTS,Timer0 PWM Accumulator Interrupt Flag Register"
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bitfld.long 0x4 0. "IFAIF,PWM Interrupt Flag Accumulator Interrupt Flag\nThis bit is set by hardware when the accumulator value reaches (IFACNT+1)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: If APDMAEN (TIMERx_PWMAPDMACTL[0]) is set this bit will be auto.." "?,1: This bit is cleared by writing 1 to it"
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line.long 0x8 "TIMER0_PWMAINTEN,Timer0 PWM Accumulator Interrupt Enable Register"
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bitfld.long 0x8 0. "IFAIEN,PWM Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag Accumulator interrupt Disabled,1: Interrupt Flag Accumulator interrupt Enabled"
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line.long 0xC "TIMER0_PWMAPDMACTL,Timer0 PWM Accumulator PDMA Control Register"
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bitfld.long 0xC 0. "APDMAEN,PWM Accumulator PDMA Enable Bit" "0: PWM interrupt accumulator event to trigger PDMA..,1: PWM interrupt accumulator event to trigger PDMA.."
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group.long 0x100++0xF
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line.long 0x0 "TIMER1_CTL,Timer1 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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bitfld.long 0x0 15. "FUNCSEL,Function Selection" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "TIMER1_CMP,Timer1 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
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line.long 0x8 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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line.long 0xC "TIMER1_CNT,Timer1 Data Register"
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rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
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hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
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rgroup.long 0x110++0x3
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line.long 0x0 "TIMER1_CAP,Timer1 Capture Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
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group.long 0x114++0xB
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line.long 0x0 "TIMER1_EXTCTL,Timer1 External Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
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bitfld.long 0x0 16.--18. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Event Counter input source is from internal USB..,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
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rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
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bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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line.long 0x8 "TIMER1_TRGCTL,Timer1 Trigger Control Register"
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bitfld.long 0x8 8. "TRGTK,Trigger Touch-key Scan Enable Bit\nIf this bit is set to 1 timer time-out interrupt can trigger Touck-Key start scan." "0: Timer time-out interrupt signal trigger..,1: Timer time-out interrupt signal trigger.."
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bitfld.long 0x8 5. "TRGLPADC,Trigger LPADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered LPADC transfer." "0: Timer interrupt trigger LPADC Disabled,1: Timer interrupt trigger LPADC Enabled"
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bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x8 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x8 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x8 1. "TRGPWM,Trigger PWM/EPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM/EPWM counter clock source." "0: Timer interrupt trigger PWM/EPWM Disabled,1: Timer interrupt trigger PWM/EPWM Enabled"
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x124++0x3
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line.long 0x0 "TIMER1_CAPNF,Timer1 Capture Input Noise Filter Register"
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bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is ECLKx,1: Noise filter clock is ECLKx/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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group.long 0x140++0x13
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line.long 0x0 "TIMER1_PWMCTL,Timer1 PWM Control Register"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 12. "PWMINTWKEN,PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode PWMINTWKEN can determine whether chip wake-up occurs or not." "0: PWM interrupt wake-up Disabled,1: PWM interrupt wake-up Enabled"
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bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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line.long 0x4 "TIMER1_PWMCLKPSC,Timer1 PWM Counter Clock Pre-scale Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0 then there is no scaling in PWM counter clock source."
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line.long 0x8 "TIMER1_PWMCNTCLR,Timer1 PWM Clear Counter Register"
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bitfld.long 0x8 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x0000 in up count.."
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line.long 0xC "TIMER1_PWMPERIOD,Timer1 PWM Period Register"
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hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn up count type:"
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line.long 0x10 "TIMER1_PWMCMPDAT,Timer1 PWM Comparator Register"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger EADC LPADC PDMA and DAC start conversion."
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rgroup.long 0x154++0x3
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line.long 0x0 "TIMER1_PWMCNT,Timer1 PWM Counter Register"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter."
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group.long 0x158++0x17
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line.long 0x0 "TIMER1_PWMPOLCTL,Timer1 PWM Pin Output Polar Control Register"
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bitfld.long 0x0 0. "PINV,PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin." "0: PWMx_OUT pin polar inverse Disabled,1: PWMx_OUT polar inverse Enabled"
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line.long 0x4 "TIMER1_PWMPOCTL,Timer1 PWM Pin Output Control Register"
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bitfld.long 0x4 8. "POSEL,PWM Output Pin Select" "0: PWMx_OUT pin is TMx,1: PWMx_OUT pin is TMx_EXT"
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bitfld.long 0x4 0. "POEN,PWMx Output Pin Enable Bit\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin." "0: PWMx_OUT pin at tri-state mode,1: PWMx_OUT pin in output mode"
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line.long 0x8 "TIMER1_PWMINTEN0,Timer1 PWM Interrupt Enable Register 0"
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bitfld.long 0x8 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x8 1. "PIEN,PWM Period Point Interrupt Enable Bit" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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line.long 0xC "TIMER1_PWMINTSTS0,Timer1 PWM Interrupt Status Register 0"
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bitfld.long 0xC 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote: If CMP equal to PERIOD there is no CMPUIF flag in up count type. Note 2: This bit is cleared by writing 1 to it." "?,?"
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bitfld.long 0xC 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it." "0,1"
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line.long 0x10 "TIMER1_PWMTRGCTL,Timer1 PWM Trigger Control Register"
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bitfld.long 0x10 10. "PWMTRGLPADC,PWM Counter Event Trigger LPADC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger LPADC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger LPADC Disabled,1: PWM trigger LPADC Enabled"
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bitfld.long 0x10 9. "PWMTRGPDMA,PWM Counter Event Trigger PDMA Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger PDMA conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger PDMA Disabled,1: PWM trigger PDMA Enabled"
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bitfld.long 0x10 8. "PWMTRGDAC,PWM Counter Event Trigger DAC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger DAC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger DAC Disabled,1: PWM trigger DAC Enabled"
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bitfld.long 0x10 7. "PWMTRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM counter event trigger EADC conversion Disabled,1: PWM counter event trigger EADC conversion Enabled"
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bitfld.long 0x10 0.--1. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at period point (PIF),1: Trigger conversion at compare up count point..,?,?"
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line.long 0x14 "TIMER1_PWMSTATUS,Timer1 PWM Status Register"
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bitfld.long 0x14 19. "LPADCTRGF,Trigger LPADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger LPADC start conversion..,1: PWM counter event trigger LPADC start conversion.."
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bitfld.long 0x14 18. "PDMATRGF,Trigger PDMA Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger PDMA start conversion..,1: PWM counter event trigger PDMA start conversion.."
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bitfld.long 0x14 17. "DACTRGF,Trigger DAC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger DAC start conversion..,1: PWM counter event trigger DAC start conversion.."
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bitfld.long 0x14 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger EADC start conversion..,1: PWM counter event trigger EADC start conversion.."
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bitfld.long 0x14 8. "PWMINTWKF,PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM interrupt wake-up has not occurred,1: PWM interrupt wake-up has occurred"
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bitfld.long 0x14 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it." "0: The PWM counter value never reached its maximum..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0x170++0x7
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line.long 0x0 "TIMER1_PWMPBUF,Timer1 PWM Period Buffer Register"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register."
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line.long 0x4 "TIMER1_PWMCMPBUF,Timer1 PWM Comparator Buffer Register"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register."
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group.long 0x1A8++0xF
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line.long 0x0 "TIMER1_PWMIFA,Timer1 PWM Interrupt Flag Accumulator Register"
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bitfld.long 0x0 31. "IFAEN,PWM Interrupt Flag Accumulator Enable Bit" "0: PWM interrupt flag accumulator function Disabled,1: PWM interrupt flag accumulator function Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM Interrupt Flag Accumulator Source Select" "?,1: Accumulate at each PWM period point,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM Accumulator Stop Mode Enable Bit" "0: PWM interrupt accumulator event to stop counting..,1: PWM interrupt accumulator event to stop counting.."
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hexmask.long.word 0x0 0.--15. 1. "IFACNT,PWM Interrupt Flag Accumulator Counter\nThis field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. \nPWM accumulator flag (IFAIF) will be set in every.."
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line.long 0x4 "TIMER1_PWMAINTSTS,Timer1 PWM Accumulator Interrupt Flag Register"
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bitfld.long 0x4 0. "IFAIF,PWM Interrupt Flag Accumulator Interrupt Flag\nThis bit is set by hardware when the accumulator value reaches (IFACNT+1)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: If APDMAEN (TIMERx_PWMAPDMACTL[0]) is set this bit will be auto.." "?,1: This bit is cleared by writing 1 to it"
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line.long 0x8 "TIMER1_PWMAINTEN,Timer1 PWM Accumulator Interrupt Enable Register"
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bitfld.long 0x8 0. "IFAIEN,PWM Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag Accumulator interrupt Disabled,1: Interrupt Flag Accumulator interrupt Enabled"
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line.long 0xC "TIMER1_PWMAPDMACTL,Timer1 PWM Accumulator PDMA Control Register"
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bitfld.long 0xC 0. "APDMAEN,PWM Accumulator PDMA Enable Bit" "0: PWM interrupt accumulator event to trigger PDMA..,1: PWM interrupt accumulator event to trigger PDMA.."
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tree.end
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tree "TMR23"
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base ad:0x40051000
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group.long 0x0++0xF
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line.long 0x0 "TIMER2_CTL,Timer2 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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bitfld.long 0x0 15. "FUNCSEL,Function Selection" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "TIMER2_CMP,Timer2 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
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line.long 0x8 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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line.long 0xC "TIMER2_CNT,Timer2 Data Register"
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rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
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hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
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rgroup.long 0x10++0x3
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line.long 0x0 "TIMER2_CAP,Timer2 Capture Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
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group.long 0x14++0xB
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line.long 0x0 "TIMER2_EXTCTL,Timer2 External Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
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bitfld.long 0x0 16.--18. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Event Counter input source is from internal USB..,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
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rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
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bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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line.long 0x8 "TIMER2_TRGCTL,Timer2 Trigger Control Register"
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bitfld.long 0x8 8. "TRGTK,Trigger Touch-key Scan Enable Bit\nIf this bit is set to 1 timer time-out interrupt can trigger Touck-Key start scan." "0: Timer time-out interrupt signal trigger..,1: Timer time-out interrupt signal trigger.."
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bitfld.long 0x8 5. "TRGLPADC,Trigger LPADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered LPADC transfer." "0: Timer interrupt trigger LPADC Disabled,1: Timer interrupt trigger LPADC Enabled"
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bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x8 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x8 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x8 1. "TRGPWM,Trigger PWM/EPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM/EPWM counter clock source." "0: Timer interrupt trigger PWM/EPWM Disabled,1: Timer interrupt trigger PWM/EPWM Enabled"
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x24++0x3
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line.long 0x0 "TIMER2_CAPNF,Timer2 Capture Input Noise Filter Register"
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bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is ECLKx,1: Noise filter clock is ECLKx/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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group.long 0x40++0x13
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line.long 0x0 "TIMER2_PWMCTL,Timer2 PWM Control Register"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 12. "PWMINTWKEN,PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode PWMINTWKEN can determine whether chip wake-up occurs or not." "0: PWM interrupt wake-up Disabled,1: PWM interrupt wake-up Enabled"
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bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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line.long 0x4 "TIMER2_PWMCLKPSC,Timer2 PWM Counter Clock Pre-scale Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0 then there is no scaling in PWM counter clock source."
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line.long 0x8 "TIMER2_PWMCNTCLR,Timer2 PWM Clear Counter Register"
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bitfld.long 0x8 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x0000 in up count.."
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line.long 0xC "TIMER2_PWMPERIOD,Timer2 PWM Period Register"
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hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn up count type:"
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line.long 0x10 "TIMER2_PWMCMPDAT,Timer2 PWM Comparator Register"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger EADC LPADC PDMA and DAC start conversion."
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rgroup.long 0x54++0x3
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line.long 0x0 "TIMER2_PWMCNT,Timer2 PWM Counter Register"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter."
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group.long 0x58++0x17
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line.long 0x0 "TIMER2_PWMPOLCTL,Timer2 PWM Pin Output Polar Control Register"
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bitfld.long 0x0 0. "PINV,PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin." "0: PWMx_OUT pin polar inverse Disabled,1: PWMx_OUT polar inverse Enabled"
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line.long 0x4 "TIMER2_PWMPOCTL,Timer2 PWM Pin Output Control Register"
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bitfld.long 0x4 8. "POSEL,PWM Output Pin Select" "0: PWMx_OUT pin is TMx,1: PWMx_OUT pin is TMx_EXT"
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bitfld.long 0x4 0. "POEN,PWMx Output Pin Enable Bit\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin." "0: PWMx_OUT pin at tri-state mode,1: PWMx_OUT pin in output mode"
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line.long 0x8 "TIMER2_PWMINTEN0,Timer2 PWM Interrupt Enable Register 0"
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bitfld.long 0x8 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x8 1. "PIEN,PWM Period Point Interrupt Enable Bit" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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line.long 0xC "TIMER2_PWMINTSTS0,Timer2 PWM Interrupt Status Register 0"
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bitfld.long 0xC 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote: If CMP equal to PERIOD there is no CMPUIF flag in up count type. Note 2: This bit is cleared by writing 1 to it." "?,?"
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bitfld.long 0xC 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it." "0,1"
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line.long 0x10 "TIMER2_PWMTRGCTL,Timer2 PWM Trigger Control Register"
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bitfld.long 0x10 10. "PWMTRGLPADC,PWM Counter Event Trigger LPADC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger LPADC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger LPADC Disabled,1: PWM trigger LPADC Enabled"
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bitfld.long 0x10 9. "PWMTRGPDMA,PWM Counter Event Trigger PDMA Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger PDMA conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger PDMA Disabled,1: PWM trigger PDMA Enabled"
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bitfld.long 0x10 8. "PWMTRGDAC,PWM Counter Event Trigger DAC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger DAC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger DAC Disabled,1: PWM trigger DAC Enabled"
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bitfld.long 0x10 7. "PWMTRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM counter event trigger EADC conversion Disabled,1: PWM counter event trigger EADC conversion Enabled"
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bitfld.long 0x10 0.--1. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at period point (PIF),1: Trigger conversion at compare up count point..,?,?"
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line.long 0x14 "TIMER2_PWMSTATUS,Timer2 PWM Status Register"
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bitfld.long 0x14 19. "LPADCTRGF,Trigger LPADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger LPADC start conversion..,1: PWM counter event trigger LPADC start conversion.."
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bitfld.long 0x14 18. "PDMATRGF,Trigger PDMA Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger PDMA start conversion..,1: PWM counter event trigger PDMA start conversion.."
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bitfld.long 0x14 17. "DACTRGF,Trigger DAC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger DAC start conversion..,1: PWM counter event trigger DAC start conversion.."
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bitfld.long 0x14 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger EADC start conversion..,1: PWM counter event trigger EADC start conversion.."
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bitfld.long 0x14 8. "PWMINTWKF,PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM interrupt wake-up has not occurred,1: PWM interrupt wake-up has occurred"
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bitfld.long 0x14 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it." "0: The PWM counter value never reached its maximum..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0x70++0x7
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line.long 0x0 "TIMER2_PWMPBUF,Timer2 PWM Period Buffer Register"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register."
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line.long 0x4 "TIMER2_PWMCMPBUF,Timer2 PWM Comparator Buffer Register"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register."
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group.long 0xA8++0xF
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line.long 0x0 "TIMER2_PWMIFA,Timer2 PWM Interrupt Flag Accumulator Register"
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bitfld.long 0x0 31. "IFAEN,PWM Interrupt Flag Accumulator Enable Bit" "0: PWM interrupt flag accumulator function Disabled,1: PWM interrupt flag accumulator function Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM Interrupt Flag Accumulator Source Select" "?,1: Accumulate at each PWM period point,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM Accumulator Stop Mode Enable Bit" "0: PWM interrupt accumulator event to stop counting..,1: PWM interrupt accumulator event to stop counting.."
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hexmask.long.word 0x0 0.--15. 1. "IFACNT,PWM Interrupt Flag Accumulator Counter\nThis field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. \nPWM accumulator flag (IFAIF) will be set in every.."
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line.long 0x4 "TIMER2_PWMAINTSTS,Timer2 PWM Accumulator Interrupt Flag Register"
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bitfld.long 0x4 0. "IFAIF,PWM Interrupt Flag Accumulator Interrupt Flag\nThis bit is set by hardware when the accumulator value reaches (IFACNT+1)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: If APDMAEN (TIMERx_PWMAPDMACTL[0]) is set this bit will be auto.." "?,1: This bit is cleared by writing 1 to it"
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line.long 0x8 "TIMER2_PWMAINTEN,Timer2 PWM Accumulator Interrupt Enable Register"
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bitfld.long 0x8 0. "IFAIEN,PWM Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag Accumulator interrupt Disabled,1: Interrupt Flag Accumulator interrupt Enabled"
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line.long 0xC "TIMER2_PWMAPDMACTL,Timer2 PWM Accumulator PDMA Control Register"
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bitfld.long 0xC 0. "APDMAEN,PWM Accumulator PDMA Enable Bit" "0: PWM interrupt accumulator event to trigger PDMA..,1: PWM interrupt accumulator event to trigger PDMA.."
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group.long 0x100++0xF
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line.long 0x0 "TIMER3_CTL,Timer3 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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bitfld.long 0x0 15. "FUNCSEL,Function Selection" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "TIMER3_CMP,Timer3 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
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line.long 0x8 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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line.long 0xC "TIMER3_CNT,Timer3 Data Register"
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rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
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hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
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rgroup.long 0x110++0x3
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line.long 0x0 "TIMER3_CAP,Timer3 Capture Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
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group.long 0x114++0xB
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line.long 0x0 "TIMER3_EXTCTL,Timer3 External Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
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bitfld.long 0x0 16.--18. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,1: Event Counter input source is from internal USB..,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1." "0: Capture Function source is from internal ACMP0..,1: Capture Function source is from internal ACMP1..,?,?,?,?,?,?"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
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rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
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bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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line.long 0x8 "TIMER3_TRGCTL,Timer3 Trigger Control Register"
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bitfld.long 0x8 8. "TRGTK,Trigger Touch-key Scan Enable Bit\nIf this bit is set to 1 timer time-out interrupt can trigger Touck-Key start scan." "0: Timer time-out interrupt signal trigger..,1: Timer time-out interrupt signal trigger.."
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bitfld.long 0x8 5. "TRGLPADC,Trigger LPADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered LPADC transfer." "0: Timer interrupt trigger LPADC Disabled,1: Timer interrupt trigger LPADC Enabled"
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bitfld.long 0x8 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x8 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x8 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x8 1. "TRGPWM,Trigger PWM/EPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM/EPWM counter clock source." "0: Timer interrupt trigger PWM/EPWM Disabled,1: Timer interrupt trigger PWM/EPWM Enabled"
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bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x124++0x3
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line.long 0x0 "TIMER3_CAPNF,Timer3 Capture Input Noise Filter Register"
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bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is ECLKx,1: Noise filter clock is ECLKx/2,?,?,?,?,?,?"
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bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
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group.long 0x140++0x13
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line.long 0x0 "TIMER3_PWMCTL,Timer3 PWM Control Register"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL control register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 12. "PWMINTWKEN,PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode PWMINTWKEN can determine whether chip wake-up occurs or not." "0: PWM interrupt wake-up Disabled,1: PWM interrupt wake-up Enabled"
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bitfld.long 0x0 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x0 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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line.long 0x4 "TIMER3_PWMCLKPSC,Timer3 PWM Counter Clock Pre-scale Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0 then there is no scaling in PWM counter clock source."
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line.long 0x8 "TIMER3_PWMCNTCLR,Timer3 PWM Clear Counter Register"
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bitfld.long 0x8 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0x0000 in up count.."
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line.long 0xC "TIMER3_PWMPERIOD,Timer3 PWM Period Register"
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hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn up count type:"
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line.long 0x10 "TIMER3_PWMCMPDAT,Timer3 PWM Comparator Register"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger EADC LPADC PDMA and DAC start conversion."
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rgroup.long 0x154++0x3
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line.long 0x0 "TIMER3_PWMCNT,Timer3 PWM Counter Register"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter."
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group.long 0x158++0x17
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line.long 0x0 "TIMER3_PWMPOLCTL,Timer3 PWM Pin Output Polar Control Register"
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bitfld.long 0x0 0. "PINV,PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin." "0: PWMx_OUT pin polar inverse Disabled,1: PWMx_OUT polar inverse Enabled"
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line.long 0x4 "TIMER3_PWMPOCTL,Timer3 PWM Pin Output Control Register"
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bitfld.long 0x4 8. "POSEL,PWM Output Pin Select" "0: PWMx_OUT pin is TMx,1: PWMx_OUT pin is TMx_EXT"
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bitfld.long 0x4 0. "POEN,PWMx Output Pin Enable Bit\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin." "0: PWMx_OUT pin at tri-state mode,1: PWMx_OUT pin in output mode"
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line.long 0x8 "TIMER3_PWMINTEN0,Timer3 PWM Interrupt Enable Register 0"
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bitfld.long 0x8 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x8 1. "PIEN,PWM Period Point Interrupt Enable Bit" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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line.long 0xC "TIMER3_PWMINTSTS0,Timer3 PWM Interrupt Status Register 0"
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bitfld.long 0xC 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote: If CMP equal to PERIOD there is no CMPUIF flag in up count type. Note 2: This bit is cleared by writing 1 to it." "?,?"
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bitfld.long 0xC 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it." "0,1"
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line.long 0x10 "TIMER3_PWMTRGCTL,Timer3 PWM Trigger Control Register"
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bitfld.long 0x10 10. "PWMTRGLPADC,PWM Counter Event Trigger LPADC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger LPADC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger LPADC Disabled,1: PWM trigger LPADC Enabled"
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bitfld.long 0x10 9. "PWMTRGPDMA,PWM Counter Event Trigger PDMA Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger PDMA conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger PDMA Disabled,1: PWM trigger PDMA Enabled"
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bitfld.long 0x10 8. "PWMTRGDAC,PWM Counter Event Trigger DAC Conversion Enable Bit\nIf this bit is set to 1 PWM can trigger DAC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM trigger DAC Disabled,1: PWM trigger DAC Enabled"
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bitfld.long 0x10 7. "PWMTRGEADC,PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source." "0: PWM counter event trigger EADC conversion Disabled,1: PWM counter event trigger EADC conversion Enabled"
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bitfld.long 0x10 0.--1. "TRGSEL,PWM Counter Event Source Select to Trigger Conversion" "0: Trigger conversion at period point (PIF),1: Trigger conversion at compare up count point..,?,?"
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line.long 0x14 "TIMER3_PWMSTATUS,Timer3 PWM Status Register"
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bitfld.long 0x14 19. "LPADCTRGF,Trigger LPADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger LPADC start conversion..,1: PWM counter event trigger LPADC start conversion.."
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bitfld.long 0x14 18. "PDMATRGF,Trigger PDMA Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger PDMA start conversion..,1: PWM counter event trigger PDMA start conversion.."
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bitfld.long 0x14 17. "DACTRGF,Trigger DAC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger DAC start conversion..,1: PWM counter event trigger DAC start conversion.."
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bitfld.long 0x14 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM counter event trigger EADC start conversion..,1: PWM counter event trigger EADC start conversion.."
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bitfld.long 0x14 8. "PWMINTWKF,PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it." "0: PWM interrupt wake-up has not occurred,1: PWM interrupt wake-up has occurred"
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bitfld.long 0x14 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it." "0: The PWM counter value never reached its maximum..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0x170++0x7
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line.long 0x0 "TIMER3_PWMPBUF,Timer3 PWM Period Buffer Register"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register."
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line.long 0x4 "TIMER3_PWMCMPBUF,Timer3 PWM Comparator Buffer Register"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register."
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group.long 0x1A8++0xF
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line.long 0x0 "TIMER3_PWMIFA,Timer3 PWM Interrupt Flag Accumulator Register"
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bitfld.long 0x0 31. "IFAEN,PWM Interrupt Flag Accumulator Enable Bit" "0: PWM interrupt flag accumulator function Disabled,1: PWM interrupt flag accumulator function Enabled"
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bitfld.long 0x0 28.--29. "IFASEL,PWM Interrupt Flag Accumulator Source Select" "?,1: Accumulate at each PWM period point,?,?"
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bitfld.long 0x0 24. "STPMOD,PWM Accumulator Stop Mode Enable Bit" "0: PWM interrupt accumulator event to stop counting..,1: PWM interrupt accumulator event to stop counting.."
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hexmask.long.word 0x0 0.--15. 1. "IFACNT,PWM Interrupt Flag Accumulator Counter\nThis field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. \nPWM accumulator flag (IFAIF) will be set in every.."
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line.long 0x4 "TIMER3_PWMAINTSTS,Timer3 PWM Accumulator Interrupt Flag Register"
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bitfld.long 0x4 0. "IFAIF,PWM Interrupt Flag Accumulator Interrupt Flag\nThis bit is set by hardware when the accumulator value reaches (IFACNT+1)\nNote 1: This bit is cleared by writing 1 to it.\nNote 2: If APDMAEN (TIMERx_PWMAPDMACTL[0]) is set this bit will be auto.." "?,1: This bit is cleared by writing 1 to it"
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line.long 0x8 "TIMER3_PWMAINTEN,Timer3 PWM Accumulator Interrupt Enable Register"
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bitfld.long 0x8 0. "IFAIEN,PWM Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag Accumulator interrupt Disabled,1: Interrupt Flag Accumulator interrupt Enabled"
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line.long 0xC "TIMER3_PWMAPDMACTL,Timer3 PWM Accumulator PDMA Control Register"
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bitfld.long 0xC 0. "APDMAEN,PWM Accumulator PDMA Enable Bit" "0: PWM interrupt accumulator event to trigger PDMA..,1: PWM interrupt accumulator event to trigger PDMA.."
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tree.end
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tree.end
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tree "TK (Touch Key)"
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base ad:0x400C4000
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group.long 0x0++0x2B
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line.long 0x0 "TK_SCANC,Touch Key Scan Control Register"
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bitfld.long 0x0 31. "TK_EN,Touch Key Scan Enable Bit" "0: Touch Key function Disabled,1: Touch Key function Enabled"
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hexmask.long.byte 0x0 25.--28. 1. "TRG_EN,Trigger Enable Bit\nTimer0~3 and RTC tick trigger key scan periodically Enabled. Key scan will be initiated by timer or RTC periodically."
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bitfld.long 0x0 24. "SCAN,Scan\nWriting '1' to this bit will immediately initiate key scan on all channels which are enabled. This bit will be self-cleared after key scan is started." "0,1"
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hexmask.long.byte 0x0 20.--23. 1. "AVDDH_S,AVDDH Voltage Select"
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bitfld.long 0x0 16. "TK16SEN,TK16 Scan Enable Bit\nThis bit is ignored if TK16REN (TK_REFC[16]) is '1'." "0: TKDAT16 (TK_DAT4[7:0]) is invalid,1: TK16 is always enabled for Touch Key scan."
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bitfld.long 0x0 15. "TK15SEN,TK15 Scan Enable Bit\nThis bit is ignored if TK15REN (TK_REFC[15]) is '1'." "0: TKDAT15 (TK_DAT3[31:24]) is invalid,1: TK15 is always enabled for Touch Key scan."
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bitfld.long 0x0 14. "TK14SEN,TK14 Scan Enable Bit\nThis bit is ignored if TK14REN (TK_REFC[14]) is '1'." "0: TKDAT14 (TK_DAT3[23:16]) is invalid,1: TK14 is always enabled for Touch Key scan."
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bitfld.long 0x0 13. "TK13SEN,TK13 Scan Enable Bit\nThis bit is ignored if TK13REN (TK_REFC[13]) is '1'." "0: TKDAT13 (TK_DAT3[15:8]) is invalid,1: TK13 is always enabled for Touch Key scan."
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bitfld.long 0x0 12. "TK12SEN,TK12 Scan Enable Bit\nThis bit is ignored if TK12REN (TK_REFC[12]) is '1'." "0: TKDAT12 (TK_DAT3[7:0]) is invalid,1: TK12 is always enabled for Touch Key scan."
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bitfld.long 0x0 11. "TK11SEN,TK11 Scan Enable Bit\nThis bit is ignored if TK11REN (TK_REFC[11]) is '1'." "0: TKDAT11 (TK_DAT2[31:24]) is invalid,1: TK11 is always enabled for Touch Key scan."
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bitfld.long 0x0 10. "TK10SEN,TK10 Scan Enable Bit\nThis bit is ignored if TK10REN (TK_REFC[10]) is '1'." "0: TKDAT10 (TK_DAT2[23:16]) is invalid,1: TK10 is always enabled for Touch Key scan."
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bitfld.long 0x0 9. "TK9SEN,TK9 Scan Enable Bit\nThis bit is ignored if TK9REN (TK_REFC[9]) is '1'." "0: TKDAT9 (TK_DAT2[15:8]) is invalid,1: TK9 is always enabled for Touch Key scan. TKDAT9.."
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bitfld.long 0x0 8. "TK8SEN,TK8 Scan Enable Bit\nThis bit is ignored if TK8REN (TK_REFC[8]) is '1'." "0: TKDAT8 (TK_DAT2[7:0]) is invalid,1: TK8 is always enabled for Touch Key scan. TKDAT8.."
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bitfld.long 0x0 7. "TK7SEN,TK7 Scan Enable Bit\nThis bit is ignored if TK7REN (TK_REFC[7]) is '1'." "0: TKDAT7 (TK_DAT1[31:24]) is invalid,1: TK7 is always enabled for Touch Key scan. TKDAT7.."
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bitfld.long 0x0 6. "TK6SEN,TK6 Scan Enable Bit\nThis bit is ignored if TK6REN (TK_REFC[6]) is '1'." "0: TKDAT6 (TK_DAT1[23:16]) is invalid,1: TK6 is always enabled for Touch Key scan. TKDAT6.."
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bitfld.long 0x0 5. "TK5SEN,TK5 Scan Enable Bit\nThis bit is ignored if TK5REN (TK_REFC[5]) is '1'." "0: TKDAT5 (TK_DAT1[15:8]) is invalid,1: TK5 is always enabled for Touch Key scan. TKDAT5.."
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bitfld.long 0x0 4. "TK4SEN,TK4 Scan Enable Bit\nThis bit is ignored if TK4REN (TK_REFC[4]) is '1'." "0: TKDAT4 (TK_DAT1[7:0]) is invalid,1: TK4 is always enabled for Touch Key scan. TKDAT4.."
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bitfld.long 0x0 3. "TK3SEN,TK3 Scan Enable Bit\nThis bit is ignored if TK3REN (TK_REFC[3]) is '1'." "0: TKDAT3 (TK_DAT0[31:24]) is invalid,1: TK3 is always enabled for Touch Key scan. TKDAT3.."
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bitfld.long 0x0 2. "TK2SEN,TK2 Scan Enable Bit\nThis bit is ignored if TK2REN (TK_REFC[2]) is '1'." "0: TKDAT2 (TK_DAT0[23:16]) is invalid,1: TK2 is always enabled for Touch Key scan. TKDAT2.."
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bitfld.long 0x0 1. "TK1SEN,TK1 Scan Enable Bit\nThis bit is ignored if TK1REN (TK_REFC[1]) is '1'." "0: TKDAT1 (TK_DAT0[15:8]) is invalid,1: TK1 is always enabled for Touch Key scan. TKDAT1.."
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bitfld.long 0x0 0. "TK0SEN,TK0 Scan Enable Bit\nThis bit is ignored if TK0REN (TK_REFC[0]) is '1' except SCAN_ALL (TK_REFC[23]) is '1'." "0: TKDAT0 (TK_DAT0[7:0]) is invalid,1: TK0 is always enabled for Touch Key scan. TKDAT0.."
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line.long 0x4 "TK_REFC,Touch Key Reference Control Register"
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bitfld.long 0x4 28.--30. "PULSET,Touch Key Sensing Pulse Width Time Control" "0: 1us,1: 2us,?,?,?,?,?,?"
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bitfld.long 0x4 24.--26. "SENSET,Touch Key Sensing Time Control" "0: 128 x PULSET,1: 255 x PULSET,?,?,?,?,?,?"
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bitfld.long 0x4 23. "SCAN_ALL,All Keys Scan Enable Bit\nThis function is used for low power key scanning operation. TKDAT_ALL (TK_DAT4[15:8]) is the only one valid data when key scan is complete." "0: All Keys Scan function Disabled,1: All Keys Scan function Enabled"
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bitfld.long 0x4 16. "TK16REN,TK16 Reference Enable Bit\nNote: This bit is forced to '1' automatically if none is set as reference." "0: TK16 is not reference,1: TK16 is set as reference and TKDAT16.."
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bitfld.long 0x4 15. "TK15REN,TK15 Reference Enable Bit" "0: TK15 is not reference,1: TK15 is set as reference and TKDAT15.."
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bitfld.long 0x4 14. "TK14REN,TK14 Reference Enable Bit" "0: TK14 is not reference,1: TK14 is set as reference and TKDAT14.."
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bitfld.long 0x4 13. "TK13REN,TK13 Reference Enable Bit" "0: TK13 is not reference,1: TK13 is set as reference and TKDAT13.."
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bitfld.long 0x4 12. "TK12REN,TK12 Reference Enable Bit" "0: TK12 is not reference,1: TK12 is set as reference and TKDAT12.."
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bitfld.long 0x4 11. "TK11REN,TK11 Reference Enable Bit" "0: TK11 is not reference,1: TK11 is set as reference and TKDAT11.."
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bitfld.long 0x4 10. "TK10REN,TK10 Reference Enable Bit" "0: TK10 is not reference,1: TK10 is set as reference and TKDAT10.."
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bitfld.long 0x4 9. "TK9REN,TK9 Reference Enable Bit" "0: TK9 is not reference,1: TK9 is set as reference and TKDAT9.."
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bitfld.long 0x4 8. "TK8REN,TK8 Reference Enable Bit" "0: TK8 is not reference,1: TK8 is set as reference and TKDAT8.."
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bitfld.long 0x4 7. "TK7REN,TK7 Reference Enable Bit" "0: TK7 is not reference,1: TK7 is set as reference and TKDAT7.."
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bitfld.long 0x4 6. "TK6REN,TK6 Reference Enable Bit" "0: TK6 is not reference,1: TK6 is set as reference and TKDAT6.."
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bitfld.long 0x4 5. "TK5REN,TK5 Reference Enable Bit" "0: TK5 is not reference,1: TK5 is set as reference and TKDAT5.."
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bitfld.long 0x4 4. "TK4REN,TK4 Reference Enable Bit" "0: TK4 is not reference,1: TK4 is set as reference and TKDAT4.."
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bitfld.long 0x4 3. "TK3REN,TK3 Reference Enable Bit" "0: TK3 is not reference,1: TK3 is set as reference and TKDAT3.."
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bitfld.long 0x4 2. "TK2REN,TK2 Reference Enable Bit" "0: TK2 is not reference,1: TK2 is set as reference and TKDAT2.."
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bitfld.long 0x4 1. "TK1REN,TK1 Reference Enable Bit" "0: TK1 is not reference,1: TK1 is set as reference and TKDAT1.."
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bitfld.long 0x4 0. "TK0REN,TK0 Reference Enable Bit" "0: TK0 is not reference,1: TK0 is set as reference and TKDAT0.."
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line.long 0x8 "TK_CCBD0,Touch Key Complement Capacitor Bank Data Register 0"
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hexmask.long.byte 0x8 24.--31. 1. "CCBD3,TK3 Complement CB Data\nThese bits are used for TK3 sensitivity adjustment."
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hexmask.long.byte 0x8 16.--23. 1. "CCBD2,TK2 Complement CB Data\nThese bits are used for TK2 sensitivity adjustment."
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hexmask.long.byte 0x8 8.--15. 1. "CCBD1,TK1 Complement CB Data\nThese bits are used for TK1 sensitivity adjustment."
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hexmask.long.byte 0x8 0.--7. 1. "CCBD0,TK0 Complement CB Data\nThese bits are used for TK0 sensitivity adjustment."
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line.long 0xC "TK_CCBD1,Touch Key Complement Capacitor Bank Data Register 1"
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hexmask.long.byte 0xC 24.--31. 1. "CCBD7,TK7 Complement CB Data\nThese bits are used for TK7 sensitivity adjustment."
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hexmask.long.byte 0xC 16.--23. 1. "CCBD6,TK6 Complement CB Data\nThese bits are used for TK6 sensitivity adjustment."
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hexmask.long.byte 0xC 8.--15. 1. "CCBD5,TK5 Complement CB Data\nThese bits are used for TK5 sensitivity adjustment."
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hexmask.long.byte 0xC 0.--7. 1. "CCBD4,TK4 Complement CB Data\nThese bits are used for TK4 sensitivity adjustment."
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line.long 0x10 "TK_CCBD2,Touch Key Complement Capacitor Bank Data Register 2"
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hexmask.long.byte 0x10 24.--31. 1. "CCBD11,TK11 Complement CB Data\nThese bits are used for TK11 sensitivity adjustment."
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hexmask.long.byte 0x10 16.--23. 1. "CCBD10,TK10 Complement CB Data\nThese bits are used for TK10 sensitivity adjustment."
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hexmask.long.byte 0x10 8.--15. 1. "CCBD9,TK9 Complement CB Data\nThese bits are used for TK9 sensitivity adjustment."
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hexmask.long.byte 0x10 0.--7. 1. "CCBD8,TK8 Complement CB Data\nThese bits are used for TK8 sensitivity adjustment."
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line.long 0x14 "TK_CCBD3,Touch Key Complement Capacitor Bank Data Register 3"
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hexmask.long.byte 0x14 24.--31. 1. "CCBD15,TK15 Complement CB Data\nThese bits are used for TK15 sensitivity adjustment."
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hexmask.long.byte 0x14 16.--23. 1. "CCBD14,TK14 Complement CB Data\nThese bits are used for TK14 sensitivity adjustment."
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hexmask.long.byte 0x14 8.--15. 1. "CCBD13,TK13 Complement CB Data\nThese bits are used for TK13 sensitivity adjustment."
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hexmask.long.byte 0x14 0.--7. 1. "CCBD12,TK12 Complement CB Data\nThese bits are used for TK12 sensitivity adjustment."
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line.long 0x18 "TK_CCBD4,Touch Key Complement Capacitor Bank Data Register 4"
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hexmask.long.byte 0x18 8.--15. 1. "CCBD_ALL,All Keys Scan Complement CB Data\nThese bits are used for All Key Scan sensitivity adjustment."
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hexmask.long.byte 0x18 0.--7. 1. "CCBD16,TK16 Complement CB Data\nThese bits are used for TK16 sensitivity adjustment."
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line.long 0x1C "TK_IDLSC,Touch Key Idle State Control Register"
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bitfld.long 0x1C 30.--31. "IDLS15,TK15 Idle State Control \nThese bits are ignored if both TK15SEN (TK_SCANC[15]) and POLEN15 (TK_POLC[23]) are '0' or TK15REN (TK_REFC[15]) is '1'." "0: TK15 connected to Gnd,1: TK15 connected to AVDDH,?,?"
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bitfld.long 0x1C 28.--29. "IDLS14,TK14 Idle State Control \nThese bits are ignored if both TK14SEN (TK_SCANC[14]) and POLEN14 (TK_POLC[22]) are '0' or TK14REN (TK_REFC[14]) is '1'." "0: TK14 connected to Gnd,1: TK14 connected to AVDDH,?,?"
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bitfld.long 0x1C 26.--27. "IDLS13,TK13 Idle State Control \nThese bits are ignored if both TK13SEN (TK_SCANC[13]) and POLEN13 (TK_POLC[21]) are '0' or TK13REN (TK_REFC[13]) is '1'." "0: TK13 connected to Gnd,1: TK13 connected to AVDDH,?,?"
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bitfld.long 0x1C 24.--25. "IDLS12,TK12 Idle State Control \nThese bits are ignored if both TK12SEN (TK_SCANC[12]) and POLEN12 (TK_POLC[20]) are '0' or TK12REN (TK_REFC[12]) is '1'." "0: TK12 connected to Gnd,1: TK12 connected to AVDDH,?,?"
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bitfld.long 0x1C 22.--23. "IDLS11,TK11 Idle State Control \nThese bits are ignored if both TK11SEN (TK_SCANC[11]) and POLEN11 (TK_POLC[19]) are '0' or TK11REN (TK_REFC[11]) is '1'." "0: TK11 connected to Gnd,1: TK11 connected to AVDDH,?,?"
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bitfld.long 0x1C 20.--21. "IDLS10,TK10 Idle State Control \nThese bits are ignored if both TK10SEN (TK_SCANC[10]) and POLEN10 (TK_POLC[18]) are '0' or TK10REN (TK_REFC[10]) is '1'." "0: TK10 connected to Gnd,1: TK10 connected to AVDDH,?,?"
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bitfld.long 0x1C 18.--19. "IDLS9,TK9 Idle State Control \nThese bits are ignored if both TK9SEN (TK_SCANC[9]) and POLEN9 (TK_POLC[17]) are '0' or TK9REN (TK_REFC[9]) is '1'." "0: TK9 connected to Gnd,1: TK9 connected to AVDDH,?,?"
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bitfld.long 0x1C 16.--17. "IDLS8,TK8 Idle State Control \nThese bits are ignored if both TK8SEN (TK_SCANC[8]) and POLEN8 (TK_POLC[16]) are '0' or TK8REN (TK_REFC[8]) is '1'." "0: TK8 connected to Gnd,1: TK8 connected to AVDDH,?,?"
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bitfld.long 0x1C 14.--15. "IDLS7,TK7 Idle State Control \nThese bits are ignored if both TK7SEN (TK_SCANC[7]) and POLEN7 (TK_POLC[15]) are '0' or TK7REN (TK_REFC[7]) is '1'." "0: TK7 connected to Gnd,1: TK7 connected to AVDDH,?,?"
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bitfld.long 0x1C 12.--13. "IDLS6,TK6 Idle State Control \nThese bits are ignored if both TK6SEN (TK_SCANC[6]) and POLEN6 (TK_POLC[14]) are '0' or TK6REN (TK_REFC[6]) is '1'." "0: TK6 connected to Gnd,1: TK6 connected to AVDDH,?,?"
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bitfld.long 0x1C 10.--11. "IDLS5,TK5 Idle State Control \nThese bits are ignored if both TK5SEN (TK_SCANC[5]) and POLEN5 (TK_POLC[13]) are '0' or TK5REN (TK_REFC[5]) is '1'." "0: TK5 connected to Gnd,1: TK5 connected to AVDDH,?,?"
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bitfld.long 0x1C 8.--9. "IDLS4,TK4 Idle State Control \nThese bits are ignored if both TK4SEN (TK_SCANC[4]) and POLEN4 (TK_POLC[12]) are '0' or TK4REN (TK_REFC[4]) is '1'." "0: TK4 connected to Gnd,1: TK4 connected to AVDDH,?,?"
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bitfld.long 0x1C 6.--7. "IDLS3,TK3 Idle State Control \nThese bits are ignored if both TK3SEN (TK_SCANC[3]) and POLEN3 (TK_POLC[11]) are '0' or TK3REN (TK_REFC[3]) is '1'." "0: TK3 connected to Gnd,1: TK3 connected to AVDDH,?,?"
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bitfld.long 0x1C 4.--5. "IDLS2,TK2 Idle State Control \nThese bits are ignored if both TK2SEN (TK_SCANC[2]) and POLEN2 (TK_POLC[10]) are '0' or TK2REN (TK_REFC[2]) is '1'." "0: TK2 connected to Gnd,1: TK2 connected to AVDDH,?,?"
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bitfld.long 0x1C 2.--3. "IDLS1,TK1 Idle State Control \nThese bits are ignored if both TK1SEN (TK_SCANC[1]) and POLEN1 (TK_POLC[9]) are '0' or TK1REN (TK_REFC[1]) is '1'." "0: TK1 connected to Gnd,1: TK1 connected to AVDDH,?,?"
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bitfld.long 0x1C 0.--1. "IDLS0,TK0 Idle State Control \nThese bits are ignored if both TK0SEN (TK_SCANC[0]) and POLEN0 (TK_POLC[8]) are '0' or TK0REN (TK_REFC[0]) is '1'." "0: TK0 connected to Gnd,1: TK0 connected to AVDDH,?,?"
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line.long 0x20 "TK_POLSEL,Touch Key Polarity Select Register"
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bitfld.long 0x20 30.--31. "POL15,TK15 Polarity Select\nThese bits are ignored if POLEN15 (TK_POLC[23]) is '0' or TK15REN (TK_REFC[15]) is '1'." "0: TK15 connected to Gnd,1: TK15 connected to AVDDH,?,?"
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bitfld.long 0x20 28.--29. "POL14,TK14 Polarity Select\nThese bits are ignored if POLEN14 (TK_POLC[22]) is '0' or TK14REN (TK_REFC[14]) is '1'." "0: TK14 connected to Gnd,1: TK14 connected to AVDDH,?,?"
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bitfld.long 0x20 26.--27. "POL13,TK13 Polarity Select \nThese bits are ignored if POLEN13 (TK_POLC[21]) is '0' or TK13REN (TK_REFC[13]) is '1'." "0: TK13 connected to Gnd,1: TK13 connected to AVDDH,?,?"
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bitfld.long 0x20 24.--25. "POL12,TK12 Polarity Select\nThese bits are ignored if POLEN12 (TK_POLC[20]) is '0' or TK12REN (TK_REFC[12]) is '1'." "0: TK12 connected to Gnd,1: TK12 connected to AVDDH,?,?"
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bitfld.long 0x20 22.--23. "POL11,TK11 Polarity Select\nThese bits are ignored if POLEN11 (TK_POLC[19]) is '0' or TK11REN (TK_REFC[11]) is '1'." "0: TK11 connected to Gnd,1: TK11 connected to AVDDH,?,?"
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bitfld.long 0x20 20.--21. "POL10,TK10 Polarity Select\nThese bits are ignored if POLEN10 (TK_POLC[18]) is '0' or TK10REN (TK_REFC[10]) is '1'." "0: TK10 connected to Gnd,1: TK10 connected to AVDDH,?,?"
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bitfld.long 0x20 18.--19. "POL9,TK9 Polarity Select\nThese bits are ignored if POLEN9 (TK_POLC[17]) is '0' or TK9REN (TK_REFC[9]) is '1'." "0: TK9 connected to Gnd,1: TK9 connected to AVDDH,?,?"
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bitfld.long 0x20 16.--17. "POL8,TK8 Polarity Select\nThese bits are ignored if POLEN8 (TK_POLC[16]) is '0' or TK8REN (TK_REFC[8]) is '1'." "0: TK8 connected to Gnd,1: TK8 connected to AVDDH,?,?"
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bitfld.long 0x20 14.--15. "POL7,TK7 Polarity Select\nThese bits are ignored if POLEN7 (TK_POLC[15]) is '0' or TK7REN (TK_REFC[7]) is '1'." "0: TK7 connected to Gnd,1: TK7 connected to AVDDH,?,?"
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bitfld.long 0x20 12.--13. "POL6,TK6 Polarity Select\nThese bits are ignored if POLEN6 (TK_POLC[14]) is '0' or TK6REN (TK_REFC[6]) is '1'." "0: TK6 connected to Gnd,1: TK6 connected to AVDDH,?,?"
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bitfld.long 0x20 10.--11. "POL5,TK5 Polarity Select\nThese bits are ignored if POLEN5 (TK_POLC[13]) is '0' or TK5REN (TK_REFC[5]) is '1'." "0: TK5 connected to Gnd,1: TK5 connected to AVDDH,?,?"
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bitfld.long 0x20 8.--9. "POL4,TK4 Polarity Select\nThese bits are ignored if POLEN4 (TK_POLC[12]) is '0' or TK4REN (TK_REFC[4]) is '1'." "0: TK4 connected to Gnd,1: TK4 connected to AVDDH,?,?"
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bitfld.long 0x20 6.--7. "POL3,TK3 Polarity Select\nThese bits are ignored if POLEN3 (TK_POLC[11]) is '0' or TK3REN (TK_REFC[3]) is '1'." "0: TK3 connected to Gnd,1: TK3 connected to AVDDH,?,?"
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bitfld.long 0x20 4.--5. "POL2,TK2 Polarity Select\nThese bits are ignored if POLEN2 (TK_POLC[10]) is '0' or TK2REN (TK_REFC[2]) is '1'." "0: TK2 connected to Gnd,1: TK2 connected to AVDDH,?,?"
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bitfld.long 0x20 2.--3. "POL1,TK1 Polarity Select \nThese bits are ignored if POLEN1 (TK_POLC[9]) is '0' or TK1REN (TK_REFC[1]) is '1'." "0: TK1 connected to Gnd,1: TK1 connected to AVDDH,?,?"
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bitfld.long 0x20 0.--1. "POL0,TK0 Polarity Select\nThese bits are ignored if POLEN0 (TK_POLC[8]) is '0' or TK0REN (TK_REFC[0]) is '1'." "0: TK0 connected to Gnd,1: TK0 connected to AVDDH,?,?"
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line.long 0x24 "TK_POLC,Touch Key Polarity Control Register"
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bitfld.long 0x24 31. "POL_INIT,Touch Key Sensing Initial Potential Control" "0: Key pad is connected to Gnd before sensing,1: Key pad is connected to AVDDH before sensing"
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bitfld.long 0x24 24. "POLEN16,TK16 Polarity Function Enable Bit" "0: TK16 polarity function Disabled,1: TK16 polarity function Enabled"
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bitfld.long 0x24 23. "POLEN15,TK15 Polarity Function Enable Bit" "0: TK15 polarity function Disabled,1: TK15 polarity function Enabled"
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bitfld.long 0x24 22. "POLEN14,TK14 Polarity Function Enable Bit" "0: TK14 polarity function Disabled,1: TK14 polarity function Enabled"
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bitfld.long 0x24 21. "POLEN13,TK13 Polarity Function Enable Bit" "0: TK13 polarity function Disabled,1: TK13 polarity function Enabled"
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bitfld.long 0x24 20. "POLEN12,TK12 Polarity Function Enable Bit" "0: TK12 polarity function Disabled,1: TK12 polarity function Enabled"
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bitfld.long 0x24 19. "POLEN11,TK11 Polarity Function Enable Bit" "0: TK11 polarity function Disabled,1: TK11 polarity function Enabled"
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bitfld.long 0x24 18. "POLEN10,TK10 Polarity Function Enable Bit" "0: TK10 polarity function Disabled,1: TK10 polarity function Enabled"
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bitfld.long 0x24 17. "POLEN9,TK9 Polarity Function Enable Bit" "0: TK9 polarity function Disabled,1: TK9 polarity function Enabled"
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bitfld.long 0x24 16. "POLEN8,TK8 Polarity Function Enable Bit" "0: TK8 polarity function Disabled,1: TK8 polarity function Enabled"
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bitfld.long 0x24 15. "POLEN7,TK7 Polarity Function Enable Bit" "0: TK7 polarity function Disabled,1: TK7 polarity function Enabled"
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bitfld.long 0x24 14. "POLEN6,TK6 Polarity Function Enable Bit" "0: TK6 polarity function Disabled,1: TK6 polarity function Enabled"
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bitfld.long 0x24 13. "POLEN5,TK5 Polarity Function Enable Bit" "0: TK5 polarity function Disabled,1: TK5 polarity function Enabled"
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bitfld.long 0x24 12. "POLEN4,TK4 Polarity Function Enable Bit" "0: TK4 polarity function Disabled,1: TK4 polarity function Enabled"
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bitfld.long 0x24 11. "POLEN3,TK3 Polarity Function Enable Bit" "0: TK3 polarity function Disabled,1: TK3 polarity function Enabled"
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bitfld.long 0x24 10. "POLEN2,TK2 Polarity Function Enable Bit" "0: TK2 polarity function Disabled,1: TK2 polarity function Enabled"
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bitfld.long 0x24 9. "POLEN1,TK1 Polarity Function Enable Bit" "0: TK1 polarity function Disabled,1: TK1 polarity function Enabled"
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bitfld.long 0x24 8. "POLEN0,TK0 Polarity Function Enable Bit" "0: TK0 polarity function Disabled,1: TK0 polarity function Enabled"
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bitfld.long 0x24 4.--5. "POL_CAP,Capacitor Bank Polarity Select" "0: Gnd,1: AVDDH,?,?"
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bitfld.long 0x24 2.--3. "POL16,TK16 Polarity Control \nThese bits are ignored if POLEN16 (TK_POLC[24]) is '0' or TK16REN (TK_REFC[16]) is '1'." "0: TK16 connected to Gnd,1: TK16 connected to AVDDH,?,?"
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bitfld.long 0x24 0.--1. "IDLS16,TK16 Idle State Control \nThese bits are ignored if both TK16SEN (TK_SCANC[16]) and POLEN16 (TK_POLC[24]) are '0' or TK16REN (TK_REFC[16]) is '1'." "0: TK16 connected to Gnd,1: TK16 connected to AVDDH,?,?"
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line.long 0x28 "TK_STA,Touch Key Status Register"
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bitfld.long 0x28 24. "TKIF16,TK16 Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK16,1: Threshold control event occurs with TK16"
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bitfld.long 0x28 23. "TKIF15,TK15 Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK15,1: Threshold control event occurs with TK15"
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bitfld.long 0x28 22. "TKIF14,TK14 Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK14,1: Threshold control event occurs with TK14"
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bitfld.long 0x28 21. "TKIF13,TK13 Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK13,1: Threshold control event occurs with TK13"
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bitfld.long 0x28 20. "TKIF12,TK12 Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK12,1: Threshold control event occurs with TK12"
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bitfld.long 0x28 19. "TKIF11,TK11 Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK11,1: Threshold control event occurs with TK11"
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bitfld.long 0x28 18. "TKIF10,TK10 Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK10,1: Threshold control event occurs with TK10"
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bitfld.long 0x28 17. "TKIF9,TK9 Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK9,1: Threshold control event occurs with TK9"
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bitfld.long 0x28 16. "TKIF8,TK8 Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK8,1: Threshold control event occurs with TK8"
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bitfld.long 0x28 15. "TKIF7,TK7 Interrupt Flag\nThis bit will be cleared by writing a '1' to this bit.\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK7,1: Threshold control event occurs with TK7"
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bitfld.long 0x28 14. "TKIF6,TK6 Interrupt Flag\nThis bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK6,1: Threshold control event occurs with TK6"
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bitfld.long 0x28 13. "TKIF5,TK5 Interrupt Flag\nThis bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK5,1: Threshold control event occurs with TK5"
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bitfld.long 0x28 12. "TKIF4,TK4 Interrupt Flag\nThis bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK4,1: Threshold control event occurs with TK4"
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bitfld.long 0x28 11. "TKIF3,TK3 Interrupt Flag\nThis bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK3,1: Threshold control event occurs with TK3"
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bitfld.long 0x28 10. "TKIF2,TK2 Interrupt Flag\nThis bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK2,1: Threshold control event occurs with TK2"
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bitfld.long 0x28 9. "TKIF1,TK1 Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK1,1: Threshold control event occurs with TK1"
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bitfld.long 0x28 8. "TKIF0,TK0 Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK0,1: Threshold control event occurs with TK0"
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bitfld.long 0x28 7. "TKIF_ALL,All Keys Scan Interrupt Flag\nNote: This bit will be cleared by writing a '1' to this bit." "0: No threshold control event with All Keys Scan,1: Threshold control event occurs with All Keys Scan"
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rbitfld.long 0x28 6. "TKIF,Key Scan Interrupt Flag (Read Only)\nNote: This bit is 1 while any one of TKIF0~TKIF17 is 1." "0: No threshold control event with each Keys Scan,1: Threshold control event occurs with each Keys Scan"
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bitfld.long 0x28 1. "SCIF,Touch Key Scan Complete Interrupt Flag\nThis bit will be cleared by writing a '1' to this bit.\nNote 1: The Touch Key interrupt asserts if SCIE bit of TK_INTEN register is set.\nNote 2: The Touch Key interrupt also asserts if STHIE bit of TK_INTEN.." "0: Key scan is proceeding and data is not ready for..,1: The Touch Key interrupt asserts if SCIE bit of.."
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rbitfld.long 0x28 0. "BUSY,Touch Key Busy (Read Only)" "0: Key scan is complete or stopped,1: Key scan is proceeding"
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rgroup.long 0x2C++0x13
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line.long 0x0 "TK_DAT0,Touch Key Data Register 0"
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hexmask.long.byte 0x0 24.--31. 1. "TKDAT3,TK3 Sensing Result Data (Read Only)\nThis data is invalid if TK3SEN (TK_SCANC[3]) is '0' or TK3REN (TK_REFC[3]) is '1'."
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hexmask.long.byte 0x0 16.--23. 1. "TKDAT2,TK2 Sensing Result Data (Read Only)\nThis data is invalid if TK2SEN (TK_SCANC[2]) is '0' or TK2REN (TK_REFC[2]) is '1'."
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hexmask.long.byte 0x0 8.--15. 1. "TKDAT1,TK1 Sensing Result Data (Read Only)\nThis data is invalid if TK1SEN (TK_SCANC[1]) is '0' or TK1REN (TK_REFC[1]) is '1'."
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hexmask.long.byte 0x0 0.--7. 1. "TKDAT0,TK0 Sensing Result Data (Read Only)\nThis data is invalid if TK0SEN (TK_SCANC[0]) is '0' or TK0REN (TK_REFC[0]) is '1' except SCAN_ALL (TK_REFC[23]) is '1'."
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line.long 0x4 "TK_DAT1,Touch Key Data Register 1"
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hexmask.long.byte 0x4 24.--31. 1. "TKDAT7,TK7 Sensing Result Data (Read Only)\nThis data is invalid if TK7SEN (TK_SCANC[7]) is '0' or TK7REN (TK_REFC[7]) is '1'."
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hexmask.long.byte 0x4 16.--23. 1. "TKDAT6,TK6 Sensing Result Data (Read Only)\nThis data is invalid if TK6SEN (TK_SCANC[6]) is '0' or TK6REN (TK_REFC[6]) is '1'."
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hexmask.long.byte 0x4 8.--15. 1. "TKDAT5,TK5 Sensing Result Data (Read Only)\nThis data is invalid if TK5SEN (TK_SCANC[5]) is '0' or TK5REN (TK_REFC[5]) is '1'."
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hexmask.long.byte 0x4 0.--7. 1. "TKDAT4,TK0 Sensing Result Data (Read Only)\nThis data is invalid if TK4SEN (TK_SCANC[4]) is '0' or TK4REN (TK_REFC[4]) is '1'."
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line.long 0x8 "TK_DAT2,Touch Key Data Register 2"
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hexmask.long.byte 0x8 24.--31. 1. "TKDAT11,TK11 Sensing Result Data (Read Only)\nThis data is invalid if TK11SEN (TK_SCANC[11]) is '0' or TK11REN (TK_REFC[11]) is '1'."
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hexmask.long.byte 0x8 16.--23. 1. "TKDAT10,TK10 Sensing Result Data (Read Only)\nThis data is invalid if TK10SEN (TK_SCANC[10]) is '0' or TK10REN (TK_REFC[10]) is '1'."
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hexmask.long.byte 0x8 8.--15. 1. "TKDAT9,TK9 Sensing Result Data (Read Only)\nThis data is invalid if TK9SEN (TK_SCANC[9]) is '0' or TK9REN (TK_REFC[9]) is '1'."
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hexmask.long.byte 0x8 0.--7. 1. "TKDAT8,TK8 Sensing Result Data (Read Only)\nThis data is invalid if TK8SEN (TK_SCANC[8]) is '0' or TK8REN (TK_REFC[8]) is '1'."
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line.long 0xC "TK_DAT3,Touch Key Data Register 3"
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hexmask.long.byte 0xC 24.--31. 1. "TKDAT15,TK15 Sensing Result Data (Read Only)\nThis data is invalid if TK15SEN (TK_SCANC[15]) is '0' or TK15REN (TK_REFC[15]) is '1'."
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hexmask.long.byte 0xC 16.--23. 1. "TKDAT14,TK14 Sensing Result Data (Read Only)\nThis data is invalid if TK14SEN (TK_SCANC[14]) is '0' or TK14REN (TK_REFC[14]) is '1'."
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hexmask.long.byte 0xC 8.--15. 1. "TKDAT13,TK13 Sensing Result Data (Read Only)\nThis data is invalid if TK13SEN (TK_SCANC[13]) is '0' or TK13REN (TK_REFC[13]) is '1'."
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hexmask.long.byte 0xC 0.--7. 1. "TKDAT12,TK12 Sensing Result Data (Read Only)\nThis data is invalid if TK12SEN (TK_SCANC[12]) is '0' or TK12REN (TK_REFC[12]) is '1'."
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line.long 0x10 "TK_DAT4,Touch Key Data Register 4"
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hexmask.long.byte 0x10 8.--15. 1. "TKDAT_ALL,All Keys Scan Sensing Result Data (Read Only)\nThis data is invalid if SCAN_ALL (TK_REFC[23]) is '0'."
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hexmask.long.byte 0x10 0.--7. 1. "TKDAT16,TK16 Sensing Result Data (Read Only)\nThis data is invalid if TK16SEN (TK_SCANC[16]) is '0' or TK16REN (TK_REFC[16]) is '1'."
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group.long 0x40++0x3B
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line.long 0x0 "TK_INTEN,Touch Key Interrupt Enable Register"
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bitfld.long 0x0 1. "SCIE,Touch Key Scan Complete Interrupt Enable Bit" "0: Key scan complete without threshold control..,1: Key scan complete without threshold control.."
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bitfld.long 0x0 0. "SCTHIE,Touch Key Scan Complete with High Threshold Control Interrupt Enable Bit" "0: Key scan complete with threshold control..,1: Key scan complete with threshold control.."
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line.long 0x4 "TK_THC01,Touch Key TK0/TK1 Threshold Control Register"
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hexmask.long.byte 0x4 24.--31. 1. "HTH1,High Threshold of TK1\nHigh level for TK1 threshold control."
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hexmask.long.byte 0x4 8.--15. 1. "HTH0,High Threshold of TK0\nHigh level for TK0 threshold control."
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line.long 0x8 "TK_THC23,Touch Key TK2/TK3 Threshold Control Register"
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hexmask.long.byte 0x8 24.--31. 1. "HTH3,High Threshold of TK3\nHigh level for TK3 threshold control."
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hexmask.long.byte 0x8 8.--15. 1. "HTH2,High Threshold of TK2\nHigh level for TK2 threshold control."
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line.long 0xC "TK_THC45,Touch Key TK4/TK5 Threshold Control Register"
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hexmask.long.byte 0xC 24.--31. 1. "HTH5,High Threshold of TK5\nHigh level for TK5 threshold control."
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hexmask.long.byte 0xC 8.--15. 1. "HTH4,High Threshold of TK4\nHigh level for TK4 threshold control."
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line.long 0x10 "TK_THC67,Touch Key TK6/TK7 Threshold Control Register"
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hexmask.long.byte 0x10 24.--31. 1. "HTH7,High Threshold of TK7\nHigh level for TK7 threshold control."
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hexmask.long.byte 0x10 8.--15. 1. "HTH6,High Threshold of TK6\nHigh level for TK6 threshold control."
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line.long 0x14 "TK_THC89,Touch Key TK8/TK9 Threshold Control Register"
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hexmask.long.byte 0x14 24.--31. 1. "HTH9,High Threshold of TK9\nHigh level for TK9 threshold control."
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hexmask.long.byte 0x14 8.--15. 1. "HTH8,High Threshold of TK8\nHigh level for TK8 threshold control."
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line.long 0x18 "TK_THC1011,Touch Key TK10/TK11 Threshold Control Register"
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hexmask.long.byte 0x18 24.--31. 1. "HTH11,High Threshold of TK11\nHigh level for TK11 threshold control."
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hexmask.long.byte 0x18 8.--15. 1. "HTH10,High Threshold of TK10\nHigh level for TK10 threshold control."
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line.long 0x1C "TK_THC1213,Touch Key TK12/TK13 Threshold Control Register"
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hexmask.long.byte 0x1C 24.--31. 1. "HTH13,High Threshold of TK13\nHigh level for TK13 threshold control."
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hexmask.long.byte 0x1C 8.--15. 1. "HTH12,High Threshold of TK12\nHigh level for TK12 threshold control."
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line.long 0x20 "TK_THC1415,Touch Key TK14/TK15 Threshold Control Register"
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hexmask.long.byte 0x20 24.--31. 1. "HTH15,High Threshold of TK15\nHigh level for TK15 threshold control."
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hexmask.long.byte 0x20 8.--15. 1. "HTH14,High Threshold of TK14\nHigh level for TK14 threshold control."
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line.long 0x24 "TK_THC16,Touch Key TK16 Threshold Control Register"
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hexmask.long.byte 0x24 24.--31. 1. "HTH_ALL,High Threshold of ALL Keys Scan\nHigh level for All Keys Scan threshold control."
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hexmask.long.byte 0x24 8.--15. 1. "HTH16,High Threshold of TK16\nHigh level for TK16 threshold control."
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line.long 0x28 "TK_REFCBD0,Touch Key Reference Capacitor Bank Data Register 0"
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hexmask.long.byte 0x28 24.--31. 1. "CBD3,TK3 Capacitor Bank Data\nThese bits are used for TK3 sensitivity adjustment."
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hexmask.long.byte 0x28 16.--23. 1. "CBD2,TK2 Capacitor Bank Data\nThese bits are used for TK2 sensitivity adjustment."
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hexmask.long.byte 0x28 8.--15. 1. "CBD1,TK1 Capacitor Bank Data\nThese bits are used for TK1 sensitivity adjustment."
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hexmask.long.byte 0x28 0.--7. 1. "CBD0,TK0 Capacitor Bank Data\nThese bits are used for TK0 sensitivity adjustment."
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line.long 0x2C "TK_REFCBD1,Touch Key Reference Capacitor Bank Data Register 1"
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hexmask.long.byte 0x2C 24.--31. 1. "CBD7,TK7 Capacitor Bank Data\nThese bits are used for TK7 sensitivity adjustment."
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hexmask.long.byte 0x2C 16.--23. 1. "CBD6,TK6 Capacitor Bank Data\nThese bits are used for TK6 sensitivity adjustment."
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hexmask.long.byte 0x2C 8.--15. 1. "CBD5,TK5 Capacitor Bank Data\nThese bits are used for TK5 sensitivity adjustment."
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hexmask.long.byte 0x2C 0.--7. 1. "CBD4,TK4 Capacitor Bank Data\nThese bits are used for TK4 sensitivity adjustment."
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line.long 0x30 "TK_REFCBD2,Touch Key Reference Capacitor Bank Data Register 2"
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hexmask.long.byte 0x30 24.--31. 1. "CBD11,TK11 Capacitor Bank Data\nThese bits are used for TK11 sensitivity adjustment."
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hexmask.long.byte 0x30 16.--23. 1. "CBD10,TK10 Capacitor Bank Data\nThese bits are used for TK10 sensitivity adjustment."
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hexmask.long.byte 0x30 8.--15. 1. "CBD9,TK9 Capacitor Bank Data\nThese bits are used for TK9 sensitivity adjustment."
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hexmask.long.byte 0x30 0.--7. 1. "CBD8,TK8 Capacitor Bank Data\nThese bits are used for TK8 sensitivity adjustment."
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line.long 0x34 "TK_REFCBD3,Touch Key Reference Capacitor Bank Data Register 3"
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hexmask.long.byte 0x34 24.--31. 1. "CBD15,TK15 Capacitor Bank Data\nThese bits are used for TK15 sensitivity adjustment."
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hexmask.long.byte 0x34 16.--23. 1. "CBD14,TK14 Capacitor Bank Data\nThese bits are used for TK14 sensitivity adjustment."
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hexmask.long.byte 0x34 8.--15. 1. "CBD13,TK13 Capacitor Bank Data\nThese bits are used for TK13 sensitivity adjustment."
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hexmask.long.byte 0x34 0.--7. 1. "CBD12,TK12 Capacitor Bank Data\nThese bits are used for TK12 sensitivity adjustment."
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line.long 0x38 "TK_REFCBD4,Touch Key Reference Capacitor Bank Data Register 4"
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hexmask.long.byte 0x38 8.--15. 1. "CBD_ALL,All Keys Scan Capacitor Bank Data\nThese bits are used for All Keys Scan sensitivity adjustment."
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hexmask.long.byte 0x38 0.--7. 1. "CBD16,TK16 Capacitor Bank Data\nThese bits are used for TK16 sensitivity adjustment."
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group.long 0x80++0xB
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line.long 0x0 "TK_SCANC1,Touch Key Scan Control Register 1"
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bitfld.long 0x0 0. "TK17SEN,TK17 Scan Enable Bit\nThis bit is ignored if TK17REN (TK_REFC[17]) is '1'." "0: TKDAT17 (TK_DAT5[7:0]) is invalid,1: TK17 is always enabled for key scan. TKDAT17.."
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line.long 0x4 "TK_REFC1,Touch Key Reference Control Register 1"
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bitfld.long 0x4 0. "TK17REN,TK17 Reference Enable Bit" "0: TK17 is not reference,1: TK17 is set as reference and TKDAT17.."
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line.long 0x8 "TK_CCBD5,Touch Key Complement Capacitor Bank Data Register 5"
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hexmask.long.byte 0x8 0.--7. 1. "CCBD17,TK17 Complement CB Data\nThese bits are used for TK17 sensitivity adjustment."
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group.long 0x9C++0xF
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line.long 0x0 "TK_IDLSC1,Touch Key Idle State Control Register 1"
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bitfld.long 0x0 0.--1. "IDLS17,TK17 Idle State Control \nThese bits are ignored if both TK17SEN (TK_SCANC1[0]) and POLEN17 (TK_POLC1[0]) are '0' or TK17REN (TK_REFC1[0]) is '1'." "0: TK17 connected to Gnd,1: TK17 connected to AVDDH,?,?"
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line.long 0x4 "TK_POLSEL1,Touch Key Polarity Select Register 1"
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bitfld.long 0x4 0.--1. "POL17,TK17 Polarity Select\nThese bits are ignored if POLEN17 (TK_POLC1[0]) is '0' or TK17REN (TK_REFC1[0]) is '1'." "0: TK17 connected to Gnd,1: TK17 connected to AVDDH,?,?"
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line.long 0x8 "TK_POLC1,Touch Key Polarity Control Register 1"
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bitfld.long 0x8 0. "POLEN17,TK17 Polarity Function Enable Bit" "0: TK17 polarity function Disabled,1: TK17 polarity function Enabled"
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line.long 0xC "TK_STA1,Touch Key Status Register 1"
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bitfld.long 0xC 0. "TKIF17,TK17 Interrupt Flag\nThis bit will be cleared by writing a '1' to this bit." "0: No threshold control event with TK17,1: Threshold control event occurs with TK17"
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rgroup.long 0xAC++0x3
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line.long 0x0 "TK_DAT5,Touch Key Data Register 5"
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hexmask.long.byte 0x0 0.--7. 1. "TKDAT17,TK17 Sensing Result Data (Read Only)\nThis data is invalid if TK17SEN (TK_SCANC1[0]) is '0' or TK17REN (TK_REFC1[0]) is '1'."
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group.long 0xC4++0x3
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line.long 0x0 "TK_THC17,Touch Key TK17 Threshold Control Register"
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hexmask.long.byte 0x0 8.--15. 1. "HTH17,High Threshold of TK17\nHigh level for TK17 threshold control."
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group.long 0xE8++0x3
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line.long 0x0 "TK_REFCBD5,Touch Key Reference Capacitor Bank Data Register 5"
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hexmask.long.byte 0x0 0.--7. 1. "CBD17,TK17 Capacitor Bank Data\nThese bits are used for TK17 sensitivity adjustment."
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group.long 0x100++0x1B
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line.long 0x0 "TK_EXTCBC,Touch Key Extend Capacitor Bank Control Register"
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bitfld.long 0x0 0.--1. "EXT_CBSEL,TK Extend Capacitor Bank Select\nTK capacitor bank data and reference capacitor bank data are 9 bits. These bits are used to select how the 9 bits are generated.\nNote: The above parameter x is 0 to 17.\nNote: The above parameter n is 0 to 3." "0: CCBDx (TK_CCBDx[8n+7:8n]) and CBDx..,1: CCBDx (TK_CCBDx[8n+7:8n]) and CBDx..,?,?"
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line.long 0x4 "TK_EXTCCBD0,Touch Key Extend Complement Capacitor Bank Data Register 0"
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bitfld.long 0x4 24. "CCBD3,TK3 Extend Complement CB Data\nThese bits are used for TK3 sensitivity adjustment." "0,1"
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bitfld.long 0x4 16. "CCBD2,TK2 Extend Complement CB Data\nThese bits are used for TK2 sensitivity adjustment." "0,1"
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bitfld.long 0x4 8. "CCBD1,TK1 Extend Complement CB Data\nThese bits are used for TK1 sensitivity adjustment." "0,1"
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bitfld.long 0x4 0. "CCBD0,TK0 Extend Complement CB Data\nThese bits are used for TK0 sensitivity adjustment." "0,1"
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line.long 0x8 "TK_EXTCCBD1,Touch Key Extend Complement Capacitor Bank Data Register 1"
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bitfld.long 0x8 24. "CCBD7,TK7 Extend Complement CB Data\nThese bits are used for TK7 sensitivity adjustment." "0,1"
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bitfld.long 0x8 16. "CCBD6,TK6 Extend Complement CB Data\nThese bits are used for TK6 sensitivity adjustment." "0,1"
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bitfld.long 0x8 8. "CCBD5,TK5 Extend Complement CB Data\nThese bits are used for TK5 sensitivity adjustment." "0,1"
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bitfld.long 0x8 0. "CCBD4,TK4 Extend Complement CB Data\nThese bits are used for TK4 sensitivity adjustment." "0,1"
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line.long 0xC "TK_EXTCCBD2,Touch Key Extend Complement Capacitor Bank Data Register 2"
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bitfld.long 0xC 24. "CCBD11,TK11 Extend Complement CB Data\nThese bits are used for TK11 sensitivity adjustment." "0,1"
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bitfld.long 0xC 16. "CCBD10,TK10 Extend Complement CB Data\nThese bits are used for TK10 sensitivity adjustment." "0,1"
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bitfld.long 0xC 8. "CCBD9,TK9 Extend Complement CB Data\nThese bits are used for TK9 sensitivity adjustment." "0,1"
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bitfld.long 0xC 0. "CCBD8,TK8 Extend Complement CB Data\nThese bits are used for TK8 sensitivity adjustment." "0,1"
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line.long 0x10 "TK_EXTCCBD3,Touch Key Extend Complement Capacitor Bank Data Register 3"
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bitfld.long 0x10 24. "CCBD15,TK15 Extend Complement CB Data\nThese bits are used for TK15 sensitivity adjustment." "0,1"
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bitfld.long 0x10 16. "CCBD14,TK14 Extend Complement CB Data\nThese bits are used for TK14 sensitivity adjustment." "0,1"
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newline
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bitfld.long 0x10 8. "CCBD13,TK13 Extend Complement CB Data\nThese bits are used for TK13 sensitivity adjustment." "0,1"
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bitfld.long 0x10 0. "CCBD12,TK12 Extend Complement CB Data\nThese bits are used for TK12 sensitivity adjustment." "0,1"
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line.long 0x14 "TK_EXTCCBD4,Touch Key Extend Complement Capacitor Bank Data Register 4"
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bitfld.long 0x14 8. "CCBDALL,All Keys Extend Complement CB Data\nThese bits are used for All Key Scan sensitivity adjustment." "0,1"
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bitfld.long 0x14 0. "CCBD16,TK16 Extend Complement CB Data\nThese bits are used for TK16 sensitivity adjustment." "0,1"
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line.long 0x18 "TK_EXTCCBD5,Touch Key Extend Complement Capacitor Bank Data Register 5"
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|
bitfld.long 0x18 0. "CCBD17,TK17 Extend Complement CB Data\nThese bits are used for TK17 sensitivity adjustment." "0,1"
|
|
group.long 0x130++0x17
|
|
line.long 0x0 "TK_EXTREFCBD0,Touch Key Extend Reference Capacitor Bank Data Register 0"
|
|
bitfld.long 0x0 24. "EXT_CBD3,TK3 Extend Capacitor Bank Data\nThese bits are used for TK3 sensitivity adjustment." "0,1"
|
|
bitfld.long 0x0 16. "EXT_CBD2,TK2 Extend Capacitor Bank Data\nThese bits are used for TK2 sensitivity adjustment." "0,1"
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|
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bitfld.long 0x0 8. "EXT_CBD1,TK1 Extend Capacitor Bank Data\nThese bits are used for TK1 sensitivity adjustment." "0,1"
|
|
bitfld.long 0x0 0. "EXT_CBD0,TK0 Extend Capacitor Bank Data\nThese bits are used for TK0 sensitivity adjustment." "0,1"
|
|
line.long 0x4 "TK_EXTREFCBD1,Touch Key Extend Reference Capacitor Bank Data Register 1"
|
|
bitfld.long 0x4 24. "EXT_CBD7,TK7 Extend Capacitor Bank Data\nThese bits are used for TK7 sensitivity adjustment." "0,1"
|
|
bitfld.long 0x4 16. "EXT_CBD6,TK6 Extend Capacitor Bank Data\nThese bits are used for TK6 sensitivity adjustment." "0,1"
|
|
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bitfld.long 0x4 8. "EXT_CBD5,TK5 Extend Capacitor Bank Data\nThese bits are used for TK5 sensitivity adjustment." "0,1"
|
|
bitfld.long 0x4 0. "EXT_CBD4,TK4 Extend Capacitor Bank Data\nThese bits are used for TK4 sensitivity adjustment." "0,1"
|
|
line.long 0x8 "TK_EXTREFCBD2,Touch Key Extend Reference Capacitor Bank Data Register 2"
|
|
bitfld.long 0x8 24. "EXT_CBD11,TK11 Extend Capacitor Bank Data\nThese bits are used for TK11 sensitivity adjustment." "0,1"
|
|
bitfld.long 0x8 16. "EXT_CBD10,TK10 Extend Capacitor Bank Data\nThese bits are used for TK10 sensitivity adjustment." "0,1"
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|
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bitfld.long 0x8 8. "EXT_CBD9,TK9 Extend Capacitor Bank Data\nThese bits are used for TK9 sensitivity adjustment." "0,1"
|
|
bitfld.long 0x8 0. "EXT_CBD8,TK8 Extend Capacitor Bank Data\nThese bits are used for TK8 sensitivity adjustment." "0,1"
|
|
line.long 0xC "TK_EXTREFCBD3,Touch Key Extend Reference Capacitor Bank Data Register 3"
|
|
bitfld.long 0xC 24. "EXT_CBD15,TK15 Extend Capacitor Bank Data\nThese bits are used for TK15 sensitivity adjustment." "0,1"
|
|
bitfld.long 0xC 16. "EXT_CBD14,TK14 Extend Capacitor Bank Data\nThese bits are used for TK14 sensitivity adjustment." "0,1"
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|
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bitfld.long 0xC 8. "EXT_CBD13,TK13 Extend Capacitor Bank Data\nThese bits are used for TK13 sensitivity adjustment." "0,1"
|
|
bitfld.long 0xC 0. "EXT_CBD12,TK12 Extend Capacitor Bank Data\nThese bits are used for TK12 sensitivity adjustment." "0,1"
|
|
line.long 0x10 "TK_EXTREFCBD4,Touch Key Extend Reference Capacitor Bank Data Register 4"
|
|
bitfld.long 0x10 8. "EXT_CBDALL,All Keys Extend Capacitor Bank Data\nThese bits are used for All Keys Scan sensitivity adjustment." "0,1"
|
|
bitfld.long 0x10 0. "EXT_CBD16,TK16 Extend Capacitor Bank Data\nThese bits are used for TK16 sensitivity adjustment." "0,1"
|
|
line.long 0x14 "TK_EXTREFCBD5,Touch Key Extend Reference Capacitor Bank Data Register 5"
|
|
bitfld.long 0x14 0. "EXT_CBD17,TK17 Extend Capacitor Bank Data\nThese bits are used for TK17 sensitivity adjustment." "0,1"
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x400B9000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TRNG_CTL,TRNG Control Register"
|
|
bitfld.long 0x0 31. "DVIEN,Data Valid Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x0 30. "ERRIEN,TRNG Error Interrupt Enable Bit" "0: Error interrupt Disabled,1: Error interrupt Enabled"
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|
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bitfld.long 0x0 25.--26. "KATSEL,CTR_DRBG Known Answer Test Selection" "0: Instantiation testing,1: Reseed testing,2: Generation testing,?"
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|
bitfld.long 0x0 24. "KATEN,CTR_DRBG Known Answer Test Enable Bit\nNote: Do not enable START (TRNG_CTL[3]) and KATEN (TRNG_CTL[24]) at the same time." "0: Disabled,1: Enabled"
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|
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|
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bitfld.long 0x0 10. "UPDATE,CTR_DRBG User Manual Update Function" "0: No effect,1: Enable CTR_DRBG update function"
|
|
bitfld.long 0x0 9. "RESEED,CTR_DRBG User Manual Reseed Function" "0: No effect,1: Enable CTR_DRBG reseed function"
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|
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|
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bitfld.long 0x0 8. "INSTANT,CTR_DRBG User Manual Instant Function" "0: No effect,1: Enable CTR_DRBG instant function"
|
|
bitfld.long 0x0 4.--5. "MODE,Random Bit Generator Output Selection" "0: Output data is from entropy (32-bits),1: Output data is from NRBG (128-bits),?,?"
|
|
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bitfld.long 0x0 3. "START,True Random Number Generator Start\nNote: Do not enable START (TRNG_CTL[3]) and KATEN (TRNG_CTL[24]) at the same time. This bit is always 0 when it is read back." "0: No effect,1: Start TRNG"
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|
bitfld.long 0x0 2. "TRNGEN,True Random Number Generator Macro Enable Bit" "0: TRNG macro Disabled,1: TRNG macro Enabled"
|
|
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|
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bitfld.long 0x0 1. "NRST,Negative-edge Trigger Reset" "0: Keep reset,1: No reset"
|
|
bitfld.long 0x0 0. "LDOEN,LDO Enable Bit" "0: LDO Disabled,1: LDO Enabled"
|
|
line.long 0x4 "TRNG_CFG,TRNG Configure Register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "CTRLEN,CTR_DRBG Bits Length Per Request"
|
|
hexmask.long 0x4 0.--25. 1. "RESEED_INTERVAL,Reseed Interval\nMaximum number of requests between reseeds.\nThe value is 1 ~ 225 ."
|
|
rgroup.long 0x8++0x13
|
|
line.long 0x0 "TRNG_STS,TRNG Status Register"
|
|
bitfld.long 0x0 31. "DVIF,Data Valid Interrupt Flag" "0: Data is invalid,1: Data is valid. A valid random number can be read.."
|
|
bitfld.long 0x0 30. "ERRIF,TRNG Error Interrupt Flag" "0: No TRNG error,1: TRNGRDY became '0' over 1ms TRNG error interrupt"
|
|
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|
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bitfld.long 0x0 27. "KATPASS,CTR_DRBG Known Answer Test Pass\nNote: When users enable KATEN (TRNG_CTL[24]) they can check this bit after DVIF (TRNG_STS[31]) become '1'." "0: Test fail,1: Test pass"
|
|
bitfld.long 0x0 6. "ESAPT,Entropy Source Adaptive Proportion Test" "0: Entropy source is still under testing or test fail,1: Test pass"
|
|
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|
|
bitfld.long 0x0 5. "ESRCT,Entropy Source Repetition Count Test" "0: Entropy source is still under testing or test fail,1: Test pass"
|
|
bitfld.long 0x0 4. "ESSUT,Entropy Source Start-Up Test" "0: Entropy source is still under testing or test fail,1: Test pass"
|
|
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|
|
bitfld.long 0x0 1. "TRNGRDY,TRNG Ready Signal" "0: True random number generator is not ready,1: True random number generator is ready"
|
|
bitfld.long 0x0 0. "LDORDY,LDO Ready Signal" "0: LDO is not ready,1: LDO is ready"
|
|
line.long 0x4 "TRNG_DATA0,TRNG Data Output Word 0 Register"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,True Random Number Generator Data (Read Only)\nThe DATA stores the output data generated by TRNG it can be read when DVIF (TRNG_STS[31]) become 1 and can be read only once.\nTRNG_DATA0 stores Entropy / NRBG word 0 / DRBG word 0.\nTRNG_DATA1 stores.."
|
|
line.long 0x8 "TRNG_DATA1,TRNG Data Output Word 1 Register"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,True Random Number Generator Data (Read Only)\nThe DATA stores the output data generated by TRNG it can be read when DVIF (TRNG_STS[31]) become 1 and can be read only once.\nTRNG_DATA0 stores Entropy / NRBG word 0 / DRBG word 0.\nTRNG_DATA1 stores.."
|
|
line.long 0xC "TRNG_DATA2,TRNG Data Output Word 2 Register"
|
|
hexmask.long 0xC 0.--31. 1. "DATA,True Random Number Generator Data (Read Only)\nThe DATA stores the output data generated by TRNG it can be read when DVIF (TRNG_STS[31]) become 1 and can be read only once.\nTRNG_DATA0 stores Entropy / NRBG word 0 / DRBG word 0.\nTRNG_DATA1 stores.."
|
|
line.long 0x10 "TRNG_DATA3,TRNG Data Output Word 3 Register"
|
|
hexmask.long 0x10 0.--31. 1. "DATA,True Random Number Generator Data (Read Only)\nThe DATA stores the output data generated by TRNG it can be read when DVIF (TRNG_STS[31]) become 1 and can be read only once.\nTRNG_DATA0 stores Entropy / NRBG word 0 / DRBG word 0.\nTRNG_DATA1 stores.."
|
|
tree.end
|
|
tree "TTMR (Tick Timer Controller)"
|
|
base ad:0x400E5000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TTMR0_CTL,TTMR0 Control Register"
|
|
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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|
bitfld.long 0x0 30. "CNTEN,Tick Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TTMR_CLK period to become active user can read ACTSTS (TTMRx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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|
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bitfld.long 0x0 29. "INTEN,Tick Timer Interrupt Enable Bit\nNote: If this bit is enabled when the tick timer time-out interrupt flag TIF is set to 1 the tick timer interrupt signal is generated and inform to CPU." "0: Tick Timer time-out interrupt Disabled,1: Tick Timer time-out interrupt Enabled"
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|
bitfld.long 0x0 27.--28. "OPMODE,Tick Timer Counting Mode Select" "0: Tick timer controller is operated in One-shot mode,1: Tick timer controller is operated in Periodic mode,?,?"
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rbitfld.long 0x0 25. "ACTSTS,Tick Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may be active when CNT 0 is transitioned to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TTMRx_INTSTS[0]) is 1 and INTEN (TTMRx_CTL[29]) is enabled the tick timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
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|
bitfld.long 0x0 16. "PDCLKEN,Power-down Engine Clock Enable" "0: Disable engine clock in Power-down mode,1: Enable engine clock in Power-down mode"
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|
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|
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
|
|
line.long 0x4 "TTMR0_CMP,TTMR0 Comparator Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Tick Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TTMRx_INTSTS[0] Tick Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in.."
|
|
line.long 0x8 "TTMR0_INTSTS,TTMR0 Interrupt Status Register"
|
|
bitfld.long 0x8 1. "TWKF,Tick Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Tick Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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|
bitfld.long 0x8 0. "TIF,Tick Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Tick Timer while 24-bit timer up counter CNT (TTMRx_CNT[23:0]) value reaches to CMPDAT (TTMRx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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|
line.long 0xC "TTMR0_CNT,TTMR0 Data Register"
|
|
rbitfld.long 0xC 31. "RSTACT,Tick Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register tick timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale.." "0: Reset operation is done,1: Reset operation triggered by writing TTMRx_CNT.."
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|
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Tick Timer Data Register\nRead operation:\nRead this register to get CNT value. For example:\nWrite operation:\nWriting any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "TTMR0_TRGCTL,TTMR0 Trigger Control Register"
|
|
bitfld.long 0x0 4. "TRGLPPDMA,Trigger LPPDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered LPPDMA transfer." "0: Tick Timer interrupt trigger LPPDMA Disabled,1: Tick Timer interrupt trigger LPPDMA Enabled"
|
|
bitfld.long 0x0 1. "TRGEN,Trigger Low power IPs Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered Low Power IPs conversion." "0: Tick Timer interrupt trigger Low Power IPs..,1: Tick Timer interrupt trigger Low Power IPs Enabled"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "TTMR1_CTL,TTMR1 Control Register"
|
|
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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|
bitfld.long 0x0 30. "CNTEN,Tick Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TTMR_CLK period to become active user can read ACTSTS (TTMRx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
|
|
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bitfld.long 0x0 29. "INTEN,Tick Timer Interrupt Enable Bit\nNote: If this bit is enabled when the tick timer time-out interrupt flag TIF is set to 1 the tick timer interrupt signal is generated and inform to CPU." "0: Tick Timer time-out interrupt Disabled,1: Tick Timer time-out interrupt Enabled"
|
|
bitfld.long 0x0 27.--28. "OPMODE,Tick Timer Counting Mode Select" "0: Tick timer controller is operated in One-shot mode,1: Tick timer controller is operated in Periodic mode,?,?"
|
|
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|
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rbitfld.long 0x0 25. "ACTSTS,Tick Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may be active when CNT 0 is transitioned to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
|
|
bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TTMRx_INTSTS[0]) is 1 and INTEN (TTMRx_CTL[29]) is enabled the tick timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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|
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bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
|
|
bitfld.long 0x0 16. "PDCLKEN,Power-down Engine Clock Enable" "0: Disable engine clock in Power-down mode,1: Enable engine clock in Power-down mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
|
|
line.long 0x4 "TTMR1_CMP,TTMR1 Comparator Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Tick Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TTMRx_INTSTS[0] Tick Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in.."
|
|
line.long 0x8 "TTMR1_INTSTS,TTMR1 Interrupt Status Register"
|
|
bitfld.long 0x8 1. "TWKF,Tick Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Tick Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x8 0. "TIF,Tick Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Tick Timer while 24-bit timer up counter CNT (TTMRx_CNT[23:0]) value reaches to CMPDAT (TTMRx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
|
|
line.long 0xC "TTMR1_CNT,TTMR1 Data Register"
|
|
rbitfld.long 0xC 31. "RSTACT,Tick Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register tick timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale.." "0: Reset operation is done,1: Reset operation triggered by writing TTMRx_CNT.."
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|
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Tick Timer Data Register\nRead operation:\nRead this register to get CNT value. For example:\nWrite operation:\nWriting any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter."
|
|
group.long 0x11C++0x3
|
|
line.long 0x0 "TTMR1_TRGCTL,TTMR1 Trigger Control Register"
|
|
bitfld.long 0x0 4. "TRGLPPDMA,Trigger LPPDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered LPPDMA transfer." "0: Tick Timer interrupt trigger LPPDMA Disabled,1: Tick Timer interrupt trigger LPPDMA Enabled"
|
|
bitfld.long 0x0 1. "TRGEN,Trigger Low power IPs Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered Low Power IPs conversion." "0: Tick Timer interrupt trigger Low Power IPs..,1: Tick Timer interrupt trigger Low Power IPs Enabled"
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
tree "UART0"
|
|
base ad:0x40070000
|
|
group.long 0x0++0x4F
|
|
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
|
|
bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
|
|
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
|
|
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
|
|
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
|
|
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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|
bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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|
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]) Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
|
|
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
|
|
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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|
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|
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
|
|
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
|
|
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|
|
bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
|
|
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
|
|
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|
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
|
|
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
|
|
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|
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
|
|
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
|
|
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
|
|
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
|
|
bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 013 and Figure 014 for UART function mode.\nNote 2: Refer to Figure 015 and Figure 016 for RS-485 function mode.\nNote 3: Before setting.." "0: nRTS pin output is high level active,1: Refer to Figure 013 and Figure 014 for UART.."
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
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rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated."
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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line.long 0x20 "UART_TOUT,UART Time-out Register"
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bitfld.long 0x20 31. "BITOMEN,Bus Idle Time-out Mode Enable Bit\nIf BITOMEN (UART_TOUT[31]) is enabled the reset conditions of the time-out counter and RXTOIF (UART_INTSTS[4]) will be changed to detect the bus idle.\nWhen BITOMEN (UART_TOUT[31]) is disabled the time-out.." "0: Bus idle time-out mode Disabled,1: Bus idle time-out mode Enabled"
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hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
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hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x24 30. "BRFDEN,Baud Rate Fractional Divider Enable Bit\nNote: This bit has effect only at baud rate mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1)." "0: Baud Rate Fractional Divider Disabled,1: Baud Rate Fractional Divider Enabled"
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bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 04."
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hexmask.long.byte 0x24 16.--23. 1. "BRFD,Baud Rate Fractional Divider\nThis field is the fractional part of the baud rate divisor. \nWhen BRFDEN (UART_BAUD[30]) is set the Baud Rate Equation goes to UART_CLK / ((BRD+2) + (BRFD/256))."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 04."
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line.long 0x28 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. \nNote:.." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
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line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
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bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
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line.long 0x34 "UART_LINCTL,UART LIN Control Register"
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hexmask.long.byte 0x34 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID[29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote 1: User can fill any 8-bit value to this.."
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bitfld.long 0x34 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?"
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bitfld.long 0x34 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1-bit time,1: The LIN break/sync delimiter length is 2-bit time,?,?"
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hexmask.long.byte 0x34 16.--19. 1. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote 1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]). User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.."
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bitfld.long 0x34 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x34 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x34 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x34 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x34 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote 1: This bit is shadow bit of LINTXEN (UART_ALTCTL[7]);.." "0: Send LIN TX header Disabled,1: This bit is shadow bit of LINTXEN"
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bitfld.long 0x34 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in Error! Reference source not found. (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x34 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote 2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) \nNote 3: The control and interactions of this field are.." "0: UART_BAUD updated is written by software (if no..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x34 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote 2: When operation in Automatic Resynchronization mode the baud rate setting must be mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote 3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x34 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x34 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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line.long 0x38 "UART_LINSTS,UART LIN Status Register"
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bitfld.long 0x38 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set." "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x38 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x38 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header by.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x38 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x38 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' 'frame error in.." "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x38 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote 3: When enable ID parity check IDPEN (UART_LINCTL[9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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line.long 0x3C "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x3C 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x3C 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x40 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x40 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
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bitfld.long 0x40 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x40 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x40 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x40 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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line.long 0x44 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x44 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x44 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x44 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x44 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x44 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0x48 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x48 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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line.long 0x4C "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
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hexmask.long.word 0x4C 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
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tree.end
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tree "UART1"
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base ad:0x40071000
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group.long 0x0++0x4F
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]) Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 013 and Figure 014 for UART function mode.\nNote 2: Refer to Figure 015 and Figure 016 for RS-485 function mode.\nNote 3: Before setting.." "0: nRTS pin output is high level active,1: Refer to Figure 013 and Figure 014 for UART.."
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
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rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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line.long 0x20 "UART_TOUT,UART Time-out Register"
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bitfld.long 0x20 31. "BITOMEN,Bus Idle Time-out Mode Enable Bit\nIf BITOMEN (UART_TOUT[31]) is enabled the reset conditions of the time-out counter and RXTOIF (UART_INTSTS[4]) will be changed to detect the bus idle.\nWhen BITOMEN (UART_TOUT[31]) is disabled the time-out.." "0: Bus idle time-out mode Disabled,1: Bus idle time-out mode Enabled"
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hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
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hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x24 30. "BRFDEN,Baud Rate Fractional Divider Enable Bit\nNote: This bit has effect only at baud rate mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1)." "0: Baud Rate Fractional Divider Disabled,1: Baud Rate Fractional Divider Enabled"
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bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 04."
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hexmask.long.byte 0x24 16.--23. 1. "BRFD,Baud Rate Fractional Divider\nThis field is the fractional part of the baud rate divisor. \nWhen BRFDEN (UART_BAUD[30]) is set the Baud Rate Equation goes to UART_CLK / ((BRD+2) + (BRFD/256))."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 04."
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line.long 0x28 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. \nNote:.." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
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line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
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bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
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line.long 0x34 "UART_LINCTL,UART LIN Control Register"
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hexmask.long.byte 0x34 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID[29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote 1: User can fill any 8-bit value to this.."
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bitfld.long 0x34 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?"
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bitfld.long 0x34 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1-bit time,1: The LIN break/sync delimiter length is 2-bit time,?,?"
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hexmask.long.byte 0x34 16.--19. 1. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote 1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]). User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.."
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bitfld.long 0x34 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x34 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x34 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x34 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x34 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote 1: This bit is shadow bit of LINTXEN (UART_ALTCTL[7]);.." "0: Send LIN TX header Disabled,1: This bit is shadow bit of LINTXEN"
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bitfld.long 0x34 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in Error! Reference source not found. (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x34 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote 2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) \nNote 3: The control and interactions of this field are.." "0: UART_BAUD updated is written by software (if no..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x34 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote 2: When operation in Automatic Resynchronization mode the baud rate setting must be mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote 3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x34 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x34 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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line.long 0x38 "UART_LINSTS,UART LIN Status Register"
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bitfld.long 0x38 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set." "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x38 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x38 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header by.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x38 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x38 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' 'frame error in.." "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x38 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote 3: When enable ID parity check IDPEN (UART_LINCTL[9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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line.long 0x3C "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x3C 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x3C 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x40 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x40 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
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bitfld.long 0x40 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x40 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x40 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x40 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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line.long 0x44 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x44 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x44 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x44 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x44 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x44 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0x48 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x48 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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line.long 0x4C "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
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hexmask.long.word 0x4C 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
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tree.end
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tree "UART2"
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base ad:0x40072000
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group.long 0x0++0x33
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]) Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 013 and Figure 014 for UART function mode.\nNote 2: Refer to Figure 015 and Figure 016 for RS-485 function mode.\nNote 3: Before setting.." "0: nRTS pin output is high level active,1: Refer to Figure 013 and Figure 014 for UART.."
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
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rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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line.long 0x20 "UART_TOUT,UART Time-out Register"
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bitfld.long 0x20 31. "BITOMEN,Bus Idle Time-out Mode Enable Bit\nIf BITOMEN (UART_TOUT[31]) is enabled the reset conditions of the time-out counter and RXTOIF (UART_INTSTS[4]) will be changed to detect the bus idle.\nWhen BITOMEN (UART_TOUT[31]) is disabled the time-out.." "0: Bus idle time-out mode Disabled,1: Bus idle time-out mode Enabled"
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hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
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hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x24 30. "BRFDEN,Baud Rate Fractional Divider Enable Bit\nNote: This bit has effect only at baud rate mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1)." "0: Baud Rate Fractional Divider Disabled,1: Baud Rate Fractional Divider Enabled"
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bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 04."
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hexmask.long.byte 0x24 16.--23. 1. "BRFD,Baud Rate Fractional Divider\nThis field is the fractional part of the baud rate divisor. \nWhen BRFDEN (UART_BAUD[30]) is set the Baud Rate Equation goes to UART_CLK / ((BRD+2) + (BRFD/256))."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 04."
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line.long 0x28 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. \nNote:.." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
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line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
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bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
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group.long 0x3C++0x13
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line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
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bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
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hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
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tree.end
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tree "UART3"
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base ad:0x40073000
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group.long 0x0++0x33
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]) Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 013 and Figure 014 for UART function mode.\nNote 2: Refer to Figure 015 and Figure 016 for RS-485 function mode.\nNote 3: Before setting.." "0: nRTS pin output is high level active,1: Refer to Figure 013 and Figure 014 for UART.."
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
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rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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line.long 0x20 "UART_TOUT,UART Time-out Register"
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bitfld.long 0x20 31. "BITOMEN,Bus Idle Time-out Mode Enable Bit\nIf BITOMEN (UART_TOUT[31]) is enabled the reset conditions of the time-out counter and RXTOIF (UART_INTSTS[4]) will be changed to detect the bus idle.\nWhen BITOMEN (UART_TOUT[31]) is disabled the time-out.." "0: Bus idle time-out mode Disabled,1: Bus idle time-out mode Enabled"
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hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
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hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x24 30. "BRFDEN,Baud Rate Fractional Divider Enable Bit\nNote: This bit has effect only at baud rate mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1)." "0: Baud Rate Fractional Divider Disabled,1: Baud Rate Fractional Divider Enabled"
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bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 04."
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hexmask.long.byte 0x24 16.--23. 1. "BRFD,Baud Rate Fractional Divider\nThis field is the fractional part of the baud rate divisor. \nWhen BRFDEN (UART_BAUD[30]) is set the Baud Rate Equation goes to UART_CLK / ((BRD+2) + (BRFD/256))."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 04."
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line.long 0x28 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. \nNote:.." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
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line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
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bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
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group.long 0x3C++0x13
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line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
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bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
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hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
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tree.end
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tree "UART4"
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base ad:0x40074000
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group.long 0x0++0x33
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]) Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 013 and Figure 014 for UART function mode.\nNote 2: Refer to Figure 015 and Figure 016 for RS-485 function mode.\nNote 3: Before setting.." "0: nRTS pin output is high level active,1: Refer to Figure 013 and Figure 014 for UART.."
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
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rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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line.long 0x20 "UART_TOUT,UART Time-out Register"
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bitfld.long 0x20 31. "BITOMEN,Bus Idle Time-out Mode Enable Bit\nIf BITOMEN (UART_TOUT[31]) is enabled the reset conditions of the time-out counter and RXTOIF (UART_INTSTS[4]) will be changed to detect the bus idle.\nWhen BITOMEN (UART_TOUT[31]) is disabled the time-out.." "0: Bus idle time-out mode Disabled,1: Bus idle time-out mode Enabled"
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hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
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hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x24 30. "BRFDEN,Baud Rate Fractional Divider Enable Bit\nNote: This bit has effect only at baud rate mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1)." "0: Baud Rate Fractional Divider Disabled,1: Baud Rate Fractional Divider Enabled"
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bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 04."
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hexmask.long.byte 0x24 16.--23. 1. "BRFD,Baud Rate Fractional Divider\nThis field is the fractional part of the baud rate divisor. \nWhen BRFDEN (UART_BAUD[30]) is set the Baud Rate Equation goes to UART_CLK / ((BRD+2) + (BRFD/256))."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 04."
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line.long 0x28 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. \nNote:.." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
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line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
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bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
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group.long 0x3C++0x13
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line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
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bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
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hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
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tree.end
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tree "UART5"
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base ad:0x40075000
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group.long 0x0++0x33
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]) Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 013 and Figure 014 for UART function mode.\nNote 2: Refer to Figure 015 and Figure 016 for RS-485 function mode.\nNote 3: Before setting.." "0: nRTS pin output is high level active,1: Refer to Figure 013 and Figure 014 for UART.."
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
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rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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line.long 0x20 "UART_TOUT,UART Time-out Register"
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bitfld.long 0x20 31. "BITOMEN,Bus Idle Time-out Mode Enable Bit\nIf BITOMEN (UART_TOUT[31]) is enabled the reset conditions of the time-out counter and RXTOIF (UART_INTSTS[4]) will be changed to detect the bus idle.\nWhen BITOMEN (UART_TOUT[31]) is disabled the time-out.." "0: Bus idle time-out mode Disabled,1: Bus idle time-out mode Enabled"
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hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
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hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x24 30. "BRFDEN,Baud Rate Fractional Divider Enable Bit\nNote: This bit has effect only at baud rate mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1)." "0: Baud Rate Fractional Divider Disabled,1: Baud Rate Fractional Divider Enabled"
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bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 04."
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hexmask.long.byte 0x24 16.--23. 1. "BRFD,Baud Rate Fractional Divider\nThis field is the fractional part of the baud rate divisor. \nWhen BRFDEN (UART_BAUD[30]) is set the Baud Rate Equation goes to UART_CLK / ((BRD+2) + (BRFD/256))."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 04."
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line.long 0x28 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. \nNote:.." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
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line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
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bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
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group.long 0x3C++0x13
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line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
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bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
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hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
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tree.end
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tree "UART6"
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base ad:0x40076000
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group.long 0x0++0x33
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]) Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 013 and Figure 014 for UART function mode.\nNote 2: Refer to Figure 015 and Figure 016 for RS-485 function mode.\nNote 3: Before setting.." "0: nRTS pin output is high level active,1: Refer to Figure 013 and Figure 014 for UART.."
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
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rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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line.long 0x20 "UART_TOUT,UART Time-out Register"
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bitfld.long 0x20 31. "BITOMEN,Bus Idle Time-out Mode Enable Bit\nIf BITOMEN (UART_TOUT[31]) is enabled the reset conditions of the time-out counter and RXTOIF (UART_INTSTS[4]) will be changed to detect the bus idle.\nWhen BITOMEN (UART_TOUT[31]) is disabled the time-out.." "0: Bus idle time-out mode Disabled,1: Bus idle time-out mode Enabled"
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hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
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hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x24 30. "BRFDEN,Baud Rate Fractional Divider Enable Bit\nNote: This bit has effect only at baud rate mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1)." "0: Baud Rate Fractional Divider Disabled,1: Baud Rate Fractional Divider Enabled"
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bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 04."
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hexmask.long.byte 0x24 16.--23. 1. "BRFD,Baud Rate Fractional Divider\nThis field is the fractional part of the baud rate divisor. \nWhen BRFDEN (UART_BAUD[30]) is set the Baud Rate Equation goes to UART_CLK / ((BRD+2) + (BRFD/256))."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 04."
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line.long 0x28 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. \nNote:.." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
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line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
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bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
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group.long 0x3C++0x13
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line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
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bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
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hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
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tree.end
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tree "UART7"
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base ad:0x40077000
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group.long 0x0++0x33
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]) Frame Error Flag.." "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the PARITY bit is transmitted and checked.." "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data." "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 013 and Figure 014 for UART function mode.\nNote 2: Refer to Figure 015 and Figure 016 for RS-485 function mode.\nNote 3: Before setting.." "0: nRTS pin output is high level active,1: Refer to Figure 013 and Figure 014 for UART.."
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bitfld.long 0x10 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x1C "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x1C 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x1C 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x1C 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x1C 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x1C 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x1C 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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rbitfld.long 0x1C 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x1C 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x1C 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
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rbitfld.long 0x1C 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x1C 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x1C 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x1C 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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rbitfld.long 0x1C 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x1C 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x1C 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled the RDA interrupt will be generated.\nNote: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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line.long 0x20 "UART_TOUT,UART Time-out Register"
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bitfld.long 0x20 31. "BITOMEN,Bus Idle Time-out Mode Enable Bit\nIf BITOMEN (UART_TOUT[31]) is enabled the reset conditions of the time-out counter and RXTOIF (UART_INTSTS[4]) will be changed to detect the bus idle.\nWhen BITOMEN (UART_TOUT[31]) is disabled the time-out.." "0: Bus idle time-out mode Disabled,1: Bus idle time-out mode Enabled"
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hexmask.long.byte 0x20 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time."
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hexmask.long.byte 0x20 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x24 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x24 30. "BRFDEN,Baud Rate Fractional Divider Enable Bit\nNote: This bit has effect only at baud rate mode 2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1)." "0: Baud Rate Fractional Divider Disabled,1: Baud Rate Fractional Divider Enabled"
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bitfld.long 0x24 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x24 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 04."
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hexmask.long.byte 0x24 16.--23. 1. "BRFD,Baud Rate Fractional Divider\nThis field is the fractional part of the baud rate divisor. \nWhen BRFDEN (UART_BAUD[30]) is set the Baud Rate Equation goes to UART_CLK / ((BRD+2) + (BRFD/256))."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 04."
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line.long 0x28 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x28 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x28 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x28 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0x2C "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x2C 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0x2C 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,?,?"
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bitfld.long 0x2C 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x2C 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. \nNote:.." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x2C 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x2C 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0x2C 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x2C 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote 1: This break field length is BRKFL + 1."
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line.long 0x30 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x30 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
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bitfld.long 0x30 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x30 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x30 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,?,?,?,?,?,?"
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group.long 0x3C++0x13
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line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote 1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote 2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: When the system is in Power-down mode"
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bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\nNote 1: When the system is in Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function.." "0: RS-485 Address Match (AAD mode) wake-up system..,1: When the system is in Power-down mode"
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode." "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0xC 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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line.long 0x10 "UART_RS485DD,UART RS485 Transceiver Deactivate Delay Register"
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hexmask.long.word 0x10 0.--15. 1. "RTSDDLY,RS485 Transceiver Deactivate Delay Value\nThese bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state."
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tree.end
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tree.end
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tree "USBD (USB 2.0 Full-Speed Device Controller)"
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base ad:0x400C0000
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group.long 0x0++0xB
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line.long 0x0 "USBD_INTEN,USB Device Interrupt Enable Register"
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bitfld.long 0x0 15. "INNAKEN,Active NAK Function and Its Status in IN Token" "0: When device responds NAK after receiving IN..,1: IN NAK status will be updated to USBD_EPSTS0 and.."
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bitfld.long 0x0 8. "WKEN,Wake-up Function Enable Bit" "0: USB wake-up function Disabled,1: USB wake-up function Enabled"
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bitfld.long 0x0 4. "SOFIEN,Start of Frame Interrupt Enable Bit" "0: SOF Interrupt Disabled,1: SOF Interrupt Enabled"
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bitfld.long 0x0 3. "NEVWKIEN,USB No-event-wake-up Interrupt Enable Bit" "0: No-event-wake-up Interrupt Disabled,1: No-event-wake-up Interrupt Enabled"
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bitfld.long 0x0 2. "VBDETIEN,VBUS Detection Interrupt Enable Bit" "0: VBUS detection Interrupt Disabled,1: VBUS detection Interrupt Enabled"
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bitfld.long 0x0 1. "USBIEN,USB Event Interrupt Enable Bit" "0: USB event interrupt Disabled,1: USB event interrupt Enabled"
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bitfld.long 0x0 0. "BUSIEN,Bus Event Interrupt Enable Bit" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled"
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line.long 0x4 "USBD_INTSTS,USB Device Interrupt Event Status Register"
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bitfld.long 0x4 31. "SETUP,Setup Event Status" "0: No Setup event,1: Setup event occurred cleared by writing 1 to.."
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bitfld.long 0x4 27. "EPEVT11,Endpoint 11's USB Event Status" "0: No event occurred in endpoint 11,1: USB event occurred on Endpoint 11. Check.."
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bitfld.long 0x4 26. "EPEVT10,Endpoint 10's USB Event Status" "0: No event occurred in endpoint 10,1: USB event occurred on Endpoint 10. Check.."
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bitfld.long 0x4 25. "EPEVT9,Endpoint 9's USB Event Status" "0: No event occurred in endpoint 9,1: USB event occurred on Endpoint 9. Check.."
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bitfld.long 0x4 24. "EPEVT8,Endpoint 8's USB Event Status" "0: No event occurred in endpoint 8,1: USB event occurred on Endpoint 8. Check.."
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bitfld.long 0x4 23. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred in endpoint 7,1: USB event occurred on Endpoint 7. Check.."
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bitfld.long 0x4 22. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred in endpoint 6,1: USB event occurred on Endpoint 6. Check.."
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bitfld.long 0x4 21. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5. Check.."
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bitfld.long 0x4 20. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4. Check.."
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bitfld.long 0x4 19. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3. Check.."
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bitfld.long 0x4 18. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2. Check.."
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bitfld.long 0x4 17. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1. Check.."
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bitfld.long 0x4 16. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0. Check.."
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bitfld.long 0x4 4. "SOFIF,Start of Frame Interrupt Status" "0: SOF event did not occur,1: SOF event occurred cleared by writing 1 to.."
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bitfld.long 0x4 3. "NEVWKIF,No-event-wake-up Interrupt Status" "0: NEVWK event did not occur,1: No-event-wake-up event occurred cleared by.."
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bitfld.long 0x4 2. "VBDETIF,VBUS Detection Interrupt Status" "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB bus.."
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bitfld.long 0x4 1. "USBIF,USB Event Interrupt Status\nThe USB event includes the SETUP Token IN Token OUT ACK ISO IN or ISO OUT events in the bus." "0: No USB event occurred,1: USB event occurred. Check EPSTS0~25 in.."
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bitfld.long 0x4 0. "BUSIF,BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus." "0: No BUS event occurred,1: Bus event occurred; check USBD_ATTR[3:0] to know.."
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line.long 0x8 "USBD_FADDR,USB Device Function Address Register"
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hexmask.long.byte 0x8 0.--6. 1. "FADDR,USB device function address"
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rgroup.long 0xC++0x3
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line.long 0x0 "USBD_EPSTS,USB Device Endpoint Status Register"
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bitfld.long 0x0 7. "OV,Overrun\nIt indicates that the received data is over the maximum payload number or not." "0: No overrun,1: Out Data is more than the Max Payload in MXPLD.."
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group.long 0x10++0x3
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line.long 0x0 "USBD_ATTR,USB Device Bus Status and Attribution Register"
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rbitfld.long 0x0 13. "L1RESUME,LPM L1 Resume (Read Only)" "0: Bus no LPM L1 state resume,1: LPM L1 state resume from LPM L1 state suspend"
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rbitfld.long 0x0 12. "L1SUSPEND,LPM L1 Suspend (Read Only)" "0: Bus no L1 state suspend,1: This bit is set by the hardware when LPM command.."
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bitfld.long 0x0 11. "LPMACK,LPM Token Acknowledge Enable Bit" "0: The valid LPM Token will be NYET,1: The valid LPM Token will be ACK"
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bitfld.long 0x0 10. "BYTEM,CPU Access USB SRAM Size Mode Selection" "0: Word mode: The size of the transfer from CPU to..,1: Byte mode: The size of the transfer from CPU to.."
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bitfld.long 0x0 9. "PWRDN,Power-down PHY Transceiver Low Active" "0: Power-down related circuit of PHY transceiver,1: Turn-on related circuit of PHY transceiver"
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bitfld.long 0x0 8. "DPPUEN,Pull-up Resistor on USB_DP Enable Bit" "0: Pull-up resistor in USB_D+ bus Disabled,1: Pull-up resistor in USB_D+ bus Active"
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bitfld.long 0x0 7. "USBEN,USB Controller Enable Bit" "0: USB Controller Disabled,1: USB Controller Enabled"
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bitfld.long 0x0 5. "RWAKEUP,Remote Wake-up" "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low USB_D- high).."
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bitfld.long 0x0 4. "PHYEN,PHY Transceiver Function Enable Bit" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled"
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rbitfld.long 0x0 3. "TOUT,Time-out Status (Read Only)" "0: No time-out,1: No Bus response more than 18 bits time"
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rbitfld.long 0x0 2. "RESUME,Resume Status (Read Only)" "0: No bus resume,1: Resume from suspend"
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rbitfld.long 0x0 1. "SUSPEND,Suspend Status (Read Only)" "0: Bus no suspend,1: Bus idle more than 3ms either cable is.."
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rbitfld.long 0x0 0. "USBRST,USB Reset Status (Read Only)" "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) more than.."
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rgroup.long 0x14++0x3
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line.long 0x0 "USBD_VBUSDET,USB Device VBUS Detection Register"
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bitfld.long 0x0 0. "VBUSDET,Device VBUS Detection" "0: Controller is not attached to the USB host,1: Controller is attached to the USB host"
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group.long 0x18++0x3
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line.long 0x0 "USBD_STBUFSEG,SETUP Token Buffer Segmentation Register"
|
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hexmask.long.byte 0x0 3.--10. 1. "STBUFSEG,SETUP Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address. The effective starting address is\nUSBD_SRAM address + {STBUFSEG 3'b000} \nNote: It is used for SETUP.."
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rgroup.long 0x20++0xB
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line.long 0x0 "USBD_EPSTS0,USB Device Endpoint Status Register 0"
|
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hexmask.long.byte 0x0 28.--31. 1. "EPSTS7,Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint."
|
|
hexmask.long.byte 0x0 24.--27. 1. "EPSTS6,Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x0 20.--23. 1. "EPSTS5,Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint."
|
|
line.long 0x4 "USBD_EPSTS1,USB Device Endpoint Status Register 1"
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hexmask.long.byte 0x4 28.--31. 1. "EPSTS15,Endpoint 15 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x4 24.--27. 1. "EPSTS14,Endpoint 14 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x4 20.--23. 1. "EPSTS13,Endpoint 13 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x4 16.--19. 1. "EPSTS12,Endpoint 12 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x4 12.--15. 1. "EPSTS11,Endpoint 11 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x4 8.--11. 1. "EPSTS10,Endpoint 10 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x4 4.--7. 1. "EPSTS9,Endpoint 9 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x4 0.--3. 1. "EPSTS8,Endpoint 8 Status\nThese bits are used to indicate the current status of this endpoint."
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line.long 0x8 "USBD_EPSTS2,USB Device Endpoint Status Register 2"
|
|
hexmask.long.byte 0x8 8.--11. 1. "EPSTS18,Endpoint 18 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x8 4.--7. 1. "EPSTS17,Endpoint 17 Status\nThese bits are used to indicate the current status of this endpoint."
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hexmask.long.byte 0x8 0.--3. 1. "EPSTS16,Endpoint 16 Status\nThese bits are used to indicate the current status of this endpoint."
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|
group.long 0x30++0x3
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line.long 0x0 "USBD_EPINTSTS,USB Device Endpoint Interrupt Event Status Register"
|
|
bitfld.long 0x0 18. "EPEVT18,Endpoint 18's USB Event Status" "0: No event occurred in endpoint 18,1: USB event occurred on Endpoint 18. Check.."
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bitfld.long 0x0 17. "EPEVT17,Endpoint 17's USB Event Status" "0: No event occurred in endpoint 17,1: USB event occurred on Endpoint 17. Check.."
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bitfld.long 0x0 16. "EPEVT16,Endpoint 16's USB Event Status" "0: No event occurred in endpoint 16,1: USB event occurred on Endpoint 16. Check.."
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bitfld.long 0x0 15. "EPEVT15,Endpoint 15's USB Event Status" "0: No event occurred in endpoint 15,1: USB event occurred on Endpoint 15. Check.."
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|
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bitfld.long 0x0 14. "EPEVT14,Endpoint 14's USB Event Status" "0: No event occurred in endpoint 14,1: USB event occurred on Endpoint 14. Check.."
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bitfld.long 0x0 13. "EPEVT13,Endpoint 13's USB Event Status" "0: No event occurred in endpoint 13,1: USB event occurred on Endpoint 13. Check.."
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|
newline
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bitfld.long 0x0 12. "EPEVT12,Endpoint 12's USB Event Status" "0: No event occurred in endpoint 12,1: USB event occurred on Endpoint 12. Check.."
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|
bitfld.long 0x0 11. "EPEVT11,Endpoint 11's USB Event Status" "0: No event occurred in endpoint 11,1: USB event occurred on Endpoint 11. Check.."
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|
newline
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bitfld.long 0x0 10. "EPEVT10,Endpoint 10's USB Event Status" "0: No event occurred in endpoint 10,1: USB event occurred on Endpoint 10. Check.."
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bitfld.long 0x0 9. "EPEVT9,Endpoint 9's USB Event Status" "0: No event occurred in endpoint 9,1: USB event occurred on Endpoint 9. Check.."
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|
newline
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bitfld.long 0x0 8. "EPEVT8,Endpoint 8's USB Event Status" "0: No event occurred in endpoint 8,1: USB event occurred on Endpoint 8. Check.."
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bitfld.long 0x0 7. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred in endpoint 7,1: USB event occurred on Endpoint 7. Check.."
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bitfld.long 0x0 6. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred in endpoint 6,1: USB event occurred on Endpoint 6. Check.."
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bitfld.long 0x0 5. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5. Check.."
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bitfld.long 0x0 4. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4. Check.."
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bitfld.long 0x0 3. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3. Check.."
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|
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bitfld.long 0x0 2. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2. Check.."
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|
bitfld.long 0x0 1. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1. Check.."
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newline
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bitfld.long 0x0 0. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0. Check.."
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|
rgroup.long 0x88++0x7
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line.long 0x0 "USBD_LPMATTR,USB LPM Attribution Register"
|
|
bitfld.long 0x0 8. "LPMRWAKUP,LPM Remote Wakeup\nThis bit contains the bRemoteWake value received with last ACK LPM Token" "0,1"
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|
hexmask.long.byte 0x0 4.--7. 1. "LPMBESL,LPM Best Effort Service Latency\nThese bits contain the BESL value received with last ACK LPM Token"
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hexmask.long.byte 0x0 0.--3. 1. "LPMLINKSTS,LPM Link State\nThese bits contain the bLinkState received with last ACK LPM Token"
|
|
line.long 0x4 "USBD_FN,USB Frame Number Register"
|
|
hexmask.long.word 0x4 0.--10. 1. "FN,Frame Number\nThese bits contain the 11-bits frame number in the last received SOF packet."
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "USBD_SE0,USB Device Drive SE0 Control Register"
|
|
bitfld.long 0x0 0. "SE0,Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low." "0: Normal operation,1: Force USB PHY transceiver to drive SE0"
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|
group.long 0x500++0x12F
|
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line.long 0x0 "USBD_BUFSEG0,Endpoint 0 Buffer Segmentation Register"
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|
hexmask.long.byte 0x0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0x4 "USBD_MXPLD0,Endpoint 0 Maximal Payload Register"
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hexmask.long.word 0x4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x8 "USBD_CFG0,Endpoint 0 Configuration Register"
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bitfld.long 0x8 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0x8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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newline
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bitfld.long 0x8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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|
bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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|
line.long 0xC "USBD_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0xC 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0xC 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0x10 "USBD_BUFSEG1,Endpoint 1 Buffer Segmentation Register"
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hexmask.long.byte 0x10 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0x14 "USBD_MXPLD1,Endpoint 1 Maximal Payload Register"
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hexmask.long.word 0x14 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x18 "USBD_CFG1,Endpoint 1 Configuration Register"
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|
bitfld.long 0x18 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0x18 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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newline
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bitfld.long 0x18 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
|
|
bitfld.long 0x18 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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|
newline
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bitfld.long 0x18 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x18 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x18 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0x1C "USBD_CFGP1,Endpoint 1 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x1C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x1C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0x20 "USBD_BUFSEG2,Endpoint 2 Buffer Segmentation Register"
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hexmask.long.byte 0x20 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0x24 "USBD_MXPLD2,Endpoint 2 Maximal Payload Register"
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hexmask.long.word 0x24 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x28 "USBD_CFG2,Endpoint 2 Configuration Register"
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bitfld.long 0x28 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0x28 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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newline
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bitfld.long 0x28 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
|
|
bitfld.long 0x28 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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newline
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bitfld.long 0x28 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x28 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x28 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0x2C "USBD_CFGP2,Endpoint 2 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x2C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x2C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0x30 "USBD_BUFSEG3,Endpoint 3 Buffer Segmentation Register"
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hexmask.long.byte 0x30 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0x34 "USBD_MXPLD3,Endpoint 3 Maximal Payload Register"
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hexmask.long.word 0x34 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x38 "USBD_CFG3,Endpoint 3 Configuration Register"
|
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bitfld.long 0x38 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
|
|
bitfld.long 0x38 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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newline
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bitfld.long 0x38 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
|
|
bitfld.long 0x38 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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newline
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bitfld.long 0x38 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
|
|
bitfld.long 0x38 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x38 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
|
|
line.long 0x3C "USBD_CFGP3,Endpoint 3 Set Stall and Clear In/Out Ready Control Register"
|
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bitfld.long 0x3C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
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bitfld.long 0x3C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0x40 "USBD_BUFSEG4,Endpoint 4 Buffer Segmentation Register"
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hexmask.long.byte 0x40 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0x44 "USBD_MXPLD4,Endpoint 4 Maximal Payload Register"
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hexmask.long.word 0x44 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x48 "USBD_CFG4,Endpoint 4 Configuration Register"
|
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bitfld.long 0x48 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
|
|
bitfld.long 0x48 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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newline
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bitfld.long 0x48 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
|
|
bitfld.long 0x48 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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newline
|
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bitfld.long 0x48 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
|
|
bitfld.long 0x48 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x48 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
|
|
line.long 0x4C "USBD_CFGP4,Endpoint 4 Set Stall and Clear In/Out Ready Control Register"
|
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bitfld.long 0x4C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x4C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0x50 "USBD_BUFSEG5,Endpoint 5 Buffer Segmentation Register"
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hexmask.long.byte 0x50 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0x54 "USBD_MXPLD5,Endpoint 5 Maximal Payload Register"
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hexmask.long.word 0x54 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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|
line.long 0x58 "USBD_CFG5,Endpoint 5 Configuration Register"
|
|
bitfld.long 0x58 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
|
|
bitfld.long 0x58 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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|
newline
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bitfld.long 0x58 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
|
|
bitfld.long 0x58 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
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bitfld.long 0x58 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
|
|
bitfld.long 0x58 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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|
newline
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hexmask.long.byte 0x58 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
|
|
line.long 0x5C "USBD_CFGP5,Endpoint 5 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x5C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x5C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
|
|
line.long 0x60 "USBD_BUFSEG6,Endpoint 6 Buffer Segmentation Register"
|
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hexmask.long.byte 0x60 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
|
|
line.long 0x64 "USBD_MXPLD6,Endpoint 6 Maximal Payload Register"
|
|
hexmask.long.word 0x64 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
|
|
line.long 0x68 "USBD_CFG6,Endpoint 6 Configuration Register"
|
|
bitfld.long 0x68 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
|
|
bitfld.long 0x68 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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|
newline
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bitfld.long 0x68 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
|
|
bitfld.long 0x68 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
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bitfld.long 0x68 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
|
|
bitfld.long 0x68 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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|
newline
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hexmask.long.byte 0x68 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
|
|
line.long 0x6C "USBD_CFGP6,Endpoint 6 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x6C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x6C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
|
|
line.long 0x70 "USBD_BUFSEG7,Endpoint 7 Buffer Segmentation Register"
|
|
hexmask.long.byte 0x70 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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|
line.long 0x74 "USBD_MXPLD7,Endpoint 7 Maximal Payload Register"
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hexmask.long.word 0x74 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x78 "USBD_CFG7,Endpoint 7 Configuration Register"
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bitfld.long 0x78 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0x78 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x78 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x78 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x78 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x78 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x78 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0x7C "USBD_CFGP7,Endpoint 7 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x7C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x7C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0x80 "USBD_BUFSEG8,Endpoint 8 Buffer Segmentation Register"
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hexmask.long.byte 0x80 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0x84 "USBD_MXPLD8,Endpoint 8 Maximal Payload Register"
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hexmask.long.word 0x84 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x88 "USBD_CFG8,Endpoint 8 Configuration Register"
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bitfld.long 0x88 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0x88 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x88 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x88 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x88 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x88 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x88 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0x8C "USBD_CFGP8,Endpoint 8 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x8C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x8C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0x90 "USBD_BUFSEG9,Endpoint 9 Buffer Segmentation Register"
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hexmask.long.byte 0x90 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0x94 "USBD_MXPLD9,Endpoint 9 Maximal Payload Register"
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hexmask.long.word 0x94 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x98 "USBD_CFG9,Endpoint 9 Configuration Register"
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bitfld.long 0x98 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0x98 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x98 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x98 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x98 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x98 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x98 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0x9C "USBD_CFGP9,Endpoint 9 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x9C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x9C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0xA0 "USBD_BUFSEG10,Endpoint 10 Buffer Segmentation Register"
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hexmask.long.byte 0xA0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0xA4 "USBD_MXPLD10,Endpoint 10 Maximal Payload Register"
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hexmask.long.word 0xA4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0xA8 "USBD_CFG10,Endpoint 10 Configuration Register"
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bitfld.long 0xA8 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0xA8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xA8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0xA8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xA8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0xA8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xA8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0xAC "USBD_CFGP10,Endpoint 10 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0xAC 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0xAC 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0xB0 "USBD_BUFSEG11,Endpoint 11 Buffer Segmentation Register"
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hexmask.long.byte 0xB0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0xB4 "USBD_MXPLD11,Endpoint 11 Maximal Payload Register"
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hexmask.long.word 0xB4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0xB8 "USBD_CFG11,Endpoint 11 Configuration Register"
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bitfld.long 0xB8 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0xB8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xB8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0xB8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xB8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0xB8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xB8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0xBC "USBD_CFGP11,Endpoint 11 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0xBC 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0xBC 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0xC0 "USBD_BUFSEG12,Endpoint 12 Buffer Segmentation Register"
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hexmask.long.byte 0xC0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0xC4 "USBD_MXPLD12,Endpoint 12 Maximal Payload Register"
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hexmask.long.word 0xC4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0xC8 "USBD_CFG12,Endpoint 12 Configuration Register"
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bitfld.long 0xC8 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0xC8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xC8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0xC8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xC8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0xC8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xC8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0xCC "USBD_CFGP12,Endpoint 12 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0xCC 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0xCC 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0xD0 "USBD_BUFSEG13,Endpoint 13 Buffer Segmentation Register"
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hexmask.long.byte 0xD0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0xD4 "USBD_MXPLD13,Endpoint 13 Maximal Payload Register"
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hexmask.long.word 0xD4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0xD8 "USBD_CFG13,Endpoint 13 Configuration Register"
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bitfld.long 0xD8 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0xD8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xD8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0xD8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xD8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0xD8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xD8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0xDC "USBD_CFGP13,Endpoint 13 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0xDC 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0xDC 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0xE0 "USBD_BUFSEG14,Endpoint 14 Buffer Segmentation Register"
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hexmask.long.byte 0xE0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0xE4 "USBD_MXPLD14,Endpoint 14 Maximal Payload Register"
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hexmask.long.word 0xE4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0xE8 "USBD_CFG14,Endpoint 14 Configuration Register"
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bitfld.long 0xE8 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0xE8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xE8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0xE8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xE8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0xE8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xE8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0xEC "USBD_CFGP14,Endpoint 14 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0xEC 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0xEC 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0xF0 "USBD_BUFSEG15,Endpoint 15 Buffer Segmentation Register"
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hexmask.long.byte 0xF0 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0xF4 "USBD_MXPLD15,Endpoint 15 Maximal Payload Register"
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hexmask.long.word 0xF4 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0xF8 "USBD_CFG15,Endpoint 15 Configuration Register"
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bitfld.long 0xF8 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0xF8 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0xF8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0xF8 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0xF8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0xF8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0xF8 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0xFC "USBD_CFGP15,Endpoint 15 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0xFC 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0xFC 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0x100 "USBD_BUFSEG16,Endpoint 16 Buffer Segmentation Register"
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hexmask.long.byte 0x100 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0x104 "USBD_MXPLD16,Endpoint 16 Maximal Payload Register"
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hexmask.long.word 0x104 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x108 "USBD_CFG16,Endpoint 16 Configuration Register"
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bitfld.long 0x108 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0x108 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x108 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x108 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x108 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x108 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x108 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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line.long 0x10C "USBD_CFGP16,Endpoint 16 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x10C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x10C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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line.long 0x110 "USBD_BUFSEG17,Endpoint 17 Buffer Segmentation Register"
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hexmask.long.byte 0x110 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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line.long 0x114 "USBD_MXPLD17,Endpoint 17 Maximal Payload Register"
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hexmask.long.word 0x114 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x118 "USBD_CFG17,Endpoint 17 Configuration Register"
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bitfld.long 0x118 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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bitfld.long 0x118 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x118 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
|
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bitfld.long 0x118 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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|
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bitfld.long 0x118 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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|
bitfld.long 0x118 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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|
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hexmask.long.byte 0x118 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
|
|
line.long 0x11C "USBD_CFGP17,Endpoint 17 Set Stall and Clear In/Out Ready Control Register"
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|
bitfld.long 0x11C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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|
bitfld.long 0x11C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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|
line.long 0x120 "USBD_BUFSEG18,Endpoint 18 Buffer Segmentation Register"
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|
hexmask.long.byte 0x120 3.--10. 1. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG 3'b000}\nRefer to the section 0 for the.."
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|
line.long 0x124 "USBD_MXPLD18,Endpoint 18 Maximal Payload Register"
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|
hexmask.long.word 0x124 0.--10. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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|
line.long 0x128 "USBD_CFG18,Endpoint 18 Configuration Register"
|
|
bitfld.long 0x128 11. "DBEN,Double Buffer Enable Bit" "0: Single buffer mode,1: Double buffer mode"
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|
bitfld.long 0x128 10. "DBTGACTIVE,Double Buffer Toggle Active Bit" "0: Inactive in double buffer mode,1: Active in double buffer mode"
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bitfld.long 0x128 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
|
|
bitfld.long 0x128 7. "DSQSYNC,Data Sequence Synchronization" "0: DATA0 PID,1: DATA1 PID"
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newline
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bitfld.long 0x128 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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|
bitfld.long 0x128 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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|
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hexmask.long.byte 0x128 0.--3. 1. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint."
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|
line.long 0x12C "USBD_CFGP18,Endpoint 18 Set Stall and Clear In/Out Ready Control Register"
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|
bitfld.long 0x12C 1. "SSTALL,Set STALL Bit" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x12C 0. "CLRRDY,Clear Ready Bit\nWhen the USBD_MXPLD0~18 register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable.." "0,1"
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tree.end
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|
tree "USBH (USB 1.1 Host Controller)"
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base ad:0x40009000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "HcRevision,Host Controller Revision Register"
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hexmask.long.byte 0x0 0.--7. 1. "REV,Revision Number\nIndicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.1 specification."
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group.long 0x4++0x33
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line.long 0x0 "HcControl,Host Controller Control Register"
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bitfld.long 0x0 6.--7. "HCFS,Host Controller Functional State\nThis field sets the Host Controller state. The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port. States are:" "0: USBRESET,1: USBRESUME,?,?"
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bitfld.long 0x0 5. "BLE,Bulk List Enable Bit" "0: Processing of the Bulk list after next SOF..,1: Processing of the Bulk list in the next frame.."
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bitfld.long 0x0 4. "CLE,Control List Enable Bit" "0: Processing of the Control list after next SOF..,1: Processing of the Control list in the next frame.."
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bitfld.long 0x0 3. "IE,Isochronous List Enable Bit\nBoth IE and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list. Either IE or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list." "0: Processing of the Isochronous list after next..,1: Processing of the Isochronous list in the next.."
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bitfld.long 0x0 2. "PLE,Periodic List Enable Bit\nWhen set this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame.\nNote: To enable the processing of the.." "0: Processing of the Periodic (Interrupt and..,1: Processing of the Periodic (Interrupt and.."
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bitfld.long 0x0 0.--1. "CBSR,Control Bulk Service Ratio\nThis specifies the service ratio between Control and Bulk EDs. Before processing any of the non-periodic lists HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been.." "0: Number of Control EDs over Bulk EDs served is 1:1,1: Number of Control EDs over Bulk EDs served is 2:1,?,?"
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line.long 0x4 "HcCommandStatus,Host Controller Command Status Register"
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rbitfld.long 0x4 16.--17. "SOC,Schedule Overrun Count (Read Only)\nThese bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has.." "0,1,2,3"
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bitfld.long 0x4 2. "BLF,Bulk List Filled\nSet high to indicate there is an active TD on the Bulk list. This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list." "0: No active TD found or Host Controller begins to..,1: An active TD added or found on the Bulk list"
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bitfld.long 0x4 1. "CLF,Control List Filled\nSet high to indicate there is an active TD on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List." "0: No active TD found or Host Controller begins to..,1: An active TD added or found on the Control list"
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bitfld.long 0x4 0. "HCR,Host Controller Reset\nThis bit is set to initiate the software reset of Host Controller. This bit is cleared by the Host Controller upon completed of the reset operation.\nThis bit when set didn't reset the Root Hub and no subsequent reset.." "0: Host Controller is not in software reset state,1: Host Controller is in software reset state"
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line.long 0x8 "HcInterruptStatus,Host Controller Interrupt Status Register"
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bitfld.long 0x8 6. "RHSC,Root Hub Status Change\nThis bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed.\nNote: This bit is cleared by writing '1Fh' to HcRhPortStatus1[20:16]." "0: The content of HcRhStatus and the content of..,1: The content of HcRhStatus or the content of.."
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bitfld.long 0x8 5. "FNO,Frame Number Overflow\nThis bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.\nNote: This bit is cleared by writing 1 to it." "0: The bit 15 of Frame Number didn't change,1: The bit 15 of Frame Number changes from 1 to 0.."
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bitfld.long 0x8 3. "RD,Resume Detected\nSet when Host Controller detects resume signaling on a downstream port.\nNote: This bit is cleared by writing 1 to it." "0: No resume signaling detected on a downstream port,1: Resume signaling detected on a downstream port"
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bitfld.long 0x8 2. "SF,Start of Frame\nSet when the Frame Management functional block signals a 'Start of Frame' event. Host Control generates a SOF token at the same time.\nNote: This bit is cleared by writing 1 to it." "0: Not the start of a frame,1: Indicate the start of a frame and Host.."
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bitfld.long 0x8 1. "WDH,Write Back Done Head\nSet after the Host Controller has written HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared.\nNote: This bit is cleared by writing 1 to it." "0: Host Controller didn't update HccaDoneHead,1: Host Controller has written HcDoneHead to.."
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bitfld.long 0x8 0. "SO,Scheduling Overrun\nSet when the List Processor determines a Schedule Overrun has occurred.\nNote: This bit is cleared by writing 1 to it." "0: Schedule Overrun didn't occur,1: Schedule Overrun has occurred"
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|
line.long 0xC "HcInterruptEnable,Host Controller Interrupt Enable Register"
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bitfld.long 0xC 31. "MIE,Master Interrupt Enable Bit\nThis bit is a global interrupt enable. A write of '1' allows interrupts to be enabled via the specific enable bits listed above.\nWrite Operation:" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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|
bitfld.long 0xC 6. "RHSC,Root Hub Status Change Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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bitfld.long 0xC 5. "FNO,Frame Number Overflow Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
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|
bitfld.long 0xC 3. "RD,Resume Detected Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
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bitfld.long 0xC 2. "SF,Start of Frame Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
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bitfld.long 0xC 1. "WDH,Write Back Done Head Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
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bitfld.long 0xC 0. "SO,Scheduling Overrun Enable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
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line.long 0x10 "HcInterruptDisable,Host Controller Interrupt Disable Register"
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bitfld.long 0x10 31. "MIE,Master Interrupt Disable Bit\nGlobal interrupt disable. Writing '1' to disable all interrupts.\nWrite Operation:" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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|
bitfld.long 0x10 6. "RHSC,Root Hub Status Change Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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bitfld.long 0x10 5. "FNO,Frame Number Overflow Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
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bitfld.long 0x10 3. "RD,Resume Detected Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
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bitfld.long 0x10 2. "SF,Start of Frame Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
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|
bitfld.long 0x10 1. "WDH,Write Back Done Head Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
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newline
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bitfld.long 0x10 0. "SO,Scheduling Overrun Disable Bit\nWrite Operation:" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
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|
line.long 0x14 "HcHCCA,Host Controller Communication Area Register"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "HCCA,Host Controller Communication Area\nPointer to indicate the base address of the Host Controller Communication Area (HCCA)."
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|
line.long 0x18 "HcPeriodCurrentED,Host Controller Period Current ED Register"
|
|
hexmask.long 0x18 4.--31. 1. "PCED,Periodic Current ED\nPointer to indicate the physical address of the current Isochronous or Interrupt Endpoint Descriptor."
|
|
line.long 0x1C "HcControlHeadED,Host Controller Control Head ED Register"
|
|
hexmask.long 0x1C 4.--31. 1. "CHED,Control Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Control list."
|
|
line.long 0x20 "HcControlCurrentED,Host Controller Control Current ED Register"
|
|
hexmask.long 0x20 4.--31. 1. "CCED,Control Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Control list."
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|
line.long 0x24 "HcBulkHeadED,Host Controller Bulk Head ED Register"
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hexmask.long 0x24 4.--31. 1. "BHED,Bulk Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list."
|
|
line.long 0x28 "HcBulkCurrentED,Host Controller Bulk Current ED Register"
|
|
hexmask.long 0x28 4.--31. 1. "BCED,Bulk Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Bulk list."
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|
line.long 0x2C "HcDoneHead,Host Controller Done Head Register"
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hexmask.long 0x2C 4.--31. 1. "DH,Done Head\nPointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue."
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|
line.long 0x30 "HcFmInterval,Host Controller Frame Interval Register"
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bitfld.long 0x30 31. "FIT,Frame Interval Toggle\nThis bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0])." "0: Host Controller Driver didn't load new value..,1: Host Controller Driver loads a new value into FI.."
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hexmask.long.word 0x30 16.--29. 1. "FSMPS,FS Largest Data Packet\nThis field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame."
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|
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hexmask.long.word 0x30 0.--13. 1. "FI,Frame Interval\nThis field specifies the length of a frame as (bit times - 1). For 12 000 bit times in a frame a value of 11 999 is stored here."
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rgroup.long 0x38++0x7
|
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line.long 0x0 "HcFmRemaining,Host Controller Frame Remaining Register"
|
|
bitfld.long 0x0 31. "FRT,Frame Remaining Toggle\nThis bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0." "0,1"
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hexmask.long.word 0x0 0.--13. 1. "FR,Frame Remaining\nWhen the Host Controller is in the USBOPERATIONAL state this 14-bit field decrements each 12 MHz clock period. When the count reaches 0 (end of frame) the counter reloads with Frame Interval. In addition the counter loads when the.."
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line.long 0x4 "HcFmNumber,Host Controller Frame Number Register"
|
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hexmask.long.word 0x4 0.--15. 1. "FN,Frame Number\nThis 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]). The count rolls over from 'FFFFh' to '0h.'"
|
|
group.long 0x40++0x13
|
|
line.long 0x0 "HcPeriodicStart,Host Controller Periodic Start Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "PS,Periodic Start\nThis field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin."
|
|
line.long 0x4 "HcLSThreshold,Host Controller Low-speed Threshold Register"
|
|
hexmask.long.word 0x4 0.--11. 1. "LST,Low-speed Threshold"
|
|
line.long 0x8 "HcRhDescriptorA,Host Controller Root Hub Descriptor A Register"
|
|
bitfld.long 0x8 12. "NOCP,No Overcurrent Protection\nThis bit describes how the overcurrent status for the Root Hub ports reported." "0: Overcurrent status is reported,1: Overcurrent status is not reported"
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|
bitfld.long 0x8 11. "OCPM,Overcurrent Protection Mode\nThis bit describes how the overcurrent status for the Root Hub ports reported. This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared." "0: Global overcurrent,1: Individual overcurrent"
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bitfld.long 0x8 8. "PSM,Power Switching Mode\nThis bit is used to specify how the power switching of the Root Hub ports is controlled." "0: Global switching,1: Individual switching"
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|
hexmask.long.byte 0x8 0.--7. 1. "NDP,Number Downstream Ports\nUSB host control supports two downstream ports and only one port is available in this series of chip."
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|
line.long 0xC "HcRhDescriptorB,Host Controller Root Hub Descriptor B Register"
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hexmask.long.word 0xC 16.--31. 1. "PPCM,Port Power Control Mask\nGlobal power switching. This field is only valid if Power Switching Mode is set (individual port switching). When set the port only responds to individual port power switching commands (Set/Clear Port Power). When cleared .."
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line.long 0x10 "HcRhStatus,Host Controller Root Hub Status Register"
|
|
bitfld.long 0x10 31. "CRWE,Clear Remote Wake-up Enable Bit\nThis bit is use to clear DRWE (HcRhStatus[15]).\nThis bit is always read as 0.\nWrite Operation:" "0: No effect,1: Clear DRWE (HcRhStatus[15])"
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|
bitfld.long 0x10 17. "OCIC,Overcurrent Indicator Change\nThis bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\nWrite 1 to clear this bit to 0." "0: OCI (HcRhStatus[1]) didn't change,1: OCI (HcRhStatus[1]) changed"
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|
newline
|
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bitfld.long 0x10 16. "LPSC,Set Global Power" "0: No effect,1: Set global power"
|
|
bitfld.long 0x10 15. "DRWE,Device Remote Wakeup Enable Bit\nThis bit controls if port's Connect Status Change as a remote wake-up event.\nWrite Operation:" "0: No effect.\nConnect Status Change as a remote..,1: Connect Status Change as a remote wake-up event.."
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newline
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rbitfld.long 0x10 1. "OCI,Overcurrent Indicator (Read Only)\nThis bit reflects the state of the overcurrent status pin. This field is only valid if NOCP (HcRhDescriptorA[12]) and OCPM (HcRhDescriptorA[11]) are cleared." "0: No overcurrent condition,1: Overcurrent condition"
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|
bitfld.long 0x10 0. "LPS,Clear Global Power" "0: No effect,1: Clear global power"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "HcRhPortStatus1,Host Controller Root Hub Port Status [1]"
|
|
bitfld.long 0x0 20. "PRSC,Port Reset Status Change\nThis bit indicates that the port reset signal has completed.\nWrite 1 to clear this bit to 0." "0: Port reset is not complete,1: Port reset is complete"
|
|
bitfld.long 0x0 19. "OCIC,Port Overcurrent Indicator Change\nThis bit is set when POCI (HcRhPortStatus1[3]) changes.\nWrite 1 to clear this bit to 0." "0: POCI (HcRhPortStatus1[3]) didn't change,1: POCI (HcRhPortStatus1[3]) changed"
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newline
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bitfld.long 0x0 18. "PSSC,Port Suspend Status Change\nThis bit indicates the completion of the selective resume sequence for the port.\nWrite 1 to clear this bit to 0." "0: Port resume is not complete,1: Port resume is complete"
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|
bitfld.long 0x0 17. "PESC,Port Enable Status Change\nThis bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.\nWrite 1 to clear this bit to 0." "0: PES (HcRhPortStatus1[1]) didn't change,1: PES (HcRhPortStatus1[1]) changed"
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newline
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bitfld.long 0x0 16. "CSC,Connect Status Change\nThis bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).\nWrite 1 to clear this bit to 0." "0: No connect/disconnect event (CCS..,1: Hardware detection of connect/disconnect event.."
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bitfld.long 0x0 9. "LSDA,Low Speed Device Attached\nThis bit defines the speed (and bus idle) of the attached device. It is only valid when CCS (HcRhPortStatus1[0]) is set.\nThis bit is also used to clear port power.\nWrite Operation:" "0: No effect.\nFull Speed device,1: Clear PPS (HcRhPortStatus1[8]).\nLow-speed device"
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|
newline
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bitfld.long 0x0 8. "PPS,Port Power Status\nThis bit reflects the power state of the port regardless of the power switching mode.\nWrite Operation:" "0: No effect.\nPort power is Disabled,1: Port Power Enabled.\nPort power is Enabled"
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bitfld.long 0x0 4. "PRS,Port Reset Status\nThis bit reflects the reset state of the port.\nWrite Operation:" "0: No effect.\nPort reset signal is not active,1: Set port reset.\nPort reset signal is active"
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newline
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bitfld.long 0x0 3. "POCI,Port Overcurrent Indicator\nThis bit reflects the state of the overcurrent status pin dedicated to this port. This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.\nThis bit is also used to initiate.." "0: No effect.\nNo overcurrent condition,1: Clear port suspend.\nOvercurrent condition"
|
|
bitfld.long 0x0 2. "PSS,Port Suspend Status\nThis bit indicates the port is suspended\nWrite Operation:" "0: No effect.\nPort is not suspended,1: Set port suspend.\nPort is selectively suspended"
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newline
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bitfld.long 0x0 1. "PES,Port Enable Status\nWrite Operation:" "0: No effect.\nPort Disabled,1: Set port enable.\nPort Enabled"
|
|
bitfld.long 0x0 0. "CCS,Current Connect Status\nWrite Operation:" "0: No effect.\nNo device connected,1: Clear port enable.\nDevice connected"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "HcPhyControl,Host Controller PHY Control Register"
|
|
bitfld.long 0x0 27. "STBYEN,USB Transceiver Standby Enable Bit\nThis bit controls if USB transceiver could enter the standby mode to reduce power consumption." "0: The USB transceiver would never enter the..,1: The USB transceiver will enter standby mode.."
|
|
line.long 0x4 "HcMiscControl,Host Controller Miscellaneous Control Register"
|
|
bitfld.long 0x4 16. "DPRT1,Disable Port 1\nThis bit controls if the connection between USB host controller and transceiver of port 1 is disabled. If the connection is disabled the USB host controller will not recognize any event of USB bus.\nSet this bit high the.." "0: The connection between USB host controller and..,1: The connection between USB host controller and.."
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|
bitfld.long 0x4 4. "PPCAL,Port Power Control Active Low\nThis bit controls the polarity of port power control to external power IC." "0: Port power control is high active,1: Port power control is low active"
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newline
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bitfld.long 0x4 3. "OCAL,Overcurrent Active Low\nThis bit controls the polarity of overcurrent flag from external power IC." "0: Overcurrent flag is high active,1: Overcurrent flag is low active"
|
|
bitfld.long 0x4 1. "ABORT,AHB Bus Error Response\nThis bit indicates there is an Error response received in AHB bus.\nNote: This bit is cleared by writing 1 to it." "0: No Error response received,1: Error response received"
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tree.end
|
|
tree "USCI (Universal Serial Control Interface)"
|
|
base ad:0x0
|
|
tree "UI2C (Inter-Integrated Circuit)"
|
|
tree "UI2C0"
|
|
base ad:0x400D0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "UI2C_CTL,USCI Control Register"
|
|
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "UI2C_BRGEN,USCI Baud Rate Generator Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width."
|
|
hexmask.long.word 0x0 16.--25. 1. "CLKDIV,Clock Divider\nNote: The minimum value of DIVIDER is 9 for USCI_I2C."
|
|
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|
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hexmask.long.byte 0x0 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
|
|
bitfld.long 0x0 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
|
|
newline
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bitfld.long 0x0 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x0 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
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bitfld.long 0x0 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?"
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bitfld.long 0x0 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x0 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x2C++0x3
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line.long 0x0 "UI2C_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x0 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI supports word length from 4 to 16 bits."
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bitfld.long 0x0 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "UI2C_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
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rgroup.long 0x34++0x3
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line.long 0x0 "UI2C_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions which defined in I2C."
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group.long 0x44++0x23
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line.long 0x0 "UI2C_DEVADDR0,USCI Device Address Register 0"
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hexmask.long.word 0x0 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB the AA bits are compared to the bits DEVADDR [9:8] to check for address match where the X is R/W bit. Then.."
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line.long 0x4 "UI2C_DEVADDR1,USCI Device Address Register 1"
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB the AA bits are compared to the bits DEVADDR [9:8] to check for address match where the X is R/W bit. Then.."
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line.long 0x8 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
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hexmask.long.word 0x8 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI supports multiple address recognition with two address mask register. When the bit in the address mask register is set to 1 it means the received corresponding address bit is don't-care. If the bit is set to 0 .."
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line.long 0xC "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
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hexmask.long.word 0xC 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI supports multiple address recognition with two address mask register. When the bit in the address mask register is set to 1 it means the received corresponding address bit is don't-care. If the bit is set to 0 .."
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line.long 0x10 "UI2C_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x10 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according to START signal,1: The chip is woken up according to address match"
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bitfld.long 0x10 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x14 "UI2C_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x14 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x18 "UI2C_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x18 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
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hexmask.long.word 0x18 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero.."
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bitfld.long 0x18 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the.." "0: The monitor mode Disabled,1: The monitor mode Enabled"
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bitfld.long 0x18 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt." "0: SCL output will be forced high due to open drain..,1: I2C module may act as a slave peripheral just.."
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bitfld.long 0x18 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags.." "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch is active"
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bitfld.long 0x18 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
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bitfld.long 0x18 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x18 2. "STO,I2C STOP Control" "0,1"
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bitfld.long 0x18 1. "AA,Assert Acknowledge Control" "0,1"
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bitfld.long 0x18 0. "GCFUNC,General Call Function\nNote: When ADDR10EN (UI2C_PROTCTL [4]) is set don't set this bit." "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x1C "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x1C 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master." "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
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bitfld.long 0x1C 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12]))." "0: The error interrupt Disabled,1: The error interrupt Enabled"
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bitfld.long 0x1C 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected." "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
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bitfld.long 0x1C 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master." "0: The non-acknowledge interrupt Disabled,1: The non-acknowledge interrupt Enabled"
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bitfld.long 0x1C 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected." "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
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bitfld.long 0x1C 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected." "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
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newline
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bitfld.long 0x1C 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event." "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
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line.long 0x20 "UI2C_PROTSTS,USCI Protocol Status Register"
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bitfld.long 0x20 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This.." "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
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bitfld.long 0x20 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL.." "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
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bitfld.long 0x20 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x20 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit cannot be released when WKUPIF is set." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x20 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
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bitfld.long 0x20 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: The device is not selected as slave,1: The device is selected as slave"
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bitfld.long 0x20 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
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bitfld.long 0x20 12. "ERRIF,Error Interrupt Flag\nNote 1: This bit is cleared by software writing 1 into this bit.\nNote 2: This bit is set for slave mode and user must write 1 into STO register to the defined 'not addressed' slave mode." "0: An I2C error has not been detected,1: This bit is cleared by software writing 1 into.."
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newline
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bitfld.long 0x20 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: An arbitration has not been lost,1: An arbitration has been lost"
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bitfld.long 0x20 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A non-acknowledge has not been received,1: A non-acknowledge has been received"
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newline
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bitfld.long 0x20 9. "STORIF,Stop Condition Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A stop condition has not yet been detected,1: A stop condition has been detected"
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bitfld.long 0x20 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However this bit also indicates that a repeated start condition has been detected on slave.." "0: A start condition has not yet been detected,1: A start condition has been detected"
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bitfld.long 0x20 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x20 5. "TOIF,Time-out Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
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group.long 0x8C++0x3
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line.long 0x0 "UI2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x0 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode."
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hexmask.long.word 0x0 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.."
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tree.end
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tree "UI2C1"
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base ad:0x400D1000
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group.long 0x0++0x3
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line.long 0x0 "UI2C_CTL,USCI Control Register"
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bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
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group.long 0x8++0x3
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line.long 0x0 "UI2C_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.byte 0x0 28.--31. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width."
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hexmask.long.word 0x0 16.--25. 1. "CLKDIV,Clock Divider\nNote: The minimum value of DIVIDER is 9 for USCI_I2C."
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hexmask.long.byte 0x0 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x0 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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newline
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bitfld.long 0x0 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x0 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
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newline
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bitfld.long 0x0 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?"
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bitfld.long 0x0 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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newline
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bitfld.long 0x0 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x2C++0x3
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line.long 0x0 "UI2C_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x0 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI supports word length from 4 to 16 bits."
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bitfld.long 0x0 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "UI2C_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
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rgroup.long 0x34++0x3
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line.long 0x0 "UI2C_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions which defined in I2C."
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group.long 0x44++0x23
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line.long 0x0 "UI2C_DEVADDR0,USCI Device Address Register 0"
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hexmask.long.word 0x0 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB the AA bits are compared to the bits DEVADDR [9:8] to check for address match where the X is R/W bit. Then.."
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line.long 0x4 "UI2C_DEVADDR1,USCI Device Address Register 1"
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hexmask.long.word 0x4 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB the AA bits are compared to the bits DEVADDR [9:8] to check for address match where the X is R/W bit. Then.."
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line.long 0x8 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
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hexmask.long.word 0x8 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI supports multiple address recognition with two address mask register. When the bit in the address mask register is set to 1 it means the received corresponding address bit is don't-care. If the bit is set to 0 .."
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line.long 0xC "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
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hexmask.long.word 0xC 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI supports multiple address recognition with two address mask register. When the bit in the address mask register is set to 1 it means the received corresponding address bit is don't-care. If the bit is set to 0 .."
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line.long 0x10 "UI2C_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x10 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according to START signal,1: The chip is woken up according to address match"
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bitfld.long 0x10 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x14 "UI2C_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x14 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x18 "UI2C_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x18 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
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hexmask.long.word 0x18 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero.."
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bitfld.long 0x18 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the.." "0: The monitor mode Disabled,1: The monitor mode Enabled"
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bitfld.long 0x18 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt." "0: SCL output will be forced high due to open drain..,1: I2C module may act as a slave peripheral just.."
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newline
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bitfld.long 0x18 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags.." "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch is active"
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bitfld.long 0x18 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
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bitfld.long 0x18 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x18 2. "STO,I2C STOP Control" "0,1"
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newline
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bitfld.long 0x18 1. "AA,Assert Acknowledge Control" "0,1"
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bitfld.long 0x18 0. "GCFUNC,General Call Function\nNote: When ADDR10EN (UI2C_PROTCTL [4]) is set don't set this bit." "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x1C "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x1C 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master." "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
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bitfld.long 0x1C 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12]))." "0: The error interrupt Disabled,1: The error interrupt Enabled"
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newline
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bitfld.long 0x1C 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected." "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
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bitfld.long 0x1C 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master." "0: The non-acknowledge interrupt Disabled,1: The non-acknowledge interrupt Enabled"
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newline
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bitfld.long 0x1C 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected." "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
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bitfld.long 0x1C 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected." "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
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newline
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bitfld.long 0x1C 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event." "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
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line.long 0x20 "UI2C_PROTSTS,USCI Protocol Status Register"
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bitfld.long 0x20 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This.." "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
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bitfld.long 0x20 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL.." "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
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newline
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bitfld.long 0x20 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x20 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit cannot be released when WKUPIF is set." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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newline
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bitfld.long 0x20 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
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bitfld.long 0x20 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: The device is not selected as slave,1: The device is selected as slave"
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newline
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bitfld.long 0x20 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
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bitfld.long 0x20 12. "ERRIF,Error Interrupt Flag\nNote 1: This bit is cleared by software writing 1 into this bit.\nNote 2: This bit is set for slave mode and user must write 1 into STO register to the defined 'not addressed' slave mode." "0: An I2C error has not been detected,1: This bit is cleared by software writing 1 into.."
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bitfld.long 0x20 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: An arbitration has not been lost,1: An arbitration has been lost"
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bitfld.long 0x20 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A non-acknowledge has not been received,1: A non-acknowledge has been received"
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bitfld.long 0x20 9. "STORIF,Stop Condition Received Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A stop condition has not yet been detected,1: A stop condition has been detected"
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bitfld.long 0x20 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However this bit also indicates that a repeated start condition has been detected on slave.." "0: A start condition has not yet been detected,1: A start condition has been detected"
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bitfld.long 0x20 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x20 5. "TOIF,Time-out Interrupt Flag\nNote: This bit is cleared by software writing 1 into this bit." "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
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group.long 0x8C++0x3
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line.long 0x0 "UI2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x0 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode."
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hexmask.long.word 0x0 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.."
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tree.end
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tree.end
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tree "USPI (Serial Peripheral Interface)"
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tree "USPI0"
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base ad:0x400D0000
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group.long 0x0++0xB
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line.long 0x0 "USPI_CTL,USCI Control Register"
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bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
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line.long 0x4 "USPI_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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line.long 0x8 "USPI_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider"
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bitfld.long 0x8 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
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bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor." "0: fDIV_CLK,1: fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x10++0x3
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line.long 0x0 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x3
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line.long 0x0 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x7
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line.long 0x0 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it is suggested this bit.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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line.long 0x4 "USPI_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
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bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol the control.." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin." "0: Data output level is not inverted,1: Data output level is inverted"
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bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "USPI_TXDAT,USCI Transmit Data Register"
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bitfld.long 0x0 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field."
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rgroup.long 0x34++0x3
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line.long 0x0 "USPI_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer."
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group.long 0x38++0xB
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line.long 0x0 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x0 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the receive-related counters state machine.."
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bitfld.long 0x0 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared. Should only be.."
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bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared. Should only be.."
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bitfld.long 0x0 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
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line.long 0x4 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x4 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]) the corresponding interrupt request is activated. It is cleared by software writes 1.." "0: A transmit buffer under-run event has not been..,1: A transmit buffer under-run event has been.."
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bitfld.long 0x4 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x4 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for the.."
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bitfld.long 0x4 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software writes 1 to.." "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been detected"
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bitfld.long 0x4 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x4 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
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line.long 0x8 "USPI_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x8 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x8 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 1. "TXPDMAEN,PDMA Transmit Channel Available\nNote 1: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
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bitfld.long 0x8 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic. This bit.."
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group.long 0x54++0x13
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line.long 0x0 "USPI_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x4 "USPI_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "USPI_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x8 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
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bitfld.long 0x8 28. "TXUDRPOL,Transmit Under-run Data Polarity for Slave Only\nThis bit defines the transmitting data level when no data is available for transferring." "0: The output data level is 0 if TX under run event..,1: The output data level is 1 if TX under run event.."
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hexmask.long.word 0x8 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period for Slave Only\nIn Slave mode this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC USPI_BRGEN[5]) between the two edges of input SCLK will assert the.."
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bitfld.long 0x8 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 8.--11. 1. "SUSPITV,Suspend Interval for Master Only\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of.."
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bitfld.long 0x8 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge." "0: MODE0. The idle state of SPI clock is low level.,1: MODE1. The idle state of SPI clock is low level.,?,?"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable for Master Only" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
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bitfld.long 0x8 2. "SS,Slave Select Control for Master Only\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the.." "0,1"
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bitfld.long 0x8 1. "SLV3WIRE,Slave 3-wire Mode Selection for Slave Only\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
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line.long 0xC "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0xC 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0xC 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event." "0: Slave time-out interrupt Disabled,1: Slave time-out interrupt Enabled"
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bitfld.long 0xC 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active." "0: Slave select active interrupt generation Disabled,1: Slave select active interrupt generation Enabled"
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bitfld.long 0xC 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive." "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation Enabled"
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line.long 0x10 "USPI_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x10 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1. This bit indicates whether the.." "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
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rbitfld.long 0x10 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
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rbitfld.long 0x10 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x10 9. "SSACTIF,Slave Select Active Interrupt Flag for Slave Only\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to active,1: The slave select signal has changed to active"
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bitfld.long 0x10 8. "SSINAIF,Slave Select Inactive Interrupt Flag for Slave Only\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
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bitfld.long 0x10 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag for Slave Only\nNote: It is cleared by software write 1 to this bit." "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
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bitfld.long 0x10 5. "SLVTOIF,Slave Time-out Interrupt Flag for Slave Only\nNote: It is cleared by software write 1 to this bit." "0: Slave time-out event did not occur,1: Slave time-out event occurred"
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bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Receive end event did not occur,1: Receive end event occurred"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Receive start event did not occur,1: Receive start event occurred"
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bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Transmit end event did not occur,1: Transmit end event occurred"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Transmit start event did not occur,1: Transmit start event occurred"
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tree.end
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tree "USPI1"
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base ad:0x400D1000
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group.long 0x0++0xB
|
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line.long 0x0 "USPI_CTL,USCI Control Register"
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bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
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line.long 0x4 "USPI_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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line.long 0x8 "USPI_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider"
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bitfld.long 0x8 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
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bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor." "0: fDIV_CLK,1: fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x10++0x3
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line.long 0x0 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x3
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line.long 0x0 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x7
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line.long 0x0 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it is suggested this bit.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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line.long 0x4 "USPI_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
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bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol the control.." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin." "0: Data output level is not inverted,1: Data output level is inverted"
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bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "USPI_TXDAT,USCI Transmit Data Register"
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bitfld.long 0x0 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field."
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rgroup.long 0x34++0x3
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line.long 0x0 "USPI_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer."
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group.long 0x38++0xB
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line.long 0x0 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x0 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the receive-related counters state machine.."
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bitfld.long 0x0 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared. Should only be.."
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bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared. Should only be.."
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bitfld.long 0x0 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
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line.long 0x4 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x4 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]) the corresponding interrupt request is activated. It is cleared by software writes 1.." "0: A transmit buffer under-run event has not been..,1: A transmit buffer under-run event has been.."
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bitfld.long 0x4 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x4 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for the.."
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bitfld.long 0x4 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software writes 1 to.." "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been detected"
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bitfld.long 0x4 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x4 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
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line.long 0x8 "USPI_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x8 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x8 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 1. "TXPDMAEN,PDMA Transmit Channel Available\nNote 1: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable.." "0: Transmit PDMA function Disabled,1: In SPI Master mode with full duplex transfer"
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bitfld.long 0x8 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic. This bit.."
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group.long 0x54++0x13
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line.long 0x0 "USPI_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x4 "USPI_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "USPI_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x8 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
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bitfld.long 0x8 28. "TXUDRPOL,Transmit Under-run Data Polarity for Slave Only\nThis bit defines the transmitting data level when no data is available for transferring." "0: The output data level is 0 if TX under run event..,1: The output data level is 1 if TX under run event.."
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hexmask.long.word 0x8 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period for Slave Only\nIn Slave mode this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC USPI_BRGEN[5]) between the two edges of input SCLK will assert the.."
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bitfld.long 0x8 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 8.--11. 1. "SUSPITV,Suspend Interval for Master Only\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of.."
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bitfld.long 0x8 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge." "0: MODE0. The idle state of SPI clock is low level.,1: MODE1. The idle state of SPI clock is low level.,?,?"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable for Master Only" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
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bitfld.long 0x8 2. "SS,Slave Select Control for Master Only\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the.." "0,1"
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bitfld.long 0x8 1. "SLV3WIRE,Slave 3-wire Mode Selection for Slave Only\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
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line.long 0xC "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0xC 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0xC 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event." "0: Slave time-out interrupt Disabled,1: Slave time-out interrupt Enabled"
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bitfld.long 0xC 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active." "0: Slave select active interrupt generation Disabled,1: Slave select active interrupt generation Enabled"
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bitfld.long 0xC 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive." "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation Enabled"
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line.long 0x10 "USPI_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x10 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1. This bit indicates whether the.." "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
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rbitfld.long 0x10 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
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rbitfld.long 0x10 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x10 9. "SSACTIF,Slave Select Active Interrupt Flag for Slave Only\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to active,1: The slave select signal has changed to active"
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bitfld.long 0x10 8. "SSINAIF,Slave Select Inactive Interrupt Flag for Slave Only\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
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bitfld.long 0x10 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag for Slave Only\nNote: It is cleared by software write 1 to this bit." "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
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bitfld.long 0x10 5. "SLVTOIF,Slave Time-out Interrupt Flag for Slave Only\nNote: It is cleared by software write 1 to this bit." "0: Slave time-out event did not occur,1: Slave time-out event occurred"
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bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Receive end event did not occur,1: Receive end event occurred"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Receive start event did not occur,1: Receive start event occurred"
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bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Transmit end event did not occur,1: Transmit end event occurred"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit." "0: Transmit start event did not occur,1: Transmit start event occurred"
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tree.end
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tree.end
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tree "UUART (Universal Asynchronous Receiver/Transmitter)"
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tree "UUART0"
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base ad:0x400D0000
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group.long 0x0++0xB
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line.long 0x0 "UUART_CTL,USCI Control Register"
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bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
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line.long 0x4 "UUART_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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line.long 0x8 "UUART_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.."
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hexmask.long.byte 0x8 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x8 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x8 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
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bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK is selected to fDIV_CLK,1: fSAMP_CLK is selected to fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x10++0x3
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line.long 0x0 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x0 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 0x2." "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,?,?"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x3
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line.long 0x0 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x7
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line.long 0x0 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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line.long 0x4 "UUART_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\nNote: In UART.."
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bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin." "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of data.."
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bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "UUART_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
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rgroup.long 0x34++0x3
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line.long 0x0 "UUART_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])."
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group.long 0x38++0x3
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line.long 0x0 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x0 17. "RXRST,Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1." "0: No effect,1: It is cleared automatically after one PCLK cycle"
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bitfld.long 0x0 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared (filling level is.."
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bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared (filling level is.."
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rgroup.long 0x3C++0x3
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line.long 0x0 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software.." "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
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bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x40++0x3
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line.long 0x0 "UUART_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x0 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x0 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x0 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x0 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic. This bit.."
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group.long 0x54++0x13
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line.long 0x0 "UUART_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x4 "UUART_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "UUART_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x8 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
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bitfld.long 0x8 30. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x8 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x8 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information." "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x8 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN[5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data.."
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hexmask.long.byte 0x8 11.--14. 1. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (START bit) when the device is wake-up from Power-down mode."
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bitfld.long 0x8 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x8 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x8 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN[1]) is enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x8 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART asserted nRTS signal automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2:.." "0: nRTS auto direction control Disabled,1: This bit is used for nRTS auto direction control.."
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bitfld.long 0x8 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x8 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x8 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x8 1. "PARITYEN,Parity Enable Bit\nThis bit defines the PARITY bit is enabled in an UART frame." "0: The PARITY bit Disabled,1: The PARITY bit Enabled"
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bitfld.long 0x8 0. "STOPB,STOP bits\nThis bit defines the number of STOP bits in an UART frame." "0: The number of STOP bits is 1,1: The number of STOP bits is 2"
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line.long 0xC "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0xC 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt." "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
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bitfld.long 0xC 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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line.long 0x10 "UUART_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x10 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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rbitfld.long 0x10 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal." "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x10 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the.." "0: Auto-baud rate detect counter is not overrun,1: This bit is set at the same time of ABRDETIF"
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rbitfld.long 0x10 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver." "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x10 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set the auto-baud rate interrupt will be generated. This bit can be set 4 times.." "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
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bitfld.long 0x10 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x10 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x10 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive finish interrupt status has not occurred,1: A receive finish interrupt status has occurred"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive start interrupt status has not occurred,1: A receive start interrupt status has occurred"
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bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A transmit end interrupt status has not occurred,1: A transmit end interrupt status has occurred"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer." "0: A transmit start interrupt status has not occurred,1: It is cleared by software writing one into this.."
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tree.end
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tree "UUART1"
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base ad:0x400D1000
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group.long 0x0++0xB
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line.long 0x0 "UUART_CTL,USCI Control Register"
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bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
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line.long 0x4 "UUART_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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line.long 0x8 "UUART_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.."
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hexmask.long.byte 0x8 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x8 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x8 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
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bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK is selected to fDIV_CLK,1: fSAMP_CLK is selected to fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
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group.long 0x10++0x3
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line.long 0x0 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x0 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 0x2." "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,?,?"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x3
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line.long 0x0 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x7
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line.long 0x0 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
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line.long 0x4 "UUART_LINECTL,USCI Line Control Register"
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hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\nNote: In UART.."
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bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin." "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of data.."
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bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x3
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line.long 0x0 "UUART_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
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rgroup.long 0x34++0x3
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line.long 0x0 "UUART_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])."
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group.long 0x38++0x3
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line.long 0x0 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x0 17. "RXRST,Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1." "0: No effect,1: It is cleared automatically after one PCLK cycle"
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bitfld.long 0x0 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared (filling level is.."
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bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared (filling level is.."
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rgroup.long 0x3C++0x3
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line.long 0x0 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software.." "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
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bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x40++0x3
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line.long 0x0 "UUART_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x0 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x0 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x0 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x0 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic. This bit.."
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group.long 0x54++0x13
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line.long 0x0 "UUART_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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line.long 0x4 "UUART_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "UUART_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x8 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
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bitfld.long 0x8 30. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x8 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x8 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information." "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x8 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN[5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data.."
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hexmask.long.byte 0x8 11.--14. 1. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (START bit) when the device is wake-up from Power-down mode."
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bitfld.long 0x8 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x8 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x8 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN[1]) is enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x8 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART asserted nRTS signal automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2:.." "0: nRTS auto direction control Disabled,1: This bit is used for nRTS auto direction control.."
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bitfld.long 0x8 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x8 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x8 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x8 1. "PARITYEN,Parity Enable Bit\nThis bit defines the PARITY bit is enabled in an UART frame." "0: The PARITY bit Disabled,1: The PARITY bit Enabled"
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bitfld.long 0x8 0. "STOPB,STOP bits\nThis bit defines the number of STOP bits in an UART frame." "0: The number of STOP bits is 1,1: The number of STOP bits is 2"
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line.long 0xC "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0xC 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt." "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
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bitfld.long 0xC 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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line.long 0x10 "UUART_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x10 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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rbitfld.long 0x10 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal." "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x10 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the.." "0: Auto-baud rate detect counter is not overrun,1: This bit is set at the same time of ABRDETIF"
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rbitfld.long 0x10 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver." "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x10 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set the auto-baud rate interrupt will be generated. This bit can be set 4 times.." "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
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bitfld.long 0x10 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x10 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x10 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive finish interrupt status has not occurred,1: A receive finish interrupt status has occurred"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive start interrupt status has not occurred,1: A receive start interrupt status has occurred"
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bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A transmit end interrupt status has not occurred,1: A transmit end interrupt status has occurred"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer." "0: A transmit start interrupt status has not occurred,1: It is cleared by software writing one into this.."
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tree.end
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tree.end
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tree.end
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tree "UTCPD (USB Type C Power Delivery Controller)"
|
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base ad:0x400C6000
|
|
group.long 0x0++0x37
|
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line.long 0x0 "UTCPD_VID,UTCPD Vendor ID Register"
|
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hexmask.long.word 0x0 0.--15. 1. "VID,UTCPD Vendor ID\nVendor identifier is used to identify the TCPC vendor the VID is a unique 16-bit unsigned integer assigned by USB-IF to the Vendor."
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line.long 0x4 "UTCPD_PID,UTCPD Product ID Register"
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hexmask.long.word 0x4 0.--15. 1. "PID,UTCPD Product ID\nUSB Product ID is used to identify the product."
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line.long 0x8 "UTCPD_DID,UTCPD Device ID Register"
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hexmask.long.word 0x8 0.--15. 1. "DID,UTCPD Device ID\nUSB Device ID is used to identify the release version of the product"
|
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line.long 0xC "UTCPD_TCREV,UTCPD USB Type C Revision Register"
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hexmask.long.byte 0xC 0.--7. 1. "TCREV,UTCPD USB Type-C Revision\nUSB Type-C Cable and Connector Specification Revision 1.3"
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line.long 0x10 "UTCPD_PDREV,UTCPD USB PD Revision Register"
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hexmask.long.byte 0x10 8.--15. 1. "PDREV,UTCPD USB PD Revision\nUSB Power Delivery Specification revision 3.1"
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hexmask.long.byte 0x10 0.--7. 1. "PDVER,UTCPD USB PD Vision\nUSB Power Delivery Specification Version 1.1"
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line.long 0x14 "UTCPD_IS,UTCPD Interrupt Status Register"
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bitfld.long 0x14 15. "VNDIS,Vendor Define Event Detected \nNote: It is cleared by software writing 1 into this bit." "0: No vendor defined interrupt status has been..,1: A vendor defined interrupt status has been.."
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bitfld.long 0x14 11. "SKDCDTIS,VBUS Sink Disconnect Detected \nNote: This bit will be set when VBMONI (UTCPD_PWRCTL[6]) is enabled and VBUS voltage drop lower than SKVBDCTH (UTCPD_SKVBDCTH[9:0]). It is cleared by software writing 1 into this bit." "0: No disconnect detected,1: A VBUS Sink disconnect threshold crossing has.."
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bitfld.long 0x14 10. "RXOFIS,Rx Buffer Overflow \nNote: Writing 1 to this bit acknowledges the overflow. The overflow is cleared by writing 1 to RXSOPIS (UTCPD_IS[2])" "0: RX buffer is functioning properly,1: RX buffer has overflowed"
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bitfld.long 0x14 9. "FUTIS,Fault Occur\nNote: It is cleared by software writing 1 into this bit." "0: No fault occurs,1: A Fault has occurred. Read the FUT_STS register"
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bitfld.long 0x14 8. "VBAMLIS,VBUS Voltage Alarm Low\nThis bit will be set high when DSVBAM (UTCPD_PWRCTL[5]]) is low and VBUS voltage is lower than VBAML (UTCPD_VBAML[9:0]).\nNote: It is cleared by software writing 1 into this bit." "0: No Low voltage alarm has occurred,1: A Low voltage alarm has occurred"
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bitfld.long 0x14 7. "VBAMHIS,VBUS Voltage Alarm High\nThis bit will be set high when DSVBAM (UTCPD_PWRCTL[5]) is low and VBUS voltage is higher than VBAMH (UTCPD_VBAMH[9:0]).\nNote: It is cleared by software writing 1 into this bit." "0: No high voltage alarm has occurred,1: A high voltage alarm has occurred"
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bitfld.long 0x14 6. "TXOKIS,Transmit SOP* Message Successful \nNote: It is cleared by software writing 1 into this bit." "0: No TX SOP* transmit,1: Reset or SOP* message transmission successful."
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bitfld.long 0x14 5. "TXDCUDIS,Transmit SOP* Message Discarded \nNote: It is cleared by software writing 1 into this bit." "0: No TX SOP discarded,1: Reset or SOP* message transmission not sent due.."
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bitfld.long 0x14 4. "TXFALIS,Transmit SOP Fail\nNote: It is cleared by software writing 1 into this bit." "0: No Transmit SOP fail,1: SOP* message transmission not successful no.."
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bitfld.long 0x14 3. "RXHRSTIS,Received Hard Reset\nNote: It is cleared by software writing 1 into this bit." "0: No Hard reset Received,1: Received Hard reset"
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bitfld.long 0x14 2. "RXSOPIS,Received SOP Message\nUTCPD_RXBCNT being set to 0 does not set this bit. \nNote: It is cleared by software writing 1 into this bit." "0: No SOP message Received,1: Received SOP message"
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bitfld.long 0x14 1. "PWRSCHIS,Power Status Changed\nNote: It is cleared by software writing 1 into this bit." "0: Power status not change,1: Power status changed"
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bitfld.long 0x14 0. "CCSCHIS,CC Status Changed\nNote: It is cleared by software writing 1 into this bit." "0: CC status not change,1: CC status changed"
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line.long 0x18 "UTCPD_IE,UTCPD Interrupt Enable Register"
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bitfld.long 0x18 15. "VNDIE,Vendor Define Event Detected Interrupt Enable Bit" "0: Vendor define event detected interrupt Disabled,1: Vendor define event detected interrupt Enabled"
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bitfld.long 0x18 11. "SKDCDTIE,VBUS Sink Disconnect Detected Interrupt Enable Bit" "0: VBUS sink disconnect detected interrupt Disabled,1: VBUS sink disconnect detected interrupt Enabled"
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bitfld.long 0x18 10. "RXOFIE,Rx Buffer Overflow Interrupt Enable Bit" "0: Received buffer interrupt Disabled,1: Received buffer interrupt Enabled"
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bitfld.long 0x18 9. "FUTIE,Fault Occur Interrupt Enable Bit" "0: Fault event occur interrupt Disabled,1: Fault event occur interrupt Enabled"
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bitfld.long 0x18 8. "VBAMLIE,VBUS Voltage Alarm Low Interrupt Enable Bit" "0: VBUS voltage reach low threshold interrupt..,1: VBUS voltage reach low threshold interrupt Enabled"
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bitfld.long 0x18 7. "VBAMHIE,VBUS Voltage Alarm High Interrupt Enable Bit" "0: VBUS voltage reach high threshold interrupt..,1: VBUS voltage reach high threshold interrupt.."
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bitfld.long 0x18 6. "TXOKIE,Transmit SOP* Message Successful Interrupt Enable Bit" "0: Transmit SOP* message successful interrupt..,1: Transmit SOP* message successful interrupt Enabled"
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bitfld.long 0x18 5. "TXDCUDIE,Transmit SOP* Message Discarded Interrupt Enable Bit" "0: Transmit SOP* message discarded interrupt Disabled,1: Transmit SOP* message discarded interrupt Enabled"
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bitfld.long 0x18 4. "TXFAILIE,Transmit SOP Fail Interrupt Enable Bit" "0: Transmit SOP fail interrupt Disabled,1: Transmit SOP fail interrupt Enabled"
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bitfld.long 0x18 3. "RXHRSTIE,Received Hard Reset Interrupt Enable Bit" "0: Received Hard Reseet interrupt Disabled,1: Received Hard Reseet interrupt Enabled"
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bitfld.long 0x18 2. "RXSOPIE,Received SOP Message Interrupt Enable Bit" "0: Received SOP message interrupt Disabled,1: Received SOP message interrupt Enabled"
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bitfld.long 0x18 1. "PWRSCHIE,Power Status Changed Interrupt Enable Bit" "0: Power status changed interrupt Disabled,1: Power status changed interrupt Enabled"
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bitfld.long 0x18 0. "CCSCHIE,CC Status Changed Interrupt Enable Bit" "0: CC pin status changed interrupt Disabled,1: CC pin status changed interrupt Enabled"
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line.long 0x1C "UTCPD_PWRSTSIE,UTCPD Power Status Interrupt Enable Register"
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bitfld.long 0x1C 7. "DACONIE,Debug Accessory Connected Status Interrupt Enable Bit" "0: Debug Accessory Connected Status Interrupt..,1: Debug Accessory Connected status Interrupt Enabled"
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bitfld.long 0x1C 5. "SRHVIE,Sourcing High Voltage Status Interrupt Enable Bit" "0: Sourcing High Voltage Status Interrupt Disabled,1: Sourcing High Voltage Status Interrupt Enabled"
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bitfld.long 0x1C 4. "SRVBIE,Sourcing VBUS Status Interrupt Enable Bit" "0: Sourcing VBUS Status Interrupt Disabled,1: Sourcing VBUS Status Interrupt Enabled"
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bitfld.long 0x1C 3. "VBDTDGIE,VBUS Detection Status Change Interrupt Enable Bit" "0: VBUS Detection Status Change Interrup Disabled,1: VBUS Detection Status Change Interrup Enabled"
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bitfld.long 0x1C 2. "VBPSIE,VBUS Present Status Interrupt Enable Bit" "0: VBUS Present Status Interrupt Disabled,1: VBUS Present Status Interrupt Enabled"
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bitfld.long 0x1C 1. "VCPSIE,VCONN Present Status Interrupt Enable Bit" "0: VCONN Present Status Interrupt Disabled,1: VCONN Present Status Interrupt Enabled"
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bitfld.long 0x1C 0. "SKVBIE,Sinking VBUS Status Interrupt Enable Bit" "0: Sinking VBUS Status Interrupt Disabled,1: Sinking VBUS Status Interrupt Enabled"
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line.long 0x20 "UTCPD_FUTSTSIE,UTCPD Fault Status Interrupt Enable Register"
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bitfld.long 0x20 6. "FOFFVBIE,Force Off VBUS Interrupt Enable Bit" "0: Force Off VBUS Interrupt Disabled,1: Force Off VBUS Interrupt Enabled"
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bitfld.long 0x20 5. "ADGFALIE,Auto Discharge Failed Interrupt Enable Bit" "0: Auto Discharge Failed Interrupt Disabled,1: Auto Discharge Failed Interrupt Enabled"
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bitfld.long 0x20 4. "FDGFALIE,Force Discharge Failed Interrupt Enable Bit" "0: Force Discharge Failed Interrupt Disabled,1: Force Discharge Failed Interrupt Enabled"
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bitfld.long 0x20 3. "VBOCIE,External VBUS OCP Fault Interrupt Enable Bit" "0: External VBUS OCP Fault Interrupt Disabled,1: External VBUS OCP Fault Interrupt Enabled"
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bitfld.long 0x20 2. "VBOVIE,Internal VBUS OVP Fault Interrupt Enable Bit" "0: Internal VBUS OVP Fault Interrupt Disabled,1: Internal VBUS OVP Fault Interrupt Enabled"
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bitfld.long 0x20 1. "VCOCIE,VCONN OCP Fault Interrupt Enable Bit" "0: VCONN OCP Fault Interrupt Disabled,1: VCONN OCP Fault Interrupt Enabled"
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line.long 0x24 "UTCPD_CTL,UTCPD Control Register"
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bitfld.long 0x24 1. "BISTEN,BIST Test Mode \nSetting this bit to 1 is intended to be used only when a USB compliance tester is using USB BIST Test Data to test the PHY layer of the UTCPD. The CPU should clear this bit when a detach is detected." "0: Normal Operation,1: BIST Test Mode"
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bitfld.long 0x24 0. "ORIENT,Plug Orientation \ncommunications if PD messaging is enabled." "0: When VCONN is enabled apply it to the CC2 pin.,1: When VCONN is enabled apply it to the CC1 pin."
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line.long 0x28 "UTCPD_PINPL,UTCPD Pin Polarity Control Register"
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bitfld.long 0x28 10. "VCOCPL,VCONN Overcurrent Event Polarity" "0: Low active,1: High active"
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bitfld.long 0x28 9. "VCDGENPL,VCONN Discharge Enable Polarity" "0: Low active,1: High active"
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bitfld.long 0x28 8. "VCENPL,VCONN Enable Polarity" "0: Low active,1: High active"
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bitfld.long 0x28 5. "VBOCPL,VBUS Overcurrent Eevent Polarity" "0: Low active,1: High active"
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bitfld.long 0x28 4. "FOFFVBPL,Force Off VBUS Event Polarity" "0: Low active,1: High active"
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bitfld.long 0x28 3. "TXFRSPL,Fast Role Swap TX Polarity" "0: Low active,1: High active"
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bitfld.long 0x28 2. "VBDGENPL,VBUS Discharge Enable Polarity \nIt is for Bleed Discharge Enable Polarity." "0: Low active,1: High active"
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bitfld.long 0x28 1. "VBSKENPL,VBUS Sink Enable Polarity" "0: Low active,1: High active"
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bitfld.long 0x28 0. "VBSRENPL,VBUS Source Enable Polarity" "0: Low active,1: High active"
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line.long 0x2C "UTCPD_ROLCTL,UTCPD Role Control Register"
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bitfld.long 0x2C 6. "DRP,Dual Role Port \nThe UTCPD toggles CC1 CC2 after receiving LK4CON (UTCPD_CMD[5]) and until a connection is detected. Upon connection the UTCPD shall resolve to either an Rp or Rd and report the CC1/CC2 State in the CC_STS register." "0: No dual role port,1: Dual role port"
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bitfld.long 0x2C 4.--5. "RPVALUE,Rp Value" "0: Rp default,1: Rp 1.5A,?,?"
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bitfld.long 0x2C 2.--3. "CC2,CC2 Connected Resistance Value" "0: Reserved.,1: Rp (Use Rp definition in RPVALUE),?,?"
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bitfld.long 0x2C 0.--1. "CC1,CC1 Connected Resistance Vaule" "0: Reserved.,?,?,?"
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line.long 0x30 "UTCPD_FUTCTL,UTCPD Fault Control Register"
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bitfld.long 0x30 4. "FOFFVBDS,Force Off VBUS Disable Bit" "0: Force Off VBUS Enabled,1: Force Off VBUS Disabled"
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bitfld.long 0x30 3. "VBDGTMDS,VBUS Discharge Fault Detection Timer Disable Bit\nThis enables the timer for both force discharge and auto discharge and no timer for bleed discharge. Once time-out UTCPD will compare VBUS voltage with VSAFE0V or SP_DGTH depending on the.." "0: VBUS Discharge Fault Detection Timer Enabled,1: VBUS Discharge Fault Detection Timer Disabled"
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bitfld.long 0x30 2. "VBOCDTDS,External VBUS Overcurrent Protection Fault Detect Disable Bit" "0: External OCP circuit Enabled,1: External OCP circuit Disabled"
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bitfld.long 0x30 1. "VBOVDTDS,Internal VBUS Over Voltage Protection Fault Detect Disable Bit\nNote: Internal VBUS over voltage protection means to use ADC to measure VBUS voltage." "0: Internal OVP circuit Enabled,1: Internal OVP circuit Disabled"
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bitfld.long 0x30 0. "VCOCDTDS,External VCONN Overcurrent Fault Detect Disable Bit" "0: External VCONN OCP circuit Enabled,1: External VCONN OCP circuit Disabled"
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line.long 0x34 "UTCPD_PWRCTL,UTCPD Power Control Register"
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bitfld.long 0x34 6. "VBMONI,VBUS Voltage Monitor Enable Bit\nNote: This bit only controls VBUS voltage monitoring. UTCPD_VBVOL shall report all zeroes if disabled." "0: VBUS voltage monitoring Enabled,1: VBUS voltage monitoring Disabled (default)"
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bitfld.long 0x34 5. "DSVBAM,Disable VBUS Voltage Alarms" "0: VBUS Voltage Alarms Power status reporting Enabled,1: VBUS Voltage Alarms Power status reporting.."
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bitfld.long 0x34 4. "ADGDC,Auto Discharge Disconnect \nSetting this bit in a Source UTCPD triggers the following actions upon a disconnect detection: \nDisable sourcing power over VBUS \nVBUS discharge \nSourcing power over VBUS shall be disabled before or at the same time.." "0: The UTCPD shall not automatically discharge VBUS..,1: The UTCPD shall automatically discharge when.."
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bitfld.long 0x34 3. "BDGEN,Enable Bleed Discharge \nNote: Bleed Discharge is a low current discharge to provide a minimum load current if needed.\n10 KOhms or 2mA is recommended. Bleed discharge is used for sink only.\nThis bit will only be cleared by CPU." "0: Bleed discharge Disabled (default),1: Bleed discharge of VBUS Enabled"
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bitfld.long 0x34 2. "FDGEN,Enable Force Discharge \nNote: Force discharge is used for source only. This bit will only be cleared by CPU." "0: Disable forced discharge (default),1: Enable forced discharge of VBUS"
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bitfld.long 0x34 1. "VCPWR,VCONN Power Supported" "0: UTCPD delivers at least 1W on VCONN,1: UTCPD delivers at least the power indicated in.."
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bitfld.long 0x34 0. "VCEN,Enable VCONN" "0: VCONN Source Disabled (default),1: VCONN Source to CC Enabled"
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rgroup.long 0x38++0xB
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line.long 0x0 "UTCPD_CCSTS,UTCPD CC Status Register"
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bitfld.long 0x0 5. "LK4CONN,Looking for Connection" "0: UTCPD is not actively looking for a connection.,1: UTCPD is looking for a connection (toggling as a.."
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bitfld.long 0x0 4. "CONRLT,Connect Result (read only)" "0: the UTCPD is presenting Rp,1: the UTCPD is presenting Rd"
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bitfld.long 0x0 2.--3. "CC2STATE,CC2 State" "0: SRC.Open (Open Rp).\nSNK.Open (Below maximum vRa),1: SRC.Ra (below maximum vRa).\nSNK.Default (Above..,?,?"
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bitfld.long 0x0 0.--1. "CC1STATE,CC1 State" "0: SRC.Open (Open Rp).\nSNK.Open (Below maximum vRa),1: SRC.Ra (below maximum vRa).\nSNK.Default (Above..,?,?"
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line.long 0x4 "UTCPD_PWRSTS,UTCPD Power Status Register"
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bitfld.long 0x4 7. "DACON,Debug Accessory Connected" "0: No Debug Accessory connected (default),1: Debug Accessory connected"
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bitfld.long 0x4 5. "SRHV,Sourcing High Voltage \nThis bit does not control the power path it just provides a monitor of the status. This bit is asserted as long as the UTCPD is sourcing nondefault voltage over VBUS (i.e. not VSAFE5V) as a response to CPU writing 0x88 to.." "0: VSAFE5V,1: Higher Voltage"
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bitfld.long 0x4 4. "SRVB,Sourcing VBUS \nThis bit does not control the path just provides a monitor of the status." "0: Sourcing VBUS Disabled,1: Sourcing VBUS Enabled"
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bitfld.long 0x4 3. "VBPSDTEN,VBUS Present Detection Enabled" "0: VBUS Present Detection Disabled,1: VBUS Present Detection Enabled (default)"
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bitfld.long 0x4 2. "VBPS,VBUS Present \nThe UTCPD shall report VBUS present when UTCPD detects VBUS rises above 4V. \nThe UTCPD shall report VBUS is not present when UTCPD detects VBUS falls below 3.5V." "0: VBUS Disconnected,1: VBUS Connected"
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bitfld.long 0x4 1. "VCPS,VCONN Present \nIf VCEN (UTCPD_PWRCTL[0])] is disabled VCONN Present should be set to 0." "0: VCONN is not present,1: This bit is asserted when VCONN present CC1 or.."
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bitfld.long 0x4 0. "SKVB,Sinking VBUS" "0: Sink is Disconnected (Default),1: UTCPD is sinking VBUS to the system load"
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line.long 0x8 "UTCPD_FUTSTS,UTCPD Fault Status Register"
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bitfld.long 0x8 6. "FOFFVB,Force Off VBUS \nThe UTCPD has disconnected VBUS due to external inputs (EINT0 ~ EINT5)" "0: No Fault Detected no action (default and not..,1: VBUS Source/Sink has been forced off due to.."
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bitfld.long 0x8 5. "ADGFAL,Auto Discharge Failed \nIf ADGDC (UTCPD_PWRCTL[4]) is set the UTCPD shall report discharge fails if VBUS is not below vSafe0V within tSafe0V" "0: No discharge failure,1: Discharge commanded by the TCPM failed"
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bitfld.long 0x8 4. "FDGFAL,Force Discharge Failed \nIf FDGEN (UTCPD_PWRCTL[2]) is set the UTCPD shall report a discharge fails if VBUS is not below vSafe0V within tSafe0V." "0: No discharge failure,1: Discharge commanded by the TCPM failed"
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bitfld.long 0x8 3. "VBOCFUT,VBUS Overcurrent Protection Fault" "0: Not in an overcurrent protection state,1: Overcurrent fault latched"
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bitfld.long 0x8 2. "VBOVFUT,VBUS Over Voltage Protection Fault" "0: No Fault detected,1: Over-voltage fault latched"
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bitfld.long 0x8 1. "VCOCFUT,VCONN Overcurrent Protection Fault" "0: Not in an overcurrent protection state,1: Overcurrent fault latched"
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group.long 0x44++0x13
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line.long 0x0 "UTCPD_CMD,UTCPD Command Register"
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hexmask.long.byte 0x0 0.--7. 1. "CMD,Command Set \nThe Command is issued by the CPU. The Command is cleared by the UTCPD after being acted upon. It always read as 0."
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line.long 0x4 "UTCPD_DVCAP1,UTCPD Device Capabilities 1 Register"
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bitfld.long 0x4 14. "CPVBOCP,VBUS OCP Reporting" "0: VBUS OCP is not reported,1: VBUS OCP is reported"
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bitfld.long 0x4 13. "CPVBOVP,VBUS OVP Reporting" "0: VBUS OVP is not reported,1: VBUS OVP is reported"
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bitfld.long 0x4 12. "CPBDG,Bleed Discharge" "0: No Bleed Discharge implemented,1: Bleed Discharge is implemented"
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bitfld.long 0x4 11. "CPFDG,Force Discharge" "0: No Force Discharge implemented,1: Force Discharge is implemented"
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bitfld.long 0x4 10. "CPVBAM,VBUS Measurement and Alarm Capable" "0: No VBUS voltage measurement nor VBUS Alarms,1: VBUS voltage measurement and VBUS Alarms"
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bitfld.long 0x4 8.--9. "CPSRRE,Source Resistor Supported" "0: Rp default only,1: Rp 1.5A and default,?,?"
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bitfld.long 0x4 5.--7. "CPROL,Roles Supported" "0: USB Type-C Port Manager can configure the Port..,1: Source only,?,?,?,?,?,?"
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bitfld.long 0x4 4. "CPSDBG,SOP'_DBG/SOP'_DBG Support" "0: All SOP* except SOP'_DBG/SOP'_DBG,1: All SOP* messages are supported"
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bitfld.long 0x4 3. "CPSRVC,Source VCONN" "0: UTCPD is not capable of switching VCONN,1: UTCPD is capable of switching VCONN"
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bitfld.long 0x4 2. "CPSKVB,Sink VBUS" "0: UTCPD is not capable controlling the sink path..,1: UTCPD is capable of controlling the sink path to.."
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bitfld.long 0x4 1. "CPSRHV,Source High Voltage VBUS" "0: UTCPD is not capable of controlling the source..,1: UTCPD is capable of controlling the source high.."
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bitfld.long 0x4 0. "CPSRVB,Source VBUS" "0: TCPC is not capable of controlling the source..,1: TCPC is capable of controlling the source path.."
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line.long 0x8 "UTCPD_DVCAP2,UTCPD Device Capabilities 2 Register"
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bitfld.long 0x8 7. "CPSKDCDT,Sink Disconnect Detection" "0: UTCPD_SKVBDCTH not implemented,1: UTCPD_SKVBDCTH implemented"
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bitfld.long 0x8 6. "CPSPDGTH,Stop Discharge Threshold" "0: UTCPD_SPDGTH not implemented,1: UTCPD_SPDGTH implemented"
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bitfld.long 0x8 4.--5. "CPVBAMLS,VBUS Voltage Alarm LSB" "0: UTCPD has 25mV LSB for its voltage alarm and..,?,?,?"
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bitfld.long 0x8 1.--3. "CPVCPWR,VCONN Power Supported" "0: 1.0W,1: 1.5W,?,?,?,?,?,?"
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bitfld.long 0x8 0. "CPVCOC,VCONN Overcurrent Fault Capable" "0: UTCPD is not capable of detecting a Vconn fault,1: UTCPD is capable of detecting a Vconn fault"
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line.long 0xC "UTCPD_MSHEAD,UTCPD Message Header Info Register"
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bitfld.long 0xC 4. "CABPLG,Cable Plug" "0: Message originated from Source Sink or DRP,1: Message originated from a Cable Plug"
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bitfld.long 0xC 3. "DAROL,Data Role" "0: UFP,1: DFP"
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bitfld.long 0xC 1.--2. "PDREV,USB PD Specification Revision" "0: Revision 1.0,1: Revision 2.0,?,?"
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bitfld.long 0xC 0. "PWRROL,Power Role" "0: Sink,1: Source"
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line.long 0x10 "UTCPD_DTRXEVNT,UTCPD Enable Detect RX Event Register"
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bitfld.long 0x10 6. "CABRSTEN,Enable Cable Reset" "0: UTCPD does not detect Cable Reset signaling..,1: UTCPD detects Cable Reset signaling"
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bitfld.long 0x10 5. "HRSTEN,Enable Hard Reset" "0: UTCPD does not detect Hard Reset signaling..,1: UTCPD detects Hard Reset signaling"
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bitfld.long 0x10 4. "SDBGPPEN,Enable SOP_DBG'' Message" "0: UTCPD does not detect SOP_DBG'' message (default),1: UTCPD detects SOP_DBG'' message"
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bitfld.long 0x10 3. "SDBGPEN,Enable SOP_DBG' Message" "0: UTCPD does not detect SOP_DBG' message (default),1: UTCPD detects SOP_DBG' message"
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bitfld.long 0x10 2. "SOPPPEN,Enable SOP'' Message" "0: UTCPD does not detect SOP'' message (default),1: UTCPD detects SOP'' message"
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bitfld.long 0x10 1. "SOPPEN,Enable SOP' Message" "0: UTCPD does not detect SOP' message (default),1: UTCPD detects SOP' message"
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bitfld.long 0x10 0. "SOPEN,Enable SOP Message" "0: UTCPD does not detect SOP message (default),1: UTCPD detects SOP message"
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rgroup.long 0x58++0xB
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line.long 0x0 "UTCPD_RXBCNT,UTCPD RX Byte Count Register"
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hexmask.long.byte 0x0 0.--7. 1. "RXBCNT,Receive Byte Count \nIndicates number of bytes in this register that are not stale. CPU should read the first RXBCNT bytes in this register. This is the number of bytes in the UTCPD_RXDAx plus three (for the RXFTYPE and RXHEAD). \nThe UTCPD shall.."
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line.long 0x4 "UTCPD_RXFTYPE,UTCPD Received Frame Type Register"
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bitfld.long 0x4 0.--2. "RXFTYPE,Received Frame Type \nAll others are reserved." "0: Received SOP,1: Received SOP',?,?,?,?,?,?"
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line.long 0x8 "UTCPD_RXHEAD,UTCPD Received Header Data Register"
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hexmask.long.byte 0x8 8.--15. 1. "RXHEAD1,RX Header Message 1\nUSB PD message header byte 1"
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hexmask.long.byte 0x8 0.--7. 1. "RXHEAD0,RX Header Message 0\nUSB PD message header byte 0"
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|
rgroup.long 0x70++0x1B
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line.long 0x0 "UTCPD_RXDA0,UTCPD Received Data0 Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDAB3,USB PD Received Data Byte 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDAB2,USB PD Received Data Byte 2"
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|
newline
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hexmask.long.byte 0x0 8.--15. 1. "RXDAB1,USB PD Received Data Byte 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDAB0,USB PD Received Data Byte 0"
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line.long 0x4 "UTCPD_RXDA1,UTCPD Received Data1 Register"
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hexmask.long.byte 0x4 24.--31. 1. "RXDAB3,USB PD Received Data Byte 3"
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hexmask.long.byte 0x4 16.--23. 1. "RXDAB2,USB PD Received Data Byte 2"
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|
newline
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hexmask.long.byte 0x4 8.--15. 1. "RXDAB1,USB PD Received Data Byte 1"
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hexmask.long.byte 0x4 0.--7. 1. "RXDAB0,USB PD Received Data Byte 0"
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line.long 0x8 "UTCPD_RXDA2,UTCPD Received Data2 Register"
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hexmask.long.byte 0x8 24.--31. 1. "RXDAB3,USB PD Received Data Byte 3"
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hexmask.long.byte 0x8 16.--23. 1. "RXDAB2,USB PD Received Data Byte 2"
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newline
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hexmask.long.byte 0x8 8.--15. 1. "RXDAB1,USB PD Received Data Byte 1"
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hexmask.long.byte 0x8 0.--7. 1. "RXDAB0,USB PD Received Data Byte 0"
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line.long 0xC "UTCPD_RXDA3,UTCPD Received Data3 Register"
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hexmask.long.byte 0xC 24.--31. 1. "RXDAB3,USB PD Received Data Byte 3"
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hexmask.long.byte 0xC 16.--23. 1. "RXDAB2,USB PD Received Data Byte 2"
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newline
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hexmask.long.byte 0xC 8.--15. 1. "RXDAB1,USB PD Received Data Byte 1"
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hexmask.long.byte 0xC 0.--7. 1. "RXDAB0,USB PD Received Data Byte 0"
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line.long 0x10 "UTCPD_RXDA4,UTCPD Received Data4 Register"
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hexmask.long.byte 0x10 24.--31. 1. "RXDAB3,USB PD Received Data Byte 3"
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hexmask.long.byte 0x10 16.--23. 1. "RXDAB2,USB PD Received Data Byte 2"
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newline
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hexmask.long.byte 0x10 8.--15. 1. "RXDAB1,USB PD Received Data Byte 1"
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hexmask.long.byte 0x10 0.--7. 1. "RXDAB0,USB PD Received Data Byte 0"
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line.long 0x14 "UTCPD_RXDA5,UTCPD Received Data5 Register"
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hexmask.long.byte 0x14 24.--31. 1. "RXDAB3,USB PD Received Data Byte 3"
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hexmask.long.byte 0x14 16.--23. 1. "RXDAB2,USB PD Received Data Byte 2"
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newline
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hexmask.long.byte 0x14 8.--15. 1. "RXDAB1,USB PD Received Data Byte 1"
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hexmask.long.byte 0x14 0.--7. 1. "RXDAB0,USB PD Received Data Byte 0"
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line.long 0x18 "UTCPD_RXDA6,UTCPD Received Data6 Register"
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hexmask.long.byte 0x18 24.--31. 1. "RXDAB3,USB PD Received Data Byte 3"
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hexmask.long.byte 0x18 16.--23. 1. "RXDAB2,USB PD Received Data Byte 2"
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newline
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hexmask.long.byte 0x18 8.--15. 1. "RXDAB1,USB PD Received Data Byte 1"
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hexmask.long.byte 0x18 0.--7. 1. "RXDAB0,USB PD Received Data Byte 0"
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group.long 0x90++0xB
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line.long 0x0 "UTCPD_TXCTL,UTCPD TX Control Register"
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bitfld.long 0x0 4.--5. "RETRYCNT,Retry Counter" "0: No message retry is required,1: Automatically retry message transmission once,?,?"
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bitfld.long 0x0 0.--2. "TXSTYPE,Transmit SOP* Message \nThe UTCPD shall ignore the Retry Counter bits when transmitting a Hard Reset Cable Reset or BIST Carrier" "0: Transmit SOP,1: Transmit SOP',?,?,?,?,?,?"
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line.long 0x4 "UTCPD_TXBCNT,UTCPD TX Byte Count Register"
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hexmask.long.byte 0x4 0.--7. 1. "TXBCNT,Transmit Byte Count\nThis is the number of bytes in the UTCPD_TXDA plus two (for the TXHEAD) \nIf a previous transmit request has not yet completed when TX_CTL is written requesting a Hard Reset the UTCPD shall assert the Transmission Discarded.."
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line.long 0x8 "UTCPD_TXHEAD,UTCPD TX Header Data Register"
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hexmask.long.byte 0x8 8.--15. 1. "TXHEAD1,Transmit Header Byte 1"
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hexmask.long.byte 0x8 0.--7. 1. "TXHEAD0,Transmit Header Byte 0"
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group.long 0xA0++0x1B
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line.long 0x0 "UTCPD_TXDA0,UTCPD Transmit Data0 Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDAB3,USB PD Transmit Data Byte 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDAB2,USB PD Transmit Data Byte 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXDAB1,USB PD Transmit Data Byte 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDAB0,USB PD Transmit Data Byte 0"
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line.long 0x4 "UTCPD_TXDA1,UTCPD Transmit Data1 Register"
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hexmask.long.byte 0x4 24.--31. 1. "TXDAB3,USB PD Transmit Data Byte 3"
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hexmask.long.byte 0x4 16.--23. 1. "TXDAB2,USB PD Transmit Data Byte 2"
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newline
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hexmask.long.byte 0x4 8.--15. 1. "TXDAB1,USB PD Transmit Data Byte 1"
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hexmask.long.byte 0x4 0.--7. 1. "TXDAB0,USB PD Transmit Data Byte 0"
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line.long 0x8 "UTCPD_TXDA2,UTCPD Transmit Data2 Register"
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hexmask.long.byte 0x8 24.--31. 1. "TXDAB3,USB PD Transmit Data Byte 3"
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hexmask.long.byte 0x8 16.--23. 1. "TXDAB2,USB PD Transmit Data Byte 2"
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newline
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hexmask.long.byte 0x8 8.--15. 1. "TXDAB1,USB PD Transmit Data Byte 1"
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hexmask.long.byte 0x8 0.--7. 1. "TXDAB0,USB PD Transmit Data Byte 0"
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line.long 0xC "UTCPD_TXDA3,UTCPD Transmit Data3 Register"
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hexmask.long.byte 0xC 24.--31. 1. "TXDAB3,USB PD Transmit Data Byte 3"
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hexmask.long.byte 0xC 16.--23. 1. "TXDAB2,USB PD Transmit Data Byte 2"
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newline
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hexmask.long.byte 0xC 8.--15. 1. "TXDAB1,USB PD Transmit Data Byte 1"
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hexmask.long.byte 0xC 0.--7. 1. "TXDAB0,USB PD Transmit Data Byte 0"
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line.long 0x10 "UTCPD_TXDA4,UTCPD Transmit Data4 Register"
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hexmask.long.byte 0x10 24.--31. 1. "TXDAB3,USB PD Transmit Data Byte 3"
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hexmask.long.byte 0x10 16.--23. 1. "TXDAB2,USB PD Transmit Data Byte 2"
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newline
|
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hexmask.long.byte 0x10 8.--15. 1. "TXDAB1,USB PD Transmit Data Byte 1"
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hexmask.long.byte 0x10 0.--7. 1. "TXDAB0,USB PD Transmit Data Byte 0"
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line.long 0x14 "UTCPD_TXDA5,UTCPD Transmit Data5 Register"
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hexmask.long.byte 0x14 24.--31. 1. "TXDAB3,USB PD Transmit Data Byte 3"
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hexmask.long.byte 0x14 16.--23. 1. "TXDAB2,USB PD Transmit Data Byte 2"
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newline
|
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hexmask.long.byte 0x14 8.--15. 1. "TXDAB1,USB PD Transmit Data Byte 1"
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hexmask.long.byte 0x14 0.--7. 1. "TXDAB0,USB PD Transmit Data Byte 0"
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line.long 0x18 "UTCPD_TXDA6,UTCPD Transmit Data6 Register"
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hexmask.long.byte 0x18 24.--31. 1. "TXDAB3,USB PD Transmit Data Byte 3"
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hexmask.long.byte 0x18 16.--23. 1. "TXDAB2,USB PD Transmit Data Byte 2"
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newline
|
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hexmask.long.byte 0x18 8.--15. 1. "TXDAB1,USB PD Transmit Data Byte 1"
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hexmask.long.byte 0x18 0.--7. 1. "TXDAB0,USB PD Transmit Data Byte 0"
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|
group.long 0xC0++0x53
|
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line.long 0x0 "UTCPD_VBVOL,UTCPD VBUS Voltage Register"
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bitfld.long 0x0 10.--11. "VBSCALE,VBUS Scale Factor" "0: VBUS measurement not scaled,1: VBUS measurement divided by 10,?,?"
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hexmask.long.word 0x0 0.--9. 1. "VBVOL,VBUS Voltage Measurement \n10-bit measurement of (VBUS / Scale Factor) \nCPU multiplies this value by the scale factor to obtain the voltage measurement. Voltages greater than or equal to 4V shall meet +/-2% absolute value or +/- 50mV whichever is.."
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line.long 0x4 "UTCPD_SKVBDCTH,UTCPD VBUS Sink disconnect threshold Register"
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hexmask.long.word 0x4 0.--9. 1. "SKVBDCTH,Sink VBUS Disconnect Threshold\n10-bit for voltage threshold with 25mV LSB. (Default 3.5V) \nA value of zero disables this threshold."
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line.long 0x8 "UTCPD_SPDGTH,UTCPD VBUS Stop Discharge threshold Register"
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hexmask.long.word 0x8 0.--9. 1. "SPDGTH,VBUS Stop Force Discharge Threshold\nThis value is used as a threshold hold for force discharge fail.\nThe default is 0.8V.\n\nThe CPU writes to this register to set the threshold at which a Source shall stop the Forced Discharge circuit when.."
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line.long 0xC "UTCPD_VBAMH,UTCPD VBUS voltage high alarm threshold Register"
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hexmask.long.word 0xC 0.--9. 1. "VBAMH,VBUS Voltage High Alarm Threshold \nVBUS voltage high alarm threshold register."
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line.long 0x10 "UTCPD_VBAML,UTCPD VBUS voltage low alarm threshold Register"
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hexmask.long.word 0x10 0.--9. 1. "VBAML,VBUS Voltage Low Alarm Threshold \nVBUS voltage low alarm threshold register."
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line.long 0x14 "UTCPD_VNDIS,UTCPD Vendor defined Interrupt Status Register"
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bitfld.long 0x14 5. "VCDGIS,VCONN Discharge Interrupt Status" "0: No VCONN discharge event,1: VCONN discharge event is detected"
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bitfld.long 0x14 3. "CRCERRIS,CRC Error Interrupt Status" "0: Cleared,1: The event has been detected"
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newline
|
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bitfld.long 0x14 1. "TXFRSIS,Fast Role Swap TX Interrupt Status" "0: Cleared,1: The event has been detected"
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bitfld.long 0x14 0. "RXFRSIS,Fast Role Swap RX Interrupt Status" "0: Cleared,1: The event has been detected"
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line.long 0x18 "UTCPD_VNDIE,UTCPD Vendor defined Interrupt Enable Register"
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bitfld.long 0x18 5. "VCDGIE,VCONN Discharge Interrupt Enable" "0: VCONN discharge interrupt is Disabled,1: VCONN discharge interrupt is Enabled"
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bitfld.long 0x18 3. "CRCERRIE,CRC Error Interrupt Enable" "0: CRC error interrupt is Disabled,1: CRC error interrupt is Enabled"
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newline
|
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bitfld.long 0x18 1. "TXFRSIE,Fast Role Swap TX Interrupt Enable" "0: Fast role swap TX interrupt is Disabled,1: Fast role swap TX interrupt is Enabled"
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bitfld.long 0x18 0. "RXFRSIE,Fast Role Swap RX Interrupt Enable" "0: Fast role swap RX interrupt is Disabled,1: Fast role swap RX interrupt is Enabled"
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line.long 0x1C "UTCPD_MUXSEL,UTCPD Mux Select Register"
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bitfld.long 0x1C 29. "CC2FRSS,CC2 VCONN Fast Role Swap Select" "0: Merged CC1 and CC2 Fast Role Swap signal,1: CC2 VCONN discharge signal"
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bitfld.long 0x1C 28. "CC2VCENS,CC2 VCONN Enable Select" "0: Merged CC1 and CC2 VCONN enable signal,1: CC2 VCONN enable signal"
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newline
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bitfld.long 0x1C 25. "CC1FRSS,CC1 VCONN Fast Role Swap Select" "0: Merged CC1 and CC2 VCONN Fast Role Swap signal,1: CC1 VCONN Fast Role Swap signal"
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bitfld.long 0x1C 24. "CC1VCENS,CC1 VCONN Enable Select" "0: Merged CC1 and CC2 VCONN enable signal,1: CC1 VCONN enable signal"
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newline
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hexmask.long.byte 0x1C 17.--21. 1. "ADCSELVC,ADC Channel Select for VCONN\nADC result will be latched into VC_VOL_MEA register once ADC_CSEL_VC matches ADC_CHSEL and ADC finishes."
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hexmask.long.byte 0x1C 12.--16. 1. "ADCSELVB,ADC Channel Select for VBUS\nADC result will be latched into VB_VOL_MEA register once ADC_CSEL_VB matches ADC_CHSEL and ADC finishes."
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newline
|
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bitfld.long 0x1C 8.--10. "FVBS,Force off VBUS Select" "0: ENIT0,1: EINT1,?,?,?,?,?,?"
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|
bitfld.long 0x1C 4.--6. "VCOCS,VCONN Overcurrent Source Select" "0: EINT0,1: EINT1,?,?,?,?,?,?"
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|
newline
|
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bitfld.long 0x1C 0.--2. "VBOCS,VBUS Overcurrent Source Select" "0: EINT0,1: EINT1,?,?,?,?,?,?"
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|
line.long 0x20 "UTCPD_VCDGCTL,UTCPD VCONN Discharge Control Register"
|
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bitfld.long 0x20 1. "VCDGEN,VCONN Discharge Enable" "0: VCONN discharge is Disabled,1: VCONN discharge isEnabled"
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bitfld.long 0x20 0. "VCUVDTEN,VCONN Under Voltage Detect Enable" "0: VCONN under voltage detection is Disabled,1: VCONN under voltage detection is Enabled"
|
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line.long 0x24 "UTCPD_PHYSLEW,UTCPD PHY Slew Rate Control Register"
|
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bitfld.long 0x24 4.--6. "TXFTRIM,TX Trim Falling Slew Rate\nIt is for BMC eye diagram.\nTrim PHY TX falling slew rate. (from ROMMAP)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 0.--2. "TXRTRIM,TX Trim Rising Slew Rate \nIt is for BMC eye diagram.\nTrim PHY TX Rising slew rate (from ROMMAP)" "0,1,2,3,4,5,6,7"
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line.long 0x28 "UTCPD_ADGTM,UTCPD Auto Discharge Time Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. "ADGTM,Auto Discharge time"
|
|
line.long 0x2C "UTCPD_VSAFE0V,UTCPD Auto Discharge VSAFE0V Register"
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hexmask.long.word 0x2C 0.--9. 1. "VSAFE0V,Set the vSafe0V voltage level\nSet the vSafe0V voltage level."
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line.long 0x30 "UTCPD_VSAFE5V,UTCPD VSAFE5V Register"
|
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hexmask.long.word 0x30 0.--9. 1. "VSAFE5V,Set the vSafe5V voltage level \nFor fast role swap voltage comparison."
|
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line.long 0x34 "UTCPD_RATIO,UTCPD DRP Toggle Ratio Register"
|
|
bitfld.long 0x34 6. "ADCAVG,ADC Moving Average Enable \nIf this bit is enabled average the ADC value for 4 times." "0,1"
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bitfld.long 0x34 3. "VBSEL,VBUS Voltage Selection\nSelect comparing value (vbus_voltage_s) during VBUS discharge determines to stop discharging or not." "0: VBUS voltage value from ADC only when VBMONI..,1: VBUS voltage value from ADC"
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newline
|
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bitfld.long 0x34 0.--2. "DRPRATIO,Percent of Time that a DRP Shall Advertise Source Sink During tDRP" "0: 50:50 (Sink : Source),1: 40:60 (Sink : Source),?,?,?,?,?,?"
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line.long 0x38 "UTCPD_INTFRAME,UTCPD Inter-Frame Time Register"
|
|
hexmask.long.byte 0x38 0.--7. 1. "INTFRAME,USB PD Inter Frame Gap \nEach unit time: 83ns (12 MHz RC)"
|
|
line.long 0x3C "UTCPD_VBOVTH,UTCPD VBUS Over Voltage Threshold Register"
|
|
hexmask.long.word 0x3C 0.--9. 1. "VBOVTH,VBUS Over Voltage Threshold\nThis value defines the VBUS over voltage threshold\n10-bit for voltage threshold with 25mV LSB."
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line.long 0x40 "UTCPD_VNDINIT,UTCPD Vendor Initial Register"
|
|
bitfld.long 0x40 4.--6. "DVCAPDEF,Device Capability Default Setting \nWrite the Register will update the value to Device_Cap.RoleSupport ROLE_CONTROL and MESSAGE_HEADER_INFO register please refer the following table. (DevCap_DEF Table)" "0,1,2,3,4,5,6,7"
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line.long 0x44 "UTCPD_BMCTXBP,UTCPD BMC TX Bit Period Register"
|
|
hexmask.long.byte 0x44 0.--7. 1. "BMCTXBP,BMC Tx Bit Period\nIt's for BMC eye diagram."
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line.long 0x48 "UTCPD_BMCTXDU,UTCPD BMC TX Duty Register"
|
|
bitfld.long 0x48 7. "DUOFFS1,BMC Tx Duty Offset Parameter 1 \nIt's for BMC eye diagram." "0: Increase duty offset? (+),1: Decrease duty offset? (-)"
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|
hexmask.long.byte 0x48 0.--6. 1. "DUOFFS2,BMC Tx Duty Offset Parameter 2 \nIt's for BMC eye diagram.\nOffset count value."
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|
line.long 0x4C "UTCPD_VCPSVOL,VCONN Present Voltage Register"
|
|
hexmask.long.word 0x4C 0.--9. 1. "VCPSVOL,VCONN Present Voltage"
|
|
line.long 0x50 "UTCPD_VCUV,VCONN Under Voltage Register"
|
|
hexmask.long.word 0x50 0.--9. 1. "VCUV,VCONN under Voltage Comparator"
|
|
group.long 0x118++0xB
|
|
line.long 0x0 "UTCPD_BMCSLICE,UTCPD BMC SLICE Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "VTRIM,VTRIM"
|
|
bitfld.long 0x0 24.--26. "TRIMVB20,Trim VBUS divided 20" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x0 20.--22. "TRIMVB10,Trim VBUS divided 10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "TRIMV1P1,TRIMV1P1" "0,1,2,3,4,5,6,7"
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|
newline
|
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hexmask.long.byte 0x0 12.--15. 1. "TRIMRP,TRIMRP"
|
|
bitfld.long 0x0 8.--10. "TRIMRD,TRIMRD" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "SLICEM,TX Slice Middle Level Control\nMiddle level slice control (The LSB is 20mV.)" "0: 0.48V,?,?,?,?,?,?,?"
|
|
bitfld.long 0x0 2.--3. "SLICEH,TX Slice High Level Control\nHigh level slice control (The LSB is 20mV.)" "0: 0.84V (Default),1: 0.86V,?,?"
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|
newline
|
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bitfld.long 0x0 0.--1. "SLICEL,TX Slice Low Level Control\nLow level slice control (The LSB is 20mV.)" "0: 0.18V,1: 0.2V,?,?"
|
|
line.long 0x4 "UTCPD_PHYCTL,UTCPD PHY Power Control Register"
|
|
bitfld.long 0x4 1. "DBCTL,Dead Battery Control\nThe dead battery function must be supported by system applications. (e.g. T and CCx port which can be connected if dead battery function is enabled)." "0: Dead Battery circuit control internal Rd/Rp,1: Role Control Register control internal Rd/Rp"
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|
bitfld.long 0x4 0. "PHYPWR,Analog PHY Power\nThe default of Analog PHY power is off before UTCPD clock is available. Once UTCPD clock is on the analog PHY power will be on as well." "0: Power down PHY,1: Enable PHY"
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|
line.long 0x8 "UTCPD_FRSRXCTL,UTCPD CC Fast Swap RX Control Register"
|
|
bitfld.long 0x8 3. "FRSRXEN,CC Receive Fast Swap RX Enable" "0: CC receive fast swap RX Disabled,1: CC receive fast swap RX Enabled"
|
|
bitfld.long 0x8 2. "FRSDVVB,CC Receive Fast Swap and Auto Drive Source VBUS" "0: CC receive fast swap and auto drive source VBUS..,1: CC receive fast swap and auto drive source VBUS.."
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|
newline
|
|
bitfld.long 0x8 0. "FRSTX,CC Transmitter Fast Swap Signal \nPulse width is 85us." "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "UTCPD_VCVOL,UTCPD VCONN Voltage Measurement Register"
|
|
hexmask.long.word 0x0 0.--9. 1. "VCVOL,VCONN Voltage Measurement\nThe LSB is 25Mv."
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "UTCPD_CLKINFO,UTCPD Clock Information Register"
|
|
bitfld.long 0x0 4. "WKEN,Wakeup Enable" "0: UTCPD wakeup function Disabled,1: UTCPD wakeup function Enabled"
|
|
bitfld.long 0x0 0. "ReadyFlag,RC32K Domain Ready Flag Check\nRC32K domain ready flag is checked if the register value is loaded to RC32K domain by reading this flag." "0: The RC32K signal is not ready,1: The RC32K signal is ready"
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40040000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "WDT_CTL,WDT Control Register"
|
|
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
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|
rbitfld.long 0x0 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 4 * WDT_CLK.." "0: Setting WDTEN bit is completed and WDT is ready,1: Setting WDTEN bit is synchronizing and not.."
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|
newline
|
|
bitfld.long 0x0 29. "PDRSTCNT,Reset Counter When Entering Power Down Enable Bit" "0: WDT up counter will keep going no matter CPU..,1: Reset WDT up counter value to 0 when entering.."
|
|
hexmask.long.byte 0x0 8.--11. 1. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese four bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register."
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bitfld.long 0x0 7. "WDTEN,WDT Enable Bit (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111 this bit is forced as 1 and user cannot change.." "0: WDT Disabled (This action will reset the..,1: This bit is write protected"
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bitfld.long 0x0 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
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bitfld.long 0x0 5. "WKF,WDT Time-out Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT\nNote: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if WDT.."
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bitfld.long 0x0 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT time-out..,1: This bit is write protected"
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bitfld.long 0x0 3. "IF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
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bitfld.long 0x0 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
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bitfld.long 0x0 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected." "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
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line.long 0x4 "WDT_ALTCTL,WDT Alternative Control Register"
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bitfld.long 0x4 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by programming 0x5AA5 to prevent WDT time-out reset happened. User can select a suitable setting of RSTDSEL.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: This bit is write protected,2: This register will be reset to 0 if WDT time-out..,?"
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wgroup.long 0x8++0x3
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line.long 0x0 "WDT_RSTCNT,WDT Reset Counter Register"
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hexmask.long 0x0 0.--31. 1. "RSTCNT,WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.\nNote: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active."
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tree.end
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tree "WWDT (Window Watchdog Timer)"
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base ad:0x40096000
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wgroup.long 0x0++0x3
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line.long 0x0 "WWDT_RLDCNT,WWDT Reload Counter Register"
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hexmask.long 0x0 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.."
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group.long 0x4++0x7
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line.long 0x0 "WWDT_CTL,WWDT Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nNote: WWDT down counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
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hexmask.long.byte 0x0 16.--21. 1. "CMPDAT,WWDT Window Compare\nSet this register to adjust the valid reload window. \nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when.."
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hexmask.long.byte 0x0 8.--11. 1. "PSCSEL,WWDT Counter Prescale Period Selection"
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bitfld.long 0x0 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU." "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
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bitfld.long 0x0 0. "WWDTEN,WWDT Enable Bit" "0: WWDT counter is stopped,1: WWDT counter starts counting"
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line.long 0x4 "WWDT_STATUS,WWDT Status Register"
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bitfld.long 0x4 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
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bitfld.long 0x4 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: WWDT counter value matches CMPDAT"
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rgroup.long 0xC++0x3
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line.long 0x0 "WWDT_CNT,WWDT Counter Value Register"
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hexmask.long.byte 0x0 0.--5. 1. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value."
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tree.end
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AUTOINDENT.OFF
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