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Work/Src/Gen4_R-Car_Trace32/2_Trunk/perrp235x.per
woody 6daf21a46d add
2026-06-16 12:20:14 +09:00

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; --------------------------------------------------------------------------------
; @Title: RP235x On-Chip Peripherals
; @Props: Released
; @Author: KRZ, NEJ
; @Changelog: 2024-10-01 KRZ
; 2024-11-28 NEJ
; @Manufacturer: RASPBERRYPI
; @Doc: Generated (TRACE32, build: 174890.), based on: RP2350.svd (Ver. 0.1)
; @Core: Cortex-M33F
; @Chip: RP2350A, RP2350B, RP2354A, RP2354B
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; Copyright (c) 2024 Raspberry Pi Ltd.
;
; SPDX-License-Identifier: BSD-3-Clause
; --------------------------------------------------------------------------------
; $Id: perrp235x.per 19151 2025-03-04 13:03:16Z pegold $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M33F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
textline " "
bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes"
bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes"
group.long 0x0C++0x0F
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core"
bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
textline " "
bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x0C "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main Extension"
newline
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xD21=Cortex-M33"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline " "
bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
textline " "
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
line.long 0x14 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault"
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault"
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault"
textline " "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
textline " "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
textline " "
bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
textline " "
bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
textline " "
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred"
textline " "
bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "UFSR,Usage Fault Status Register"
eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
textline " "
eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
textline " "
eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x03
line.long 0x00 "HFSR,HardFault Status Register"
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
group.long 0xD8C++0x03
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
else
hgroup.long 0xD8C++0x03
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
endif
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x03
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
textline " "
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
textline " "
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
textline " "
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline " "
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
endif
rgroup.long 0xD80++0x03
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
textline " "
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline " "
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
wgroup.long 0xF58++0x23
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
rgroup.long 0xD4C++0x03
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
textline " "
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
rgroup.long 0xD54++0x03
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD5C++0x03
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
rgroup.long 0xD60++0x03
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
rgroup.long 0xD64++0x03
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
rgroup.long 0xD68++0x03
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
textline " "
bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline " "
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
rgroup.long 0xD6C++0x03
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline " "
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
textline " "
bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
rgroup.long 0xD70++0x03
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
textline " "
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
tree.end
tree "CoreSight Identification Registers"
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "DPIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DPIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DPIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DPIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DCIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DCIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DCIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
endif
tree.end
newline
group.long 0xDC0++0x07
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Security Attribution Unit (SAU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
group.long 0xDD0++0x03
line.long 0x00 "SAU_CTRL,SAU Control Register"
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
rgroup.long 0xDD4++0x03
line.long 0x00 "SAU_TYPE,SAU Type Register"
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xDD8++0x03
line.long 0x00 "SAU_RNR,SAU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
tree.close "SAU regions"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
group.long 0xDDC++0x03 "Region 0"
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
group.long 0xDDC++0x03 "Region 1"
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
group.long 0xDDC++0x03 "Region 2"
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
group.long 0xDDC++0x03 "Region 3"
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
group.long 0xDDC++0x03 "Region 4"
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
group.long 0xDDC++0x03 "Region 5"
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
group.long 0xDDC++0x03 "Region 6"
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
group.long 0xDDC++0x03 "Region 7"
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
else
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
tree.end
group.long 0xDE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
group.long 0xDE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
group.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
width 24.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x104++0x03
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x104++0x03
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x108++0x03
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x108++0x03
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x10C++0x03
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x10C++0x03
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x110++0x03
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x110++0x03
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x114++0x03
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x114++0x03
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x118++0x03
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x118++0x03
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x11C++0x03
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x11C++0x03
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x120++0x03
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x120++0x03
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x124++0x03
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x124++0x03
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x128++0x03
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x128++0x03
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x12C++0x03
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x12C++0x03
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x130++0x03
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x130++0x03
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x134++0x03
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x134++0x03
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x138++0x03
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x138++0x03
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x13C++0x03
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x13C++0x03
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
width 24.
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x204++0x03
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x204++0x03
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x208++0x03
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x208++0x03
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x20C++0x03
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x20C++0x03
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x210++0x03
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x210++0x03
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x214++0x03
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x214++0x03
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x218++0x03
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x218++0x03
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x21C++0x03
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x21C++0x03
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x220++0x03
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x220++0x03
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x224++0x03
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x224++0x03
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x228++0x03
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x228++0x03
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x22C++0x03
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x22C++0x03
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x230++0x03
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x230++0x03
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x234++0x03
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x234++0x03
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x238++0x03
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x238++0x03
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x23C++0x03
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x23C++0x03
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
width 11.
tree "Interrupt Active Bit Registers"
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE0,Active Bit Register 0"
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
rgroup.long 0x304++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x304++0x03
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
rgroup.long 0x308++0x03
line.long 0x00 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x308++0x03
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
rgroup.long 0x30C++0x03
line.long 0x00 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x30C++0x03
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
rgroup.long 0x310++0x03
line.long 0x00 "ACTIVE4,Active Bit Register 4"
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x310++0x03
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
rgroup.long 0x314++0x03
line.long 0x00 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x314++0x03
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
rgroup.long 0x318++0x03
line.long 0x00 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x318++0x03
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
rgroup.long 0x31C++0x03
line.long 0x00 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x31C++0x03
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
rgroup.long 0x320++0x03
line.long 0x00 "ACTIVE8,Active Bit Register 8"
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x320++0x03
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
rgroup.long 0x324++0x03
line.long 0x00 "ACTIVE9,Active Bit Register 9"
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x324++0x03
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
rgroup.long 0x328++0x03
line.long 0x00 "ACTIVE10,Active Bit Register 10"
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x328++0x03
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
rgroup.long 0x32C++0x03
line.long 0x00 "ACTIVE11,Active Bit Register 11"
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x32C++0x03
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
rgroup.long 0x330++0x03
line.long 0x00 "ACTIVE12,Active Bit Register 12"
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x330++0x03
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
rgroup.long 0x334++0x03
line.long 0x00 "ACTIVE13,Active Bit Register 13"
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x334++0x03
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
rgroup.long 0x338++0x03
line.long 0x00 "ACTIVE14,Active Bit Register 14"
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x338++0x03
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
rgroup.long 0x33C++0x03
line.long 0x00 "ACTIVE15,Active Bit Register 15"
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x33C++0x03
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
endif
tree.end
width 13.
tree "Interrupt Target Non-Secure Registers"
group.long 0x380++0x03
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x384++0x03
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
else
hgroup.long 0x384++0x03
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x388++0x03
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
else
hgroup.long 0x388++0x03
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x38C++0x03
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
else
hgroup.long 0x38C++0x03
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x390++0x03
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
else
hgroup.long 0x390++0x03
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x394++0x03
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
else
hgroup.long 0x394++0x03
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x398++0x03
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
else
hgroup.long 0x398++0x03
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x39C++0x03
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
else
hgroup.long 0x39C++0x03
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x3A0++0x03
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
else
hgroup.long 0x3A0++0x03
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x3A4++0x03
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
else
hgroup.long 0x3A4++0x03
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x3A8++0x03
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
else
hgroup.long 0x3A8++0x03
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x3AC++0x03
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
else
hgroup.long 0x3AC++0x03
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x3B0++0x03
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
else
hgroup.long 0x3B0++0x03
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x3B4++0x03
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
else
hgroup.long 0x3B4++0x03
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x3B8++0x03
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
else
hgroup.long 0x3B8++0x03
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
group.long 0x3BC++0x03
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
else
hgroup.long 0x3BC++0x03
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
endif
tree.end
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x420++0x1F
line.long 0x0 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
line.long 0x4 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
line.long 0x8 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
line.long 0xC "IPR11,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
line.long 0x10 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
line.long 0x14 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
line.long 0x18 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
line.long 0x1C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
else
hgroup.long 0x420++0x1F
hide.long 0x0 "IPR8,Interrupt Priority Register"
hide.long 0x4 "IPR9,Interrupt Priority Register"
hide.long 0x8 "IPR10,Interrupt Priority Register"
hide.long 0xC "IPR11,Interrupt Priority Register"
hide.long 0x10 "IPR12,Interrupt Priority Register"
hide.long 0x14 "IPR13,Interrupt Priority Register"
hide.long 0x18 "IPR14,Interrupt Priority Register"
hide.long 0x1C "IPR15,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x440++0x1F
line.long 0x0 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
line.long 0x4 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
line.long 0x8 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
line.long 0xC "IPR19,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
line.long 0x10 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
line.long 0x14 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
line.long 0x18 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
line.long 0x1C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
else
hgroup.long 0x440++0x1F
hide.long 0x0 "IPR16,Interrupt Priority Register"
hide.long 0x4 "IPR17,Interrupt Priority Register"
hide.long 0x8 "IPR18,Interrupt Priority Register"
hide.long 0xC "IPR19,Interrupt Priority Register"
hide.long 0x10 "IPR20,Interrupt Priority Register"
hide.long 0x14 "IPR21,Interrupt Priority Register"
hide.long 0x18 "IPR22,Interrupt Priority Register"
hide.long 0x1C "IPR23,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x460++0x1F
line.long 0x0 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
line.long 0x4 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
line.long 0x8 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
line.long 0xC "IPR27,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
line.long 0x10 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
line.long 0x14 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
line.long 0x18 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
line.long 0x1C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
else
hgroup.long 0x460++0x1F
hide.long 0x0 "IPR24,Interrupt Priority Register"
hide.long 0x4 "IPR25,Interrupt Priority Register"
hide.long 0x8 "IPR26,Interrupt Priority Register"
hide.long 0xC "IPR27,Interrupt Priority Register"
hide.long 0x10 "IPR28,Interrupt Priority Register"
hide.long 0x14 "IPR29,Interrupt Priority Register"
hide.long 0x18 "IPR30,Interrupt Priority Register"
hide.long 0x1C "IPR31,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x480++0x1F
line.long 0x0 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
line.long 0x4 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
line.long 0x8 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
line.long 0xC "IPR35,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
line.long 0x10 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
line.long 0x14 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
line.long 0x18 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
line.long 0x1C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
else
hgroup.long 0x480++0x1F
hide.long 0x0 "IPR32,Interrupt Priority Register"
hide.long 0x4 "IPR33,Interrupt Priority Register"
hide.long 0x8 "IPR34,Interrupt Priority Register"
hide.long 0xC "IPR35,Interrupt Priority Register"
hide.long 0x10 "IPR36,Interrupt Priority Register"
hide.long 0x14 "IPR37,Interrupt Priority Register"
hide.long 0x18 "IPR38,Interrupt Priority Register"
hide.long 0x1C "IPR39,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x4A0++0x1F
line.long 0x0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
line.long 0x4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
line.long 0x8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
line.long 0xC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
line.long 0x10 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
line.long 0x14 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
line.long 0x18 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
line.long 0x1C "IPR47,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
else
hgroup.long 0x4A0++0x1F
hide.long 0x0 "IPR40,Interrupt Priority Register"
hide.long 0x4 "IPR41,Interrupt Priority Register"
hide.long 0x8 "IPR42,Interrupt Priority Register"
hide.long 0xC "IPR43,Interrupt Priority Register"
hide.long 0x10 "IPR44,Interrupt Priority Register"
hide.long 0x14 "IPR45,Interrupt Priority Register"
hide.long 0x18 "IPR46,Interrupt Priority Register"
hide.long 0x1C "IPR47,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x4C0++0x1F
line.long 0x0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
line.long 0x4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
line.long 0x8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
line.long 0xC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
line.long 0x10 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
line.long 0x14 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
line.long 0x18 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
line.long 0x1C "IPR55,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
else
hgroup.long 0x4C0++0x1F
hide.long 0x0 "IPR48,Interrupt Priority Register"
hide.long 0x4 "IPR49,Interrupt Priority Register"
hide.long 0x8 "IPR50,Interrupt Priority Register"
hide.long 0xC "IPR51,Interrupt Priority Register"
hide.long 0x10 "IPR52,Interrupt Priority Register"
hide.long 0x14 "IPR53,Interrupt Priority Register"
hide.long 0x18 "IPR54,Interrupt Priority Register"
hide.long 0x1C "IPR55,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x4E0++0x1F
line.long 0x0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
line.long 0x4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
line.long 0x8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
line.long 0xC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
line.long 0x10 "IPR60,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority"
line.long 0x14 "IPR61,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority"
line.long 0x18 "IPR62,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority"
line.long 0x1C "IPR63,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority"
else
hgroup.long 0x4E0++0x1F
hide.long 0x0 "IPR56,Interrupt Priority Register"
hide.long 0x4 "IPR57,Interrupt Priority Register"
hide.long 0x8 "IPR58,Interrupt Priority Register"
hide.long 0xC "IPR59,Interrupt Priority Register"
hide.long 0x10 "IPR60,Interrupt Priority Register"
hide.long 0x14 "IPR61,Interrupt Priority Register"
hide.long 0x18 "IPR62,Interrupt Priority Register"
hide.long 0x1C "IPR63,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x500++0x1F
line.long 0x0 "IPR64,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority"
line.long 0x4 "IPR65,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority"
line.long 0x8 "IPR66,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority"
line.long 0xC "IPR67,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority"
line.long 0x10 "IPR68,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority"
line.long 0x14 "IPR69,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority"
line.long 0x18 "IPR70,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority"
line.long 0x1C "IPR71,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority"
else
hgroup.long 0x500++0x1F
hide.long 0x0 "IPR64,Interrupt Priority Register"
hide.long 0x4 "IPR65,Interrupt Priority Register"
hide.long 0x8 "IPR66,Interrupt Priority Register"
hide.long 0xC "IPR67,Interrupt Priority Register"
hide.long 0x10 "IPR68,Interrupt Priority Register"
hide.long 0x14 "IPR69,Interrupt Priority Register"
hide.long 0x18 "IPR70,Interrupt Priority Register"
hide.long 0x1C "IPR71,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x520++0x1F
line.long 0x0 "IPR72,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority"
line.long 0x4 "IPR73,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority"
line.long 0x8 "IPR74,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority"
line.long 0xC "IPR75,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority"
line.long 0x10 "IPR76,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority"
line.long 0x14 "IPR77,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority"
line.long 0x18 "IPR78,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority"
line.long 0x1C "IPR79,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority"
else
hgroup.long 0x520++0x1F
hide.long 0x0 "IPR72,Interrupt Priority Register"
hide.long 0x4 "IPR73,Interrupt Priority Register"
hide.long 0x8 "IPR74,Interrupt Priority Register"
hide.long 0xC "IPR75,Interrupt Priority Register"
hide.long 0x10 "IPR76,Interrupt Priority Register"
hide.long 0x14 "IPR77,Interrupt Priority Register"
hide.long 0x18 "IPR78,Interrupt Priority Register"
hide.long 0x1C "IPR79,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x540++0x1F
line.long 0x0 "IPR80,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority"
line.long 0x4 "IPR81,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority"
line.long 0x8 "IPR82,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority"
line.long 0xC "IPR83,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority"
line.long 0x10 "IPR84,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority"
line.long 0x14 "IPR85,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority"
line.long 0x18 "IPR86,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority"
line.long 0x1C "IPR87,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority"
else
hgroup.long 0x540++0x1F
hide.long 0x0 "IPR80,Interrupt Priority Register"
hide.long 0x4 "IPR81,Interrupt Priority Register"
hide.long 0x8 "IPR82,Interrupt Priority Register"
hide.long 0xC "IPR83,Interrupt Priority Register"
hide.long 0x10 "IPR84,Interrupt Priority Register"
hide.long 0x14 "IPR85,Interrupt Priority Register"
hide.long 0x18 "IPR86,Interrupt Priority Register"
hide.long 0x1C "IPR87,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x560++0x1F
line.long 0x0 "IPR88,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority"
line.long 0x4 "IPR89,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority"
line.long 0x8 "IPR90,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority"
line.long 0xC "IPR91,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority"
line.long 0x10 "IPR92,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority"
line.long 0x14 "IPR93,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority"
line.long 0x18 "IPR94,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority"
line.long 0x1C "IPR95,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority"
else
hgroup.long 0x560++0x1F
hide.long 0x0 "IPR88,Interrupt Priority Register"
hide.long 0x4 "IPR89,Interrupt Priority Register"
hide.long 0x8 "IPR90,Interrupt Priority Register"
hide.long 0xC "IPR91,Interrupt Priority Register"
hide.long 0x10 "IPR92,Interrupt Priority Register"
hide.long 0x14 "IPR93,Interrupt Priority Register"
hide.long 0x18 "IPR94,Interrupt Priority Register"
hide.long 0x1C "IPR95,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x580++0x1F
line.long 0x0 "IPR96,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority"
line.long 0x4 "IPR97,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority"
line.long 0x8 "IPR98,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority"
line.long 0xC "IPR99,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority"
line.long 0x10 "IPR100,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority"
line.long 0x14 "IPR101,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority"
line.long 0x18 "IPR102,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority"
line.long 0x1C "IPR103,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority"
else
hgroup.long 0x580++0x1F
hide.long 0x0 "IPR96,Interrupt Priority Register"
hide.long 0x4 "IPR97,Interrupt Priority Register"
hide.long 0x8 "IPR98,Interrupt Priority Register"
hide.long 0xC "IPR99,Interrupt Priority Register"
hide.long 0x10 "IPR100,Interrupt Priority Register"
hide.long 0x14 "IPR101,Interrupt Priority Register"
hide.long 0x18 "IPR102,Interrupt Priority Register"
hide.long 0x1C "IPR103,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x5A0++0x1F
line.long 0x0 "IPR104,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority"
line.long 0x4 "IPR105,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority"
line.long 0x8 "IPR106,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority"
line.long 0xC "IPR107,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority"
line.long 0x10 "IPR108,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority"
line.long 0x14 "IPR109,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority"
line.long 0x18 "IPR110,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority"
line.long 0x1C "IPR111,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority"
else
hgroup.long 0x5A0++0x1F
hide.long 0x0 "IPR104,Interrupt Priority Register"
hide.long 0x4 "IPR105,Interrupt Priority Register"
hide.long 0x8 "IPR106,Interrupt Priority Register"
hide.long 0xC "IPR107,Interrupt Priority Register"
hide.long 0x10 "IPR108,Interrupt Priority Register"
hide.long 0x14 "IPR109,Interrupt Priority Register"
hide.long 0x18 "IPR110,Interrupt Priority Register"
hide.long 0x1C "IPR111,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x5C0++0x1F
line.long 0x0 "IPR112,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority"
line.long 0x4 "IPR113,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority"
line.long 0x8 "IPR114,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority"
line.long 0xC "IPR115,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority"
line.long 0x10 "IPR116,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority"
line.long 0x14 "IPR117,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority"
line.long 0x18 "IPR118,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority"
line.long 0x1C "IPR119,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority"
else
hgroup.long 0x5C0++0x1F
hide.long 0x0 "IPR112,Interrupt Priority Register"
hide.long 0x4 "IPR113,Interrupt Priority Register"
hide.long 0x8 "IPR114,Interrupt Priority Register"
hide.long 0xC "IPR115,Interrupt Priority Register"
hide.long 0x10 "IPR116,Interrupt Priority Register"
hide.long 0x14 "IPR117,Interrupt Priority Register"
hide.long 0x18 "IPR118,Interrupt Priority Register"
hide.long 0x1C "IPR119,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif (CORENAME()=="CORTEXM33F")
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
newline
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
newline
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
newline
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
newline
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
newline
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
newline
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
newline
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 13.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
newline
group.long 0xE04++0x07
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
rgroup.long 0xFB8++0x03
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
newline
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 12.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline " "
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address"
else
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
tree "CoreSight Identification Registers"
width 12.
rgroup.long 0xFCC++0x03
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "FP_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "FP_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "FP_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "FP_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "FP_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "FP_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "FP_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 16.
group.long 0x00++0x03
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
textline " "
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline " "
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
group.long 0x04++0x03
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
group.long 0x08++0x17
line.long 0x00 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter"
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter"
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
endif
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline " "
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
endif
group.long (0x20+0x08)++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
endif
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
endif
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
endif
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
tree "CoreSight Identification Registers"
width 13.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFCC++0x03
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
rgroup.long 0xFE0++0x0F
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DWT_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DWT_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DWT_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ACCESSCTRL (Access Control Registers)"
base ad:0x40060000
group.long 0x0++0x7
line.long 0x0 "LOCK,Once a LOCK bit is written to 1. ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure. Privileged processor or debugger."
bitfld.long 0x0 3. "DEBUG" "0,1"
rbitfld.long 0x0 2. "DMA" "0,1"
bitfld.long 0x0 1. "CORE1" "0,1"
bitfld.long 0x0 0. "CORE0" "0,1"
line.long 0x4 "FORCE_CORE_NS,Force core 1's bus accesses to always be Non-secure. no matter the core's internal state."
bitfld.long 0x4 1. "CORE1" "0,1"
wgroup.long 0x8++0x3
line.long 0x0 "CFGRESET,Write 1 to reset all ACCESSCTRL configuration. except for the LOCK and FORCE_CORE_NS registers."
bitfld.long 0x0 0. "CFGRESET" "0,1"
group.long 0xC++0xDF
line.long 0x0 "GPIO_NSMASK0,Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure. Privileged processor or debugger."
hexmask.long 0x0 0.--31. 1. "GPIO_NSMASK0"
line.long 0x4 "GPIO_NSMASK1,Control whether GPIO32..47 are accessible to Non-secure code. and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure. Privileged processor or debugger."
hexmask.long.byte 0x4 28.--31. 1. "QSPI_SD"
bitfld.long 0x4 27. "QSPI_CSN" "0,1"
bitfld.long 0x4 26. "QSPI_SCK" "0,1"
bitfld.long 0x4 25. "USB_DM" "0,1"
bitfld.long 0x4 24. "USB_DP" "0,1"
hexmask.long.word 0x4 0.--15. 1. "GPIO"
line.long 0x8 "ROM,Control whether debugger. DMA. core 0 and core 1 can access ROM. and at what security/privilege levels they can do so."
bitfld.long 0x8 7. "DBG,If 1 ROM can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x8 6. "DMA,If 1 ROM can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x8 5. "CORE1,If 1 ROM can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x8 4. "CORE0,If 1 ROM can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x8 3. "SP,If 1 ROM can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x8 2. "SU,If 1 and SP is also set ROM can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x8 1. "NSP,If 1 ROM can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x8 0. "NSU,If 1 and NSP is also set ROM can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xC "XIP_MAIN,Control whether debugger. DMA. core 0 and core 1 can access XIP_MAIN. and at what security/privilege levels they can do so."
bitfld.long 0xC 7. "DBG,If 1 XIP_MAIN can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC 6. "DMA,If 1 XIP_MAIN can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC 5. "CORE1,If 1 XIP_MAIN can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC 4. "CORE0,If 1 XIP_MAIN can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC 3. "SP,If 1 XIP_MAIN can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xC 2. "SU,If 1 and SP is also set XIP_MAIN can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xC 1. "NSP,If 1 XIP_MAIN can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xC 0. "NSU,If 1 and NSP is also set XIP_MAIN can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x10 "SRAM0,Control whether debugger. DMA. core 0 and core 1 can access SRAM0. and at what security/privilege levels they can do so."
bitfld.long 0x10 7. "DBG,If 1 SRAM0 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x10 6. "DMA,If 1 SRAM0 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x10 5. "CORE1,If 1 SRAM0 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x10 4. "CORE0,If 1 SRAM0 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x10 3. "SP,If 1 SRAM0 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x10 2. "SU,If 1 and SP is also set SRAM0 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x10 1. "NSP,If 1 SRAM0 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x10 0. "NSU,If 1 and NSP is also set SRAM0 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x14 "SRAM1,Control whether debugger. DMA. core 0 and core 1 can access SRAM1. and at what security/privilege levels they can do so."
bitfld.long 0x14 7. "DBG,If 1 SRAM1 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x14 6. "DMA,If 1 SRAM1 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x14 5. "CORE1,If 1 SRAM1 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x14 4. "CORE0,If 1 SRAM1 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x14 3. "SP,If 1 SRAM1 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x14 2. "SU,If 1 and SP is also set SRAM1 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x14 1. "NSP,If 1 SRAM1 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x14 0. "NSU,If 1 and NSP is also set SRAM1 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x18 "SRAM2,Control whether debugger. DMA. core 0 and core 1 can access SRAM2. and at what security/privilege levels they can do so."
bitfld.long 0x18 7. "DBG,If 1 SRAM2 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x18 6. "DMA,If 1 SRAM2 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x18 5. "CORE1,If 1 SRAM2 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x18 4. "CORE0,If 1 SRAM2 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x18 3. "SP,If 1 SRAM2 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x18 2. "SU,If 1 and SP is also set SRAM2 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x18 1. "NSP,If 1 SRAM2 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x18 0. "NSU,If 1 and NSP is also set SRAM2 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x1C "SRAM3,Control whether debugger. DMA. core 0 and core 1 can access SRAM3. and at what security/privilege levels they can do so."
bitfld.long 0x1C 7. "DBG,If 1 SRAM3 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x1C 6. "DMA,If 1 SRAM3 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x1C 5. "CORE1,If 1 SRAM3 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x1C 4. "CORE0,If 1 SRAM3 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x1C 3. "SP,If 1 SRAM3 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x1C 2. "SU,If 1 and SP is also set SRAM3 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x1C 1. "NSP,If 1 SRAM3 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x1C 0. "NSU,If 1 and NSP is also set SRAM3 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x20 "SRAM4,Control whether debugger. DMA. core 0 and core 1 can access SRAM4. and at what security/privilege levels they can do so."
bitfld.long 0x20 7. "DBG,If 1 SRAM4 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x20 6. "DMA,If 1 SRAM4 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x20 5. "CORE1,If 1 SRAM4 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x20 4. "CORE0,If 1 SRAM4 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x20 3. "SP,If 1 SRAM4 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x20 2. "SU,If 1 and SP is also set SRAM4 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x20 1. "NSP,If 1 SRAM4 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x20 0. "NSU,If 1 and NSP is also set SRAM4 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x24 "SRAM5,Control whether debugger. DMA. core 0 and core 1 can access SRAM5. and at what security/privilege levels they can do so."
bitfld.long 0x24 7. "DBG,If 1 SRAM5 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x24 6. "DMA,If 1 SRAM5 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x24 5. "CORE1,If 1 SRAM5 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x24 4. "CORE0,If 1 SRAM5 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x24 3. "SP,If 1 SRAM5 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x24 2. "SU,If 1 and SP is also set SRAM5 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x24 1. "NSP,If 1 SRAM5 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x24 0. "NSU,If 1 and NSP is also set SRAM5 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x28 "SRAM6,Control whether debugger. DMA. core 0 and core 1 can access SRAM6. and at what security/privilege levels they can do so."
bitfld.long 0x28 7. "DBG,If 1 SRAM6 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x28 6. "DMA,If 1 SRAM6 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x28 5. "CORE1,If 1 SRAM6 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x28 4. "CORE0,If 1 SRAM6 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x28 3. "SP,If 1 SRAM6 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x28 2. "SU,If 1 and SP is also set SRAM6 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x28 1. "NSP,If 1 SRAM6 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x28 0. "NSU,If 1 and NSP is also set SRAM6 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x2C "SRAM7,Control whether debugger. DMA. core 0 and core 1 can access SRAM7. and at what security/privilege levels they can do so."
bitfld.long 0x2C 7. "DBG,If 1 SRAM7 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x2C 6. "DMA,If 1 SRAM7 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x2C 5. "CORE1,If 1 SRAM7 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x2C 4. "CORE0,If 1 SRAM7 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x2C 3. "SP,If 1 SRAM7 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x2C 2. "SU,If 1 and SP is also set SRAM7 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x2C 1. "NSP,If 1 SRAM7 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x2C 0. "NSU,If 1 and NSP is also set SRAM7 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x30 "SRAM8,Control whether debugger. DMA. core 0 and core 1 can access SRAM8. and at what security/privilege levels they can do so."
bitfld.long 0x30 7. "DBG,If 1 SRAM8 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x30 6. "DMA,If 1 SRAM8 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x30 5. "CORE1,If 1 SRAM8 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x30 4. "CORE0,If 1 SRAM8 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x30 3. "SP,If 1 SRAM8 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x30 2. "SU,If 1 and SP is also set SRAM8 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x30 1. "NSP,If 1 SRAM8 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x30 0. "NSU,If 1 and NSP is also set SRAM8 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x34 "SRAM9,Control whether debugger. DMA. core 0 and core 1 can access SRAM9. and at what security/privilege levels they can do so."
bitfld.long 0x34 7. "DBG,If 1 SRAM9 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x34 6. "DMA,If 1 SRAM9 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x34 5. "CORE1,If 1 SRAM9 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x34 4. "CORE0,If 1 SRAM9 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x34 3. "SP,If 1 SRAM9 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x34 2. "SU,If 1 and SP is also set SRAM9 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x34 1. "NSP,If 1 SRAM9 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x34 0. "NSU,If 1 and NSP is also set SRAM9 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x38 "DMA,Control whether debugger. DMA. core 0 and core 1 can access DMA. and at what security/privilege levels they can do so."
bitfld.long 0x38 7. "DBG,If 1 DMA can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x38 6. "DMA,If 1 DMA can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x38 5. "CORE1,If 1 DMA can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x38 4. "CORE0,If 1 DMA can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x38 3. "SP,If 1 DMA can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x38 2. "SU,If 1 and SP is also set DMA can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x38 1. "NSP,If 1 DMA can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x38 0. "NSU,If 1 and NSP is also set DMA can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x3C "USBCTRL,Control whether debugger. DMA. core 0 and core 1 can access USBCTRL. and at what security/privilege levels they can do so."
bitfld.long 0x3C 7. "DBG,If 1 USBCTRL can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x3C 6. "DMA,If 1 USBCTRL can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x3C 5. "CORE1,If 1 USBCTRL can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x3C 4. "CORE0,If 1 USBCTRL can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x3C 3. "SP,If 1 USBCTRL can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x3C 2. "SU,If 1 and SP is also set USBCTRL can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x3C 1. "NSP,If 1 USBCTRL can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x3C 0. "NSU,If 1 and NSP is also set USBCTRL can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x40 "PIO0,Control whether debugger. DMA. core 0 and core 1 can access PIO0. and at what security/privilege levels they can do so."
bitfld.long 0x40 7. "DBG,If 1 PIO0 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x40 6. "DMA,If 1 PIO0 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x40 5. "CORE1,If 1 PIO0 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x40 4. "CORE0,If 1 PIO0 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x40 3. "SP,If 1 PIO0 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x40 2. "SU,If 1 and SP is also set PIO0 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x40 1. "NSP,If 1 PIO0 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x40 0. "NSU,If 1 and NSP is also set PIO0 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x44 "PIO1,Control whether debugger. DMA. core 0 and core 1 can access PIO1. and at what security/privilege levels they can do so."
bitfld.long 0x44 7. "DBG,If 1 PIO1 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x44 6. "DMA,If 1 PIO1 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x44 5. "CORE1,If 1 PIO1 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x44 4. "CORE0,If 1 PIO1 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x44 3. "SP,If 1 PIO1 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x44 2. "SU,If 1 and SP is also set PIO1 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x44 1. "NSP,If 1 PIO1 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x44 0. "NSU,If 1 and NSP is also set PIO1 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x48 "PIO2,Control whether debugger. DMA. core 0 and core 1 can access PIO2. and at what security/privilege levels they can do so."
bitfld.long 0x48 7. "DBG,If 1 PIO2 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x48 6. "DMA,If 1 PIO2 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x48 5. "CORE1,If 1 PIO2 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x48 4. "CORE0,If 1 PIO2 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x48 3. "SP,If 1 PIO2 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x48 2. "SU,If 1 and SP is also set PIO2 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x48 1. "NSP,If 1 PIO2 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x48 0. "NSU,If 1 and NSP is also set PIO2 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x4C "CORESIGHT_TRACE,Control whether debugger. DMA. core 0 and core 1 can access CORESIGHT_TRACE. and at what security/privilege levels they can do so."
bitfld.long 0x4C 7. "DBG,If 1 CORESIGHT_TRACE can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x4C 6. "DMA,If 1 CORESIGHT_TRACE can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x4C 5. "CORE1,If 1 CORESIGHT_TRACE can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x4C 4. "CORE0,If 1 CORESIGHT_TRACE can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x4C 3. "SP,If 1 CORESIGHT_TRACE can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x4C 2. "SU,If 1 and SP is also set CORESIGHT_TRACE can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x4C 1. "NSP,If 1 CORESIGHT_TRACE can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x4C 0. "NSU,If 1 and NSP is also set CORESIGHT_TRACE can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x50 "CORESIGHT_PERIPH,Control whether debugger. DMA. core 0 and core 1 can access CORESIGHT_PERIPH. and at what security/privilege levels they can do so."
bitfld.long 0x50 7. "DBG,If 1 CORESIGHT_PERIPH can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x50 6. "DMA,If 1 CORESIGHT_PERIPH can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x50 5. "CORE1,If 1 CORESIGHT_PERIPH can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x50 4. "CORE0,If 1 CORESIGHT_PERIPH can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x50 3. "SP,If 1 CORESIGHT_PERIPH can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x50 2. "SU,If 1 and SP is also set CORESIGHT_PERIPH can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x50 1. "NSP,If 1 CORESIGHT_PERIPH can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x50 0. "NSU,If 1 and NSP is also set CORESIGHT_PERIPH can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x54 "SYSINFO,Control whether debugger. DMA. core 0 and core 1 can access SYSINFO. and at what security/privilege levels they can do so."
bitfld.long 0x54 7. "DBG,If 1 SYSINFO can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x54 6. "DMA,If 1 SYSINFO can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x54 5. "CORE1,If 1 SYSINFO can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x54 4. "CORE0,If 1 SYSINFO can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x54 3. "SP,If 1 SYSINFO can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x54 2. "SU,If 1 and SP is also set SYSINFO can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x54 1. "NSP,If 1 SYSINFO can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x54 0. "NSU,If 1 and NSP is also set SYSINFO can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x58 "RESETS,Control whether debugger. DMA. core 0 and core 1 can access RESETS. and at what security/privilege levels they can do so."
bitfld.long 0x58 7. "DBG,If 1 RESETS can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x58 6. "DMA,If 1 RESETS can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x58 5. "CORE1,If 1 RESETS can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x58 4. "CORE0,If 1 RESETS can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x58 3. "SP,If 1 RESETS can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x58 2. "SU,If 1 and SP is also set RESETS can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x58 1. "NSP,If 1 RESETS can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x58 0. "NSU,If 1 and NSP is also set RESETS can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x5C "IO_BANK0,Control whether debugger. DMA. core 0 and core 1 can access IO_BANK0. and at what security/privilege levels they can do so."
bitfld.long 0x5C 7. "DBG,If 1 IO_BANK0 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x5C 6. "DMA,If 1 IO_BANK0 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x5C 5. "CORE1,If 1 IO_BANK0 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x5C 4. "CORE0,If 1 IO_BANK0 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x5C 3. "SP,If 1 IO_BANK0 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x5C 2. "SU,If 1 and SP is also set IO_BANK0 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x5C 1. "NSP,If 1 IO_BANK0 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x5C 0. "NSU,If 1 and NSP is also set IO_BANK0 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x60 "IO_BANK1,Control whether debugger. DMA. core 0 and core 1 can access IO_BANK1. and at what security/privilege levels they can do so."
bitfld.long 0x60 7. "DBG,If 1 IO_BANK1 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x60 6. "DMA,If 1 IO_BANK1 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x60 5. "CORE1,If 1 IO_BANK1 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x60 4. "CORE0,If 1 IO_BANK1 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x60 3. "SP,If 1 IO_BANK1 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x60 2. "SU,If 1 and SP is also set IO_BANK1 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x60 1. "NSP,If 1 IO_BANK1 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x60 0. "NSU,If 1 and NSP is also set IO_BANK1 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x64 "PADS_BANK0,Control whether debugger. DMA. core 0 and core 1 can access PADS_BANK0. and at what security/privilege levels they can do so."
bitfld.long 0x64 7. "DBG,If 1 PADS_BANK0 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x64 6. "DMA,If 1 PADS_BANK0 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x64 5. "CORE1,If 1 PADS_BANK0 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x64 4. "CORE0,If 1 PADS_BANK0 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x64 3. "SP,If 1 PADS_BANK0 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x64 2. "SU,If 1 and SP is also set PADS_BANK0 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x64 1. "NSP,If 1 PADS_BANK0 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x64 0. "NSU,If 1 and NSP is also set PADS_BANK0 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x68 "PADS_QSPI,Control whether debugger. DMA. core 0 and core 1 can access PADS_QSPI. and at what security/privilege levels they can do so."
bitfld.long 0x68 7. "DBG,If 1 PADS_QSPI can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x68 6. "DMA,If 1 PADS_QSPI can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x68 5. "CORE1,If 1 PADS_QSPI can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x68 4. "CORE0,If 1 PADS_QSPI can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x68 3. "SP,If 1 PADS_QSPI can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x68 2. "SU,If 1 and SP is also set PADS_QSPI can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x68 1. "NSP,If 1 PADS_QSPI can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x68 0. "NSU,If 1 and NSP is also set PADS_QSPI can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x6C "BUSCTRL,Control whether debugger. DMA. core 0 and core 1 can access BUSCTRL. and at what security/privilege levels they can do so."
bitfld.long 0x6C 7. "DBG,If 1 BUSCTRL can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x6C 6. "DMA,If 1 BUSCTRL can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x6C 5. "CORE1,If 1 BUSCTRL can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x6C 4. "CORE0,If 1 BUSCTRL can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x6C 3. "SP,If 1 BUSCTRL can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x6C 2. "SU,If 1 and SP is also set BUSCTRL can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x6C 1. "NSP,If 1 BUSCTRL can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x6C 0. "NSU,If 1 and NSP is also set BUSCTRL can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x70 "ADC0,Control whether debugger. DMA. core 0 and core 1 can access ADC0. and at what security/privilege levels they can do so."
bitfld.long 0x70 7. "DBG,If 1 ADC0 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x70 6. "DMA,If 1 ADC0 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x70 5. "CORE1,If 1 ADC0 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x70 4. "CORE0,If 1 ADC0 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x70 3. "SP,If 1 ADC0 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x70 2. "SU,If 1 and SP is also set ADC0 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x70 1. "NSP,If 1 ADC0 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x70 0. "NSU,If 1 and NSP is also set ADC0 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x74 "HSTX,Control whether debugger. DMA. core 0 and core 1 can access HSTX. and at what security/privilege levels they can do so."
bitfld.long 0x74 7. "DBG,If 1 HSTX can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x74 6. "DMA,If 1 HSTX can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x74 5. "CORE1,If 1 HSTX can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x74 4. "CORE0,If 1 HSTX can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x74 3. "SP,If 1 HSTX can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x74 2. "SU,If 1 and SP is also set HSTX can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x74 1. "NSP,If 1 HSTX can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x74 0. "NSU,If 1 and NSP is also set HSTX can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x78 "I2C0,Control whether debugger. DMA. core 0 and core 1 can access I2C0. and at what security/privilege levels they can do so."
bitfld.long 0x78 7. "DBG,If 1 I2C0 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x78 6. "DMA,If 1 I2C0 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x78 5. "CORE1,If 1 I2C0 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x78 4. "CORE0,If 1 I2C0 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x78 3. "SP,If 1 I2C0 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x78 2. "SU,If 1 and SP is also set I2C0 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x78 1. "NSP,If 1 I2C0 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x78 0. "NSU,If 1 and NSP is also set I2C0 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x7C "I2C1,Control whether debugger. DMA. core 0 and core 1 can access I2C1. and at what security/privilege levels they can do so."
bitfld.long 0x7C 7. "DBG,If 1 I2C1 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x7C 6. "DMA,If 1 I2C1 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x7C 5. "CORE1,If 1 I2C1 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x7C 4. "CORE0,If 1 I2C1 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x7C 3. "SP,If 1 I2C1 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x7C 2. "SU,If 1 and SP is also set I2C1 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x7C 1. "NSP,If 1 I2C1 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x7C 0. "NSU,If 1 and NSP is also set I2C1 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x80 "PWM,Control whether debugger. DMA. core 0 and core 1 can access PWM. and at what security/privilege levels they can do so."
bitfld.long 0x80 7. "DBG,If 1 PWM can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x80 6. "DMA,If 1 PWM can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x80 5. "CORE1,If 1 PWM can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x80 4. "CORE0,If 1 PWM can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x80 3. "SP,If 1 PWM can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x80 2. "SU,If 1 and SP is also set PWM can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x80 1. "NSP,If 1 PWM can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x80 0. "NSU,If 1 and NSP is also set PWM can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x84 "SPI0,Control whether debugger. DMA. core 0 and core 1 can access SPI0. and at what security/privilege levels they can do so."
bitfld.long 0x84 7. "DBG,If 1 SPI0 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x84 6. "DMA,If 1 SPI0 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x84 5. "CORE1,If 1 SPI0 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x84 4. "CORE0,If 1 SPI0 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x84 3. "SP,If 1 SPI0 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x84 2. "SU,If 1 and SP is also set SPI0 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x84 1. "NSP,If 1 SPI0 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x84 0. "NSU,If 1 and NSP is also set SPI0 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x88 "SPI1,Control whether debugger. DMA. core 0 and core 1 can access SPI1. and at what security/privilege levels they can do so."
bitfld.long 0x88 7. "DBG,If 1 SPI1 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x88 6. "DMA,If 1 SPI1 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x88 5. "CORE1,If 1 SPI1 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x88 4. "CORE0,If 1 SPI1 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x88 3. "SP,If 1 SPI1 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x88 2. "SU,If 1 and SP is also set SPI1 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x88 1. "NSP,If 1 SPI1 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x88 0. "NSU,If 1 and NSP is also set SPI1 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x8C "TIMER0,Control whether debugger. DMA. core 0 and core 1 can access TIMER0. and at what security/privilege levels they can do so."
bitfld.long 0x8C 7. "DBG,If 1 TIMER0 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x8C 6. "DMA,If 1 TIMER0 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x8C 5. "CORE1,If 1 TIMER0 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x8C 4. "CORE0,If 1 TIMER0 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x8C 3. "SP,If 1 TIMER0 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x8C 2. "SU,If 1 and SP is also set TIMER0 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x8C 1. "NSP,If 1 TIMER0 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x8C 0. "NSU,If 1 and NSP is also set TIMER0 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x90 "TIMER1,Control whether debugger. DMA. core 0 and core 1 can access TIMER1. and at what security/privilege levels they can do so."
bitfld.long 0x90 7. "DBG,If 1 TIMER1 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x90 6. "DMA,If 1 TIMER1 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x90 5. "CORE1,If 1 TIMER1 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x90 4. "CORE0,If 1 TIMER1 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x90 3. "SP,If 1 TIMER1 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x90 2. "SU,If 1 and SP is also set TIMER1 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x90 1. "NSP,If 1 TIMER1 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x90 0. "NSU,If 1 and NSP is also set TIMER1 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x94 "UART0,Control whether debugger. DMA. core 0 and core 1 can access UART0. and at what security/privilege levels they can do so."
bitfld.long 0x94 7. "DBG,If 1 UART0 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x94 6. "DMA,If 1 UART0 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x94 5. "CORE1,If 1 UART0 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x94 4. "CORE0,If 1 UART0 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x94 3. "SP,If 1 UART0 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x94 2. "SU,If 1 and SP is also set UART0 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x94 1. "NSP,If 1 UART0 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x94 0. "NSU,If 1 and NSP is also set UART0 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x98 "UART1,Control whether debugger. DMA. core 0 and core 1 can access UART1. and at what security/privilege levels they can do so."
bitfld.long 0x98 7. "DBG,If 1 UART1 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x98 6. "DMA,If 1 UART1 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x98 5. "CORE1,If 1 UART1 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x98 4. "CORE0,If 1 UART1 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x98 3. "SP,If 1 UART1 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x98 2. "SU,If 1 and SP is also set UART1 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x98 1. "NSP,If 1 UART1 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x98 0. "NSU,If 1 and NSP is also set UART1 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0x9C "OTP,Control whether debugger. DMA. core 0 and core 1 can access OTP. and at what security/privilege levels they can do so."
bitfld.long 0x9C 7. "DBG,If 1 OTP can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x9C 6. "DMA,If 1 OTP can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x9C 5. "CORE1,If 1 OTP can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x9C 4. "CORE0,If 1 OTP can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0x9C 3. "SP,If 1 OTP can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0x9C 2. "SU,If 1 and SP is also set OTP can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0x9C 1. "NSP,If 1 OTP can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0x9C 0. "NSU,If 1 and NSP is also set OTP can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xA0 "TBMAN,Control whether debugger. DMA. core 0 and core 1 can access TBMAN. and at what security/privilege levels they can do so."
bitfld.long 0xA0 7. "DBG,If 1 TBMAN can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA0 6. "DMA,If 1 TBMAN can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA0 5. "CORE1,If 1 TBMAN can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA0 4. "CORE0,If 1 TBMAN can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA0 3. "SP,If 1 TBMAN can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xA0 2. "SU,If 1 and SP is also set TBMAN can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xA0 1. "NSP,If 1 TBMAN can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xA0 0. "NSU,If 1 and NSP is also set TBMAN can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xA4 "POWMAN,Control whether debugger. DMA. core 0 and core 1 can access POWMAN. and at what security/privilege levels they can do so."
bitfld.long 0xA4 7. "DBG,If 1 POWMAN can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA4 6. "DMA,If 1 POWMAN can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA4 5. "CORE1,If 1 POWMAN can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA4 4. "CORE0,If 1 POWMAN can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA4 3. "SP,If 1 POWMAN can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xA4 2. "SU,If 1 and SP is also set POWMAN can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xA4 1. "NSP,If 1 POWMAN can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xA4 0. "NSU,If 1 and NSP is also set POWMAN can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xA8 "TRNG,Control whether debugger. DMA. core 0 and core 1 can access TRNG. and at what security/privilege levels they can do so."
bitfld.long 0xA8 7. "DBG,If 1 TRNG can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA8 6. "DMA,If 1 TRNG can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA8 5. "CORE1,If 1 TRNG can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA8 4. "CORE0,If 1 TRNG can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xA8 3. "SP,If 1 TRNG can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xA8 2. "SU,If 1 and SP is also set TRNG can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xA8 1. "NSP,If 1 TRNG can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xA8 0. "NSU,If 1 and NSP is also set TRNG can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xAC "SHA256,Control whether debugger. DMA. core 0 and core 1 can access SHA256. and at what security/privilege levels they can do so."
bitfld.long 0xAC 7. "DBG,If 1 SHA256 can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xAC 6. "DMA,If 1 SHA256 can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xAC 5. "CORE1,If 1 SHA256 can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xAC 4. "CORE0,If 1 SHA256 can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xAC 3. "SP,If 1 SHA256 can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xAC 2. "SU,If 1 and SP is also set SHA256 can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xAC 1. "NSP,If 1 SHA256 can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xAC 0. "NSU,If 1 and NSP is also set SHA256 can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xB0 "SYSCFG,Control whether debugger. DMA. core 0 and core 1 can access SYSCFG. and at what security/privilege levels they can do so."
bitfld.long 0xB0 7. "DBG,If 1 SYSCFG can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB0 6. "DMA,If 1 SYSCFG can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB0 5. "CORE1,If 1 SYSCFG can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB0 4. "CORE0,If 1 SYSCFG can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB0 3. "SP,If 1 SYSCFG can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xB0 2. "SU,If 1 and SP is also set SYSCFG can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xB0 1. "NSP,If 1 SYSCFG can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xB0 0. "NSU,If 1 and NSP is also set SYSCFG can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xB4 "CLOCKS,Control whether debugger. DMA. core 0 and core 1 can access CLOCKS. and at what security/privilege levels they can do so."
bitfld.long 0xB4 7. "DBG,If 1 CLOCKS can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB4 6. "DMA,If 1 CLOCKS can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB4 5. "CORE1,If 1 CLOCKS can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB4 4. "CORE0,If 1 CLOCKS can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB4 3. "SP,If 1 CLOCKS can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xB4 2. "SU,If 1 and SP is also set CLOCKS can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xB4 1. "NSP,If 1 CLOCKS can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xB4 0. "NSU,If 1 and NSP is also set CLOCKS can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xB8 "XOSC,Control whether debugger. DMA. core 0 and core 1 can access XOSC. and at what security/privilege levels they can do so."
bitfld.long 0xB8 7. "DBG,If 1 XOSC can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB8 6. "DMA,If 1 XOSC can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB8 5. "CORE1,If 1 XOSC can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB8 4. "CORE0,If 1 XOSC can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xB8 3. "SP,If 1 XOSC can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xB8 2. "SU,If 1 and SP is also set XOSC can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xB8 1. "NSP,If 1 XOSC can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xB8 0. "NSU,If 1 and NSP is also set XOSC can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xBC "ROSC,Control whether debugger. DMA. core 0 and core 1 can access ROSC. and at what security/privilege levels they can do so."
bitfld.long 0xBC 7. "DBG,If 1 ROSC can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xBC 6. "DMA,If 1 ROSC can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xBC 5. "CORE1,If 1 ROSC can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xBC 4. "CORE0,If 1 ROSC can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xBC 3. "SP,If 1 ROSC can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xBC 2. "SU,If 1 and SP is also set ROSC can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xBC 1. "NSP,If 1 ROSC can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xBC 0. "NSU,If 1 and NSP is also set ROSC can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xC0 "PLL_SYS,Control whether debugger. DMA. core 0 and core 1 can access PLL_SYS. and at what security/privilege levels they can do so."
bitfld.long 0xC0 7. "DBG,If 1 PLL_SYS can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC0 6. "DMA,If 1 PLL_SYS can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC0 5. "CORE1,If 1 PLL_SYS can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC0 4. "CORE0,If 1 PLL_SYS can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC0 3. "SP,If 1 PLL_SYS can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xC0 2. "SU,If 1 and SP is also set PLL_SYS can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xC0 1. "NSP,If 1 PLL_SYS can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xC0 0. "NSU,If 1 and NSP is also set PLL_SYS can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xC4 "PLL_USB,Control whether debugger. DMA. core 0 and core 1 can access PLL_USB. and at what security/privilege levels they can do so."
bitfld.long 0xC4 7. "DBG,If 1 PLL_USB can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC4 6. "DMA,If 1 PLL_USB can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC4 5. "CORE1,If 1 PLL_USB can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC4 4. "CORE0,If 1 PLL_USB can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC4 3. "SP,If 1 PLL_USB can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xC4 2. "SU,If 1 and SP is also set PLL_USB can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xC4 1. "NSP,If 1 PLL_USB can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xC4 0. "NSU,If 1 and NSP is also set PLL_USB can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xC8 "TICKS,Control whether debugger. DMA. core 0 and core 1 can access TICKS. and at what security/privilege levels they can do so."
bitfld.long 0xC8 7. "DBG,If 1 TICKS can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC8 6. "DMA,If 1 TICKS can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC8 5. "CORE1,If 1 TICKS can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC8 4. "CORE0,If 1 TICKS can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xC8 3. "SP,If 1 TICKS can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xC8 2. "SU,If 1 and SP is also set TICKS can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xC8 1. "NSP,If 1 TICKS can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xC8 0. "NSU,If 1 and NSP is also set TICKS can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xCC "WATCHDOG,Control whether debugger. DMA. core 0 and core 1 can access WATCHDOG. and at what security/privilege levels they can do so."
bitfld.long 0xCC 7. "DBG,If 1 WATCHDOG can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xCC 6. "DMA,If 1 WATCHDOG can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xCC 5. "CORE1,If 1 WATCHDOG can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xCC 4. "CORE0,If 1 WATCHDOG can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xCC 3. "SP,If 1 WATCHDOG can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xCC 2. "SU,If 1 and SP is also set WATCHDOG can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xCC 1. "NSP,If 1 WATCHDOG can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xCC 0. "NSU,If 1 and NSP is also set WATCHDOG can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xD0 "RSM,Control whether debugger. DMA. core 0 and core 1 can access RSM. and at what security/privilege levels they can do so."
bitfld.long 0xD0 7. "DBG,If 1 RSM can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD0 6. "DMA,If 1 RSM can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD0 5. "CORE1,If 1 RSM can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD0 4. "CORE0,If 1 RSM can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD0 3. "SP,If 1 RSM can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xD0 2. "SU,If 1 and SP is also set RSM can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xD0 1. "NSP,If 1 RSM can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xD0 0. "NSU,If 1 and NSP is also set RSM can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xD4 "XIP_CTRL,Control whether debugger. DMA. core 0 and core 1 can access XIP_CTRL. and at what security/privilege levels they can do so."
bitfld.long 0xD4 7. "DBG,If 1 XIP_CTRL can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD4 6. "DMA,If 1 XIP_CTRL can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD4 5. "CORE1,If 1 XIP_CTRL can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD4 4. "CORE0,If 1 XIP_CTRL can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD4 3. "SP,If 1 XIP_CTRL can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xD4 2. "SU,If 1 and SP is also set XIP_CTRL can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xD4 1. "NSP,If 1 XIP_CTRL can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xD4 0. "NSU,If 1 and NSP is also set XIP_CTRL can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xD8 "XIP_QMI,Control whether debugger. DMA. core 0 and core 1 can access XIP_QMI. and at what security/privilege levels they can do so."
bitfld.long 0xD8 7. "DBG,If 1 XIP_QMI can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD8 6. "DMA,If 1 XIP_QMI can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD8 5. "CORE1,If 1 XIP_QMI can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD8 4. "CORE0,If 1 XIP_QMI can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xD8 3. "SP,If 1 XIP_QMI can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xD8 2. "SU,If 1 and SP is also set XIP_QMI can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xD8 1. "NSP,If 1 XIP_QMI can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xD8 0. "NSU,If 1 and NSP is also set XIP_QMI can be accessed from a Non-secure Unprivileged context." "0,1"
line.long 0xDC "XIP_AUX,Control whether debugger. DMA. core 0 and core 1 can access XIP_AUX. and at what security/privilege levels they can do so."
bitfld.long 0xDC 7. "DBG,If 1 XIP_AUX can be accessed by the debugger at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xDC 6. "DMA,If 1 XIP_AUX can be accessed by the DMA at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xDC 5. "CORE1,If 1 XIP_AUX can be accessed by core 1 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xDC 4. "CORE0,If 1 XIP_AUX can be accessed by core 0 at security/privilege levels permitted by SP/NSP/SU/NSU in this register." "0,1"
bitfld.long 0xDC 3. "SP,If 1 XIP_AUX can be accessed from a Secure Privileged context." "0,1"
bitfld.long 0xDC 2. "SU,If 1 and SP is also set XIP_AUX can be accessed from a Secure Unprivileged context." "0,1"
bitfld.long 0xDC 1. "NSP,If 1 XIP_AUX can be accessed from a Non-secure Privileged context." "0,1"
newline
bitfld.long 0xDC 0. "NSU,If 1 and NSP is also set XIP_AUX can be accessed from a Non-secure Unprivileged context." "0,1"
tree.end
tree "ADC (Analog-Digital Converter)"
base ad:0x400A0000
group.long 0x0++0x3
line.long 0x0 "CS,ADC Control and Status"
hexmask.long.word 0x0 16.--24. 1. "RROBIN,Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable."
hexmask.long.byte 0x0 12.--15. 1. "AINSEL,Select analog mux input. Updated automatically in round-robin mode."
newline
eventfld.long 0x0 10. "ERR_STICKY,Some past ADC conversion encountered an error. Write 1 to clear." "0,1"
rbitfld.long 0x0 9. "ERR,The most recent ADC conversion encountered an error; result is undefined or noisy." "0,1"
newline
rbitfld.long 0x0 8. "READY,1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed." "0,1"
bitfld.long 0x0 3. "START_MANY,Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes." "0,1"
newline
bitfld.long 0x0 2. "START_ONCE,Start a single conversion. Self-clearing. Ignored if start_many is asserted." "0,1"
bitfld.long 0x0 1. "TS_EN,Power on temperature sensor. 1 - enabled. 0 - disabled." "0,1"
newline
bitfld.long 0x0 0. "EN,Power on ADC and enable its clock." "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "RESULT,Result of most recent ADC conversion"
hexmask.long.word 0x0 0.--11. 1. "RESULT"
group.long 0x8++0x3
line.long 0x0 "FCS,FIFO control and status"
hexmask.long.byte 0x0 24.--27. 1. "THRESH,DREQ/IRQ asserted when level >= threshold"
hexmask.long.byte 0x0 16.--19. 1. "LEVEL,The number of conversion results currently waiting in the FIFO"
newline
eventfld.long 0x0 11. "OVER,1 if the FIFO has been overflowed. Write 1 to clear." "0,1"
eventfld.long 0x0 10. "UNDER,1 if the FIFO has been underflowed. Write 1 to clear." "0,1"
newline
rbitfld.long 0x0 9. "FULL" "0,1"
rbitfld.long 0x0 8. "EMPTY" "0,1"
newline
bitfld.long 0x0 3. "DREQ_EN,If 1: assert DMA requests when FIFO contains data" "?,1: assert DMA requests when FIFO contains data"
bitfld.long 0x0 2. "ERR,If 1: conversion error bit appears in the FIFO alongside the result" "?,1: conversion error bit appears in the FIFO.."
newline
bitfld.long 0x0 1. "SHIFT,If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers." "?,1: FIFO results are right-shifted to be one byte in.."
bitfld.long 0x0 0. "EN,If 1: write result to the FIFO after each conversion." "?,1: write result to the FIFO after each conversion"
rgroup.long 0xC++0x3
line.long 0x0 "FIFO,Conversion result FIFO"
bitfld.long 0x0 15. "ERR,1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted." "0,1"
hexmask.long.word 0x0 0.--11. 1. "VAL"
group.long 0x10++0x3
line.long 0x0 "DIV,Clock divider. If non-zero. CS_START_MANY will start conversions"
hexmask.long.word 0x0 8.--23. 1. "INT,Integer part of clock divisor."
hexmask.long.byte 0x0 0.--7. 1. "FRAC,Fractional part of clock divisor. First-order delta-sigma."
rgroup.long 0x14++0x3
line.long 0x0 "INTR,Raw Interrupts"
bitfld.long 0x0 0. "FIFO,Triggered when the sample FIFO reaches a certain level." "0,1"
group.long 0x18++0x7
line.long 0x0 "INTE,Interrupt Enable"
bitfld.long 0x0 0. "FIFO,Triggered when the sample FIFO reaches a certain level." "0,1"
line.long 0x4 "INTF,Interrupt Force"
bitfld.long 0x4 0. "FIFO,Triggered when the sample FIFO reaches a certain level." "0,1"
rgroup.long 0x20++0x3
line.long 0x0 "INTS,Interrupt status after masking & forcing"
bitfld.long 0x0 0. "FIFO,Triggered when the sample FIFO reaches a certain level." "0,1"
tree.end
tree "BOOTRAM (Boot RAM)"
base ad:0x400E0000
group.long 0x800++0x2B
line.long 0x0 "WRITE_ONCE0,This registers always ORs writes into its current contents. Once a bit is set. it can only be cleared by a reset."
hexmask.long 0x0 0.--31. 1. "WRITE_ONCE0"
line.long 0x4 "WRITE_ONCE1,This registers always ORs writes into its current contents. Once a bit is set. it can only be cleared by a reset."
hexmask.long 0x4 0.--31. 1. "WRITE_ONCE1"
line.long 0x8 "BOOTLOCK_STAT,Bootlock status register. 1=unclaimed. 0=claimed. These locks function identically to the SIO spinlocks. but are reserved for bootrom use."
hexmask.long.byte 0x8 0.--7. 1. "BOOTLOCK_STAT"
line.long 0xC "BOOTLOCK0,Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n. and on failed claim is zero."
hexmask.long 0xC 0.--31. 1. "BOOTLOCK0"
line.long 0x10 "BOOTLOCK1,Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n. and on failed claim is zero."
hexmask.long 0x10 0.--31. 1. "BOOTLOCK1"
line.long 0x14 "BOOTLOCK2,Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n. and on failed claim is zero."
hexmask.long 0x14 0.--31. 1. "BOOTLOCK2"
line.long 0x18 "BOOTLOCK3,Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n. and on failed claim is zero."
hexmask.long 0x18 0.--31. 1. "BOOTLOCK3"
line.long 0x1C "BOOTLOCK4,Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n. and on failed claim is zero."
hexmask.long 0x1C 0.--31. 1. "BOOTLOCK4"
line.long 0x20 "BOOTLOCK5,Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n. and on failed claim is zero."
hexmask.long 0x20 0.--31. 1. "BOOTLOCK5"
line.long 0x24 "BOOTLOCK6,Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n. and on failed claim is zero."
hexmask.long 0x24 0.--31. 1. "BOOTLOCK6"
line.long 0x28 "BOOTLOCK7,Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n. and on failed claim is zero."
hexmask.long 0x28 0.--31. 1. "BOOTLOCK7"
tree.end
tree "BUSCTRL"
base ad:0x40068000
group.long 0x0++0x3
line.long 0x0 "BUS_PRIORITY,Set the priority of each master for bus arbitration."
bitfld.long 0x0 12. "DMA_W,0 - low priority 1 - high priority" "0,1"
bitfld.long 0x0 8. "DMA_R,0 - low priority 1 - high priority" "0,1"
bitfld.long 0x0 4. "PROC1,0 - low priority 1 - high priority" "0,1"
bitfld.long 0x0 0. "PROC0,0 - low priority 1 - high priority" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "BUS_PRIORITY_ACK,Bus priority acknowledge"
bitfld.long 0x0 0. "BUS_PRIORITY_ACK,Goes to 1 once all arbiters have registered the new global priority levels." "0,1"
group.long 0x8++0x23
line.long 0x0 "PERFCTR_EN,Enable the performance counters. If 0. the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code."
bitfld.long 0x0 0. "PERFCTR_EN" "0,1"
line.long 0x4 "PERFCTR0,Bus fabric performance counter 0"
hexmask.long.tbyte 0x4 0.--23. 1. "PERFCTR0,Busfabric saturating performance counter 0"
line.long 0x8 "PERFSEL0,Bus fabric performance event select for PERFCTR0"
hexmask.long.byte 0x8 0.--6. 1. "PERFSEL0,Select an event for PERFCTR0. For each downstream port of the main crossbar four events are available: ACCESS an access took place; ACCESS_CONTESTED an access took place that previously stalled due to contention from other masters;.."
line.long 0xC "PERFCTR1,Bus fabric performance counter 1"
hexmask.long.tbyte 0xC 0.--23. 1. "PERFCTR1,Busfabric saturating performance counter 1"
line.long 0x10 "PERFSEL1,Bus fabric performance event select for PERFCTR1"
hexmask.long.byte 0x10 0.--6. 1. "PERFSEL1,Select an event for PERFCTR1. For each downstream port of the main crossbar four events are available: ACCESS an access took place; ACCESS_CONTESTED an access took place that previously stalled due to contention from other masters;.."
line.long 0x14 "PERFCTR2,Bus fabric performance counter 2"
hexmask.long.tbyte 0x14 0.--23. 1. "PERFCTR2,Busfabric saturating performance counter 2"
line.long 0x18 "PERFSEL2,Bus fabric performance event select for PERFCTR2"
hexmask.long.byte 0x18 0.--6. 1. "PERFSEL2,Select an event for PERFCTR2. For each downstream port of the main crossbar four events are available: ACCESS an access took place; ACCESS_CONTESTED an access took place that previously stalled due to contention from other masters;.."
line.long 0x1C "PERFCTR3,Bus fabric performance counter 3"
hexmask.long.tbyte 0x1C 0.--23. 1. "PERFCTR3,Busfabric saturating performance counter 3"
line.long 0x20 "PERFSEL3,Bus fabric performance event select for PERFCTR3"
hexmask.long.byte 0x20 0.--6. 1. "PERFSEL3,Select an event for PERFCTR3. For each downstream port of the main crossbar four events are available: ACCESS an access took place; ACCESS_CONTESTED an access took place that previously stalled due to contention from other masters;.."
tree.end
tree "CLOCKS"
base ad:0x40010000
group.long 0x0++0x7
line.long 0x0 "CLK_GPOUT0_CTRL,Clock control. can be changed on-the-fly (except for auxsrc)"
rbitfld.long 0x0 28. "ENABLED,clock generator is enabled" "0,1"
bitfld.long 0x0 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock" "0,1"
bitfld.long 0x0 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock" "0,1,2,3"
bitfld.long 0x0 12. "DC50,Enables duty cycle correction for odd divisors can be changed on-the-fly" "0,1"
newline
bitfld.long 0x0 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1"
bitfld.long 0x0 10. "KILL,Asynchronously kills the clock generator enable must be set low before deasserting kill" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "AUXSRC,Selects the auxiliary clock source will glitch when switching"
line.long 0x4 "CLK_GPOUT0_DIV"
hexmask.long.word 0x4 16.--31. 1. "INT"
hexmask.long.word 0x4 0.--15. 1. "FRAC,Fractional component of the divisor can be changed on-the-fly"
rgroup.long 0x8++0x3
line.long 0x0 "CLK_GPOUT0_SELECTED,Indicates which src is currently selected (one-hot)"
bitfld.long 0x0 0. "CLK_GPOUT0_SELECTED,This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1." "0,1"
group.long 0xC++0x7
line.long 0x0 "CLK_GPOUT1_CTRL,Clock control. can be changed on-the-fly (except for auxsrc)"
rbitfld.long 0x0 28. "ENABLED,clock generator is enabled" "0,1"
bitfld.long 0x0 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock" "0,1"
bitfld.long 0x0 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock" "0,1,2,3"
bitfld.long 0x0 12. "DC50,Enables duty cycle correction for odd divisors can be changed on-the-fly" "0,1"
newline
bitfld.long 0x0 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1"
bitfld.long 0x0 10. "KILL,Asynchronously kills the clock generator enable must be set low before deasserting kill" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "AUXSRC,Selects the auxiliary clock source will glitch when switching"
line.long 0x4 "CLK_GPOUT1_DIV"
hexmask.long.word 0x4 16.--31. 1. "INT"
hexmask.long.word 0x4 0.--15. 1. "FRAC,Fractional component of the divisor can be changed on-the-fly"
rgroup.long 0x14++0x3
line.long 0x0 "CLK_GPOUT1_SELECTED,Indicates which src is currently selected (one-hot)"
bitfld.long 0x0 0. "CLK_GPOUT1_SELECTED,This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1." "0,1"
group.long 0x18++0x7
line.long 0x0 "CLK_GPOUT2_CTRL,Clock control. can be changed on-the-fly (except for auxsrc)"
rbitfld.long 0x0 28. "ENABLED,clock generator is enabled" "0,1"
bitfld.long 0x0 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock" "0,1"
bitfld.long 0x0 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock" "0,1,2,3"
bitfld.long 0x0 12. "DC50,Enables duty cycle correction for odd divisors can be changed on-the-fly" "0,1"
newline
bitfld.long 0x0 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1"
bitfld.long 0x0 10. "KILL,Asynchronously kills the clock generator enable must be set low before deasserting kill" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "AUXSRC,Selects the auxiliary clock source will glitch when switching"
line.long 0x4 "CLK_GPOUT2_DIV"
hexmask.long.word 0x4 16.--31. 1. "INT"
hexmask.long.word 0x4 0.--15. 1. "FRAC,Fractional component of the divisor can be changed on-the-fly"
rgroup.long 0x20++0x3
line.long 0x0 "CLK_GPOUT2_SELECTED,Indicates which src is currently selected (one-hot)"
bitfld.long 0x0 0. "CLK_GPOUT2_SELECTED,This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1." "0,1"
group.long 0x24++0x7
line.long 0x0 "CLK_GPOUT3_CTRL,Clock control. can be changed on-the-fly (except for auxsrc)"
rbitfld.long 0x0 28. "ENABLED,clock generator is enabled" "0,1"
bitfld.long 0x0 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock" "0,1"
bitfld.long 0x0 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock" "0,1,2,3"
bitfld.long 0x0 12. "DC50,Enables duty cycle correction for odd divisors can be changed on-the-fly" "0,1"
newline
bitfld.long 0x0 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1"
bitfld.long 0x0 10. "KILL,Asynchronously kills the clock generator enable must be set low before deasserting kill" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "AUXSRC,Selects the auxiliary clock source will glitch when switching"
line.long 0x4 "CLK_GPOUT3_DIV"
hexmask.long.word 0x4 16.--31. 1. "INT"
hexmask.long.word 0x4 0.--15. 1. "FRAC,Fractional component of the divisor can be changed on-the-fly"
rgroup.long 0x2C++0x3
line.long 0x0 "CLK_GPOUT3_SELECTED,Indicates which src is currently selected (one-hot)"
bitfld.long 0x0 0. "CLK_GPOUT3_SELECTED,This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1." "0,1"
group.long 0x30++0x7
line.long 0x0 "CLK_REF_CTRL,Clock control. can be changed on-the-fly (except for auxsrc)"
bitfld.long 0x0 5.--6. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0,1,2,3"
bitfld.long 0x0 0.--1. "SRC,Selects the clock source glitchlessly can be changed on-the-fly" "0,1,2,3"
line.long 0x4 "CLK_REF_DIV"
hexmask.long.byte 0x4 16.--23. 1. "INT"
rgroup.long 0x38++0x3
line.long 0x0 "CLK_REF_SELECTED,Indicates which src is currently selected (one-hot)"
hexmask.long.byte 0x0 0.--3. 1. "CLK_REF_SELECTED,The glitchless multiplexer does not switch instantaneously (to avoid glitches) so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in.."
group.long 0x3C++0x7
line.long 0x0 "CLK_SYS_CTRL,Clock control. can be changed on-the-fly (except for auxsrc)"
bitfld.long 0x0 5.--7. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "SRC,Selects the clock source glitchlessly can be changed on-the-fly" "0,1"
line.long 0x4 "CLK_SYS_DIV"
hexmask.long.word 0x4 16.--31. 1. "INT"
hexmask.long.word 0x4 0.--15. 1. "FRAC,Fractional component of the divisor can be changed on-the-fly"
rgroup.long 0x44++0x3
line.long 0x0 "CLK_SYS_SELECTED,Indicates which src is currently selected (one-hot)"
bitfld.long 0x0 0.--1. "CLK_SYS_SELECTED,The glitchless multiplexer does not switch instantaneously (to avoid glitches) so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in.." "0,1,2,3"
group.long 0x48++0x7
line.long 0x0 "CLK_PERI_CTRL,Clock control. can be changed on-the-fly (except for auxsrc)"
rbitfld.long 0x0 28. "ENABLED,clock generator is enabled" "0,1"
bitfld.long 0x0 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1"
bitfld.long 0x0 10. "KILL,Asynchronously kills the clock generator enable must be set low before deasserting kill" "0,1"
bitfld.long 0x0 5.--7. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0,1,2,3,4,5,6,7"
line.long 0x4 "CLK_PERI_DIV"
bitfld.long 0x4 16.--17. "INT" "0,1,2,3"
rgroup.long 0x50++0x3
line.long 0x0 "CLK_PERI_SELECTED,Indicates which src is currently selected (one-hot)"
bitfld.long 0x0 0. "CLK_PERI_SELECTED,This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1." "0,1"
group.long 0x54++0x7
line.long 0x0 "CLK_HSTX_CTRL,Clock control. can be changed on-the-fly (except for auxsrc)"
rbitfld.long 0x0 28. "ENABLED,clock generator is enabled" "0,1"
bitfld.long 0x0 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock" "0,1"
bitfld.long 0x0 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock" "0,1,2,3"
bitfld.long 0x0 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1"
newline
bitfld.long 0x0 10. "KILL,Asynchronously kills the clock generator enable must be set low before deasserting kill" "0,1"
bitfld.long 0x0 5.--7. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0,1,2,3,4,5,6,7"
line.long 0x4 "CLK_HSTX_DIV"
bitfld.long 0x4 16.--17. "INT" "0,1,2,3"
rgroup.long 0x5C++0x3
line.long 0x0 "CLK_HSTX_SELECTED,Indicates which src is currently selected (one-hot)"
bitfld.long 0x0 0. "CLK_HSTX_SELECTED,This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1." "0,1"
group.long 0x60++0x7
line.long 0x0 "CLK_USB_CTRL,Clock control. can be changed on-the-fly (except for auxsrc)"
rbitfld.long 0x0 28. "ENABLED,clock generator is enabled" "0,1"
bitfld.long 0x0 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock" "0,1"
bitfld.long 0x0 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock" "0,1,2,3"
bitfld.long 0x0 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1"
newline
bitfld.long 0x0 10. "KILL,Asynchronously kills the clock generator enable must be set low before deasserting kill" "0,1"
bitfld.long 0x0 5.--7. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0,1,2,3,4,5,6,7"
line.long 0x4 "CLK_USB_DIV"
hexmask.long.byte 0x4 16.--19. 1. "INT"
rgroup.long 0x68++0x3
line.long 0x0 "CLK_USB_SELECTED,Indicates which src is currently selected (one-hot)"
bitfld.long 0x0 0. "CLK_USB_SELECTED,This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1." "0,1"
group.long 0x6C++0x7
line.long 0x0 "CLK_ADC_CTRL,Clock control. can be changed on-the-fly (except for auxsrc)"
rbitfld.long 0x0 28. "ENABLED,clock generator is enabled" "0,1"
bitfld.long 0x0 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock" "0,1"
bitfld.long 0x0 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock" "0,1,2,3"
bitfld.long 0x0 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1"
newline
bitfld.long 0x0 10. "KILL,Asynchronously kills the clock generator enable must be set low before deasserting kill" "0,1"
bitfld.long 0x0 5.--7. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0,1,2,3,4,5,6,7"
line.long 0x4 "CLK_ADC_DIV"
hexmask.long.byte 0x4 16.--19. 1. "INT"
rgroup.long 0x74++0x3
line.long 0x0 "CLK_ADC_SELECTED,Indicates which src is currently selected (one-hot)"
bitfld.long 0x0 0. "CLK_ADC_SELECTED,This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1." "0,1"
group.long 0x78++0xF
line.long 0x0 "DFTCLK_XOSC_CTRL"
bitfld.long 0x0 0.--1. "SRC" "0,1,2,3"
line.long 0x4 "DFTCLK_ROSC_CTRL"
bitfld.long 0x4 0.--1. "SRC" "0,1,2,3"
line.long 0x8 "DFTCLK_LPOSC_CTRL"
bitfld.long 0x8 0.--1. "SRC" "0,1,2,3"
line.long 0xC "CLK_SYS_RESUS_CTRL"
bitfld.long 0xC 16. "CLEAR,For clearing the resus after the fault that triggered it has been corrected" "0,1"
bitfld.long 0xC 12. "FRCE,Force a resus for test purposes only" "0,1"
bitfld.long 0xC 8. "ENABLE,Enable resus" "0,1"
hexmask.long.byte 0xC 0.--7. 1. "TIMEOUT,This is expressed as a number of clk_ref cycles"
rgroup.long 0x88++0x3
line.long 0x0 "CLK_SYS_RESUS_STATUS"
bitfld.long 0x0 0. "RESUSSED,Clock has been resuscitated correct the error then send ctrl_clear=1" "0,1"
group.long 0x8C++0x17
line.long 0x0 "FC0_REF_KHZ,Reference clock frequency in kHz"
hexmask.long.tbyte 0x0 0.--19. 1. "FC0_REF_KHZ"
line.long 0x4 "FC0_MIN_KHZ,Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags"
hexmask.long 0x4 0.--24. 1. "FC0_MIN_KHZ"
line.long 0x8 "FC0_MAX_KHZ,Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"
hexmask.long 0x8 0.--24. 1. "FC0_MAX_KHZ"
line.long 0xC "FC0_DELAY,Delays the start of frequency counting to allow the mux to settle"
bitfld.long 0xC 0.--2. "FC0_DELAY" "0,1,2,3,4,5,6,7"
line.long 0x10 "FC0_INTERVAL,The test interval is 0.98us * 2**interval. but let's call it 1us * 2**interval"
hexmask.long.byte 0x10 0.--3. 1. "FC0_INTERVAL"
line.long 0x14 "FC0_SRC,Clock sent to frequency counter. set to 0 when not required"
hexmask.long.byte 0x14 0.--7. 1. "FC0_SRC"
rgroup.long 0xA4++0x7
line.long 0x0 "FC0_STATUS,Frequency counter status"
bitfld.long 0x0 28. "DIED,Test clock stopped during test" "0,1"
bitfld.long 0x0 24. "FAST,Test clock faster than expected only valid when status_done=1" "0,1"
bitfld.long 0x0 20. "SLOW,Test clock slower than expected only valid when status_done=1" "0,1"
bitfld.long 0x0 16. "FAIL,Test failed" "0,1"
newline
bitfld.long 0x0 12. "WAITING,Waiting for test clock to start" "0,1"
bitfld.long 0x0 8. "RUNNING,Test running" "0,1"
bitfld.long 0x0 4. "DONE,Test complete" "0,1"
bitfld.long 0x0 0. "PASS,Test passed" "0,1"
line.long 0x4 "FC0_RESULT,Result of frequency measurement. only valid when status_done=1"
hexmask.long 0x4 5.--29. 1. "KHZ"
hexmask.long.byte 0x4 0.--4. 1. "FRAC"
group.long 0xAC++0xF
line.long 0x0 "WAKE_EN0,enable clock in wake mode"
bitfld.long 0x0 31. "CLK_SYS_SIO" "0,1"
bitfld.long 0x0 30. "CLK_SYS_SHA256" "0,1"
bitfld.long 0x0 29. "CLK_SYS_PSM" "0,1"
bitfld.long 0x0 28. "CLK_SYS_ROSC" "0,1"
newline
bitfld.long 0x0 27. "CLK_SYS_ROM" "0,1"
bitfld.long 0x0 26. "CLK_SYS_RESETS" "0,1"
bitfld.long 0x0 25. "CLK_SYS_PWM" "0,1"
bitfld.long 0x0 24. "CLK_SYS_POWMAN" "0,1"
newline
bitfld.long 0x0 23. "CLK_REF_POWMAN" "0,1"
bitfld.long 0x0 22. "CLK_SYS_PLL_USB" "0,1"
bitfld.long 0x0 21. "CLK_SYS_PLL_SYS" "0,1"
bitfld.long 0x0 20. "CLK_SYS_PIO2" "0,1"
newline
bitfld.long 0x0 19. "CLK_SYS_PIO1" "0,1"
bitfld.long 0x0 18. "CLK_SYS_PIO0" "0,1"
bitfld.long 0x0 17. "CLK_SYS_PADS" "0,1"
bitfld.long 0x0 16. "CLK_SYS_OTP" "0,1"
newline
bitfld.long 0x0 15. "CLK_REF_OTP" "0,1"
bitfld.long 0x0 14. "CLK_SYS_JTAG" "0,1"
bitfld.long 0x0 13. "CLK_SYS_IO" "0,1"
bitfld.long 0x0 12. "CLK_SYS_I2C1" "0,1"
newline
bitfld.long 0x0 11. "CLK_SYS_I2C0" "0,1"
bitfld.long 0x0 10. "CLK_SYS_HSTX" "0,1"
bitfld.long 0x0 9. "CLK_HSTX" "0,1"
bitfld.long 0x0 8. "CLK_SYS_GLITCH_DETECTOR" "0,1"
newline
bitfld.long 0x0 7. "CLK_SYS_DMA" "0,1"
bitfld.long 0x0 6. "CLK_SYS_BUSFABRIC" "0,1"
bitfld.long 0x0 5. "CLK_SYS_BUSCTRL" "0,1"
bitfld.long 0x0 4. "CLK_SYS_BOOTRAM" "0,1"
newline
bitfld.long 0x0 3. "CLK_SYS_ADC" "0,1"
bitfld.long 0x0 2. "CLK_ADC" "0,1"
bitfld.long 0x0 1. "CLK_SYS_ACCESSCTRL" "0,1"
bitfld.long 0x0 0. "CLK_SYS_CLOCKS" "0,1"
line.long 0x4 "WAKE_EN1,enable clock in wake mode"
bitfld.long 0x4 30. "CLK_SYS_XOSC" "0,1"
bitfld.long 0x4 29. "CLK_SYS_XIP" "0,1"
bitfld.long 0x4 28. "CLK_SYS_WATCHDOG" "0,1"
bitfld.long 0x4 27. "CLK_USB" "0,1"
newline
bitfld.long 0x4 26. "CLK_SYS_USBCTRL" "0,1"
bitfld.long 0x4 25. "CLK_SYS_UART1" "0,1"
bitfld.long 0x4 24. "CLK_PERI_UART1" "0,1"
bitfld.long 0x4 23. "CLK_SYS_UART0" "0,1"
newline
bitfld.long 0x4 22. "CLK_PERI_UART0" "0,1"
bitfld.long 0x4 21. "CLK_SYS_TRNG" "0,1"
bitfld.long 0x4 20. "CLK_SYS_TIMER1" "0,1"
bitfld.long 0x4 19. "CLK_SYS_TIMER0" "0,1"
newline
bitfld.long 0x4 18. "CLK_SYS_TICKS" "0,1"
bitfld.long 0x4 17. "CLK_REF_TICKS" "0,1"
bitfld.long 0x4 16. "CLK_SYS_TBMAN" "0,1"
bitfld.long 0x4 15. "CLK_SYS_SYSINFO" "0,1"
newline
bitfld.long 0x4 14. "CLK_SYS_SYSCFG" "0,1"
bitfld.long 0x4 13. "CLK_SYS_SRAM9" "0,1"
bitfld.long 0x4 12. "CLK_SYS_SRAM8" "0,1"
bitfld.long 0x4 11. "CLK_SYS_SRAM7" "0,1"
newline
bitfld.long 0x4 10. "CLK_SYS_SRAM6" "0,1"
bitfld.long 0x4 9. "CLK_SYS_SRAM5" "0,1"
bitfld.long 0x4 8. "CLK_SYS_SRAM4" "0,1"
bitfld.long 0x4 7. "CLK_SYS_SRAM3" "0,1"
newline
bitfld.long 0x4 6. "CLK_SYS_SRAM2" "0,1"
bitfld.long 0x4 5. "CLK_SYS_SRAM1" "0,1"
bitfld.long 0x4 4. "CLK_SYS_SRAM0" "0,1"
bitfld.long 0x4 3. "CLK_SYS_SPI1" "0,1"
newline
bitfld.long 0x4 2. "CLK_PERI_SPI1" "0,1"
bitfld.long 0x4 1. "CLK_SYS_SPI0" "0,1"
bitfld.long 0x4 0. "CLK_PERI_SPI0" "0,1"
line.long 0x8 "SLEEP_EN0,enable clock in sleep mode"
bitfld.long 0x8 31. "CLK_SYS_SIO" "0,1"
bitfld.long 0x8 30. "CLK_SYS_SHA256" "0,1"
bitfld.long 0x8 29. "CLK_SYS_PSM" "0,1"
bitfld.long 0x8 28. "CLK_SYS_ROSC" "0,1"
newline
bitfld.long 0x8 27. "CLK_SYS_ROM" "0,1"
bitfld.long 0x8 26. "CLK_SYS_RESETS" "0,1"
bitfld.long 0x8 25. "CLK_SYS_PWM" "0,1"
bitfld.long 0x8 24. "CLK_SYS_POWMAN" "0,1"
newline
bitfld.long 0x8 23. "CLK_REF_POWMAN" "0,1"
bitfld.long 0x8 22. "CLK_SYS_PLL_USB" "0,1"
bitfld.long 0x8 21. "CLK_SYS_PLL_SYS" "0,1"
bitfld.long 0x8 20. "CLK_SYS_PIO2" "0,1"
newline
bitfld.long 0x8 19. "CLK_SYS_PIO1" "0,1"
bitfld.long 0x8 18. "CLK_SYS_PIO0" "0,1"
bitfld.long 0x8 17. "CLK_SYS_PADS" "0,1"
bitfld.long 0x8 16. "CLK_SYS_OTP" "0,1"
newline
bitfld.long 0x8 15. "CLK_REF_OTP" "0,1"
bitfld.long 0x8 14. "CLK_SYS_JTAG" "0,1"
bitfld.long 0x8 13. "CLK_SYS_IO" "0,1"
bitfld.long 0x8 12. "CLK_SYS_I2C1" "0,1"
newline
bitfld.long 0x8 11. "CLK_SYS_I2C0" "0,1"
bitfld.long 0x8 10. "CLK_SYS_HSTX" "0,1"
bitfld.long 0x8 9. "CLK_HSTX" "0,1"
bitfld.long 0x8 8. "CLK_SYS_GLITCH_DETECTOR" "0,1"
newline
bitfld.long 0x8 7. "CLK_SYS_DMA" "0,1"
bitfld.long 0x8 6. "CLK_SYS_BUSFABRIC" "0,1"
bitfld.long 0x8 5. "CLK_SYS_BUSCTRL" "0,1"
bitfld.long 0x8 4. "CLK_SYS_BOOTRAM" "0,1"
newline
bitfld.long 0x8 3. "CLK_SYS_ADC" "0,1"
bitfld.long 0x8 2. "CLK_ADC" "0,1"
bitfld.long 0x8 1. "CLK_SYS_ACCESSCTRL" "0,1"
bitfld.long 0x8 0. "CLK_SYS_CLOCKS" "0,1"
line.long 0xC "SLEEP_EN1,enable clock in sleep mode"
bitfld.long 0xC 30. "CLK_SYS_XOSC" "0,1"
bitfld.long 0xC 29. "CLK_SYS_XIP" "0,1"
bitfld.long 0xC 28. "CLK_SYS_WATCHDOG" "0,1"
bitfld.long 0xC 27. "CLK_USB" "0,1"
newline
bitfld.long 0xC 26. "CLK_SYS_USBCTRL" "0,1"
bitfld.long 0xC 25. "CLK_SYS_UART1" "0,1"
bitfld.long 0xC 24. "CLK_PERI_UART1" "0,1"
bitfld.long 0xC 23. "CLK_SYS_UART0" "0,1"
newline
bitfld.long 0xC 22. "CLK_PERI_UART0" "0,1"
bitfld.long 0xC 21. "CLK_SYS_TRNG" "0,1"
bitfld.long 0xC 20. "CLK_SYS_TIMER1" "0,1"
bitfld.long 0xC 19. "CLK_SYS_TIMER0" "0,1"
newline
bitfld.long 0xC 18. "CLK_SYS_TICKS" "0,1"
bitfld.long 0xC 17. "CLK_REF_TICKS" "0,1"
bitfld.long 0xC 16. "CLK_SYS_TBMAN" "0,1"
bitfld.long 0xC 15. "CLK_SYS_SYSINFO" "0,1"
newline
bitfld.long 0xC 14. "CLK_SYS_SYSCFG" "0,1"
bitfld.long 0xC 13. "CLK_SYS_SRAM9" "0,1"
bitfld.long 0xC 12. "CLK_SYS_SRAM8" "0,1"
bitfld.long 0xC 11. "CLK_SYS_SRAM7" "0,1"
newline
bitfld.long 0xC 10. "CLK_SYS_SRAM6" "0,1"
bitfld.long 0xC 9. "CLK_SYS_SRAM5" "0,1"
bitfld.long 0xC 8. "CLK_SYS_SRAM4" "0,1"
bitfld.long 0xC 7. "CLK_SYS_SRAM3" "0,1"
newline
bitfld.long 0xC 6. "CLK_SYS_SRAM2" "0,1"
bitfld.long 0xC 5. "CLK_SYS_SRAM1" "0,1"
bitfld.long 0xC 4. "CLK_SYS_SRAM0" "0,1"
bitfld.long 0xC 3. "CLK_SYS_SPI1" "0,1"
newline
bitfld.long 0xC 2. "CLK_PERI_SPI1" "0,1"
bitfld.long 0xC 1. "CLK_SYS_SPI0" "0,1"
bitfld.long 0xC 0. "CLK_PERI_SPI0" "0,1"
rgroup.long 0xBC++0xB
line.long 0x0 "ENABLED0,indicates the state of the clock enable"
bitfld.long 0x0 31. "CLK_SYS_SIO" "0,1"
bitfld.long 0x0 30. "CLK_SYS_SHA256" "0,1"
bitfld.long 0x0 29. "CLK_SYS_PSM" "0,1"
bitfld.long 0x0 28. "CLK_SYS_ROSC" "0,1"
newline
bitfld.long 0x0 27. "CLK_SYS_ROM" "0,1"
bitfld.long 0x0 26. "CLK_SYS_RESETS" "0,1"
bitfld.long 0x0 25. "CLK_SYS_PWM" "0,1"
bitfld.long 0x0 24. "CLK_SYS_POWMAN" "0,1"
newline
bitfld.long 0x0 23. "CLK_REF_POWMAN" "0,1"
bitfld.long 0x0 22. "CLK_SYS_PLL_USB" "0,1"
bitfld.long 0x0 21. "CLK_SYS_PLL_SYS" "0,1"
bitfld.long 0x0 20. "CLK_SYS_PIO2" "0,1"
newline
bitfld.long 0x0 19. "CLK_SYS_PIO1" "0,1"
bitfld.long 0x0 18. "CLK_SYS_PIO0" "0,1"
bitfld.long 0x0 17. "CLK_SYS_PADS" "0,1"
bitfld.long 0x0 16. "CLK_SYS_OTP" "0,1"
newline
bitfld.long 0x0 15. "CLK_REF_OTP" "0,1"
bitfld.long 0x0 14. "CLK_SYS_JTAG" "0,1"
bitfld.long 0x0 13. "CLK_SYS_IO" "0,1"
bitfld.long 0x0 12. "CLK_SYS_I2C1" "0,1"
newline
bitfld.long 0x0 11. "CLK_SYS_I2C0" "0,1"
bitfld.long 0x0 10. "CLK_SYS_HSTX" "0,1"
bitfld.long 0x0 9. "CLK_HSTX" "0,1"
bitfld.long 0x0 8. "CLK_SYS_GLITCH_DETECTOR" "0,1"
newline
bitfld.long 0x0 7. "CLK_SYS_DMA" "0,1"
bitfld.long 0x0 6. "CLK_SYS_BUSFABRIC" "0,1"
bitfld.long 0x0 5. "CLK_SYS_BUSCTRL" "0,1"
bitfld.long 0x0 4. "CLK_SYS_BOOTRAM" "0,1"
newline
bitfld.long 0x0 3. "CLK_SYS_ADC" "0,1"
bitfld.long 0x0 2. "CLK_ADC" "0,1"
bitfld.long 0x0 1. "CLK_SYS_ACCESSCTRL" "0,1"
bitfld.long 0x0 0. "CLK_SYS_CLOCKS" "0,1"
line.long 0x4 "ENABLED1,indicates the state of the clock enable"
bitfld.long 0x4 30. "CLK_SYS_XOSC" "0,1"
bitfld.long 0x4 29. "CLK_SYS_XIP" "0,1"
bitfld.long 0x4 28. "CLK_SYS_WATCHDOG" "0,1"
bitfld.long 0x4 27. "CLK_USB" "0,1"
newline
bitfld.long 0x4 26. "CLK_SYS_USBCTRL" "0,1"
bitfld.long 0x4 25. "CLK_SYS_UART1" "0,1"
bitfld.long 0x4 24. "CLK_PERI_UART1" "0,1"
bitfld.long 0x4 23. "CLK_SYS_UART0" "0,1"
newline
bitfld.long 0x4 22. "CLK_PERI_UART0" "0,1"
bitfld.long 0x4 21. "CLK_SYS_TRNG" "0,1"
bitfld.long 0x4 20. "CLK_SYS_TIMER1" "0,1"
bitfld.long 0x4 19. "CLK_SYS_TIMER0" "0,1"
newline
bitfld.long 0x4 18. "CLK_SYS_TICKS" "0,1"
bitfld.long 0x4 17. "CLK_REF_TICKS" "0,1"
bitfld.long 0x4 16. "CLK_SYS_TBMAN" "0,1"
bitfld.long 0x4 15. "CLK_SYS_SYSINFO" "0,1"
newline
bitfld.long 0x4 14. "CLK_SYS_SYSCFG" "0,1"
bitfld.long 0x4 13. "CLK_SYS_SRAM9" "0,1"
bitfld.long 0x4 12. "CLK_SYS_SRAM8" "0,1"
bitfld.long 0x4 11. "CLK_SYS_SRAM7" "0,1"
newline
bitfld.long 0x4 10. "CLK_SYS_SRAM6" "0,1"
bitfld.long 0x4 9. "CLK_SYS_SRAM5" "0,1"
bitfld.long 0x4 8. "CLK_SYS_SRAM4" "0,1"
bitfld.long 0x4 7. "CLK_SYS_SRAM3" "0,1"
newline
bitfld.long 0x4 6. "CLK_SYS_SRAM2" "0,1"
bitfld.long 0x4 5. "CLK_SYS_SRAM1" "0,1"
bitfld.long 0x4 4. "CLK_SYS_SRAM0" "0,1"
bitfld.long 0x4 3. "CLK_SYS_SPI1" "0,1"
newline
bitfld.long 0x4 2. "CLK_PERI_SPI1" "0,1"
bitfld.long 0x4 1. "CLK_SYS_SPI0" "0,1"
bitfld.long 0x4 0. "CLK_PERI_SPI0" "0,1"
line.long 0x8 "INTR,Raw Interrupts"
bitfld.long 0x8 0. "CLK_SYS_RESUS" "0,1"
group.long 0xC8++0x7
line.long 0x0 "INTE,Interrupt Enable"
bitfld.long 0x0 0. "CLK_SYS_RESUS" "0,1"
line.long 0x4 "INTF,Interrupt Force"
bitfld.long 0x4 0. "CLK_SYS_RESUS" "0,1"
rgroup.long 0xD0++0x3
line.long 0x0 "INTS,Interrupt status after masking & forcing"
bitfld.long 0x0 0. "CLK_SYS_RESUS" "0,1"
tree.end
tree "CORESIGHT_TRACE"
base ad:0x50700000
group.long 0x0++0x3
line.long 0x0 "CTRL_STATUS,Control and status register"
bitfld.long 0x0 1. "TRACE_CAPTURE_FIFO_OVERFLOW,This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit." "0,1"
bitfld.long 0x0 0. "TRACE_CAPTURE_FIFO_FLUSH,Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow." "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "TRACE_CAPTURE_FIFO,FIFO for trace data captured from the TPIU"
hexmask.long 0x0 0.--31. 1. "RDATA,Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU."
tree.end
tree "DMA (Direct Memory Access)"
base ad:0x50000000
group.long 0x0++0x44F
line.long 0x0 "CH0_READ_ADDR,DMA Channel 0 Read Address pointer"
hexmask.long 0x0 0.--31. 1. "CH0_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x4 "CH0_WRITE_ADDR,DMA Channel 0 Write Address pointer"
hexmask.long 0x4 0.--31. 1. "CH0_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x8 "CH0_TRANS_COUNT,DMA Channel 0 Transfer Count"
hexmask.long.byte 0x8 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x8 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0xC "CH0_CTRL_TRIG,DMA Channel 0 Control and Status"
rbitfld.long 0xC 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0xC 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0xC 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
newline
rbitfld.long 0xC 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0xC 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0xC 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0xC 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0xC 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0xC 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
newline
bitfld.long 0xC 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0xC 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0xC 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
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bitfld.long 0xC 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0xC 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0xC 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
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bitfld.long 0xC 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0xC 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0xC 0. "EN,DMA Channel Enable." "0,1"
line.long 0x10 "CH0_AL1_CTRL,Alias for channel 0 CTRL register"
hexmask.long 0x10 0.--31. 1. "CH0_AL1_CTRL"
line.long 0x14 "CH0_AL1_READ_ADDR,Alias for channel 0 READ_ADDR register"
hexmask.long 0x14 0.--31. 1. "CH0_AL1_READ_ADDR"
line.long 0x18 "CH0_AL1_WRITE_ADDR,Alias for channel 0 WRITE_ADDR register"
hexmask.long 0x18 0.--31. 1. "CH0_AL1_WRITE_ADDR"
line.long 0x1C "CH0_AL1_TRANS_COUNT_TRIG,Alias for channel 0 TRANS_COUNT register"
hexmask.long 0x1C 0.--31. 1. "CH0_AL1_TRANS_COUNT_TRIG"
line.long 0x20 "CH0_AL2_CTRL,Alias for channel 0 CTRL register"
hexmask.long 0x20 0.--31. 1. "CH0_AL2_CTRL"
line.long 0x24 "CH0_AL2_TRANS_COUNT,Alias for channel 0 TRANS_COUNT register"
hexmask.long 0x24 0.--31. 1. "CH0_AL2_TRANS_COUNT"
line.long 0x28 "CH0_AL2_READ_ADDR,Alias for channel 0 READ_ADDR register"
hexmask.long 0x28 0.--31. 1. "CH0_AL2_READ_ADDR"
line.long 0x2C "CH0_AL2_WRITE_ADDR_TRIG,Alias for channel 0 WRITE_ADDR register"
hexmask.long 0x2C 0.--31. 1. "CH0_AL2_WRITE_ADDR_TRIG"
line.long 0x30 "CH0_AL3_CTRL,Alias for channel 0 CTRL register"
hexmask.long 0x30 0.--31. 1. "CH0_AL3_CTRL"
line.long 0x34 "CH0_AL3_WRITE_ADDR,Alias for channel 0 WRITE_ADDR register"
hexmask.long 0x34 0.--31. 1. "CH0_AL3_WRITE_ADDR"
line.long 0x38 "CH0_AL3_TRANS_COUNT,Alias for channel 0 TRANS_COUNT register"
hexmask.long 0x38 0.--31. 1. "CH0_AL3_TRANS_COUNT"
line.long 0x3C "CH0_AL3_READ_ADDR_TRIG,Alias for channel 0 READ_ADDR register"
hexmask.long 0x3C 0.--31. 1. "CH0_AL3_READ_ADDR_TRIG"
line.long 0x40 "CH1_READ_ADDR,DMA Channel 1 Read Address pointer"
hexmask.long 0x40 0.--31. 1. "CH1_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x44 "CH1_WRITE_ADDR,DMA Channel 1 Write Address pointer"
hexmask.long 0x44 0.--31. 1. "CH1_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x48 "CH1_TRANS_COUNT,DMA Channel 1 Transfer Count"
hexmask.long.byte 0x48 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x48 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x4C "CH1_CTRL_TRIG,DMA Channel 1 Control and Status"
rbitfld.long 0x4C 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x4C 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x4C 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
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rbitfld.long 0x4C 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x4C 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x4C 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
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bitfld.long 0x4C 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x4C 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x4C 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
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bitfld.long 0x4C 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x4C 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x4C 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
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bitfld.long 0x4C 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x4C 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x4C 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
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bitfld.long 0x4C 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x4C 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x4C 0. "EN,DMA Channel Enable." "0,1"
line.long 0x50 "CH1_AL1_CTRL,Alias for channel 1 CTRL register"
hexmask.long 0x50 0.--31. 1. "CH1_AL1_CTRL"
line.long 0x54 "CH1_AL1_READ_ADDR,Alias for channel 1 READ_ADDR register"
hexmask.long 0x54 0.--31. 1. "CH1_AL1_READ_ADDR"
line.long 0x58 "CH1_AL1_WRITE_ADDR,Alias for channel 1 WRITE_ADDR register"
hexmask.long 0x58 0.--31. 1. "CH1_AL1_WRITE_ADDR"
line.long 0x5C "CH1_AL1_TRANS_COUNT_TRIG,Alias for channel 1 TRANS_COUNT register"
hexmask.long 0x5C 0.--31. 1. "CH1_AL1_TRANS_COUNT_TRIG"
line.long 0x60 "CH1_AL2_CTRL,Alias for channel 1 CTRL register"
hexmask.long 0x60 0.--31. 1. "CH1_AL2_CTRL"
line.long 0x64 "CH1_AL2_TRANS_COUNT,Alias for channel 1 TRANS_COUNT register"
hexmask.long 0x64 0.--31. 1. "CH1_AL2_TRANS_COUNT"
line.long 0x68 "CH1_AL2_READ_ADDR,Alias for channel 1 READ_ADDR register"
hexmask.long 0x68 0.--31. 1. "CH1_AL2_READ_ADDR"
line.long 0x6C "CH1_AL2_WRITE_ADDR_TRIG,Alias for channel 1 WRITE_ADDR register"
hexmask.long 0x6C 0.--31. 1. "CH1_AL2_WRITE_ADDR_TRIG"
line.long 0x70 "CH1_AL3_CTRL,Alias for channel 1 CTRL register"
hexmask.long 0x70 0.--31. 1. "CH1_AL3_CTRL"
line.long 0x74 "CH1_AL3_WRITE_ADDR,Alias for channel 1 WRITE_ADDR register"
hexmask.long 0x74 0.--31. 1. "CH1_AL3_WRITE_ADDR"
line.long 0x78 "CH1_AL3_TRANS_COUNT,Alias for channel 1 TRANS_COUNT register"
hexmask.long 0x78 0.--31. 1. "CH1_AL3_TRANS_COUNT"
line.long 0x7C "CH1_AL3_READ_ADDR_TRIG,Alias for channel 1 READ_ADDR register"
hexmask.long 0x7C 0.--31. 1. "CH1_AL3_READ_ADDR_TRIG"
line.long 0x80 "CH2_READ_ADDR,DMA Channel 2 Read Address pointer"
hexmask.long 0x80 0.--31. 1. "CH2_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x84 "CH2_WRITE_ADDR,DMA Channel 2 Write Address pointer"
hexmask.long 0x84 0.--31. 1. "CH2_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x88 "CH2_TRANS_COUNT,DMA Channel 2 Transfer Count"
hexmask.long.byte 0x88 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x88 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x8C "CH2_CTRL_TRIG,DMA Channel 2 Control and Status"
rbitfld.long 0x8C 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x8C 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x8C 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
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rbitfld.long 0x8C 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x8C 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x8C 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
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bitfld.long 0x8C 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x8C 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x8C 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
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bitfld.long 0x8C 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x8C 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x8C 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
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bitfld.long 0x8C 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x8C 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x8C 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
newline
bitfld.long 0x8C 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x8C 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x8C 0. "EN,DMA Channel Enable." "0,1"
line.long 0x90 "CH2_AL1_CTRL,Alias for channel 2 CTRL register"
hexmask.long 0x90 0.--31. 1. "CH2_AL1_CTRL"
line.long 0x94 "CH2_AL1_READ_ADDR,Alias for channel 2 READ_ADDR register"
hexmask.long 0x94 0.--31. 1. "CH2_AL1_READ_ADDR"
line.long 0x98 "CH2_AL1_WRITE_ADDR,Alias for channel 2 WRITE_ADDR register"
hexmask.long 0x98 0.--31. 1. "CH2_AL1_WRITE_ADDR"
line.long 0x9C "CH2_AL1_TRANS_COUNT_TRIG,Alias for channel 2 TRANS_COUNT register"
hexmask.long 0x9C 0.--31. 1. "CH2_AL1_TRANS_COUNT_TRIG"
line.long 0xA0 "CH2_AL2_CTRL,Alias for channel 2 CTRL register"
hexmask.long 0xA0 0.--31. 1. "CH2_AL2_CTRL"
line.long 0xA4 "CH2_AL2_TRANS_COUNT,Alias for channel 2 TRANS_COUNT register"
hexmask.long 0xA4 0.--31. 1. "CH2_AL2_TRANS_COUNT"
line.long 0xA8 "CH2_AL2_READ_ADDR,Alias for channel 2 READ_ADDR register"
hexmask.long 0xA8 0.--31. 1. "CH2_AL2_READ_ADDR"
line.long 0xAC "CH2_AL2_WRITE_ADDR_TRIG,Alias for channel 2 WRITE_ADDR register"
hexmask.long 0xAC 0.--31. 1. "CH2_AL2_WRITE_ADDR_TRIG"
line.long 0xB0 "CH2_AL3_CTRL,Alias for channel 2 CTRL register"
hexmask.long 0xB0 0.--31. 1. "CH2_AL3_CTRL"
line.long 0xB4 "CH2_AL3_WRITE_ADDR,Alias for channel 2 WRITE_ADDR register"
hexmask.long 0xB4 0.--31. 1. "CH2_AL3_WRITE_ADDR"
line.long 0xB8 "CH2_AL3_TRANS_COUNT,Alias for channel 2 TRANS_COUNT register"
hexmask.long 0xB8 0.--31. 1. "CH2_AL3_TRANS_COUNT"
line.long 0xBC "CH2_AL3_READ_ADDR_TRIG,Alias for channel 2 READ_ADDR register"
hexmask.long 0xBC 0.--31. 1. "CH2_AL3_READ_ADDR_TRIG"
line.long 0xC0 "CH3_READ_ADDR,DMA Channel 3 Read Address pointer"
hexmask.long 0xC0 0.--31. 1. "CH3_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0xC4 "CH3_WRITE_ADDR,DMA Channel 3 Write Address pointer"
hexmask.long 0xC4 0.--31. 1. "CH3_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0xC8 "CH3_TRANS_COUNT,DMA Channel 3 Transfer Count"
hexmask.long.byte 0xC8 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0xC8 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0xCC "CH3_CTRL_TRIG,DMA Channel 3 Control and Status"
rbitfld.long 0xCC 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0xCC 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0xCC 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
newline
rbitfld.long 0xCC 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0xCC 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0xCC 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0xCC 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0xCC 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0xCC 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
newline
bitfld.long 0xCC 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0xCC 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0xCC 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
newline
bitfld.long 0xCC 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0xCC 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0xCC 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
newline
bitfld.long 0xCC 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0xCC 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0xCC 0. "EN,DMA Channel Enable." "0,1"
line.long 0xD0 "CH3_AL1_CTRL,Alias for channel 3 CTRL register"
hexmask.long 0xD0 0.--31. 1. "CH3_AL1_CTRL"
line.long 0xD4 "CH3_AL1_READ_ADDR,Alias for channel 3 READ_ADDR register"
hexmask.long 0xD4 0.--31. 1. "CH3_AL1_READ_ADDR"
line.long 0xD8 "CH3_AL1_WRITE_ADDR,Alias for channel 3 WRITE_ADDR register"
hexmask.long 0xD8 0.--31. 1. "CH3_AL1_WRITE_ADDR"
line.long 0xDC "CH3_AL1_TRANS_COUNT_TRIG,Alias for channel 3 TRANS_COUNT register"
hexmask.long 0xDC 0.--31. 1. "CH3_AL1_TRANS_COUNT_TRIG"
line.long 0xE0 "CH3_AL2_CTRL,Alias for channel 3 CTRL register"
hexmask.long 0xE0 0.--31. 1. "CH3_AL2_CTRL"
line.long 0xE4 "CH3_AL2_TRANS_COUNT,Alias for channel 3 TRANS_COUNT register"
hexmask.long 0xE4 0.--31. 1. "CH3_AL2_TRANS_COUNT"
line.long 0xE8 "CH3_AL2_READ_ADDR,Alias for channel 3 READ_ADDR register"
hexmask.long 0xE8 0.--31. 1. "CH3_AL2_READ_ADDR"
line.long 0xEC "CH3_AL2_WRITE_ADDR_TRIG,Alias for channel 3 WRITE_ADDR register"
hexmask.long 0xEC 0.--31. 1. "CH3_AL2_WRITE_ADDR_TRIG"
line.long 0xF0 "CH3_AL3_CTRL,Alias for channel 3 CTRL register"
hexmask.long 0xF0 0.--31. 1. "CH3_AL3_CTRL"
line.long 0xF4 "CH3_AL3_WRITE_ADDR,Alias for channel 3 WRITE_ADDR register"
hexmask.long 0xF4 0.--31. 1. "CH3_AL3_WRITE_ADDR"
line.long 0xF8 "CH3_AL3_TRANS_COUNT,Alias for channel 3 TRANS_COUNT register"
hexmask.long 0xF8 0.--31. 1. "CH3_AL3_TRANS_COUNT"
line.long 0xFC "CH3_AL3_READ_ADDR_TRIG,Alias for channel 3 READ_ADDR register"
hexmask.long 0xFC 0.--31. 1. "CH3_AL3_READ_ADDR_TRIG"
line.long 0x100 "CH4_READ_ADDR,DMA Channel 4 Read Address pointer"
hexmask.long 0x100 0.--31. 1. "CH4_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x104 "CH4_WRITE_ADDR,DMA Channel 4 Write Address pointer"
hexmask.long 0x104 0.--31. 1. "CH4_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x108 "CH4_TRANS_COUNT,DMA Channel 4 Transfer Count"
hexmask.long.byte 0x108 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x108 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x10C "CH4_CTRL_TRIG,DMA Channel 4 Control and Status"
rbitfld.long 0x10C 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x10C 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x10C 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
newline
rbitfld.long 0x10C 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x10C 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x10C 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0x10C 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x10C 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x10C 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
newline
bitfld.long 0x10C 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x10C 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x10C 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
newline
bitfld.long 0x10C 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x10C 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x10C 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
newline
bitfld.long 0x10C 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x10C 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x10C 0. "EN,DMA Channel Enable." "0,1"
line.long 0x110 "CH4_AL1_CTRL,Alias for channel 4 CTRL register"
hexmask.long 0x110 0.--31. 1. "CH4_AL1_CTRL"
line.long 0x114 "CH4_AL1_READ_ADDR,Alias for channel 4 READ_ADDR register"
hexmask.long 0x114 0.--31. 1. "CH4_AL1_READ_ADDR"
line.long 0x118 "CH4_AL1_WRITE_ADDR,Alias for channel 4 WRITE_ADDR register"
hexmask.long 0x118 0.--31. 1. "CH4_AL1_WRITE_ADDR"
line.long 0x11C "CH4_AL1_TRANS_COUNT_TRIG,Alias for channel 4 TRANS_COUNT register"
hexmask.long 0x11C 0.--31. 1. "CH4_AL1_TRANS_COUNT_TRIG"
line.long 0x120 "CH4_AL2_CTRL,Alias for channel 4 CTRL register"
hexmask.long 0x120 0.--31. 1. "CH4_AL2_CTRL"
line.long 0x124 "CH4_AL2_TRANS_COUNT,Alias for channel 4 TRANS_COUNT register"
hexmask.long 0x124 0.--31. 1. "CH4_AL2_TRANS_COUNT"
line.long 0x128 "CH4_AL2_READ_ADDR,Alias for channel 4 READ_ADDR register"
hexmask.long 0x128 0.--31. 1. "CH4_AL2_READ_ADDR"
line.long 0x12C "CH4_AL2_WRITE_ADDR_TRIG,Alias for channel 4 WRITE_ADDR register"
hexmask.long 0x12C 0.--31. 1. "CH4_AL2_WRITE_ADDR_TRIG"
line.long 0x130 "CH4_AL3_CTRL,Alias for channel 4 CTRL register"
hexmask.long 0x130 0.--31. 1. "CH4_AL3_CTRL"
line.long 0x134 "CH4_AL3_WRITE_ADDR,Alias for channel 4 WRITE_ADDR register"
hexmask.long 0x134 0.--31. 1. "CH4_AL3_WRITE_ADDR"
line.long 0x138 "CH4_AL3_TRANS_COUNT,Alias for channel 4 TRANS_COUNT register"
hexmask.long 0x138 0.--31. 1. "CH4_AL3_TRANS_COUNT"
line.long 0x13C "CH4_AL3_READ_ADDR_TRIG,Alias for channel 4 READ_ADDR register"
hexmask.long 0x13C 0.--31. 1. "CH4_AL3_READ_ADDR_TRIG"
line.long 0x140 "CH5_READ_ADDR,DMA Channel 5 Read Address pointer"
hexmask.long 0x140 0.--31. 1. "CH5_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x144 "CH5_WRITE_ADDR,DMA Channel 5 Write Address pointer"
hexmask.long 0x144 0.--31. 1. "CH5_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x148 "CH5_TRANS_COUNT,DMA Channel 5 Transfer Count"
hexmask.long.byte 0x148 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x148 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x14C "CH5_CTRL_TRIG,DMA Channel 5 Control and Status"
rbitfld.long 0x14C 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x14C 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x14C 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
newline
rbitfld.long 0x14C 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x14C 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x14C 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0x14C 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x14C 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x14C 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
newline
bitfld.long 0x14C 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x14C 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x14C 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
newline
bitfld.long 0x14C 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x14C 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x14C 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
newline
bitfld.long 0x14C 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x14C 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x14C 0. "EN,DMA Channel Enable." "0,1"
line.long 0x150 "CH5_AL1_CTRL,Alias for channel 5 CTRL register"
hexmask.long 0x150 0.--31. 1. "CH5_AL1_CTRL"
line.long 0x154 "CH5_AL1_READ_ADDR,Alias for channel 5 READ_ADDR register"
hexmask.long 0x154 0.--31. 1. "CH5_AL1_READ_ADDR"
line.long 0x158 "CH5_AL1_WRITE_ADDR,Alias for channel 5 WRITE_ADDR register"
hexmask.long 0x158 0.--31. 1. "CH5_AL1_WRITE_ADDR"
line.long 0x15C "CH5_AL1_TRANS_COUNT_TRIG,Alias for channel 5 TRANS_COUNT register"
hexmask.long 0x15C 0.--31. 1. "CH5_AL1_TRANS_COUNT_TRIG"
line.long 0x160 "CH5_AL2_CTRL,Alias for channel 5 CTRL register"
hexmask.long 0x160 0.--31. 1. "CH5_AL2_CTRL"
line.long 0x164 "CH5_AL2_TRANS_COUNT,Alias for channel 5 TRANS_COUNT register"
hexmask.long 0x164 0.--31. 1. "CH5_AL2_TRANS_COUNT"
line.long 0x168 "CH5_AL2_READ_ADDR,Alias for channel 5 READ_ADDR register"
hexmask.long 0x168 0.--31. 1. "CH5_AL2_READ_ADDR"
line.long 0x16C "CH5_AL2_WRITE_ADDR_TRIG,Alias for channel 5 WRITE_ADDR register"
hexmask.long 0x16C 0.--31. 1. "CH5_AL2_WRITE_ADDR_TRIG"
line.long 0x170 "CH5_AL3_CTRL,Alias for channel 5 CTRL register"
hexmask.long 0x170 0.--31. 1. "CH5_AL3_CTRL"
line.long 0x174 "CH5_AL3_WRITE_ADDR,Alias for channel 5 WRITE_ADDR register"
hexmask.long 0x174 0.--31. 1. "CH5_AL3_WRITE_ADDR"
line.long 0x178 "CH5_AL3_TRANS_COUNT,Alias for channel 5 TRANS_COUNT register"
hexmask.long 0x178 0.--31. 1. "CH5_AL3_TRANS_COUNT"
line.long 0x17C "CH5_AL3_READ_ADDR_TRIG,Alias for channel 5 READ_ADDR register"
hexmask.long 0x17C 0.--31. 1. "CH5_AL3_READ_ADDR_TRIG"
line.long 0x180 "CH6_READ_ADDR,DMA Channel 6 Read Address pointer"
hexmask.long 0x180 0.--31. 1. "CH6_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x184 "CH6_WRITE_ADDR,DMA Channel 6 Write Address pointer"
hexmask.long 0x184 0.--31. 1. "CH6_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x188 "CH6_TRANS_COUNT,DMA Channel 6 Transfer Count"
hexmask.long.byte 0x188 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x188 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x18C "CH6_CTRL_TRIG,DMA Channel 6 Control and Status"
rbitfld.long 0x18C 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x18C 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x18C 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
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rbitfld.long 0x18C 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x18C 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x18C 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0x18C 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x18C 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x18C 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
newline
bitfld.long 0x18C 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x18C 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x18C 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
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bitfld.long 0x18C 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x18C 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x18C 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
newline
bitfld.long 0x18C 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x18C 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x18C 0. "EN,DMA Channel Enable." "0,1"
line.long 0x190 "CH6_AL1_CTRL,Alias for channel 6 CTRL register"
hexmask.long 0x190 0.--31. 1. "CH6_AL1_CTRL"
line.long 0x194 "CH6_AL1_READ_ADDR,Alias for channel 6 READ_ADDR register"
hexmask.long 0x194 0.--31. 1. "CH6_AL1_READ_ADDR"
line.long 0x198 "CH6_AL1_WRITE_ADDR,Alias for channel 6 WRITE_ADDR register"
hexmask.long 0x198 0.--31. 1. "CH6_AL1_WRITE_ADDR"
line.long 0x19C "CH6_AL1_TRANS_COUNT_TRIG,Alias for channel 6 TRANS_COUNT register"
hexmask.long 0x19C 0.--31. 1. "CH6_AL1_TRANS_COUNT_TRIG"
line.long 0x1A0 "CH6_AL2_CTRL,Alias for channel 6 CTRL register"
hexmask.long 0x1A0 0.--31. 1. "CH6_AL2_CTRL"
line.long 0x1A4 "CH6_AL2_TRANS_COUNT,Alias for channel 6 TRANS_COUNT register"
hexmask.long 0x1A4 0.--31. 1. "CH6_AL2_TRANS_COUNT"
line.long 0x1A8 "CH6_AL2_READ_ADDR,Alias for channel 6 READ_ADDR register"
hexmask.long 0x1A8 0.--31. 1. "CH6_AL2_READ_ADDR"
line.long 0x1AC "CH6_AL2_WRITE_ADDR_TRIG,Alias for channel 6 WRITE_ADDR register"
hexmask.long 0x1AC 0.--31. 1. "CH6_AL2_WRITE_ADDR_TRIG"
line.long 0x1B0 "CH6_AL3_CTRL,Alias for channel 6 CTRL register"
hexmask.long 0x1B0 0.--31. 1. "CH6_AL3_CTRL"
line.long 0x1B4 "CH6_AL3_WRITE_ADDR,Alias for channel 6 WRITE_ADDR register"
hexmask.long 0x1B4 0.--31. 1. "CH6_AL3_WRITE_ADDR"
line.long 0x1B8 "CH6_AL3_TRANS_COUNT,Alias for channel 6 TRANS_COUNT register"
hexmask.long 0x1B8 0.--31. 1. "CH6_AL3_TRANS_COUNT"
line.long 0x1BC "CH6_AL3_READ_ADDR_TRIG,Alias for channel 6 READ_ADDR register"
hexmask.long 0x1BC 0.--31. 1. "CH6_AL3_READ_ADDR_TRIG"
line.long 0x1C0 "CH7_READ_ADDR,DMA Channel 7 Read Address pointer"
hexmask.long 0x1C0 0.--31. 1. "CH7_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x1C4 "CH7_WRITE_ADDR,DMA Channel 7 Write Address pointer"
hexmask.long 0x1C4 0.--31. 1. "CH7_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x1C8 "CH7_TRANS_COUNT,DMA Channel 7 Transfer Count"
hexmask.long.byte 0x1C8 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x1C8 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x1CC "CH7_CTRL_TRIG,DMA Channel 7 Control and Status"
rbitfld.long 0x1CC 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x1CC 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x1CC 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
newline
rbitfld.long 0x1CC 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x1CC 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x1CC 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0x1CC 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x1CC 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x1CC 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
newline
bitfld.long 0x1CC 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x1CC 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x1CC 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
newline
bitfld.long 0x1CC 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x1CC 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x1CC 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
newline
bitfld.long 0x1CC 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x1CC 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x1CC 0. "EN,DMA Channel Enable." "0,1"
line.long 0x1D0 "CH7_AL1_CTRL,Alias for channel 7 CTRL register"
hexmask.long 0x1D0 0.--31. 1. "CH7_AL1_CTRL"
line.long 0x1D4 "CH7_AL1_READ_ADDR,Alias for channel 7 READ_ADDR register"
hexmask.long 0x1D4 0.--31. 1. "CH7_AL1_READ_ADDR"
line.long 0x1D8 "CH7_AL1_WRITE_ADDR,Alias for channel 7 WRITE_ADDR register"
hexmask.long 0x1D8 0.--31. 1. "CH7_AL1_WRITE_ADDR"
line.long 0x1DC "CH7_AL1_TRANS_COUNT_TRIG,Alias for channel 7 TRANS_COUNT register"
hexmask.long 0x1DC 0.--31. 1. "CH7_AL1_TRANS_COUNT_TRIG"
line.long 0x1E0 "CH7_AL2_CTRL,Alias for channel 7 CTRL register"
hexmask.long 0x1E0 0.--31. 1. "CH7_AL2_CTRL"
line.long 0x1E4 "CH7_AL2_TRANS_COUNT,Alias for channel 7 TRANS_COUNT register"
hexmask.long 0x1E4 0.--31. 1. "CH7_AL2_TRANS_COUNT"
line.long 0x1E8 "CH7_AL2_READ_ADDR,Alias for channel 7 READ_ADDR register"
hexmask.long 0x1E8 0.--31. 1. "CH7_AL2_READ_ADDR"
line.long 0x1EC "CH7_AL2_WRITE_ADDR_TRIG,Alias for channel 7 WRITE_ADDR register"
hexmask.long 0x1EC 0.--31. 1. "CH7_AL2_WRITE_ADDR_TRIG"
line.long 0x1F0 "CH7_AL3_CTRL,Alias for channel 7 CTRL register"
hexmask.long 0x1F0 0.--31. 1. "CH7_AL3_CTRL"
line.long 0x1F4 "CH7_AL3_WRITE_ADDR,Alias for channel 7 WRITE_ADDR register"
hexmask.long 0x1F4 0.--31. 1. "CH7_AL3_WRITE_ADDR"
line.long 0x1F8 "CH7_AL3_TRANS_COUNT,Alias for channel 7 TRANS_COUNT register"
hexmask.long 0x1F8 0.--31. 1. "CH7_AL3_TRANS_COUNT"
line.long 0x1FC "CH7_AL3_READ_ADDR_TRIG,Alias for channel 7 READ_ADDR register"
hexmask.long 0x1FC 0.--31. 1. "CH7_AL3_READ_ADDR_TRIG"
line.long 0x200 "CH8_READ_ADDR,DMA Channel 8 Read Address pointer"
hexmask.long 0x200 0.--31. 1. "CH8_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x204 "CH8_WRITE_ADDR,DMA Channel 8 Write Address pointer"
hexmask.long 0x204 0.--31. 1. "CH8_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x208 "CH8_TRANS_COUNT,DMA Channel 8 Transfer Count"
hexmask.long.byte 0x208 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x208 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x20C "CH8_CTRL_TRIG,DMA Channel 8 Control and Status"
rbitfld.long 0x20C 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x20C 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x20C 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
newline
rbitfld.long 0x20C 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x20C 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x20C 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0x20C 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x20C 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x20C 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
newline
bitfld.long 0x20C 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x20C 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x20C 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
newline
bitfld.long 0x20C 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x20C 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x20C 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
newline
bitfld.long 0x20C 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x20C 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x20C 0. "EN,DMA Channel Enable." "0,1"
line.long 0x210 "CH8_AL1_CTRL,Alias for channel 8 CTRL register"
hexmask.long 0x210 0.--31. 1. "CH8_AL1_CTRL"
line.long 0x214 "CH8_AL1_READ_ADDR,Alias for channel 8 READ_ADDR register"
hexmask.long 0x214 0.--31. 1. "CH8_AL1_READ_ADDR"
line.long 0x218 "CH8_AL1_WRITE_ADDR,Alias for channel 8 WRITE_ADDR register"
hexmask.long 0x218 0.--31. 1. "CH8_AL1_WRITE_ADDR"
line.long 0x21C "CH8_AL1_TRANS_COUNT_TRIG,Alias for channel 8 TRANS_COUNT register"
hexmask.long 0x21C 0.--31. 1. "CH8_AL1_TRANS_COUNT_TRIG"
line.long 0x220 "CH8_AL2_CTRL,Alias for channel 8 CTRL register"
hexmask.long 0x220 0.--31. 1. "CH8_AL2_CTRL"
line.long 0x224 "CH8_AL2_TRANS_COUNT,Alias for channel 8 TRANS_COUNT register"
hexmask.long 0x224 0.--31. 1. "CH8_AL2_TRANS_COUNT"
line.long 0x228 "CH8_AL2_READ_ADDR,Alias for channel 8 READ_ADDR register"
hexmask.long 0x228 0.--31. 1. "CH8_AL2_READ_ADDR"
line.long 0x22C "CH8_AL2_WRITE_ADDR_TRIG,Alias for channel 8 WRITE_ADDR register"
hexmask.long 0x22C 0.--31. 1. "CH8_AL2_WRITE_ADDR_TRIG"
line.long 0x230 "CH8_AL3_CTRL,Alias for channel 8 CTRL register"
hexmask.long 0x230 0.--31. 1. "CH8_AL3_CTRL"
line.long 0x234 "CH8_AL3_WRITE_ADDR,Alias for channel 8 WRITE_ADDR register"
hexmask.long 0x234 0.--31. 1. "CH8_AL3_WRITE_ADDR"
line.long 0x238 "CH8_AL3_TRANS_COUNT,Alias for channel 8 TRANS_COUNT register"
hexmask.long 0x238 0.--31. 1. "CH8_AL3_TRANS_COUNT"
line.long 0x23C "CH8_AL3_READ_ADDR_TRIG,Alias for channel 8 READ_ADDR register"
hexmask.long 0x23C 0.--31. 1. "CH8_AL3_READ_ADDR_TRIG"
line.long 0x240 "CH9_READ_ADDR,DMA Channel 9 Read Address pointer"
hexmask.long 0x240 0.--31. 1. "CH9_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x244 "CH9_WRITE_ADDR,DMA Channel 9 Write Address pointer"
hexmask.long 0x244 0.--31. 1. "CH9_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x248 "CH9_TRANS_COUNT,DMA Channel 9 Transfer Count"
hexmask.long.byte 0x248 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x248 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x24C "CH9_CTRL_TRIG,DMA Channel 9 Control and Status"
rbitfld.long 0x24C 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x24C 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x24C 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
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rbitfld.long 0x24C 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x24C 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x24C 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
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bitfld.long 0x24C 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x24C 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x24C 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
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bitfld.long 0x24C 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x24C 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x24C 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
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bitfld.long 0x24C 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x24C 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x24C 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
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bitfld.long 0x24C 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x24C 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x24C 0. "EN,DMA Channel Enable." "0,1"
line.long 0x250 "CH9_AL1_CTRL,Alias for channel 9 CTRL register"
hexmask.long 0x250 0.--31. 1. "CH9_AL1_CTRL"
line.long 0x254 "CH9_AL1_READ_ADDR,Alias for channel 9 READ_ADDR register"
hexmask.long 0x254 0.--31. 1. "CH9_AL1_READ_ADDR"
line.long 0x258 "CH9_AL1_WRITE_ADDR,Alias for channel 9 WRITE_ADDR register"
hexmask.long 0x258 0.--31. 1. "CH9_AL1_WRITE_ADDR"
line.long 0x25C "CH9_AL1_TRANS_COUNT_TRIG,Alias for channel 9 TRANS_COUNT register"
hexmask.long 0x25C 0.--31. 1. "CH9_AL1_TRANS_COUNT_TRIG"
line.long 0x260 "CH9_AL2_CTRL,Alias for channel 9 CTRL register"
hexmask.long 0x260 0.--31. 1. "CH9_AL2_CTRL"
line.long 0x264 "CH9_AL2_TRANS_COUNT,Alias for channel 9 TRANS_COUNT register"
hexmask.long 0x264 0.--31. 1. "CH9_AL2_TRANS_COUNT"
line.long 0x268 "CH9_AL2_READ_ADDR,Alias for channel 9 READ_ADDR register"
hexmask.long 0x268 0.--31. 1. "CH9_AL2_READ_ADDR"
line.long 0x26C "CH9_AL2_WRITE_ADDR_TRIG,Alias for channel 9 WRITE_ADDR register"
hexmask.long 0x26C 0.--31. 1. "CH9_AL2_WRITE_ADDR_TRIG"
line.long 0x270 "CH9_AL3_CTRL,Alias for channel 9 CTRL register"
hexmask.long 0x270 0.--31. 1. "CH9_AL3_CTRL"
line.long 0x274 "CH9_AL3_WRITE_ADDR,Alias for channel 9 WRITE_ADDR register"
hexmask.long 0x274 0.--31. 1. "CH9_AL3_WRITE_ADDR"
line.long 0x278 "CH9_AL3_TRANS_COUNT,Alias for channel 9 TRANS_COUNT register"
hexmask.long 0x278 0.--31. 1. "CH9_AL3_TRANS_COUNT"
line.long 0x27C "CH9_AL3_READ_ADDR_TRIG,Alias for channel 9 READ_ADDR register"
hexmask.long 0x27C 0.--31. 1. "CH9_AL3_READ_ADDR_TRIG"
line.long 0x280 "CH10_READ_ADDR,DMA Channel 10 Read Address pointer"
hexmask.long 0x280 0.--31. 1. "CH10_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x284 "CH10_WRITE_ADDR,DMA Channel 10 Write Address pointer"
hexmask.long 0x284 0.--31. 1. "CH10_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x288 "CH10_TRANS_COUNT,DMA Channel 10 Transfer Count"
hexmask.long.byte 0x288 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x288 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x28C "CH10_CTRL_TRIG,DMA Channel 10 Control and Status"
rbitfld.long 0x28C 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x28C 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x28C 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
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rbitfld.long 0x28C 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x28C 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x28C 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
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bitfld.long 0x28C 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x28C 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x28C 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
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bitfld.long 0x28C 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x28C 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x28C 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
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bitfld.long 0x28C 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x28C 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x28C 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
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bitfld.long 0x28C 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x28C 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x28C 0. "EN,DMA Channel Enable." "0,1"
line.long 0x290 "CH10_AL1_CTRL,Alias for channel 10 CTRL register"
hexmask.long 0x290 0.--31. 1. "CH10_AL1_CTRL"
line.long 0x294 "CH10_AL1_READ_ADDR,Alias for channel 10 READ_ADDR register"
hexmask.long 0x294 0.--31. 1. "CH10_AL1_READ_ADDR"
line.long 0x298 "CH10_AL1_WRITE_ADDR,Alias for channel 10 WRITE_ADDR register"
hexmask.long 0x298 0.--31. 1. "CH10_AL1_WRITE_ADDR"
line.long 0x29C "CH10_AL1_TRANS_COUNT_TRIG,Alias for channel 10 TRANS_COUNT register"
hexmask.long 0x29C 0.--31. 1. "CH10_AL1_TRANS_COUNT_TRIG"
line.long 0x2A0 "CH10_AL2_CTRL,Alias for channel 10 CTRL register"
hexmask.long 0x2A0 0.--31. 1. "CH10_AL2_CTRL"
line.long 0x2A4 "CH10_AL2_TRANS_COUNT,Alias for channel 10 TRANS_COUNT register"
hexmask.long 0x2A4 0.--31. 1. "CH10_AL2_TRANS_COUNT"
line.long 0x2A8 "CH10_AL2_READ_ADDR,Alias for channel 10 READ_ADDR register"
hexmask.long 0x2A8 0.--31. 1. "CH10_AL2_READ_ADDR"
line.long 0x2AC "CH10_AL2_WRITE_ADDR_TRIG,Alias for channel 10 WRITE_ADDR register"
hexmask.long 0x2AC 0.--31. 1. "CH10_AL2_WRITE_ADDR_TRIG"
line.long 0x2B0 "CH10_AL3_CTRL,Alias for channel 10 CTRL register"
hexmask.long 0x2B0 0.--31. 1. "CH10_AL3_CTRL"
line.long 0x2B4 "CH10_AL3_WRITE_ADDR,Alias for channel 10 WRITE_ADDR register"
hexmask.long 0x2B4 0.--31. 1. "CH10_AL3_WRITE_ADDR"
line.long 0x2B8 "CH10_AL3_TRANS_COUNT,Alias for channel 10 TRANS_COUNT register"
hexmask.long 0x2B8 0.--31. 1. "CH10_AL3_TRANS_COUNT"
line.long 0x2BC "CH10_AL3_READ_ADDR_TRIG,Alias for channel 10 READ_ADDR register"
hexmask.long 0x2BC 0.--31. 1. "CH10_AL3_READ_ADDR_TRIG"
line.long 0x2C0 "CH11_READ_ADDR,DMA Channel 11 Read Address pointer"
hexmask.long 0x2C0 0.--31. 1. "CH11_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x2C4 "CH11_WRITE_ADDR,DMA Channel 11 Write Address pointer"
hexmask.long 0x2C4 0.--31. 1. "CH11_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x2C8 "CH11_TRANS_COUNT,DMA Channel 11 Transfer Count"
hexmask.long.byte 0x2C8 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x2C8 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x2CC "CH11_CTRL_TRIG,DMA Channel 11 Control and Status"
rbitfld.long 0x2CC 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x2CC 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x2CC 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
newline
rbitfld.long 0x2CC 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x2CC 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x2CC 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0x2CC 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x2CC 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x2CC 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
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bitfld.long 0x2CC 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x2CC 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x2CC 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
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bitfld.long 0x2CC 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x2CC 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x2CC 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
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bitfld.long 0x2CC 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x2CC 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x2CC 0. "EN,DMA Channel Enable." "0,1"
line.long 0x2D0 "CH11_AL1_CTRL,Alias for channel 11 CTRL register"
hexmask.long 0x2D0 0.--31. 1. "CH11_AL1_CTRL"
line.long 0x2D4 "CH11_AL1_READ_ADDR,Alias for channel 11 READ_ADDR register"
hexmask.long 0x2D4 0.--31. 1. "CH11_AL1_READ_ADDR"
line.long 0x2D8 "CH11_AL1_WRITE_ADDR,Alias for channel 11 WRITE_ADDR register"
hexmask.long 0x2D8 0.--31. 1. "CH11_AL1_WRITE_ADDR"
line.long 0x2DC "CH11_AL1_TRANS_COUNT_TRIG,Alias for channel 11 TRANS_COUNT register"
hexmask.long 0x2DC 0.--31. 1. "CH11_AL1_TRANS_COUNT_TRIG"
line.long 0x2E0 "CH11_AL2_CTRL,Alias for channel 11 CTRL register"
hexmask.long 0x2E0 0.--31. 1. "CH11_AL2_CTRL"
line.long 0x2E4 "CH11_AL2_TRANS_COUNT,Alias for channel 11 TRANS_COUNT register"
hexmask.long 0x2E4 0.--31. 1. "CH11_AL2_TRANS_COUNT"
line.long 0x2E8 "CH11_AL2_READ_ADDR,Alias for channel 11 READ_ADDR register"
hexmask.long 0x2E8 0.--31. 1. "CH11_AL2_READ_ADDR"
line.long 0x2EC "CH11_AL2_WRITE_ADDR_TRIG,Alias for channel 11 WRITE_ADDR register"
hexmask.long 0x2EC 0.--31. 1. "CH11_AL2_WRITE_ADDR_TRIG"
line.long 0x2F0 "CH11_AL3_CTRL,Alias for channel 11 CTRL register"
hexmask.long 0x2F0 0.--31. 1. "CH11_AL3_CTRL"
line.long 0x2F4 "CH11_AL3_WRITE_ADDR,Alias for channel 11 WRITE_ADDR register"
hexmask.long 0x2F4 0.--31. 1. "CH11_AL3_WRITE_ADDR"
line.long 0x2F8 "CH11_AL3_TRANS_COUNT,Alias for channel 11 TRANS_COUNT register"
hexmask.long 0x2F8 0.--31. 1. "CH11_AL3_TRANS_COUNT"
line.long 0x2FC "CH11_AL3_READ_ADDR_TRIG,Alias for channel 11 READ_ADDR register"
hexmask.long 0x2FC 0.--31. 1. "CH11_AL3_READ_ADDR_TRIG"
line.long 0x300 "CH12_READ_ADDR,DMA Channel 12 Read Address pointer"
hexmask.long 0x300 0.--31. 1. "CH12_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x304 "CH12_WRITE_ADDR,DMA Channel 12 Write Address pointer"
hexmask.long 0x304 0.--31. 1. "CH12_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x308 "CH12_TRANS_COUNT,DMA Channel 12 Transfer Count"
hexmask.long.byte 0x308 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x308 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x30C "CH12_CTRL_TRIG,DMA Channel 12 Control and Status"
rbitfld.long 0x30C 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x30C 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x30C 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
newline
rbitfld.long 0x30C 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x30C 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x30C 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0x30C 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x30C 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x30C 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
newline
bitfld.long 0x30C 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x30C 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x30C 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
newline
bitfld.long 0x30C 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x30C 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x30C 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
newline
bitfld.long 0x30C 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x30C 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x30C 0. "EN,DMA Channel Enable." "0,1"
line.long 0x310 "CH12_AL1_CTRL,Alias for channel 12 CTRL register"
hexmask.long 0x310 0.--31. 1. "CH12_AL1_CTRL"
line.long 0x314 "CH12_AL1_READ_ADDR,Alias for channel 12 READ_ADDR register"
hexmask.long 0x314 0.--31. 1. "CH12_AL1_READ_ADDR"
line.long 0x318 "CH12_AL1_WRITE_ADDR,Alias for channel 12 WRITE_ADDR register"
hexmask.long 0x318 0.--31. 1. "CH12_AL1_WRITE_ADDR"
line.long 0x31C "CH12_AL1_TRANS_COUNT_TRIG,Alias for channel 12 TRANS_COUNT register"
hexmask.long 0x31C 0.--31. 1. "CH12_AL1_TRANS_COUNT_TRIG"
line.long 0x320 "CH12_AL2_CTRL,Alias for channel 12 CTRL register"
hexmask.long 0x320 0.--31. 1. "CH12_AL2_CTRL"
line.long 0x324 "CH12_AL2_TRANS_COUNT,Alias for channel 12 TRANS_COUNT register"
hexmask.long 0x324 0.--31. 1. "CH12_AL2_TRANS_COUNT"
line.long 0x328 "CH12_AL2_READ_ADDR,Alias for channel 12 READ_ADDR register"
hexmask.long 0x328 0.--31. 1. "CH12_AL2_READ_ADDR"
line.long 0x32C "CH12_AL2_WRITE_ADDR_TRIG,Alias for channel 12 WRITE_ADDR register"
hexmask.long 0x32C 0.--31. 1. "CH12_AL2_WRITE_ADDR_TRIG"
line.long 0x330 "CH12_AL3_CTRL,Alias for channel 12 CTRL register"
hexmask.long 0x330 0.--31. 1. "CH12_AL3_CTRL"
line.long 0x334 "CH12_AL3_WRITE_ADDR,Alias for channel 12 WRITE_ADDR register"
hexmask.long 0x334 0.--31. 1. "CH12_AL3_WRITE_ADDR"
line.long 0x338 "CH12_AL3_TRANS_COUNT,Alias for channel 12 TRANS_COUNT register"
hexmask.long 0x338 0.--31. 1. "CH12_AL3_TRANS_COUNT"
line.long 0x33C "CH12_AL3_READ_ADDR_TRIG,Alias for channel 12 READ_ADDR register"
hexmask.long 0x33C 0.--31. 1. "CH12_AL3_READ_ADDR_TRIG"
line.long 0x340 "CH13_READ_ADDR,DMA Channel 13 Read Address pointer"
hexmask.long 0x340 0.--31. 1. "CH13_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x344 "CH13_WRITE_ADDR,DMA Channel 13 Write Address pointer"
hexmask.long 0x344 0.--31. 1. "CH13_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x348 "CH13_TRANS_COUNT,DMA Channel 13 Transfer Count"
hexmask.long.byte 0x348 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x348 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x34C "CH13_CTRL_TRIG,DMA Channel 13 Control and Status"
rbitfld.long 0x34C 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x34C 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x34C 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
newline
rbitfld.long 0x34C 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x34C 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x34C 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0x34C 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x34C 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x34C 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
newline
bitfld.long 0x34C 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x34C 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x34C 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
newline
bitfld.long 0x34C 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x34C 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x34C 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
newline
bitfld.long 0x34C 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x34C 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x34C 0. "EN,DMA Channel Enable." "0,1"
line.long 0x350 "CH13_AL1_CTRL,Alias for channel 13 CTRL register"
hexmask.long 0x350 0.--31. 1. "CH13_AL1_CTRL"
line.long 0x354 "CH13_AL1_READ_ADDR,Alias for channel 13 READ_ADDR register"
hexmask.long 0x354 0.--31. 1. "CH13_AL1_READ_ADDR"
line.long 0x358 "CH13_AL1_WRITE_ADDR,Alias for channel 13 WRITE_ADDR register"
hexmask.long 0x358 0.--31. 1. "CH13_AL1_WRITE_ADDR"
line.long 0x35C "CH13_AL1_TRANS_COUNT_TRIG,Alias for channel 13 TRANS_COUNT register"
hexmask.long 0x35C 0.--31. 1. "CH13_AL1_TRANS_COUNT_TRIG"
line.long 0x360 "CH13_AL2_CTRL,Alias for channel 13 CTRL register"
hexmask.long 0x360 0.--31. 1. "CH13_AL2_CTRL"
line.long 0x364 "CH13_AL2_TRANS_COUNT,Alias for channel 13 TRANS_COUNT register"
hexmask.long 0x364 0.--31. 1. "CH13_AL2_TRANS_COUNT"
line.long 0x368 "CH13_AL2_READ_ADDR,Alias for channel 13 READ_ADDR register"
hexmask.long 0x368 0.--31. 1. "CH13_AL2_READ_ADDR"
line.long 0x36C "CH13_AL2_WRITE_ADDR_TRIG,Alias for channel 13 WRITE_ADDR register"
hexmask.long 0x36C 0.--31. 1. "CH13_AL2_WRITE_ADDR_TRIG"
line.long 0x370 "CH13_AL3_CTRL,Alias for channel 13 CTRL register"
hexmask.long 0x370 0.--31. 1. "CH13_AL3_CTRL"
line.long 0x374 "CH13_AL3_WRITE_ADDR,Alias for channel 13 WRITE_ADDR register"
hexmask.long 0x374 0.--31. 1. "CH13_AL3_WRITE_ADDR"
line.long 0x378 "CH13_AL3_TRANS_COUNT,Alias for channel 13 TRANS_COUNT register"
hexmask.long 0x378 0.--31. 1. "CH13_AL3_TRANS_COUNT"
line.long 0x37C "CH13_AL3_READ_ADDR_TRIG,Alias for channel 13 READ_ADDR register"
hexmask.long 0x37C 0.--31. 1. "CH13_AL3_READ_ADDR_TRIG"
line.long 0x380 "CH14_READ_ADDR,DMA Channel 14 Read Address pointer"
hexmask.long 0x380 0.--31. 1. "CH14_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x384 "CH14_WRITE_ADDR,DMA Channel 14 Write Address pointer"
hexmask.long 0x384 0.--31. 1. "CH14_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x388 "CH14_TRANS_COUNT,DMA Channel 14 Transfer Count"
hexmask.long.byte 0x388 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x388 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x38C "CH14_CTRL_TRIG,DMA Channel 14 Control and Status"
rbitfld.long 0x38C 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x38C 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x38C 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
newline
rbitfld.long 0x38C 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x38C 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x38C 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0x38C 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x38C 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x38C 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
newline
bitfld.long 0x38C 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x38C 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x38C 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
newline
bitfld.long 0x38C 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x38C 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x38C 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
newline
bitfld.long 0x38C 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x38C 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x38C 0. "EN,DMA Channel Enable." "0,1"
line.long 0x390 "CH14_AL1_CTRL,Alias for channel 14 CTRL register"
hexmask.long 0x390 0.--31. 1. "CH14_AL1_CTRL"
line.long 0x394 "CH14_AL1_READ_ADDR,Alias for channel 14 READ_ADDR register"
hexmask.long 0x394 0.--31. 1. "CH14_AL1_READ_ADDR"
line.long 0x398 "CH14_AL1_WRITE_ADDR,Alias for channel 14 WRITE_ADDR register"
hexmask.long 0x398 0.--31. 1. "CH14_AL1_WRITE_ADDR"
line.long 0x39C "CH14_AL1_TRANS_COUNT_TRIG,Alias for channel 14 TRANS_COUNT register"
hexmask.long 0x39C 0.--31. 1. "CH14_AL1_TRANS_COUNT_TRIG"
line.long 0x3A0 "CH14_AL2_CTRL,Alias for channel 14 CTRL register"
hexmask.long 0x3A0 0.--31. 1. "CH14_AL2_CTRL"
line.long 0x3A4 "CH14_AL2_TRANS_COUNT,Alias for channel 14 TRANS_COUNT register"
hexmask.long 0x3A4 0.--31. 1. "CH14_AL2_TRANS_COUNT"
line.long 0x3A8 "CH14_AL2_READ_ADDR,Alias for channel 14 READ_ADDR register"
hexmask.long 0x3A8 0.--31. 1. "CH14_AL2_READ_ADDR"
line.long 0x3AC "CH14_AL2_WRITE_ADDR_TRIG,Alias for channel 14 WRITE_ADDR register"
hexmask.long 0x3AC 0.--31. 1. "CH14_AL2_WRITE_ADDR_TRIG"
line.long 0x3B0 "CH14_AL3_CTRL,Alias for channel 14 CTRL register"
hexmask.long 0x3B0 0.--31. 1. "CH14_AL3_CTRL"
line.long 0x3B4 "CH14_AL3_WRITE_ADDR,Alias for channel 14 WRITE_ADDR register"
hexmask.long 0x3B4 0.--31. 1. "CH14_AL3_WRITE_ADDR"
line.long 0x3B8 "CH14_AL3_TRANS_COUNT,Alias for channel 14 TRANS_COUNT register"
hexmask.long 0x3B8 0.--31. 1. "CH14_AL3_TRANS_COUNT"
line.long 0x3BC "CH14_AL3_READ_ADDR_TRIG,Alias for channel 14 READ_ADDR register"
hexmask.long 0x3BC 0.--31. 1. "CH14_AL3_READ_ADDR_TRIG"
line.long 0x3C0 "CH15_READ_ADDR,DMA Channel 15 Read Address pointer"
hexmask.long 0x3C0 0.--31. 1. "CH15_READ_ADDR,This register updates automatically each time a read completes. The current value is the next address to be read by this channel."
line.long 0x3C4 "CH15_WRITE_ADDR,DMA Channel 15 Write Address pointer"
hexmask.long 0x3C4 0.--31. 1. "CH15_WRITE_ADDR,This register updates automatically each time a write completes. The current value is the next address to be written by this channel."
line.long 0x3C8 "CH15_TRANS_COUNT,DMA Channel 15 Transfer Count"
hexmask.long.byte 0x3C8 28.--31. 1. "MODE,When MODE is 0x0 the transfer count decrements with each transfer until 0 and then the channel triggers the next channel indicated by CTRL_CHAIN_TO."
hexmask.long 0x3C8 0.--27. 1. "COUNT,28-bit transfer count (256 million transfers maximum)."
line.long 0x3CC "CH15_CTRL_TRIG,DMA Channel 15 Control and Status"
rbitfld.long 0x3CC 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error and always raises its channel IRQ flag." "0,1"
eventfld.long 0x3CC 30. "READ_ERROR,If 1 the channel received a read bus error. Write one to clear." "0,1"
eventfld.long 0x3CC 29. "WRITE_ERROR,If 1 the channel received a write bus error. Write one to clear." "0,1"
newline
rbitfld.long 0x3CC 26. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel and BUSY will stay high while paused." "0,1"
bitfld.long 0x3CC 25. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled and has this channel selected." "0,1"
bitfld.long 0x3CC 24. "BSWAP,Apply byte-swap transformation to DMA data." "0,1"
newline
bitfld.long 0x3CC 23. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block. Instead an IRQ is raised when NULL is written to a trigger register indicating the end of a control block chain." "0,1"
hexmask.long.byte 0x3CC 17.--22. 1. "TREQ_SEL,Select a Transfer Request signal."
hexmask.long.byte 0x3CC 13.--16. 1. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_."
newline
bitfld.long 0x3CC 12. "RING_SEL,Select whether RING_SIZE applies to read or write addresses." "0,1"
hexmask.long.byte 0x3CC 8.--11. 1. "RING_SIZE,Size of address wrap region. If 0 don't wrap. For values n > 0 only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary facilitating access to naturally-aligned ring buffers."
bitfld.long 0x3CC 7. "INCR_WRITE_REV,If 1 and INCR_WRITE is 1 the write address is decremented rather than incremented with each transfer." "0,1"
newline
bitfld.long 0x3CC 6. "INCR_WRITE,If 1 the write address increments with each transfer. If 0 each write is directed to the same initial address." "0,1"
bitfld.long 0x3CC 5. "INCR_READ_REV,If 1 and INCR_READ is 1 the read address is decremented rather than incremented with each transfer." "0,1"
bitfld.long 0x3CC 4. "INCR_READ,If 1 the read address increments with each transfer. If 0 each read is directed to the same initial address." "0,1"
newline
bitfld.long 0x3CC 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer." "0,1,2,3"
bitfld.long 0x3CC 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority channels." "0,1"
bitfld.long 0x3CC 0. "EN,DMA Channel Enable." "0,1"
line.long 0x3D0 "CH15_AL1_CTRL,Alias for channel 15 CTRL register"
hexmask.long 0x3D0 0.--31. 1. "CH15_AL1_CTRL"
line.long 0x3D4 "CH15_AL1_READ_ADDR,Alias for channel 15 READ_ADDR register"
hexmask.long 0x3D4 0.--31. 1. "CH15_AL1_READ_ADDR"
line.long 0x3D8 "CH15_AL1_WRITE_ADDR,Alias for channel 15 WRITE_ADDR register"
hexmask.long 0x3D8 0.--31. 1. "CH15_AL1_WRITE_ADDR"
line.long 0x3DC "CH15_AL1_TRANS_COUNT_TRIG,Alias for channel 15 TRANS_COUNT register"
hexmask.long 0x3DC 0.--31. 1. "CH15_AL1_TRANS_COUNT_TRIG"
line.long 0x3E0 "CH15_AL2_CTRL,Alias for channel 15 CTRL register"
hexmask.long 0x3E0 0.--31. 1. "CH15_AL2_CTRL"
line.long 0x3E4 "CH15_AL2_TRANS_COUNT,Alias for channel 15 TRANS_COUNT register"
hexmask.long 0x3E4 0.--31. 1. "CH15_AL2_TRANS_COUNT"
line.long 0x3E8 "CH15_AL2_READ_ADDR,Alias for channel 15 READ_ADDR register"
hexmask.long 0x3E8 0.--31. 1. "CH15_AL2_READ_ADDR"
line.long 0x3EC "CH15_AL2_WRITE_ADDR_TRIG,Alias for channel 15 WRITE_ADDR register"
hexmask.long 0x3EC 0.--31. 1. "CH15_AL2_WRITE_ADDR_TRIG"
line.long 0x3F0 "CH15_AL3_CTRL,Alias for channel 15 CTRL register"
hexmask.long 0x3F0 0.--31. 1. "CH15_AL3_CTRL"
line.long 0x3F4 "CH15_AL3_WRITE_ADDR,Alias for channel 15 WRITE_ADDR register"
hexmask.long 0x3F4 0.--31. 1. "CH15_AL3_WRITE_ADDR"
line.long 0x3F8 "CH15_AL3_TRANS_COUNT,Alias for channel 15 TRANS_COUNT register"
hexmask.long 0x3F8 0.--31. 1. "CH15_AL3_TRANS_COUNT"
line.long 0x3FC "CH15_AL3_READ_ADDR_TRIG,Alias for channel 15 READ_ADDR register"
hexmask.long 0x3FC 0.--31. 1. "CH15_AL3_READ_ADDR_TRIG"
line.long 0x400 "INTR,Interrupt Status (raw)"
hexmask.long.word 0x400 0.--15. 1. "INTR,Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3."
line.long 0x404 "INTE0,Interrupt Enables for IRQ 0"
hexmask.long.word 0x404 0.--15. 1. "INTE0,Set bit n to pass interrupts from channel n to DMA IRQ 0."
line.long 0x408 "INTF0,Force Interrupts"
hexmask.long.word 0x408 0.--15. 1. "INTF0,Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared."
line.long 0x40C "INTS0,Interrupt Status for IRQ 0"
hexmask.long.word 0x40C 0.--15. 1. "INTS0,Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted."
line.long 0x410 "INTR1,Interrupt Status (raw)"
hexmask.long.word 0x410 0.--15. 1. "INTR1,Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3."
line.long 0x414 "INTE1,Interrupt Enables for IRQ 1"
hexmask.long.word 0x414 0.--15. 1. "INTE1,Set bit n to pass interrupts from channel n to DMA IRQ 1."
line.long 0x418 "INTF1,Force Interrupts"
hexmask.long.word 0x418 0.--15. 1. "INTF1,Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared."
line.long 0x41C "INTS1,Interrupt Status for IRQ 1"
hexmask.long.word 0x41C 0.--15. 1. "INTS1,Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted."
line.long 0x420 "INTR2,Interrupt Status (raw)"
hexmask.long.word 0x420 0.--15. 1. "INTR2,Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3."
line.long 0x424 "INTE2,Interrupt Enables for IRQ 2"
hexmask.long.word 0x424 0.--15. 1. "INTE2,Set bit n to pass interrupts from channel n to DMA IRQ 2."
line.long 0x428 "INTF2,Force Interrupts"
hexmask.long.word 0x428 0.--15. 1. "INTF2,Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared."
line.long 0x42C "INTS2,Interrupt Status for IRQ 2"
hexmask.long.word 0x42C 0.--15. 1. "INTS2,Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted."
line.long 0x430 "INTR3,Interrupt Status (raw)"
hexmask.long.word 0x430 0.--15. 1. "INTR3,Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3."
line.long 0x434 "INTE3,Interrupt Enables for IRQ 3"
hexmask.long.word 0x434 0.--15. 1. "INTE3,Set bit n to pass interrupts from channel n to DMA IRQ 3."
line.long 0x438 "INTF3,Force Interrupts"
hexmask.long.word 0x438 0.--15. 1. "INTF3,Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared."
line.long 0x43C "INTS3,Interrupt Status for IRQ 3"
hexmask.long.word 0x43C 0.--15. 1. "INTS3,Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted."
line.long 0x440 "TIMER0,Pacing (X/Y) fractional timer"
hexmask.long.word 0x440 16.--31. 1. "X,Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."
hexmask.long.word 0x440 0.--15. 1. "Y,Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."
line.long 0x444 "TIMER1,Pacing (X/Y) fractional timer"
hexmask.long.word 0x444 16.--31. 1. "X,Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."
hexmask.long.word 0x444 0.--15. 1. "Y,Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."
line.long 0x448 "TIMER2,Pacing (X/Y) fractional timer"
hexmask.long.word 0x448 16.--31. 1. "X,Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."
hexmask.long.word 0x448 0.--15. 1. "Y,Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."
line.long 0x44C "TIMER3,Pacing (X/Y) fractional timer"
hexmask.long.word 0x44C 16.--31. 1. "X,Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."
hexmask.long.word 0x44C 0.--15. 1. "Y,Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."
wgroup.long 0x450++0x3
line.long 0x0 "MULTI_CHAN_TRIGGER,Trigger one or more channels simultaneously"
hexmask.long.word 0x0 0.--15. 1. "MULTI_CHAN_TRIGGER,Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."
group.long 0x454++0x7
line.long 0x0 "SNIFF_CTRL,Sniffer Control"
bitfld.long 0x0 11. "OUT_INV,If set the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus." "0,1"
bitfld.long 0x0 10. "OUT_REV,If set the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus." "0,1"
bitfld.long 0x0 9. "BSWAP,Locally perform a byte reverse on the sniffed data before feeding into checksum." "0,1"
newline
hexmask.long.byte 0x0 5.--8. 1. "CALC"
hexmask.long.byte 0x0 1.--4. 1. "DMACH,DMA channel for Sniffer to observe"
bitfld.long 0x0 0. "EN,Enable sniffer" "0,1"
line.long 0x4 "SNIFF_DATA,Data accumulator for sniff hardware"
hexmask.long 0x4 0.--31. 1. "SNIFF_DATA,Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes the final.."
rgroup.long 0x460++0x3
line.long 0x0 "FIFO_LEVELS,Debug RAF. WAF. TDF levels"
hexmask.long.byte 0x0 16.--23. 1. "RAF_LVL,Current Read-Address-FIFO fill level"
hexmask.long.byte 0x0 8.--15. 1. "WAF_LVL,Current Write-Address-FIFO fill level"
hexmask.long.byte 0x0 0.--7. 1. "TDF_LVL,Current Transfer-Data-FIFO fill level"
wgroup.long 0x464++0x3
line.long 0x0 "CHAN_ABORT,Abort an in-progress transfer sequence on one or more channels"
hexmask.long.word 0x0 0.--15. 1. "CHAN_ABORT,Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs."
rgroup.long 0x468++0x3
line.long 0x0 "N_CHANNELS,The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels. but can be configured with as few as one. to minimise silicon area."
hexmask.long.byte 0x0 0.--4. 1. "N_CHANNELS"
group.long 0x480++0x53
line.long 0x0 "SECCFG_CH0,Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x0 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x0 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x0 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x4 "SECCFG_CH1,Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x4 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x4 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x4 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x8 "SECCFG_CH2,Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x8 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x8 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x8 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0xC "SECCFG_CH3,Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0xC 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0xC 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0xC 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x10 "SECCFG_CH4,Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x10 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x10 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x10 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x14 "SECCFG_CH5,Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x14 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x14 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x14 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x18 "SECCFG_CH6,Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x18 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x18 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x18 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x1C "SECCFG_CH7,Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x1C 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x1C 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x1C 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x20 "SECCFG_CH8,Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x20 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x20 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x20 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x24 "SECCFG_CH9,Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x24 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x24 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x24 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x28 "SECCFG_CH10,Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x28 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x28 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x28 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x2C "SECCFG_CH11,Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x2C 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x2C 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x2C 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x30 "SECCFG_CH12,Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x30 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x30 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x30 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x34 "SECCFG_CH13,Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x34 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x34 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x34 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x38 "SECCFG_CH14,Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x38 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x38 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x38 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x3C "SECCFG_CH15,Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses."
bitfld.long 0x3C 2. "LOCK,LOCK is 0 at reset and is set to 1 automatically upon a successful write to this channel's control registers. That is a write to CTRL READ_ADDR WRITE_ADDR TRANS_COUNT and their aliases." "0,1"
bitfld.long 0x3C 1. "S,Secure channel. If 1 this channel performs Secure bus accesses. If 0 it performs Non-secure bus accesses." "0,1"
bitfld.long 0x3C 0. "P,Privileged channel. If 1 this channel performs Privileged bus accesses. If 0 it performs Unprivileged bus accesses." "0,1"
line.long 0x40 "SECCFG_IRQ0,Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts. and whether it can observe Secure/Privileged channel interrupt flags."
bitfld.long 0x40 1. "S,Secure IRQ. If 1 this IRQ's control registers can only be accessed from a Secure context." "0,1"
bitfld.long 0x40 0. "P,Privileged IRQ. If 1 this IRQ's control registers can only be accessed from a Privileged context." "0,1"
line.long 0x44 "SECCFG_IRQ1,Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts. and whether it can observe Secure/Privileged channel interrupt flags."
bitfld.long 0x44 1. "S,Secure IRQ. If 1 this IRQ's control registers can only be accessed from a Secure context." "0,1"
bitfld.long 0x44 0. "P,Privileged IRQ. If 1 this IRQ's control registers can only be accessed from a Privileged context." "0,1"
line.long 0x48 "SECCFG_IRQ2,Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts. and whether it can observe Secure/Privileged channel interrupt flags."
bitfld.long 0x48 1. "S,Secure IRQ. If 1 this IRQ's control registers can only be accessed from a Secure context." "0,1"
bitfld.long 0x48 0. "P,Privileged IRQ. If 1 this IRQ's control registers can only be accessed from a Privileged context." "0,1"
line.long 0x4C "SECCFG_IRQ3,Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts. and whether it can observe Secure/Privileged channel interrupt flags."
bitfld.long 0x4C 1. "S,Secure IRQ. If 1 this IRQ's control registers can only be accessed from a Secure context." "0,1"
bitfld.long 0x4C 0. "P,Privileged IRQ. If 1 this IRQ's control registers can only be accessed from a Privileged context." "0,1"
line.long 0x50 "SECCFG_MISC,Miscellaneous security configuration"
bitfld.long 0x50 9. "TIMER3_S,If 1 the TIMER3 register is only accessible from a Secure context and timer DREQ 3 is only visible to Secure channels." "0,1"
bitfld.long 0x50 8. "TIMER3_P,If 1 the TIMER3 register is only accessible from a Privileged (or more Secure) context and timer DREQ 3 is only visible to Privileged (or more Secure) channels." "0,1"
bitfld.long 0x50 7. "TIMER2_S,If 1 the TIMER2 register is only accessible from a Secure context and timer DREQ 2 is only visible to Secure channels." "0,1"
newline
bitfld.long 0x50 6. "TIMER2_P,If 1 the TIMER2 register is only accessible from a Privileged (or more Secure) context and timer DREQ 2 is only visible to Privileged (or more Secure) channels." "0,1"
bitfld.long 0x50 5. "TIMER1_S,If 1 the TIMER1 register is only accessible from a Secure context and timer DREQ 1 is only visible to Secure channels." "0,1"
bitfld.long 0x50 4. "TIMER1_P,If 1 the TIMER1 register is only accessible from a Privileged (or more Secure) context and timer DREQ 1 is only visible to Privileged (or more Secure) channels." "0,1"
newline
bitfld.long 0x50 3. "TIMER0_S,If 1 the TIMER0 register is only accessible from a Secure context and timer DREQ 0 is only visible to Secure channels." "0,1"
bitfld.long 0x50 2. "TIMER0_P,If 1 the TIMER0 register is only accessible from a Privileged (or more Secure) context and timer DREQ 0 is only visible to Privileged (or more Secure) channels." "0,1"
bitfld.long 0x50 1. "SNIFF_S,If 1 the sniffer can see data transfers from Secure channels and can itself only be accessed from a Secure context." "0,1"
newline
bitfld.long 0x50 0. "SNIFF_P,If 1 the sniffer can see data transfers from Privileged channels and can itself only be accessed from a privileged context or from a Secure context when SNIFF_S is 0." "0,1"
group.long 0x500++0x43
line.long 0x0 "MPU_CTRL,Control register for DMA MPU. Accessible only from a Privileged context."
bitfld.long 0x0 3. "NS_HIDE_ADDR,By default when a region's S bit is clear Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads even when the region is Non-secure to avoid.." "0,1"
bitfld.long 0x0 2. "S,Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)" "0,1"
bitfld.long 0x0 1. "P,Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)" "0,1"
line.long 0x4 "MPU_BAR0,Base address register for MPU region 0. Writable only from a Secure. Privileged context."
hexmask.long 0x4 5.--31. 1. "ADDR,This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR and less than or equal to LAR_ADDR."
line.long 0x8 "MPU_LAR0,Limit address register for MPU region 0. Writable only from a Secure. Privileged context. with the exception of the P bit."
hexmask.long 0x8 5.--31. 1. "ADDR,Limit address bits 31:5. Readable from any Privileged context if and only if this region's S bit is clear and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure Privileged context."
bitfld.long 0x8 2. "S,Determines the Secure/Non-secure (=1/0) status of addresses matching this region if this region is enabled." "0,1"
bitfld.long 0x8 1. "P,Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region if this region is enabled. Writable from any Privileged context if and only if the S bit is clear. Otherwise writable only from a Secure Privileged context." "0,1"
newline
bitfld.long 0x8 0. "EN,Region enable. If 1 any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P." "0,1"
line.long 0xC "MPU_BAR1,Base address register for MPU region 1. Writable only from a Secure. Privileged context."
hexmask.long 0xC 5.--31. 1. "ADDR,This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR and less than or equal to LAR_ADDR."
line.long 0x10 "MPU_LAR1,Limit address register for MPU region 1. Writable only from a Secure. Privileged context. with the exception of the P bit."
hexmask.long 0x10 5.--31. 1. "ADDR,Limit address bits 31:5. Readable from any Privileged context if and only if this region's S bit is clear and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure Privileged context."
bitfld.long 0x10 2. "S,Determines the Secure/Non-secure (=1/0) status of addresses matching this region if this region is enabled." "0,1"
bitfld.long 0x10 1. "P,Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region if this region is enabled. Writable from any Privileged context if and only if the S bit is clear. Otherwise writable only from a Secure Privileged context." "0,1"
newline
bitfld.long 0x10 0. "EN,Region enable. If 1 any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P." "0,1"
line.long 0x14 "MPU_BAR2,Base address register for MPU region 2. Writable only from a Secure. Privileged context."
hexmask.long 0x14 5.--31. 1. "ADDR,This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR and less than or equal to LAR_ADDR."
line.long 0x18 "MPU_LAR2,Limit address register for MPU region 2. Writable only from a Secure. Privileged context. with the exception of the P bit."
hexmask.long 0x18 5.--31. 1. "ADDR,Limit address bits 31:5. Readable from any Privileged context if and only if this region's S bit is clear and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure Privileged context."
bitfld.long 0x18 2. "S,Determines the Secure/Non-secure (=1/0) status of addresses matching this region if this region is enabled." "0,1"
bitfld.long 0x18 1. "P,Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region if this region is enabled. Writable from any Privileged context if and only if the S bit is clear. Otherwise writable only from a Secure Privileged context." "0,1"
newline
bitfld.long 0x18 0. "EN,Region enable. If 1 any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P." "0,1"
line.long 0x1C "MPU_BAR3,Base address register for MPU region 3. Writable only from a Secure. Privileged context."
hexmask.long 0x1C 5.--31. 1. "ADDR,This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR and less than or equal to LAR_ADDR."
line.long 0x20 "MPU_LAR3,Limit address register for MPU region 3. Writable only from a Secure. Privileged context. with the exception of the P bit."
hexmask.long 0x20 5.--31. 1. "ADDR,Limit address bits 31:5. Readable from any Privileged context if and only if this region's S bit is clear and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure Privileged context."
bitfld.long 0x20 2. "S,Determines the Secure/Non-secure (=1/0) status of addresses matching this region if this region is enabled." "0,1"
bitfld.long 0x20 1. "P,Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region if this region is enabled. Writable from any Privileged context if and only if the S bit is clear. Otherwise writable only from a Secure Privileged context." "0,1"
newline
bitfld.long 0x20 0. "EN,Region enable. If 1 any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P." "0,1"
line.long 0x24 "MPU_BAR4,Base address register for MPU region 4. Writable only from a Secure. Privileged context."
hexmask.long 0x24 5.--31. 1. "ADDR,This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR and less than or equal to LAR_ADDR."
line.long 0x28 "MPU_LAR4,Limit address register for MPU region 4. Writable only from a Secure. Privileged context. with the exception of the P bit."
hexmask.long 0x28 5.--31. 1. "ADDR,Limit address bits 31:5. Readable from any Privileged context if and only if this region's S bit is clear and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure Privileged context."
bitfld.long 0x28 2. "S,Determines the Secure/Non-secure (=1/0) status of addresses matching this region if this region is enabled." "0,1"
bitfld.long 0x28 1. "P,Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region if this region is enabled. Writable from any Privileged context if and only if the S bit is clear. Otherwise writable only from a Secure Privileged context." "0,1"
newline
bitfld.long 0x28 0. "EN,Region enable. If 1 any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P." "0,1"
line.long 0x2C "MPU_BAR5,Base address register for MPU region 5. Writable only from a Secure. Privileged context."
hexmask.long 0x2C 5.--31. 1. "ADDR,This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR and less than or equal to LAR_ADDR."
line.long 0x30 "MPU_LAR5,Limit address register for MPU region 5. Writable only from a Secure. Privileged context. with the exception of the P bit."
hexmask.long 0x30 5.--31. 1. "ADDR,Limit address bits 31:5. Readable from any Privileged context if and only if this region's S bit is clear and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure Privileged context."
bitfld.long 0x30 2. "S,Determines the Secure/Non-secure (=1/0) status of addresses matching this region if this region is enabled." "0,1"
bitfld.long 0x30 1. "P,Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region if this region is enabled. Writable from any Privileged context if and only if the S bit is clear. Otherwise writable only from a Secure Privileged context." "0,1"
newline
bitfld.long 0x30 0. "EN,Region enable. If 1 any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P." "0,1"
line.long 0x34 "MPU_BAR6,Base address register for MPU region 6. Writable only from a Secure. Privileged context."
hexmask.long 0x34 5.--31. 1. "ADDR,This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR and less than or equal to LAR_ADDR."
line.long 0x38 "MPU_LAR6,Limit address register for MPU region 6. Writable only from a Secure. Privileged context. with the exception of the P bit."
hexmask.long 0x38 5.--31. 1. "ADDR,Limit address bits 31:5. Readable from any Privileged context if and only if this region's S bit is clear and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure Privileged context."
bitfld.long 0x38 2. "S,Determines the Secure/Non-secure (=1/0) status of addresses matching this region if this region is enabled." "0,1"
bitfld.long 0x38 1. "P,Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region if this region is enabled. Writable from any Privileged context if and only if the S bit is clear. Otherwise writable only from a Secure Privileged context." "0,1"
newline
bitfld.long 0x38 0. "EN,Region enable. If 1 any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P." "0,1"
line.long 0x3C "MPU_BAR7,Base address register for MPU region 7. Writable only from a Secure. Privileged context."
hexmask.long 0x3C 5.--31. 1. "ADDR,This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR and less than or equal to LAR_ADDR."
line.long 0x40 "MPU_LAR7,Limit address register for MPU region 7. Writable only from a Secure. Privileged context. with the exception of the P bit."
hexmask.long 0x40 5.--31. 1. "ADDR,Limit address bits 31:5. Readable from any Privileged context if and only if this region's S bit is clear and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure Privileged context."
bitfld.long 0x40 2. "S,Determines the Secure/Non-secure (=1/0) status of addresses matching this region if this region is enabled." "0,1"
bitfld.long 0x40 1. "P,Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region if this region is enabled. Writable from any Privileged context if and only if the S bit is clear. Otherwise writable only from a Secure Privileged context." "0,1"
newline
bitfld.long 0x40 0. "EN,Region enable. If 1 any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P." "0,1"
group.long 0x800++0x3
line.long 0x0 "CH0_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH0_DBG_CTDREQ"
rgroup.long 0x804++0x3
line.long 0x0 "CH0_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH0_DBG_TCR"
group.long 0x840++0x3
line.long 0x0 "CH1_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH1_DBG_CTDREQ"
rgroup.long 0x844++0x3
line.long 0x0 "CH1_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH1_DBG_TCR"
group.long 0x880++0x3
line.long 0x0 "CH2_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH2_DBG_CTDREQ"
rgroup.long 0x884++0x3
line.long 0x0 "CH2_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH2_DBG_TCR"
group.long 0x8C0++0x3
line.long 0x0 "CH3_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH3_DBG_CTDREQ"
rgroup.long 0x8C4++0x3
line.long 0x0 "CH3_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH3_DBG_TCR"
group.long 0x900++0x3
line.long 0x0 "CH4_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH4_DBG_CTDREQ"
rgroup.long 0x904++0x3
line.long 0x0 "CH4_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH4_DBG_TCR"
group.long 0x940++0x3
line.long 0x0 "CH5_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH5_DBG_CTDREQ"
rgroup.long 0x944++0x3
line.long 0x0 "CH5_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH5_DBG_TCR"
group.long 0x980++0x3
line.long 0x0 "CH6_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH6_DBG_CTDREQ"
rgroup.long 0x984++0x3
line.long 0x0 "CH6_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH6_DBG_TCR"
group.long 0x9C0++0x3
line.long 0x0 "CH7_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH7_DBG_CTDREQ"
rgroup.long 0x9C4++0x3
line.long 0x0 "CH7_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH7_DBG_TCR"
group.long 0xA00++0x3
line.long 0x0 "CH8_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH8_DBG_CTDREQ"
rgroup.long 0xA04++0x3
line.long 0x0 "CH8_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH8_DBG_TCR"
group.long 0xA40++0x3
line.long 0x0 "CH9_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH9_DBG_CTDREQ"
rgroup.long 0xA44++0x3
line.long 0x0 "CH9_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH9_DBG_TCR"
group.long 0xA80++0x3
line.long 0x0 "CH10_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH10_DBG_CTDREQ"
rgroup.long 0xA84++0x3
line.long 0x0 "CH10_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH10_DBG_TCR"
group.long 0xAC0++0x3
line.long 0x0 "CH11_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH11_DBG_CTDREQ"
rgroup.long 0xAC4++0x3
line.long 0x0 "CH11_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH11_DBG_TCR"
group.long 0xB00++0x3
line.long 0x0 "CH12_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH12_DBG_CTDREQ"
rgroup.long 0xB04++0x3
line.long 0x0 "CH12_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH12_DBG_TCR"
group.long 0xB40++0x3
line.long 0x0 "CH13_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH13_DBG_CTDREQ"
rgroup.long 0xB44++0x3
line.long 0x0 "CH13_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH13_DBG_TCR"
group.long 0xB80++0x3
line.long 0x0 "CH14_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH14_DBG_CTDREQ"
rgroup.long 0xB84++0x3
line.long 0x0 "CH14_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH14_DBG_TCR"
group.long 0xBC0++0x3
line.long 0x0 "CH15_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter. and cause channel to re-initiate DREQ handshake."
hexmask.long.byte 0x0 0.--5. 1. "CH15_DBG_CTDREQ"
rgroup.long 0xBC4++0x3
line.long 0x0 "CH15_DBG_TCR,Read to get channel TRANS_COUNT reload value. i.e. the length of the next transfer"
hexmask.long 0x0 0.--31. 1. "CH15_DBG_TCR"
tree.end
tree "EPPB (External PPB APB Interface)"
base ad:0xE0080000
group.long 0x0++0xB
line.long 0x0 "NMI_MASK0,NMI mask for IRQs 0 through 31. This register is core-local. and is reset by a processor warm reset."
hexmask.long 0x0 0.--31. 1. "NMI_MASK0"
line.long 0x4 "NMI_MASK1,NMI mask for IRQs 0 though 51. This register is core-local. and is reset by a processor warm reset."
hexmask.long.tbyte 0x4 0.--19. 1. "NMI_MASK1"
line.long 0x8 "SLEEPCTRL,Nonstandard sleep control register"
rbitfld.long 0x8 2. "WICENACK,Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK." "0,1"
bitfld.long 0x8 1. "WICENREQ,Request that the next processor deep sleep is a WIC sleep. After setting this bit before sleeping poll WICENACK to ensure the processor interrupt controller has acknowledged the change." "0,1"
bitfld.long 0x8 0. "LIGHT_SLEEP,By default any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup." "0,1"
tree.end
tree "GLITCH_DETECTOR"
base ad:0x40158000
group.long 0x0++0x13
line.long 0x0 "ARM,Forcibly arm the glitch detectors. if they are not already armed by OTP. When armed. any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine."
hexmask.long.word 0x0 0.--15. 1. "ARM"
line.long 0x4 "DISARM"
hexmask.long.word 0x4 0.--15. 1. "DISARM,Forcibly disarm the glitch detectors if they are armed by OTP. Ignored if ARM is YES."
line.long 0x8 "SENSITIVITY,Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults."
hexmask.long.byte 0x8 24.--31. 1. "DEFAULT"
bitfld.long 0x8 14.--15. "DET3_INV,Must be the inverse of DET3 else the default value is used." "0,1,2,3"
bitfld.long 0x8 12.--13. "DET2_INV,Must be the inverse of DET2 else the default value is used." "0,1,2,3"
bitfld.long 0x8 10.--11. "DET1_INV,Must be the inverse of DET1 else the default value is used." "0,1,2,3"
bitfld.long 0x8 8.--9. "DET0_INV,Must be the inverse of DET0 else the default value is used." "0,1,2,3"
bitfld.long 0x8 6.--7. "DET3,Set sensitivity for detector 3. Higher values are more sensitive." "0,1,2,3"
bitfld.long 0x8 4.--5. "DET2,Set sensitivity for detector 2. Higher values are more sensitive." "0,1,2,3"
bitfld.long 0x8 2.--3. "DET1,Set sensitivity for detector 1. Higher values are more sensitive." "0,1,2,3"
bitfld.long 0x8 0.--1. "DET0,Set sensitivity for detector 0. Higher values are more sensitive." "0,1,2,3"
line.long 0xC "LOCK"
hexmask.long.byte 0xC 0.--7. 1. "LOCK,Write any nonzero value to disable writes to ARM DISARM SENSITIVITY and LOCK. This register is Secure read/write only."
line.long 0x10 "TRIG_STATUS,Set when a detector output triggers. Write-1-clear."
eventfld.long 0x10 3. "DET3" "0,1"
eventfld.long 0x10 2. "DET2" "0,1"
eventfld.long 0x10 1. "DET1" "0,1"
eventfld.long 0x10 0. "DET0" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "TRIG_FORCE,Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG."
hexmask.long.byte 0x0 0.--3. 1. "TRIG_FORCE"
tree.end
tree "GPIO (General Purpose Input/Output)"
base ad:0x0
tree "IO (IO Banks)"
tree "IO_BANK0"
base ad:0x40028000
rgroup.long 0x0++0x3
line.long 0x0 "GPIO0_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x4++0x3
line.long 0x0 "GPIO0_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x8++0x3
line.long 0x0 "GPIO1_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xC++0x3
line.long 0x0 "GPIO1_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x10++0x3
line.long 0x0 "GPIO2_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x14++0x3
line.long 0x0 "GPIO2_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x18++0x3
line.long 0x0 "GPIO3_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x1C++0x3
line.long 0x0 "GPIO3_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x20++0x3
line.long 0x0 "GPIO4_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x24++0x3
line.long 0x0 "GPIO4_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x28++0x3
line.long 0x0 "GPIO5_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x2C++0x3
line.long 0x0 "GPIO5_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x30++0x3
line.long 0x0 "GPIO6_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x34++0x3
line.long 0x0 "GPIO6_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x38++0x3
line.long 0x0 "GPIO7_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x3C++0x3
line.long 0x0 "GPIO7_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x40++0x3
line.long 0x0 "GPIO8_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x44++0x3
line.long 0x0 "GPIO8_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x48++0x3
line.long 0x0 "GPIO9_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x4C++0x3
line.long 0x0 "GPIO9_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x50++0x3
line.long 0x0 "GPIO10_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x54++0x3
line.long 0x0 "GPIO10_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x58++0x3
line.long 0x0 "GPIO11_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x5C++0x3
line.long 0x0 "GPIO11_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x60++0x3
line.long 0x0 "GPIO12_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x64++0x3
line.long 0x0 "GPIO12_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x68++0x3
line.long 0x0 "GPIO13_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x6C++0x3
line.long 0x0 "GPIO13_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x70++0x3
line.long 0x0 "GPIO14_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x74++0x3
line.long 0x0 "GPIO14_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x78++0x3
line.long 0x0 "GPIO15_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x7C++0x3
line.long 0x0 "GPIO15_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x80++0x3
line.long 0x0 "GPIO16_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x84++0x3
line.long 0x0 "GPIO16_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x88++0x3
line.long 0x0 "GPIO17_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x8C++0x3
line.long 0x0 "GPIO17_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x90++0x3
line.long 0x0 "GPIO18_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x94++0x3
line.long 0x0 "GPIO18_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x98++0x3
line.long 0x0 "GPIO19_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x9C++0x3
line.long 0x0 "GPIO19_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xA0++0x3
line.long 0x0 "GPIO20_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xA4++0x3
line.long 0x0 "GPIO20_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xA8++0x3
line.long 0x0 "GPIO21_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xAC++0x3
line.long 0x0 "GPIO21_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xB0++0x3
line.long 0x0 "GPIO22_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xB4++0x3
line.long 0x0 "GPIO22_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xB8++0x3
line.long 0x0 "GPIO23_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xBC++0x3
line.long 0x0 "GPIO23_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xC0++0x3
line.long 0x0 "GPIO24_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xC4++0x3
line.long 0x0 "GPIO24_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xC8++0x3
line.long 0x0 "GPIO25_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xCC++0x3
line.long 0x0 "GPIO25_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xD0++0x3
line.long 0x0 "GPIO26_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xD4++0x3
line.long 0x0 "GPIO26_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xD8++0x3
line.long 0x0 "GPIO27_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xDC++0x3
line.long 0x0 "GPIO27_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xE0++0x3
line.long 0x0 "GPIO28_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xE4++0x3
line.long 0x0 "GPIO28_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xE8++0x3
line.long 0x0 "GPIO29_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xEC++0x3
line.long 0x0 "GPIO29_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xF0++0x3
line.long 0x0 "GPIO30_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xF4++0x3
line.long 0x0 "GPIO30_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0xF8++0x3
line.long 0x0 "GPIO31_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xFC++0x3
line.long 0x0 "GPIO31_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x100++0x3
line.long 0x0 "GPIO32_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x104++0x3
line.long 0x0 "GPIO32_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x108++0x3
line.long 0x0 "GPIO33_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x10C++0x3
line.long 0x0 "GPIO33_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x110++0x3
line.long 0x0 "GPIO34_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x114++0x3
line.long 0x0 "GPIO34_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x118++0x3
line.long 0x0 "GPIO35_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x11C++0x3
line.long 0x0 "GPIO35_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x120++0x3
line.long 0x0 "GPIO36_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x124++0x3
line.long 0x0 "GPIO36_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x128++0x3
line.long 0x0 "GPIO37_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x12C++0x3
line.long 0x0 "GPIO37_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x130++0x3
line.long 0x0 "GPIO38_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x134++0x3
line.long 0x0 "GPIO38_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x138++0x3
line.long 0x0 "GPIO39_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x13C++0x3
line.long 0x0 "GPIO39_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x140++0x3
line.long 0x0 "GPIO40_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x144++0x3
line.long 0x0 "GPIO40_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x148++0x3
line.long 0x0 "GPIO41_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x14C++0x3
line.long 0x0 "GPIO41_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x150++0x3
line.long 0x0 "GPIO42_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x154++0x3
line.long 0x0 "GPIO42_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x158++0x3
line.long 0x0 "GPIO43_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x15C++0x3
line.long 0x0 "GPIO43_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x160++0x3
line.long 0x0 "GPIO44_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x164++0x3
line.long 0x0 "GPIO44_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x168++0x3
line.long 0x0 "GPIO45_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x16C++0x3
line.long 0x0 "GPIO45_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x170++0x3
line.long 0x0 "GPIO46_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x174++0x3
line.long 0x0 "GPIO46_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x178++0x3
line.long 0x0 "GPIO47_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x17C++0x3
line.long 0x0 "GPIO47_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x200++0x2F
line.long 0x0 "IRQSUMMARY_PROC0_SECURE0"
bitfld.long 0x0 31. "GPIO31" "0,1"
newline
bitfld.long 0x0 30. "GPIO30" "0,1"
newline
bitfld.long 0x0 29. "GPIO29" "0,1"
newline
bitfld.long 0x0 28. "GPIO28" "0,1"
newline
bitfld.long 0x0 27. "GPIO27" "0,1"
newline
bitfld.long 0x0 26. "GPIO26" "0,1"
newline
bitfld.long 0x0 25. "GPIO25" "0,1"
newline
bitfld.long 0x0 24. "GPIO24" "0,1"
newline
bitfld.long 0x0 23. "GPIO23" "0,1"
newline
bitfld.long 0x0 22. "GPIO22" "0,1"
newline
bitfld.long 0x0 21. "GPIO21" "0,1"
newline
bitfld.long 0x0 20. "GPIO20" "0,1"
newline
bitfld.long 0x0 19. "GPIO19" "0,1"
newline
bitfld.long 0x0 18. "GPIO18" "0,1"
newline
bitfld.long 0x0 17. "GPIO17" "0,1"
newline
bitfld.long 0x0 16. "GPIO16" "0,1"
newline
bitfld.long 0x0 15. "GPIO15" "0,1"
newline
bitfld.long 0x0 14. "GPIO14" "0,1"
newline
bitfld.long 0x0 13. "GPIO13" "0,1"
newline
bitfld.long 0x0 12. "GPIO12" "0,1"
newline
bitfld.long 0x0 11. "GPIO11" "0,1"
newline
bitfld.long 0x0 10. "GPIO10" "0,1"
newline
bitfld.long 0x0 9. "GPIO9" "0,1"
newline
bitfld.long 0x0 8. "GPIO8" "0,1"
newline
bitfld.long 0x0 7. "GPIO7" "0,1"
newline
bitfld.long 0x0 6. "GPIO6" "0,1"
newline
bitfld.long 0x0 5. "GPIO5" "0,1"
newline
bitfld.long 0x0 4. "GPIO4" "0,1"
newline
bitfld.long 0x0 3. "GPIO3" "0,1"
newline
bitfld.long 0x0 2. "GPIO2" "0,1"
newline
bitfld.long 0x0 1. "GPIO1" "0,1"
newline
bitfld.long 0x0 0. "GPIO0" "0,1"
line.long 0x4 "IRQSUMMARY_PROC0_SECURE1"
bitfld.long 0x4 15. "GPIO47" "0,1"
newline
bitfld.long 0x4 14. "GPIO46" "0,1"
newline
bitfld.long 0x4 13. "GPIO45" "0,1"
newline
bitfld.long 0x4 12. "GPIO44" "0,1"
newline
bitfld.long 0x4 11. "GPIO43" "0,1"
newline
bitfld.long 0x4 10. "GPIO42" "0,1"
newline
bitfld.long 0x4 9. "GPIO41" "0,1"
newline
bitfld.long 0x4 8. "GPIO40" "0,1"
newline
bitfld.long 0x4 7. "GPIO39" "0,1"
newline
bitfld.long 0x4 6. "GPIO38" "0,1"
newline
bitfld.long 0x4 5. "GPIO37" "0,1"
newline
bitfld.long 0x4 4. "GPIO36" "0,1"
newline
bitfld.long 0x4 3. "GPIO35" "0,1"
newline
bitfld.long 0x4 2. "GPIO34" "0,1"
newline
bitfld.long 0x4 1. "GPIO33" "0,1"
newline
bitfld.long 0x4 0. "GPIO32" "0,1"
line.long 0x8 "IRQSUMMARY_PROC0_NONSECURE0"
bitfld.long 0x8 31. "GPIO31" "0,1"
newline
bitfld.long 0x8 30. "GPIO30" "0,1"
newline
bitfld.long 0x8 29. "GPIO29" "0,1"
newline
bitfld.long 0x8 28. "GPIO28" "0,1"
newline
bitfld.long 0x8 27. "GPIO27" "0,1"
newline
bitfld.long 0x8 26. "GPIO26" "0,1"
newline
bitfld.long 0x8 25. "GPIO25" "0,1"
newline
bitfld.long 0x8 24. "GPIO24" "0,1"
newline
bitfld.long 0x8 23. "GPIO23" "0,1"
newline
bitfld.long 0x8 22. "GPIO22" "0,1"
newline
bitfld.long 0x8 21. "GPIO21" "0,1"
newline
bitfld.long 0x8 20. "GPIO20" "0,1"
newline
bitfld.long 0x8 19. "GPIO19" "0,1"
newline
bitfld.long 0x8 18. "GPIO18" "0,1"
newline
bitfld.long 0x8 17. "GPIO17" "0,1"
newline
bitfld.long 0x8 16. "GPIO16" "0,1"
newline
bitfld.long 0x8 15. "GPIO15" "0,1"
newline
bitfld.long 0x8 14. "GPIO14" "0,1"
newline
bitfld.long 0x8 13. "GPIO13" "0,1"
newline
bitfld.long 0x8 12. "GPIO12" "0,1"
newline
bitfld.long 0x8 11. "GPIO11" "0,1"
newline
bitfld.long 0x8 10. "GPIO10" "0,1"
newline
bitfld.long 0x8 9. "GPIO9" "0,1"
newline
bitfld.long 0x8 8. "GPIO8" "0,1"
newline
bitfld.long 0x8 7. "GPIO7" "0,1"
newline
bitfld.long 0x8 6. "GPIO6" "0,1"
newline
bitfld.long 0x8 5. "GPIO5" "0,1"
newline
bitfld.long 0x8 4. "GPIO4" "0,1"
newline
bitfld.long 0x8 3. "GPIO3" "0,1"
newline
bitfld.long 0x8 2. "GPIO2" "0,1"
newline
bitfld.long 0x8 1. "GPIO1" "0,1"
newline
bitfld.long 0x8 0. "GPIO0" "0,1"
line.long 0xC "IRQSUMMARY_PROC0_NONSECURE1"
bitfld.long 0xC 15. "GPIO47" "0,1"
newline
bitfld.long 0xC 14. "GPIO46" "0,1"
newline
bitfld.long 0xC 13. "GPIO45" "0,1"
newline
bitfld.long 0xC 12. "GPIO44" "0,1"
newline
bitfld.long 0xC 11. "GPIO43" "0,1"
newline
bitfld.long 0xC 10. "GPIO42" "0,1"
newline
bitfld.long 0xC 9. "GPIO41" "0,1"
newline
bitfld.long 0xC 8. "GPIO40" "0,1"
newline
bitfld.long 0xC 7. "GPIO39" "0,1"
newline
bitfld.long 0xC 6. "GPIO38" "0,1"
newline
bitfld.long 0xC 5. "GPIO37" "0,1"
newline
bitfld.long 0xC 4. "GPIO36" "0,1"
newline
bitfld.long 0xC 3. "GPIO35" "0,1"
newline
bitfld.long 0xC 2. "GPIO34" "0,1"
newline
bitfld.long 0xC 1. "GPIO33" "0,1"
newline
bitfld.long 0xC 0. "GPIO32" "0,1"
line.long 0x10 "IRQSUMMARY_PROC1_SECURE0"
bitfld.long 0x10 31. "GPIO31" "0,1"
newline
bitfld.long 0x10 30. "GPIO30" "0,1"
newline
bitfld.long 0x10 29. "GPIO29" "0,1"
newline
bitfld.long 0x10 28. "GPIO28" "0,1"
newline
bitfld.long 0x10 27. "GPIO27" "0,1"
newline
bitfld.long 0x10 26. "GPIO26" "0,1"
newline
bitfld.long 0x10 25. "GPIO25" "0,1"
newline
bitfld.long 0x10 24. "GPIO24" "0,1"
newline
bitfld.long 0x10 23. "GPIO23" "0,1"
newline
bitfld.long 0x10 22. "GPIO22" "0,1"
newline
bitfld.long 0x10 21. "GPIO21" "0,1"
newline
bitfld.long 0x10 20. "GPIO20" "0,1"
newline
bitfld.long 0x10 19. "GPIO19" "0,1"
newline
bitfld.long 0x10 18. "GPIO18" "0,1"
newline
bitfld.long 0x10 17. "GPIO17" "0,1"
newline
bitfld.long 0x10 16. "GPIO16" "0,1"
newline
bitfld.long 0x10 15. "GPIO15" "0,1"
newline
bitfld.long 0x10 14. "GPIO14" "0,1"
newline
bitfld.long 0x10 13. "GPIO13" "0,1"
newline
bitfld.long 0x10 12. "GPIO12" "0,1"
newline
bitfld.long 0x10 11. "GPIO11" "0,1"
newline
bitfld.long 0x10 10. "GPIO10" "0,1"
newline
bitfld.long 0x10 9. "GPIO9" "0,1"
newline
bitfld.long 0x10 8. "GPIO8" "0,1"
newline
bitfld.long 0x10 7. "GPIO7" "0,1"
newline
bitfld.long 0x10 6. "GPIO6" "0,1"
newline
bitfld.long 0x10 5. "GPIO5" "0,1"
newline
bitfld.long 0x10 4. "GPIO4" "0,1"
newline
bitfld.long 0x10 3. "GPIO3" "0,1"
newline
bitfld.long 0x10 2. "GPIO2" "0,1"
newline
bitfld.long 0x10 1. "GPIO1" "0,1"
newline
bitfld.long 0x10 0. "GPIO0" "0,1"
line.long 0x14 "IRQSUMMARY_PROC1_SECURE1"
bitfld.long 0x14 15. "GPIO47" "0,1"
newline
bitfld.long 0x14 14. "GPIO46" "0,1"
newline
bitfld.long 0x14 13. "GPIO45" "0,1"
newline
bitfld.long 0x14 12. "GPIO44" "0,1"
newline
bitfld.long 0x14 11. "GPIO43" "0,1"
newline
bitfld.long 0x14 10. "GPIO42" "0,1"
newline
bitfld.long 0x14 9. "GPIO41" "0,1"
newline
bitfld.long 0x14 8. "GPIO40" "0,1"
newline
bitfld.long 0x14 7. "GPIO39" "0,1"
newline
bitfld.long 0x14 6. "GPIO38" "0,1"
newline
bitfld.long 0x14 5. "GPIO37" "0,1"
newline
bitfld.long 0x14 4. "GPIO36" "0,1"
newline
bitfld.long 0x14 3. "GPIO35" "0,1"
newline
bitfld.long 0x14 2. "GPIO34" "0,1"
newline
bitfld.long 0x14 1. "GPIO33" "0,1"
newline
bitfld.long 0x14 0. "GPIO32" "0,1"
line.long 0x18 "IRQSUMMARY_PROC1_NONSECURE0"
bitfld.long 0x18 31. "GPIO31" "0,1"
newline
bitfld.long 0x18 30. "GPIO30" "0,1"
newline
bitfld.long 0x18 29. "GPIO29" "0,1"
newline
bitfld.long 0x18 28. "GPIO28" "0,1"
newline
bitfld.long 0x18 27. "GPIO27" "0,1"
newline
bitfld.long 0x18 26. "GPIO26" "0,1"
newline
bitfld.long 0x18 25. "GPIO25" "0,1"
newline
bitfld.long 0x18 24. "GPIO24" "0,1"
newline
bitfld.long 0x18 23. "GPIO23" "0,1"
newline
bitfld.long 0x18 22. "GPIO22" "0,1"
newline
bitfld.long 0x18 21. "GPIO21" "0,1"
newline
bitfld.long 0x18 20. "GPIO20" "0,1"
newline
bitfld.long 0x18 19. "GPIO19" "0,1"
newline
bitfld.long 0x18 18. "GPIO18" "0,1"
newline
bitfld.long 0x18 17. "GPIO17" "0,1"
newline
bitfld.long 0x18 16. "GPIO16" "0,1"
newline
bitfld.long 0x18 15. "GPIO15" "0,1"
newline
bitfld.long 0x18 14. "GPIO14" "0,1"
newline
bitfld.long 0x18 13. "GPIO13" "0,1"
newline
bitfld.long 0x18 12. "GPIO12" "0,1"
newline
bitfld.long 0x18 11. "GPIO11" "0,1"
newline
bitfld.long 0x18 10. "GPIO10" "0,1"
newline
bitfld.long 0x18 9. "GPIO9" "0,1"
newline
bitfld.long 0x18 8. "GPIO8" "0,1"
newline
bitfld.long 0x18 7. "GPIO7" "0,1"
newline
bitfld.long 0x18 6. "GPIO6" "0,1"
newline
bitfld.long 0x18 5. "GPIO5" "0,1"
newline
bitfld.long 0x18 4. "GPIO4" "0,1"
newline
bitfld.long 0x18 3. "GPIO3" "0,1"
newline
bitfld.long 0x18 2. "GPIO2" "0,1"
newline
bitfld.long 0x18 1. "GPIO1" "0,1"
newline
bitfld.long 0x18 0. "GPIO0" "0,1"
line.long 0x1C "IRQSUMMARY_PROC1_NONSECURE1"
bitfld.long 0x1C 15. "GPIO47" "0,1"
newline
bitfld.long 0x1C 14. "GPIO46" "0,1"
newline
bitfld.long 0x1C 13. "GPIO45" "0,1"
newline
bitfld.long 0x1C 12. "GPIO44" "0,1"
newline
bitfld.long 0x1C 11. "GPIO43" "0,1"
newline
bitfld.long 0x1C 10. "GPIO42" "0,1"
newline
bitfld.long 0x1C 9. "GPIO41" "0,1"
newline
bitfld.long 0x1C 8. "GPIO40" "0,1"
newline
bitfld.long 0x1C 7. "GPIO39" "0,1"
newline
bitfld.long 0x1C 6. "GPIO38" "0,1"
newline
bitfld.long 0x1C 5. "GPIO37" "0,1"
newline
bitfld.long 0x1C 4. "GPIO36" "0,1"
newline
bitfld.long 0x1C 3. "GPIO35" "0,1"
newline
bitfld.long 0x1C 2. "GPIO34" "0,1"
newline
bitfld.long 0x1C 1. "GPIO33" "0,1"
newline
bitfld.long 0x1C 0. "GPIO32" "0,1"
line.long 0x20 "IRQSUMMARY_DORMANT_WAKE_SECURE0"
bitfld.long 0x20 31. "GPIO31" "0,1"
newline
bitfld.long 0x20 30. "GPIO30" "0,1"
newline
bitfld.long 0x20 29. "GPIO29" "0,1"
newline
bitfld.long 0x20 28. "GPIO28" "0,1"
newline
bitfld.long 0x20 27. "GPIO27" "0,1"
newline
bitfld.long 0x20 26. "GPIO26" "0,1"
newline
bitfld.long 0x20 25. "GPIO25" "0,1"
newline
bitfld.long 0x20 24. "GPIO24" "0,1"
newline
bitfld.long 0x20 23. "GPIO23" "0,1"
newline
bitfld.long 0x20 22. "GPIO22" "0,1"
newline
bitfld.long 0x20 21. "GPIO21" "0,1"
newline
bitfld.long 0x20 20. "GPIO20" "0,1"
newline
bitfld.long 0x20 19. "GPIO19" "0,1"
newline
bitfld.long 0x20 18. "GPIO18" "0,1"
newline
bitfld.long 0x20 17. "GPIO17" "0,1"
newline
bitfld.long 0x20 16. "GPIO16" "0,1"
newline
bitfld.long 0x20 15. "GPIO15" "0,1"
newline
bitfld.long 0x20 14. "GPIO14" "0,1"
newline
bitfld.long 0x20 13. "GPIO13" "0,1"
newline
bitfld.long 0x20 12. "GPIO12" "0,1"
newline
bitfld.long 0x20 11. "GPIO11" "0,1"
newline
bitfld.long 0x20 10. "GPIO10" "0,1"
newline
bitfld.long 0x20 9. "GPIO9" "0,1"
newline
bitfld.long 0x20 8. "GPIO8" "0,1"
newline
bitfld.long 0x20 7. "GPIO7" "0,1"
newline
bitfld.long 0x20 6. "GPIO6" "0,1"
newline
bitfld.long 0x20 5. "GPIO5" "0,1"
newline
bitfld.long 0x20 4. "GPIO4" "0,1"
newline
bitfld.long 0x20 3. "GPIO3" "0,1"
newline
bitfld.long 0x20 2. "GPIO2" "0,1"
newline
bitfld.long 0x20 1. "GPIO1" "0,1"
newline
bitfld.long 0x20 0. "GPIO0" "0,1"
line.long 0x24 "IRQSUMMARY_DORMANT_WAKE_SECURE1"
bitfld.long 0x24 15. "GPIO47" "0,1"
newline
bitfld.long 0x24 14. "GPIO46" "0,1"
newline
bitfld.long 0x24 13. "GPIO45" "0,1"
newline
bitfld.long 0x24 12. "GPIO44" "0,1"
newline
bitfld.long 0x24 11. "GPIO43" "0,1"
newline
bitfld.long 0x24 10. "GPIO42" "0,1"
newline
bitfld.long 0x24 9. "GPIO41" "0,1"
newline
bitfld.long 0x24 8. "GPIO40" "0,1"
newline
bitfld.long 0x24 7. "GPIO39" "0,1"
newline
bitfld.long 0x24 6. "GPIO38" "0,1"
newline
bitfld.long 0x24 5. "GPIO37" "0,1"
newline
bitfld.long 0x24 4. "GPIO36" "0,1"
newline
bitfld.long 0x24 3. "GPIO35" "0,1"
newline
bitfld.long 0x24 2. "GPIO34" "0,1"
newline
bitfld.long 0x24 1. "GPIO33" "0,1"
newline
bitfld.long 0x24 0. "GPIO32" "0,1"
line.long 0x28 "IRQSUMMARY_DORMANT_WAKE_NONSECURE0"
bitfld.long 0x28 31. "GPIO31" "0,1"
newline
bitfld.long 0x28 30. "GPIO30" "0,1"
newline
bitfld.long 0x28 29. "GPIO29" "0,1"
newline
bitfld.long 0x28 28. "GPIO28" "0,1"
newline
bitfld.long 0x28 27. "GPIO27" "0,1"
newline
bitfld.long 0x28 26. "GPIO26" "0,1"
newline
bitfld.long 0x28 25. "GPIO25" "0,1"
newline
bitfld.long 0x28 24. "GPIO24" "0,1"
newline
bitfld.long 0x28 23. "GPIO23" "0,1"
newline
bitfld.long 0x28 22. "GPIO22" "0,1"
newline
bitfld.long 0x28 21. "GPIO21" "0,1"
newline
bitfld.long 0x28 20. "GPIO20" "0,1"
newline
bitfld.long 0x28 19. "GPIO19" "0,1"
newline
bitfld.long 0x28 18. "GPIO18" "0,1"
newline
bitfld.long 0x28 17. "GPIO17" "0,1"
newline
bitfld.long 0x28 16. "GPIO16" "0,1"
newline
bitfld.long 0x28 15. "GPIO15" "0,1"
newline
bitfld.long 0x28 14. "GPIO14" "0,1"
newline
bitfld.long 0x28 13. "GPIO13" "0,1"
newline
bitfld.long 0x28 12. "GPIO12" "0,1"
newline
bitfld.long 0x28 11. "GPIO11" "0,1"
newline
bitfld.long 0x28 10. "GPIO10" "0,1"
newline
bitfld.long 0x28 9. "GPIO9" "0,1"
newline
bitfld.long 0x28 8. "GPIO8" "0,1"
newline
bitfld.long 0x28 7. "GPIO7" "0,1"
newline
bitfld.long 0x28 6. "GPIO6" "0,1"
newline
bitfld.long 0x28 5. "GPIO5" "0,1"
newline
bitfld.long 0x28 4. "GPIO4" "0,1"
newline
bitfld.long 0x28 3. "GPIO3" "0,1"
newline
bitfld.long 0x28 2. "GPIO2" "0,1"
newline
bitfld.long 0x28 1. "GPIO1" "0,1"
newline
bitfld.long 0x28 0. "GPIO0" "0,1"
line.long 0x2C "IRQSUMMARY_DORMANT_WAKE_NONSECURE1"
bitfld.long 0x2C 15. "GPIO47" "0,1"
newline
bitfld.long 0x2C 14. "GPIO46" "0,1"
newline
bitfld.long 0x2C 13. "GPIO45" "0,1"
newline
bitfld.long 0x2C 12. "GPIO44" "0,1"
newline
bitfld.long 0x2C 11. "GPIO43" "0,1"
newline
bitfld.long 0x2C 10. "GPIO42" "0,1"
newline
bitfld.long 0x2C 9. "GPIO41" "0,1"
newline
bitfld.long 0x2C 8. "GPIO40" "0,1"
newline
bitfld.long 0x2C 7. "GPIO39" "0,1"
newline
bitfld.long 0x2C 6. "GPIO38" "0,1"
newline
bitfld.long 0x2C 5. "GPIO37" "0,1"
newline
bitfld.long 0x2C 4. "GPIO36" "0,1"
newline
bitfld.long 0x2C 3. "GPIO35" "0,1"
newline
bitfld.long 0x2C 2. "GPIO34" "0,1"
newline
bitfld.long 0x2C 1. "GPIO33" "0,1"
newline
bitfld.long 0x2C 0. "GPIO32" "0,1"
group.long 0x230++0x47
line.long 0x0 "INTR0,Raw Interrupts"
eventfld.long 0x0 31. "GPIO7_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 30. "GPIO7_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 29. "GPIO7_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 28. "GPIO7_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 27. "GPIO6_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 26. "GPIO6_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 25. "GPIO6_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 24. "GPIO6_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 23. "GPIO5_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 22. "GPIO5_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 21. "GPIO5_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 20. "GPIO5_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 19. "GPIO4_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 18. "GPIO4_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 17. "GPIO4_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 16. "GPIO4_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 15. "GPIO3_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 14. "GPIO3_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 13. "GPIO3_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 12. "GPIO3_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 11. "GPIO2_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 10. "GPIO2_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 9. "GPIO2_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 8. "GPIO2_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 7. "GPIO1_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 6. "GPIO1_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 5. "GPIO1_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 4. "GPIO1_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 3. "GPIO0_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 2. "GPIO0_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 1. "GPIO0_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 0. "GPIO0_LEVEL_LOW" "0,1"
line.long 0x4 "INTR1,Raw Interrupts"
eventfld.long 0x4 31. "GPIO15_EDGE_HIGH" "0,1"
newline
eventfld.long 0x4 30. "GPIO15_EDGE_LOW" "0,1"
newline
rbitfld.long 0x4 29. "GPIO15_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x4 28. "GPIO15_LEVEL_LOW" "0,1"
newline
eventfld.long 0x4 27. "GPIO14_EDGE_HIGH" "0,1"
newline
eventfld.long 0x4 26. "GPIO14_EDGE_LOW" "0,1"
newline
rbitfld.long 0x4 25. "GPIO14_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x4 24. "GPIO14_LEVEL_LOW" "0,1"
newline
eventfld.long 0x4 23. "GPIO13_EDGE_HIGH" "0,1"
newline
eventfld.long 0x4 22. "GPIO13_EDGE_LOW" "0,1"
newline
rbitfld.long 0x4 21. "GPIO13_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x4 20. "GPIO13_LEVEL_LOW" "0,1"
newline
eventfld.long 0x4 19. "GPIO12_EDGE_HIGH" "0,1"
newline
eventfld.long 0x4 18. "GPIO12_EDGE_LOW" "0,1"
newline
rbitfld.long 0x4 17. "GPIO12_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x4 16. "GPIO12_LEVEL_LOW" "0,1"
newline
eventfld.long 0x4 15. "GPIO11_EDGE_HIGH" "0,1"
newline
eventfld.long 0x4 14. "GPIO11_EDGE_LOW" "0,1"
newline
rbitfld.long 0x4 13. "GPIO11_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x4 12. "GPIO11_LEVEL_LOW" "0,1"
newline
eventfld.long 0x4 11. "GPIO10_EDGE_HIGH" "0,1"
newline
eventfld.long 0x4 10. "GPIO10_EDGE_LOW" "0,1"
newline
rbitfld.long 0x4 9. "GPIO10_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x4 8. "GPIO10_LEVEL_LOW" "0,1"
newline
eventfld.long 0x4 7. "GPIO9_EDGE_HIGH" "0,1"
newline
eventfld.long 0x4 6. "GPIO9_EDGE_LOW" "0,1"
newline
rbitfld.long 0x4 5. "GPIO9_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x4 4. "GPIO9_LEVEL_LOW" "0,1"
newline
eventfld.long 0x4 3. "GPIO8_EDGE_HIGH" "0,1"
newline
eventfld.long 0x4 2. "GPIO8_EDGE_LOW" "0,1"
newline
rbitfld.long 0x4 1. "GPIO8_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x4 0. "GPIO8_LEVEL_LOW" "0,1"
line.long 0x8 "INTR2,Raw Interrupts"
eventfld.long 0x8 31. "GPIO23_EDGE_HIGH" "0,1"
newline
eventfld.long 0x8 30. "GPIO23_EDGE_LOW" "0,1"
newline
rbitfld.long 0x8 29. "GPIO23_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x8 28. "GPIO23_LEVEL_LOW" "0,1"
newline
eventfld.long 0x8 27. "GPIO22_EDGE_HIGH" "0,1"
newline
eventfld.long 0x8 26. "GPIO22_EDGE_LOW" "0,1"
newline
rbitfld.long 0x8 25. "GPIO22_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x8 24. "GPIO22_LEVEL_LOW" "0,1"
newline
eventfld.long 0x8 23. "GPIO21_EDGE_HIGH" "0,1"
newline
eventfld.long 0x8 22. "GPIO21_EDGE_LOW" "0,1"
newline
rbitfld.long 0x8 21. "GPIO21_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x8 20. "GPIO21_LEVEL_LOW" "0,1"
newline
eventfld.long 0x8 19. "GPIO20_EDGE_HIGH" "0,1"
newline
eventfld.long 0x8 18. "GPIO20_EDGE_LOW" "0,1"
newline
rbitfld.long 0x8 17. "GPIO20_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x8 16. "GPIO20_LEVEL_LOW" "0,1"
newline
eventfld.long 0x8 15. "GPIO19_EDGE_HIGH" "0,1"
newline
eventfld.long 0x8 14. "GPIO19_EDGE_LOW" "0,1"
newline
rbitfld.long 0x8 13. "GPIO19_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x8 12. "GPIO19_LEVEL_LOW" "0,1"
newline
eventfld.long 0x8 11. "GPIO18_EDGE_HIGH" "0,1"
newline
eventfld.long 0x8 10. "GPIO18_EDGE_LOW" "0,1"
newline
rbitfld.long 0x8 9. "GPIO18_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x8 8. "GPIO18_LEVEL_LOW" "0,1"
newline
eventfld.long 0x8 7. "GPIO17_EDGE_HIGH" "0,1"
newline
eventfld.long 0x8 6. "GPIO17_EDGE_LOW" "0,1"
newline
rbitfld.long 0x8 5. "GPIO17_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x8 4. "GPIO17_LEVEL_LOW" "0,1"
newline
eventfld.long 0x8 3. "GPIO16_EDGE_HIGH" "0,1"
newline
eventfld.long 0x8 2. "GPIO16_EDGE_LOW" "0,1"
newline
rbitfld.long 0x8 1. "GPIO16_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x8 0. "GPIO16_LEVEL_LOW" "0,1"
line.long 0xC "INTR3,Raw Interrupts"
eventfld.long 0xC 31. "GPIO31_EDGE_HIGH" "0,1"
newline
eventfld.long 0xC 30. "GPIO31_EDGE_LOW" "0,1"
newline
rbitfld.long 0xC 29. "GPIO31_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0xC 28. "GPIO31_LEVEL_LOW" "0,1"
newline
eventfld.long 0xC 27. "GPIO30_EDGE_HIGH" "0,1"
newline
eventfld.long 0xC 26. "GPIO30_EDGE_LOW" "0,1"
newline
rbitfld.long 0xC 25. "GPIO30_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0xC 24. "GPIO30_LEVEL_LOW" "0,1"
newline
eventfld.long 0xC 23. "GPIO29_EDGE_HIGH" "0,1"
newline
eventfld.long 0xC 22. "GPIO29_EDGE_LOW" "0,1"
newline
rbitfld.long 0xC 21. "GPIO29_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0xC 20. "GPIO29_LEVEL_LOW" "0,1"
newline
eventfld.long 0xC 19. "GPIO28_EDGE_HIGH" "0,1"
newline
eventfld.long 0xC 18. "GPIO28_EDGE_LOW" "0,1"
newline
rbitfld.long 0xC 17. "GPIO28_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0xC 16. "GPIO28_LEVEL_LOW" "0,1"
newline
eventfld.long 0xC 15. "GPIO27_EDGE_HIGH" "0,1"
newline
eventfld.long 0xC 14. "GPIO27_EDGE_LOW" "0,1"
newline
rbitfld.long 0xC 13. "GPIO27_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0xC 12. "GPIO27_LEVEL_LOW" "0,1"
newline
eventfld.long 0xC 11. "GPIO26_EDGE_HIGH" "0,1"
newline
eventfld.long 0xC 10. "GPIO26_EDGE_LOW" "0,1"
newline
rbitfld.long 0xC 9. "GPIO26_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0xC 8. "GPIO26_LEVEL_LOW" "0,1"
newline
eventfld.long 0xC 7. "GPIO25_EDGE_HIGH" "0,1"
newline
eventfld.long 0xC 6. "GPIO25_EDGE_LOW" "0,1"
newline
rbitfld.long 0xC 5. "GPIO25_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0xC 4. "GPIO25_LEVEL_LOW" "0,1"
newline
eventfld.long 0xC 3. "GPIO24_EDGE_HIGH" "0,1"
newline
eventfld.long 0xC 2. "GPIO24_EDGE_LOW" "0,1"
newline
rbitfld.long 0xC 1. "GPIO24_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0xC 0. "GPIO24_LEVEL_LOW" "0,1"
line.long 0x10 "INTR4,Raw Interrupts"
eventfld.long 0x10 31. "GPIO39_EDGE_HIGH" "0,1"
newline
eventfld.long 0x10 30. "GPIO39_EDGE_LOW" "0,1"
newline
rbitfld.long 0x10 29. "GPIO39_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x10 28. "GPIO39_LEVEL_LOW" "0,1"
newline
eventfld.long 0x10 27. "GPIO38_EDGE_HIGH" "0,1"
newline
eventfld.long 0x10 26. "GPIO38_EDGE_LOW" "0,1"
newline
rbitfld.long 0x10 25. "GPIO38_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x10 24. "GPIO38_LEVEL_LOW" "0,1"
newline
eventfld.long 0x10 23. "GPIO37_EDGE_HIGH" "0,1"
newline
eventfld.long 0x10 22. "GPIO37_EDGE_LOW" "0,1"
newline
rbitfld.long 0x10 21. "GPIO37_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x10 20. "GPIO37_LEVEL_LOW" "0,1"
newline
eventfld.long 0x10 19. "GPIO36_EDGE_HIGH" "0,1"
newline
eventfld.long 0x10 18. "GPIO36_EDGE_LOW" "0,1"
newline
rbitfld.long 0x10 17. "GPIO36_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x10 16. "GPIO36_LEVEL_LOW" "0,1"
newline
eventfld.long 0x10 15. "GPIO35_EDGE_HIGH" "0,1"
newline
eventfld.long 0x10 14. "GPIO35_EDGE_LOW" "0,1"
newline
rbitfld.long 0x10 13. "GPIO35_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x10 12. "GPIO35_LEVEL_LOW" "0,1"
newline
eventfld.long 0x10 11. "GPIO34_EDGE_HIGH" "0,1"
newline
eventfld.long 0x10 10. "GPIO34_EDGE_LOW" "0,1"
newline
rbitfld.long 0x10 9. "GPIO34_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x10 8. "GPIO34_LEVEL_LOW" "0,1"
newline
eventfld.long 0x10 7. "GPIO33_EDGE_HIGH" "0,1"
newline
eventfld.long 0x10 6. "GPIO33_EDGE_LOW" "0,1"
newline
rbitfld.long 0x10 5. "GPIO33_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x10 4. "GPIO33_LEVEL_LOW" "0,1"
newline
eventfld.long 0x10 3. "GPIO32_EDGE_HIGH" "0,1"
newline
eventfld.long 0x10 2. "GPIO32_EDGE_LOW" "0,1"
newline
rbitfld.long 0x10 1. "GPIO32_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x10 0. "GPIO32_LEVEL_LOW" "0,1"
line.long 0x14 "INTR5,Raw Interrupts"
eventfld.long 0x14 31. "GPIO47_EDGE_HIGH" "0,1"
newline
eventfld.long 0x14 30. "GPIO47_EDGE_LOW" "0,1"
newline
rbitfld.long 0x14 29. "GPIO47_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x14 28. "GPIO47_LEVEL_LOW" "0,1"
newline
eventfld.long 0x14 27. "GPIO46_EDGE_HIGH" "0,1"
newline
eventfld.long 0x14 26. "GPIO46_EDGE_LOW" "0,1"
newline
rbitfld.long 0x14 25. "GPIO46_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x14 24. "GPIO46_LEVEL_LOW" "0,1"
newline
eventfld.long 0x14 23. "GPIO45_EDGE_HIGH" "0,1"
newline
eventfld.long 0x14 22. "GPIO45_EDGE_LOW" "0,1"
newline
rbitfld.long 0x14 21. "GPIO45_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x14 20. "GPIO45_LEVEL_LOW" "0,1"
newline
eventfld.long 0x14 19. "GPIO44_EDGE_HIGH" "0,1"
newline
eventfld.long 0x14 18. "GPIO44_EDGE_LOW" "0,1"
newline
rbitfld.long 0x14 17. "GPIO44_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x14 16. "GPIO44_LEVEL_LOW" "0,1"
newline
eventfld.long 0x14 15. "GPIO43_EDGE_HIGH" "0,1"
newline
eventfld.long 0x14 14. "GPIO43_EDGE_LOW" "0,1"
newline
rbitfld.long 0x14 13. "GPIO43_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x14 12. "GPIO43_LEVEL_LOW" "0,1"
newline
eventfld.long 0x14 11. "GPIO42_EDGE_HIGH" "0,1"
newline
eventfld.long 0x14 10. "GPIO42_EDGE_LOW" "0,1"
newline
rbitfld.long 0x14 9. "GPIO42_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x14 8. "GPIO42_LEVEL_LOW" "0,1"
newline
eventfld.long 0x14 7. "GPIO41_EDGE_HIGH" "0,1"
newline
eventfld.long 0x14 6. "GPIO41_EDGE_LOW" "0,1"
newline
rbitfld.long 0x14 5. "GPIO41_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x14 4. "GPIO41_LEVEL_LOW" "0,1"
newline
eventfld.long 0x14 3. "GPIO40_EDGE_HIGH" "0,1"
newline
eventfld.long 0x14 2. "GPIO40_EDGE_LOW" "0,1"
newline
rbitfld.long 0x14 1. "GPIO40_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x14 0. "GPIO40_LEVEL_LOW" "0,1"
line.long 0x18 "PROC0_INTE0,Interrupt Enable for proc0"
bitfld.long 0x18 31. "GPIO7_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 30. "GPIO7_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 29. "GPIO7_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 28. "GPIO7_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 27. "GPIO6_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 26. "GPIO6_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 25. "GPIO6_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 24. "GPIO6_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 23. "GPIO5_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 22. "GPIO5_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 21. "GPIO5_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 20. "GPIO5_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 19. "GPIO4_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 18. "GPIO4_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 17. "GPIO4_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 16. "GPIO4_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 15. "GPIO3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 14. "GPIO3_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 13. "GPIO3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 12. "GPIO3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 11. "GPIO2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 10. "GPIO2_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 9. "GPIO2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 8. "GPIO2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 7. "GPIO1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 6. "GPIO1_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 5. "GPIO1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 4. "GPIO1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 3. "GPIO0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 2. "GPIO0_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 1. "GPIO0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 0. "GPIO0_LEVEL_LOW" "0,1"
line.long 0x1C "PROC0_INTE1,Interrupt Enable for proc0"
bitfld.long 0x1C 31. "GPIO15_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 30. "GPIO15_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 29. "GPIO15_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 28. "GPIO15_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 27. "GPIO14_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 26. "GPIO14_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 25. "GPIO14_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 24. "GPIO14_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 23. "GPIO13_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 22. "GPIO13_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 21. "GPIO13_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 20. "GPIO13_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 19. "GPIO12_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 18. "GPIO12_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 17. "GPIO12_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 16. "GPIO12_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 15. "GPIO11_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 14. "GPIO11_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 13. "GPIO11_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 12. "GPIO11_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 11. "GPIO10_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 10. "GPIO10_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 9. "GPIO10_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 8. "GPIO10_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 7. "GPIO9_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 6. "GPIO9_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 5. "GPIO9_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 4. "GPIO9_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 3. "GPIO8_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 2. "GPIO8_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 1. "GPIO8_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 0. "GPIO8_LEVEL_LOW" "0,1"
line.long 0x20 "PROC0_INTE2,Interrupt Enable for proc0"
bitfld.long 0x20 31. "GPIO23_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 30. "GPIO23_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 29. "GPIO23_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 28. "GPIO23_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 27. "GPIO22_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 26. "GPIO22_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 25. "GPIO22_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 24. "GPIO22_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 23. "GPIO21_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 22. "GPIO21_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 21. "GPIO21_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 20. "GPIO21_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 19. "GPIO20_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 18. "GPIO20_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 17. "GPIO20_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 16. "GPIO20_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 15. "GPIO19_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 14. "GPIO19_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 13. "GPIO19_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 12. "GPIO19_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 11. "GPIO18_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 10. "GPIO18_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 9. "GPIO18_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 8. "GPIO18_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 7. "GPIO17_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 6. "GPIO17_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 5. "GPIO17_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 4. "GPIO17_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 3. "GPIO16_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 2. "GPIO16_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 1. "GPIO16_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 0. "GPIO16_LEVEL_LOW" "0,1"
line.long 0x24 "PROC0_INTE3,Interrupt Enable for proc0"
bitfld.long 0x24 31. "GPIO31_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 30. "GPIO31_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 29. "GPIO31_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 28. "GPIO31_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 27. "GPIO30_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 26. "GPIO30_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 25. "GPIO30_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 24. "GPIO30_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 23. "GPIO29_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 22. "GPIO29_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 21. "GPIO29_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 20. "GPIO29_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 19. "GPIO28_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 18. "GPIO28_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 17. "GPIO28_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 16. "GPIO28_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 15. "GPIO27_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 14. "GPIO27_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 13. "GPIO27_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 12. "GPIO27_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 11. "GPIO26_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 10. "GPIO26_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 9. "GPIO26_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 8. "GPIO26_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 7. "GPIO25_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 6. "GPIO25_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 5. "GPIO25_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 4. "GPIO25_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 3. "GPIO24_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 2. "GPIO24_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 1. "GPIO24_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 0. "GPIO24_LEVEL_LOW" "0,1"
line.long 0x28 "PROC0_INTE4,Interrupt Enable for proc0"
bitfld.long 0x28 31. "GPIO39_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 30. "GPIO39_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 29. "GPIO39_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 28. "GPIO39_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 27. "GPIO38_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 26. "GPIO38_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 25. "GPIO38_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 24. "GPIO38_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 23. "GPIO37_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 22. "GPIO37_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 21. "GPIO37_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 20. "GPIO37_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 19. "GPIO36_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 18. "GPIO36_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 17. "GPIO36_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 16. "GPIO36_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 15. "GPIO35_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 14. "GPIO35_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 13. "GPIO35_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 12. "GPIO35_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 11. "GPIO34_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 10. "GPIO34_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 9. "GPIO34_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 8. "GPIO34_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 7. "GPIO33_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 6. "GPIO33_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 5. "GPIO33_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 4. "GPIO33_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 3. "GPIO32_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 2. "GPIO32_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 1. "GPIO32_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 0. "GPIO32_LEVEL_LOW" "0,1"
line.long 0x2C "PROC0_INTE5,Interrupt Enable for proc0"
bitfld.long 0x2C 31. "GPIO47_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 30. "GPIO47_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 29. "GPIO47_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 28. "GPIO47_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 27. "GPIO46_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 26. "GPIO46_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 25. "GPIO46_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 24. "GPIO46_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 23. "GPIO45_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 22. "GPIO45_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 21. "GPIO45_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 20. "GPIO45_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 19. "GPIO44_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 18. "GPIO44_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 17. "GPIO44_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 16. "GPIO44_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 15. "GPIO43_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 14. "GPIO43_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 13. "GPIO43_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 12. "GPIO43_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 11. "GPIO42_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 10. "GPIO42_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 9. "GPIO42_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 8. "GPIO42_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 7. "GPIO41_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 6. "GPIO41_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 5. "GPIO41_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 4. "GPIO41_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 3. "GPIO40_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 2. "GPIO40_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 1. "GPIO40_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 0. "GPIO40_LEVEL_LOW" "0,1"
line.long 0x30 "PROC0_INTF0,Interrupt Force for proc0"
bitfld.long 0x30 31. "GPIO7_EDGE_HIGH" "0,1"
newline
bitfld.long 0x30 30. "GPIO7_EDGE_LOW" "0,1"
newline
bitfld.long 0x30 29. "GPIO7_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x30 28. "GPIO7_LEVEL_LOW" "0,1"
newline
bitfld.long 0x30 27. "GPIO6_EDGE_HIGH" "0,1"
newline
bitfld.long 0x30 26. "GPIO6_EDGE_LOW" "0,1"
newline
bitfld.long 0x30 25. "GPIO6_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x30 24. "GPIO6_LEVEL_LOW" "0,1"
newline
bitfld.long 0x30 23. "GPIO5_EDGE_HIGH" "0,1"
newline
bitfld.long 0x30 22. "GPIO5_EDGE_LOW" "0,1"
newline
bitfld.long 0x30 21. "GPIO5_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x30 20. "GPIO5_LEVEL_LOW" "0,1"
newline
bitfld.long 0x30 19. "GPIO4_EDGE_HIGH" "0,1"
newline
bitfld.long 0x30 18. "GPIO4_EDGE_LOW" "0,1"
newline
bitfld.long 0x30 17. "GPIO4_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x30 16. "GPIO4_LEVEL_LOW" "0,1"
newline
bitfld.long 0x30 15. "GPIO3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x30 14. "GPIO3_EDGE_LOW" "0,1"
newline
bitfld.long 0x30 13. "GPIO3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x30 12. "GPIO3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x30 11. "GPIO2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x30 10. "GPIO2_EDGE_LOW" "0,1"
newline
bitfld.long 0x30 9. "GPIO2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x30 8. "GPIO2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x30 7. "GPIO1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x30 6. "GPIO1_EDGE_LOW" "0,1"
newline
bitfld.long 0x30 5. "GPIO1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x30 4. "GPIO1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x30 3. "GPIO0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x30 2. "GPIO0_EDGE_LOW" "0,1"
newline
bitfld.long 0x30 1. "GPIO0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x30 0. "GPIO0_LEVEL_LOW" "0,1"
line.long 0x34 "PROC0_INTF1,Interrupt Force for proc0"
bitfld.long 0x34 31. "GPIO15_EDGE_HIGH" "0,1"
newline
bitfld.long 0x34 30. "GPIO15_EDGE_LOW" "0,1"
newline
bitfld.long 0x34 29. "GPIO15_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x34 28. "GPIO15_LEVEL_LOW" "0,1"
newline
bitfld.long 0x34 27. "GPIO14_EDGE_HIGH" "0,1"
newline
bitfld.long 0x34 26. "GPIO14_EDGE_LOW" "0,1"
newline
bitfld.long 0x34 25. "GPIO14_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x34 24. "GPIO14_LEVEL_LOW" "0,1"
newline
bitfld.long 0x34 23. "GPIO13_EDGE_HIGH" "0,1"
newline
bitfld.long 0x34 22. "GPIO13_EDGE_LOW" "0,1"
newline
bitfld.long 0x34 21. "GPIO13_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x34 20. "GPIO13_LEVEL_LOW" "0,1"
newline
bitfld.long 0x34 19. "GPIO12_EDGE_HIGH" "0,1"
newline
bitfld.long 0x34 18. "GPIO12_EDGE_LOW" "0,1"
newline
bitfld.long 0x34 17. "GPIO12_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x34 16. "GPIO12_LEVEL_LOW" "0,1"
newline
bitfld.long 0x34 15. "GPIO11_EDGE_HIGH" "0,1"
newline
bitfld.long 0x34 14. "GPIO11_EDGE_LOW" "0,1"
newline
bitfld.long 0x34 13. "GPIO11_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x34 12. "GPIO11_LEVEL_LOW" "0,1"
newline
bitfld.long 0x34 11. "GPIO10_EDGE_HIGH" "0,1"
newline
bitfld.long 0x34 10. "GPIO10_EDGE_LOW" "0,1"
newline
bitfld.long 0x34 9. "GPIO10_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x34 8. "GPIO10_LEVEL_LOW" "0,1"
newline
bitfld.long 0x34 7. "GPIO9_EDGE_HIGH" "0,1"
newline
bitfld.long 0x34 6. "GPIO9_EDGE_LOW" "0,1"
newline
bitfld.long 0x34 5. "GPIO9_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x34 4. "GPIO9_LEVEL_LOW" "0,1"
newline
bitfld.long 0x34 3. "GPIO8_EDGE_HIGH" "0,1"
newline
bitfld.long 0x34 2. "GPIO8_EDGE_LOW" "0,1"
newline
bitfld.long 0x34 1. "GPIO8_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x34 0. "GPIO8_LEVEL_LOW" "0,1"
line.long 0x38 "PROC0_INTF2,Interrupt Force for proc0"
bitfld.long 0x38 31. "GPIO23_EDGE_HIGH" "0,1"
newline
bitfld.long 0x38 30. "GPIO23_EDGE_LOW" "0,1"
newline
bitfld.long 0x38 29. "GPIO23_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x38 28. "GPIO23_LEVEL_LOW" "0,1"
newline
bitfld.long 0x38 27. "GPIO22_EDGE_HIGH" "0,1"
newline
bitfld.long 0x38 26. "GPIO22_EDGE_LOW" "0,1"
newline
bitfld.long 0x38 25. "GPIO22_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x38 24. "GPIO22_LEVEL_LOW" "0,1"
newline
bitfld.long 0x38 23. "GPIO21_EDGE_HIGH" "0,1"
newline
bitfld.long 0x38 22. "GPIO21_EDGE_LOW" "0,1"
newline
bitfld.long 0x38 21. "GPIO21_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x38 20. "GPIO21_LEVEL_LOW" "0,1"
newline
bitfld.long 0x38 19. "GPIO20_EDGE_HIGH" "0,1"
newline
bitfld.long 0x38 18. "GPIO20_EDGE_LOW" "0,1"
newline
bitfld.long 0x38 17. "GPIO20_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x38 16. "GPIO20_LEVEL_LOW" "0,1"
newline
bitfld.long 0x38 15. "GPIO19_EDGE_HIGH" "0,1"
newline
bitfld.long 0x38 14. "GPIO19_EDGE_LOW" "0,1"
newline
bitfld.long 0x38 13. "GPIO19_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x38 12. "GPIO19_LEVEL_LOW" "0,1"
newline
bitfld.long 0x38 11. "GPIO18_EDGE_HIGH" "0,1"
newline
bitfld.long 0x38 10. "GPIO18_EDGE_LOW" "0,1"
newline
bitfld.long 0x38 9. "GPIO18_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x38 8. "GPIO18_LEVEL_LOW" "0,1"
newline
bitfld.long 0x38 7. "GPIO17_EDGE_HIGH" "0,1"
newline
bitfld.long 0x38 6. "GPIO17_EDGE_LOW" "0,1"
newline
bitfld.long 0x38 5. "GPIO17_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x38 4. "GPIO17_LEVEL_LOW" "0,1"
newline
bitfld.long 0x38 3. "GPIO16_EDGE_HIGH" "0,1"
newline
bitfld.long 0x38 2. "GPIO16_EDGE_LOW" "0,1"
newline
bitfld.long 0x38 1. "GPIO16_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x38 0. "GPIO16_LEVEL_LOW" "0,1"
line.long 0x3C "PROC0_INTF3,Interrupt Force for proc0"
bitfld.long 0x3C 31. "GPIO31_EDGE_HIGH" "0,1"
newline
bitfld.long 0x3C 30. "GPIO31_EDGE_LOW" "0,1"
newline
bitfld.long 0x3C 29. "GPIO31_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x3C 28. "GPIO31_LEVEL_LOW" "0,1"
newline
bitfld.long 0x3C 27. "GPIO30_EDGE_HIGH" "0,1"
newline
bitfld.long 0x3C 26. "GPIO30_EDGE_LOW" "0,1"
newline
bitfld.long 0x3C 25. "GPIO30_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x3C 24. "GPIO30_LEVEL_LOW" "0,1"
newline
bitfld.long 0x3C 23. "GPIO29_EDGE_HIGH" "0,1"
newline
bitfld.long 0x3C 22. "GPIO29_EDGE_LOW" "0,1"
newline
bitfld.long 0x3C 21. "GPIO29_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x3C 20. "GPIO29_LEVEL_LOW" "0,1"
newline
bitfld.long 0x3C 19. "GPIO28_EDGE_HIGH" "0,1"
newline
bitfld.long 0x3C 18. "GPIO28_EDGE_LOW" "0,1"
newline
bitfld.long 0x3C 17. "GPIO28_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x3C 16. "GPIO28_LEVEL_LOW" "0,1"
newline
bitfld.long 0x3C 15. "GPIO27_EDGE_HIGH" "0,1"
newline
bitfld.long 0x3C 14. "GPIO27_EDGE_LOW" "0,1"
newline
bitfld.long 0x3C 13. "GPIO27_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x3C 12. "GPIO27_LEVEL_LOW" "0,1"
newline
bitfld.long 0x3C 11. "GPIO26_EDGE_HIGH" "0,1"
newline
bitfld.long 0x3C 10. "GPIO26_EDGE_LOW" "0,1"
newline
bitfld.long 0x3C 9. "GPIO26_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x3C 8. "GPIO26_LEVEL_LOW" "0,1"
newline
bitfld.long 0x3C 7. "GPIO25_EDGE_HIGH" "0,1"
newline
bitfld.long 0x3C 6. "GPIO25_EDGE_LOW" "0,1"
newline
bitfld.long 0x3C 5. "GPIO25_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x3C 4. "GPIO25_LEVEL_LOW" "0,1"
newline
bitfld.long 0x3C 3. "GPIO24_EDGE_HIGH" "0,1"
newline
bitfld.long 0x3C 2. "GPIO24_EDGE_LOW" "0,1"
newline
bitfld.long 0x3C 1. "GPIO24_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x3C 0. "GPIO24_LEVEL_LOW" "0,1"
line.long 0x40 "PROC0_INTF4,Interrupt Force for proc0"
bitfld.long 0x40 31. "GPIO39_EDGE_HIGH" "0,1"
newline
bitfld.long 0x40 30. "GPIO39_EDGE_LOW" "0,1"
newline
bitfld.long 0x40 29. "GPIO39_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x40 28. "GPIO39_LEVEL_LOW" "0,1"
newline
bitfld.long 0x40 27. "GPIO38_EDGE_HIGH" "0,1"
newline
bitfld.long 0x40 26. "GPIO38_EDGE_LOW" "0,1"
newline
bitfld.long 0x40 25. "GPIO38_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x40 24. "GPIO38_LEVEL_LOW" "0,1"
newline
bitfld.long 0x40 23. "GPIO37_EDGE_HIGH" "0,1"
newline
bitfld.long 0x40 22. "GPIO37_EDGE_LOW" "0,1"
newline
bitfld.long 0x40 21. "GPIO37_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x40 20. "GPIO37_LEVEL_LOW" "0,1"
newline
bitfld.long 0x40 19. "GPIO36_EDGE_HIGH" "0,1"
newline
bitfld.long 0x40 18. "GPIO36_EDGE_LOW" "0,1"
newline
bitfld.long 0x40 17. "GPIO36_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x40 16. "GPIO36_LEVEL_LOW" "0,1"
newline
bitfld.long 0x40 15. "GPIO35_EDGE_HIGH" "0,1"
newline
bitfld.long 0x40 14. "GPIO35_EDGE_LOW" "0,1"
newline
bitfld.long 0x40 13. "GPIO35_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x40 12. "GPIO35_LEVEL_LOW" "0,1"
newline
bitfld.long 0x40 11. "GPIO34_EDGE_HIGH" "0,1"
newline
bitfld.long 0x40 10. "GPIO34_EDGE_LOW" "0,1"
newline
bitfld.long 0x40 9. "GPIO34_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x40 8. "GPIO34_LEVEL_LOW" "0,1"
newline
bitfld.long 0x40 7. "GPIO33_EDGE_HIGH" "0,1"
newline
bitfld.long 0x40 6. "GPIO33_EDGE_LOW" "0,1"
newline
bitfld.long 0x40 5. "GPIO33_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x40 4. "GPIO33_LEVEL_LOW" "0,1"
newline
bitfld.long 0x40 3. "GPIO32_EDGE_HIGH" "0,1"
newline
bitfld.long 0x40 2. "GPIO32_EDGE_LOW" "0,1"
newline
bitfld.long 0x40 1. "GPIO32_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x40 0. "GPIO32_LEVEL_LOW" "0,1"
line.long 0x44 "PROC0_INTF5,Interrupt Force for proc0"
bitfld.long 0x44 31. "GPIO47_EDGE_HIGH" "0,1"
newline
bitfld.long 0x44 30. "GPIO47_EDGE_LOW" "0,1"
newline
bitfld.long 0x44 29. "GPIO47_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x44 28. "GPIO47_LEVEL_LOW" "0,1"
newline
bitfld.long 0x44 27. "GPIO46_EDGE_HIGH" "0,1"
newline
bitfld.long 0x44 26. "GPIO46_EDGE_LOW" "0,1"
newline
bitfld.long 0x44 25. "GPIO46_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x44 24. "GPIO46_LEVEL_LOW" "0,1"
newline
bitfld.long 0x44 23. "GPIO45_EDGE_HIGH" "0,1"
newline
bitfld.long 0x44 22. "GPIO45_EDGE_LOW" "0,1"
newline
bitfld.long 0x44 21. "GPIO45_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x44 20. "GPIO45_LEVEL_LOW" "0,1"
newline
bitfld.long 0x44 19. "GPIO44_EDGE_HIGH" "0,1"
newline
bitfld.long 0x44 18. "GPIO44_EDGE_LOW" "0,1"
newline
bitfld.long 0x44 17. "GPIO44_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x44 16. "GPIO44_LEVEL_LOW" "0,1"
newline
bitfld.long 0x44 15. "GPIO43_EDGE_HIGH" "0,1"
newline
bitfld.long 0x44 14. "GPIO43_EDGE_LOW" "0,1"
newline
bitfld.long 0x44 13. "GPIO43_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x44 12. "GPIO43_LEVEL_LOW" "0,1"
newline
bitfld.long 0x44 11. "GPIO42_EDGE_HIGH" "0,1"
newline
bitfld.long 0x44 10. "GPIO42_EDGE_LOW" "0,1"
newline
bitfld.long 0x44 9. "GPIO42_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x44 8. "GPIO42_LEVEL_LOW" "0,1"
newline
bitfld.long 0x44 7. "GPIO41_EDGE_HIGH" "0,1"
newline
bitfld.long 0x44 6. "GPIO41_EDGE_LOW" "0,1"
newline
bitfld.long 0x44 5. "GPIO41_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x44 4. "GPIO41_LEVEL_LOW" "0,1"
newline
bitfld.long 0x44 3. "GPIO40_EDGE_HIGH" "0,1"
newline
bitfld.long 0x44 2. "GPIO40_EDGE_LOW" "0,1"
newline
bitfld.long 0x44 1. "GPIO40_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x44 0. "GPIO40_LEVEL_LOW" "0,1"
rgroup.long 0x278++0x17
line.long 0x0 "PROC0_INTS0,Interrupt status after masking & forcing for proc0"
bitfld.long 0x0 31. "GPIO7_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 30. "GPIO7_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 29. "GPIO7_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 28. "GPIO7_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 27. "GPIO6_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 26. "GPIO6_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 25. "GPIO6_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 24. "GPIO6_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 23. "GPIO5_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 22. "GPIO5_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 21. "GPIO5_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 20. "GPIO5_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 19. "GPIO4_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 18. "GPIO4_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 17. "GPIO4_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 16. "GPIO4_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 15. "GPIO3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 14. "GPIO3_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 13. "GPIO3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 12. "GPIO3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 11. "GPIO2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 10. "GPIO2_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 9. "GPIO2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 8. "GPIO2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 7. "GPIO1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 6. "GPIO1_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 5. "GPIO1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 4. "GPIO1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 3. "GPIO0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 2. "GPIO0_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 1. "GPIO0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 0. "GPIO0_LEVEL_LOW" "0,1"
line.long 0x4 "PROC0_INTS1,Interrupt status after masking & forcing for proc0"
bitfld.long 0x4 31. "GPIO15_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 30. "GPIO15_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 29. "GPIO15_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 28. "GPIO15_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 27. "GPIO14_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 26. "GPIO14_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 25. "GPIO14_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 24. "GPIO14_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 23. "GPIO13_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 22. "GPIO13_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 21. "GPIO13_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 20. "GPIO13_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 19. "GPIO12_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 18. "GPIO12_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 17. "GPIO12_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 16. "GPIO12_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 15. "GPIO11_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 14. "GPIO11_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 13. "GPIO11_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 12. "GPIO11_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 11. "GPIO10_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 10. "GPIO10_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 9. "GPIO10_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 8. "GPIO10_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 7. "GPIO9_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 6. "GPIO9_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 5. "GPIO9_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 4. "GPIO9_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 3. "GPIO8_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 2. "GPIO8_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 1. "GPIO8_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 0. "GPIO8_LEVEL_LOW" "0,1"
line.long 0x8 "PROC0_INTS2,Interrupt status after masking & forcing for proc0"
bitfld.long 0x8 31. "GPIO23_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 30. "GPIO23_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 29. "GPIO23_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 28. "GPIO23_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 27. "GPIO22_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 26. "GPIO22_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 25. "GPIO22_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 24. "GPIO22_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 23. "GPIO21_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 22. "GPIO21_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 21. "GPIO21_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 20. "GPIO21_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 19. "GPIO20_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 18. "GPIO20_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 17. "GPIO20_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 16. "GPIO20_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 15. "GPIO19_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 14. "GPIO19_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 13. "GPIO19_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 12. "GPIO19_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 11. "GPIO18_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 10. "GPIO18_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 9. "GPIO18_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 8. "GPIO18_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 7. "GPIO17_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 6. "GPIO17_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 5. "GPIO17_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 4. "GPIO17_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 3. "GPIO16_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 2. "GPIO16_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 1. "GPIO16_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 0. "GPIO16_LEVEL_LOW" "0,1"
line.long 0xC "PROC0_INTS3,Interrupt status after masking & forcing for proc0"
bitfld.long 0xC 31. "GPIO31_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 30. "GPIO31_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 29. "GPIO31_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 28. "GPIO31_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 27. "GPIO30_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 26. "GPIO30_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 25. "GPIO30_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 24. "GPIO30_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 23. "GPIO29_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 22. "GPIO29_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 21. "GPIO29_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 20. "GPIO29_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 19. "GPIO28_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 18. "GPIO28_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 17. "GPIO28_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 16. "GPIO28_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 15. "GPIO27_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 14. "GPIO27_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 13. "GPIO27_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 12. "GPIO27_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 11. "GPIO26_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 10. "GPIO26_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 9. "GPIO26_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 8. "GPIO26_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 7. "GPIO25_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 6. "GPIO25_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 5. "GPIO25_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 4. "GPIO25_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 3. "GPIO24_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 2. "GPIO24_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 1. "GPIO24_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 0. "GPIO24_LEVEL_LOW" "0,1"
line.long 0x10 "PROC0_INTS4,Interrupt status after masking & forcing for proc0"
bitfld.long 0x10 31. "GPIO39_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 30. "GPIO39_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 29. "GPIO39_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 28. "GPIO39_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 27. "GPIO38_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 26. "GPIO38_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 25. "GPIO38_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 24. "GPIO38_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 23. "GPIO37_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 22. "GPIO37_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 21. "GPIO37_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 20. "GPIO37_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 19. "GPIO36_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 18. "GPIO36_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 17. "GPIO36_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 16. "GPIO36_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 15. "GPIO35_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 14. "GPIO35_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 13. "GPIO35_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 12. "GPIO35_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 11. "GPIO34_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 10. "GPIO34_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 9. "GPIO34_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 8. "GPIO34_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 7. "GPIO33_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 6. "GPIO33_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 5. "GPIO33_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 4. "GPIO33_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 3. "GPIO32_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 2. "GPIO32_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 1. "GPIO32_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 0. "GPIO32_LEVEL_LOW" "0,1"
line.long 0x14 "PROC0_INTS5,Interrupt status after masking & forcing for proc0"
bitfld.long 0x14 31. "GPIO47_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 30. "GPIO47_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 29. "GPIO47_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 28. "GPIO47_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 27. "GPIO46_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 26. "GPIO46_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 25. "GPIO46_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 24. "GPIO46_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 23. "GPIO45_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 22. "GPIO45_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 21. "GPIO45_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 20. "GPIO45_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 19. "GPIO44_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 18. "GPIO44_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 17. "GPIO44_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 16. "GPIO44_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 15. "GPIO43_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 14. "GPIO43_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 13. "GPIO43_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 12. "GPIO43_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 11. "GPIO42_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 10. "GPIO42_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 9. "GPIO42_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 8. "GPIO42_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 7. "GPIO41_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 6. "GPIO41_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 5. "GPIO41_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 4. "GPIO41_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 3. "GPIO40_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 2. "GPIO40_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 1. "GPIO40_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 0. "GPIO40_LEVEL_LOW" "0,1"
group.long 0x290++0x2F
line.long 0x0 "PROC1_INTE0,Interrupt Enable for proc1"
bitfld.long 0x0 31. "GPIO7_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 30. "GPIO7_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 29. "GPIO7_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 28. "GPIO7_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 27. "GPIO6_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 26. "GPIO6_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 25. "GPIO6_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 24. "GPIO6_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 23. "GPIO5_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 22. "GPIO5_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 21. "GPIO5_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 20. "GPIO5_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 19. "GPIO4_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 18. "GPIO4_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 17. "GPIO4_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 16. "GPIO4_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 15. "GPIO3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 14. "GPIO3_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 13. "GPIO3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 12. "GPIO3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 11. "GPIO2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 10. "GPIO2_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 9. "GPIO2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 8. "GPIO2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 7. "GPIO1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 6. "GPIO1_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 5. "GPIO1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 4. "GPIO1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 3. "GPIO0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 2. "GPIO0_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 1. "GPIO0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 0. "GPIO0_LEVEL_LOW" "0,1"
line.long 0x4 "PROC1_INTE1,Interrupt Enable for proc1"
bitfld.long 0x4 31. "GPIO15_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 30. "GPIO15_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 29. "GPIO15_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 28. "GPIO15_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 27. "GPIO14_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 26. "GPIO14_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 25. "GPIO14_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 24. "GPIO14_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 23. "GPIO13_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 22. "GPIO13_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 21. "GPIO13_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 20. "GPIO13_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 19. "GPIO12_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 18. "GPIO12_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 17. "GPIO12_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 16. "GPIO12_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 15. "GPIO11_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 14. "GPIO11_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 13. "GPIO11_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 12. "GPIO11_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 11. "GPIO10_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 10. "GPIO10_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 9. "GPIO10_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 8. "GPIO10_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 7. "GPIO9_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 6. "GPIO9_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 5. "GPIO9_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 4. "GPIO9_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 3. "GPIO8_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 2. "GPIO8_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 1. "GPIO8_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 0. "GPIO8_LEVEL_LOW" "0,1"
line.long 0x8 "PROC1_INTE2,Interrupt Enable for proc1"
bitfld.long 0x8 31. "GPIO23_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 30. "GPIO23_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 29. "GPIO23_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 28. "GPIO23_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 27. "GPIO22_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 26. "GPIO22_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 25. "GPIO22_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 24. "GPIO22_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 23. "GPIO21_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 22. "GPIO21_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 21. "GPIO21_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 20. "GPIO21_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 19. "GPIO20_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 18. "GPIO20_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 17. "GPIO20_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 16. "GPIO20_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 15. "GPIO19_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 14. "GPIO19_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 13. "GPIO19_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 12. "GPIO19_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 11. "GPIO18_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 10. "GPIO18_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 9. "GPIO18_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 8. "GPIO18_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 7. "GPIO17_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 6. "GPIO17_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 5. "GPIO17_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 4. "GPIO17_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 3. "GPIO16_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 2. "GPIO16_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 1. "GPIO16_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 0. "GPIO16_LEVEL_LOW" "0,1"
line.long 0xC "PROC1_INTE3,Interrupt Enable for proc1"
bitfld.long 0xC 31. "GPIO31_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 30. "GPIO31_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 29. "GPIO31_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 28. "GPIO31_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 27. "GPIO30_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 26. "GPIO30_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 25. "GPIO30_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 24. "GPIO30_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 23. "GPIO29_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 22. "GPIO29_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 21. "GPIO29_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 20. "GPIO29_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 19. "GPIO28_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 18. "GPIO28_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 17. "GPIO28_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 16. "GPIO28_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 15. "GPIO27_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 14. "GPIO27_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 13. "GPIO27_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 12. "GPIO27_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 11. "GPIO26_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 10. "GPIO26_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 9. "GPIO26_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 8. "GPIO26_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 7. "GPIO25_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 6. "GPIO25_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 5. "GPIO25_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 4. "GPIO25_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 3. "GPIO24_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 2. "GPIO24_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 1. "GPIO24_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 0. "GPIO24_LEVEL_LOW" "0,1"
line.long 0x10 "PROC1_INTE4,Interrupt Enable for proc1"
bitfld.long 0x10 31. "GPIO39_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 30. "GPIO39_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 29. "GPIO39_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 28. "GPIO39_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 27. "GPIO38_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 26. "GPIO38_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 25. "GPIO38_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 24. "GPIO38_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 23. "GPIO37_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 22. "GPIO37_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 21. "GPIO37_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 20. "GPIO37_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 19. "GPIO36_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 18. "GPIO36_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 17. "GPIO36_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 16. "GPIO36_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 15. "GPIO35_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 14. "GPIO35_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 13. "GPIO35_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 12. "GPIO35_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 11. "GPIO34_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 10. "GPIO34_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 9. "GPIO34_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 8. "GPIO34_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 7. "GPIO33_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 6. "GPIO33_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 5. "GPIO33_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 4. "GPIO33_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 3. "GPIO32_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 2. "GPIO32_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 1. "GPIO32_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 0. "GPIO32_LEVEL_LOW" "0,1"
line.long 0x14 "PROC1_INTE5,Interrupt Enable for proc1"
bitfld.long 0x14 31. "GPIO47_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 30. "GPIO47_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 29. "GPIO47_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 28. "GPIO47_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 27. "GPIO46_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 26. "GPIO46_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 25. "GPIO46_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 24. "GPIO46_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 23. "GPIO45_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 22. "GPIO45_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 21. "GPIO45_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 20. "GPIO45_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 19. "GPIO44_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 18. "GPIO44_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 17. "GPIO44_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 16. "GPIO44_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 15. "GPIO43_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 14. "GPIO43_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 13. "GPIO43_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 12. "GPIO43_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 11. "GPIO42_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 10. "GPIO42_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 9. "GPIO42_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 8. "GPIO42_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 7. "GPIO41_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 6. "GPIO41_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 5. "GPIO41_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 4. "GPIO41_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 3. "GPIO40_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 2. "GPIO40_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 1. "GPIO40_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 0. "GPIO40_LEVEL_LOW" "0,1"
line.long 0x18 "PROC1_INTF0,Interrupt Force for proc1"
bitfld.long 0x18 31. "GPIO7_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 30. "GPIO7_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 29. "GPIO7_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 28. "GPIO7_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 27. "GPIO6_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 26. "GPIO6_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 25. "GPIO6_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 24. "GPIO6_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 23. "GPIO5_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 22. "GPIO5_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 21. "GPIO5_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 20. "GPIO5_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 19. "GPIO4_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 18. "GPIO4_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 17. "GPIO4_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 16. "GPIO4_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 15. "GPIO3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 14. "GPIO3_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 13. "GPIO3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 12. "GPIO3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 11. "GPIO2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 10. "GPIO2_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 9. "GPIO2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 8. "GPIO2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 7. "GPIO1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 6. "GPIO1_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 5. "GPIO1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 4. "GPIO1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 3. "GPIO0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 2. "GPIO0_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 1. "GPIO0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 0. "GPIO0_LEVEL_LOW" "0,1"
line.long 0x1C "PROC1_INTF1,Interrupt Force for proc1"
bitfld.long 0x1C 31. "GPIO15_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 30. "GPIO15_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 29. "GPIO15_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 28. "GPIO15_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 27. "GPIO14_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 26. "GPIO14_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 25. "GPIO14_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 24. "GPIO14_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 23. "GPIO13_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 22. "GPIO13_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 21. "GPIO13_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 20. "GPIO13_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 19. "GPIO12_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 18. "GPIO12_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 17. "GPIO12_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 16. "GPIO12_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 15. "GPIO11_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 14. "GPIO11_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 13. "GPIO11_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 12. "GPIO11_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 11. "GPIO10_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 10. "GPIO10_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 9. "GPIO10_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 8. "GPIO10_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 7. "GPIO9_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 6. "GPIO9_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 5. "GPIO9_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 4. "GPIO9_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 3. "GPIO8_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 2. "GPIO8_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 1. "GPIO8_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 0. "GPIO8_LEVEL_LOW" "0,1"
line.long 0x20 "PROC1_INTF2,Interrupt Force for proc1"
bitfld.long 0x20 31. "GPIO23_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 30. "GPIO23_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 29. "GPIO23_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 28. "GPIO23_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 27. "GPIO22_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 26. "GPIO22_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 25. "GPIO22_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 24. "GPIO22_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 23. "GPIO21_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 22. "GPIO21_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 21. "GPIO21_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 20. "GPIO21_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 19. "GPIO20_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 18. "GPIO20_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 17. "GPIO20_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 16. "GPIO20_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 15. "GPIO19_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 14. "GPIO19_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 13. "GPIO19_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 12. "GPIO19_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 11. "GPIO18_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 10. "GPIO18_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 9. "GPIO18_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 8. "GPIO18_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 7. "GPIO17_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 6. "GPIO17_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 5. "GPIO17_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 4. "GPIO17_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 3. "GPIO16_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 2. "GPIO16_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 1. "GPIO16_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 0. "GPIO16_LEVEL_LOW" "0,1"
line.long 0x24 "PROC1_INTF3,Interrupt Force for proc1"
bitfld.long 0x24 31. "GPIO31_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 30. "GPIO31_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 29. "GPIO31_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 28. "GPIO31_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 27. "GPIO30_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 26. "GPIO30_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 25. "GPIO30_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 24. "GPIO30_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 23. "GPIO29_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 22. "GPIO29_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 21. "GPIO29_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 20. "GPIO29_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 19. "GPIO28_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 18. "GPIO28_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 17. "GPIO28_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 16. "GPIO28_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 15. "GPIO27_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 14. "GPIO27_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 13. "GPIO27_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 12. "GPIO27_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 11. "GPIO26_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 10. "GPIO26_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 9. "GPIO26_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 8. "GPIO26_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 7. "GPIO25_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 6. "GPIO25_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 5. "GPIO25_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 4. "GPIO25_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 3. "GPIO24_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 2. "GPIO24_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 1. "GPIO24_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 0. "GPIO24_LEVEL_LOW" "0,1"
line.long 0x28 "PROC1_INTF4,Interrupt Force for proc1"
bitfld.long 0x28 31. "GPIO39_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 30. "GPIO39_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 29. "GPIO39_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 28. "GPIO39_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 27. "GPIO38_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 26. "GPIO38_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 25. "GPIO38_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 24. "GPIO38_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 23. "GPIO37_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 22. "GPIO37_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 21. "GPIO37_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 20. "GPIO37_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 19. "GPIO36_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 18. "GPIO36_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 17. "GPIO36_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 16. "GPIO36_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 15. "GPIO35_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 14. "GPIO35_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 13. "GPIO35_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 12. "GPIO35_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 11. "GPIO34_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 10. "GPIO34_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 9. "GPIO34_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 8. "GPIO34_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 7. "GPIO33_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 6. "GPIO33_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 5. "GPIO33_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 4. "GPIO33_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 3. "GPIO32_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 2. "GPIO32_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 1. "GPIO32_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 0. "GPIO32_LEVEL_LOW" "0,1"
line.long 0x2C "PROC1_INTF5,Interrupt Force for proc1"
bitfld.long 0x2C 31. "GPIO47_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 30. "GPIO47_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 29. "GPIO47_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 28. "GPIO47_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 27. "GPIO46_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 26. "GPIO46_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 25. "GPIO46_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 24. "GPIO46_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 23. "GPIO45_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 22. "GPIO45_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 21. "GPIO45_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 20. "GPIO45_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 19. "GPIO44_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 18. "GPIO44_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 17. "GPIO44_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 16. "GPIO44_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 15. "GPIO43_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 14. "GPIO43_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 13. "GPIO43_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 12. "GPIO43_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 11. "GPIO42_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 10. "GPIO42_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 9. "GPIO42_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 8. "GPIO42_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 7. "GPIO41_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 6. "GPIO41_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 5. "GPIO41_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 4. "GPIO41_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 3. "GPIO40_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 2. "GPIO40_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 1. "GPIO40_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 0. "GPIO40_LEVEL_LOW" "0,1"
rgroup.long 0x2C0++0x17
line.long 0x0 "PROC1_INTS0,Interrupt status after masking & forcing for proc1"
bitfld.long 0x0 31. "GPIO7_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 30. "GPIO7_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 29. "GPIO7_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 28. "GPIO7_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 27. "GPIO6_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 26. "GPIO6_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 25. "GPIO6_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 24. "GPIO6_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 23. "GPIO5_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 22. "GPIO5_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 21. "GPIO5_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 20. "GPIO5_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 19. "GPIO4_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 18. "GPIO4_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 17. "GPIO4_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 16. "GPIO4_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 15. "GPIO3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 14. "GPIO3_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 13. "GPIO3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 12. "GPIO3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 11. "GPIO2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 10. "GPIO2_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 9. "GPIO2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 8. "GPIO2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 7. "GPIO1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 6. "GPIO1_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 5. "GPIO1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 4. "GPIO1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 3. "GPIO0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 2. "GPIO0_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 1. "GPIO0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 0. "GPIO0_LEVEL_LOW" "0,1"
line.long 0x4 "PROC1_INTS1,Interrupt status after masking & forcing for proc1"
bitfld.long 0x4 31. "GPIO15_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 30. "GPIO15_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 29. "GPIO15_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 28. "GPIO15_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 27. "GPIO14_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 26. "GPIO14_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 25. "GPIO14_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 24. "GPIO14_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 23. "GPIO13_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 22. "GPIO13_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 21. "GPIO13_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 20. "GPIO13_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 19. "GPIO12_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 18. "GPIO12_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 17. "GPIO12_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 16. "GPIO12_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 15. "GPIO11_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 14. "GPIO11_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 13. "GPIO11_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 12. "GPIO11_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 11. "GPIO10_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 10. "GPIO10_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 9. "GPIO10_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 8. "GPIO10_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 7. "GPIO9_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 6. "GPIO9_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 5. "GPIO9_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 4. "GPIO9_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 3. "GPIO8_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 2. "GPIO8_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 1. "GPIO8_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 0. "GPIO8_LEVEL_LOW" "0,1"
line.long 0x8 "PROC1_INTS2,Interrupt status after masking & forcing for proc1"
bitfld.long 0x8 31. "GPIO23_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 30. "GPIO23_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 29. "GPIO23_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 28. "GPIO23_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 27. "GPIO22_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 26. "GPIO22_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 25. "GPIO22_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 24. "GPIO22_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 23. "GPIO21_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 22. "GPIO21_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 21. "GPIO21_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 20. "GPIO21_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 19. "GPIO20_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 18. "GPIO20_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 17. "GPIO20_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 16. "GPIO20_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 15. "GPIO19_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 14. "GPIO19_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 13. "GPIO19_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 12. "GPIO19_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 11. "GPIO18_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 10. "GPIO18_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 9. "GPIO18_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 8. "GPIO18_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 7. "GPIO17_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 6. "GPIO17_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 5. "GPIO17_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 4. "GPIO17_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 3. "GPIO16_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 2. "GPIO16_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 1. "GPIO16_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 0. "GPIO16_LEVEL_LOW" "0,1"
line.long 0xC "PROC1_INTS3,Interrupt status after masking & forcing for proc1"
bitfld.long 0xC 31. "GPIO31_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 30. "GPIO31_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 29. "GPIO31_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 28. "GPIO31_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 27. "GPIO30_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 26. "GPIO30_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 25. "GPIO30_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 24. "GPIO30_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 23. "GPIO29_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 22. "GPIO29_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 21. "GPIO29_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 20. "GPIO29_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 19. "GPIO28_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 18. "GPIO28_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 17. "GPIO28_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 16. "GPIO28_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 15. "GPIO27_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 14. "GPIO27_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 13. "GPIO27_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 12. "GPIO27_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 11. "GPIO26_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 10. "GPIO26_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 9. "GPIO26_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 8. "GPIO26_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 7. "GPIO25_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 6. "GPIO25_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 5. "GPIO25_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 4. "GPIO25_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 3. "GPIO24_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 2. "GPIO24_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 1. "GPIO24_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 0. "GPIO24_LEVEL_LOW" "0,1"
line.long 0x10 "PROC1_INTS4,Interrupt status after masking & forcing for proc1"
bitfld.long 0x10 31. "GPIO39_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 30. "GPIO39_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 29. "GPIO39_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 28. "GPIO39_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 27. "GPIO38_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 26. "GPIO38_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 25. "GPIO38_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 24. "GPIO38_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 23. "GPIO37_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 22. "GPIO37_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 21. "GPIO37_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 20. "GPIO37_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 19. "GPIO36_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 18. "GPIO36_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 17. "GPIO36_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 16. "GPIO36_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 15. "GPIO35_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 14. "GPIO35_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 13. "GPIO35_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 12. "GPIO35_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 11. "GPIO34_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 10. "GPIO34_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 9. "GPIO34_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 8. "GPIO34_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 7. "GPIO33_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 6. "GPIO33_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 5. "GPIO33_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 4. "GPIO33_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 3. "GPIO32_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 2. "GPIO32_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 1. "GPIO32_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 0. "GPIO32_LEVEL_LOW" "0,1"
line.long 0x14 "PROC1_INTS5,Interrupt status after masking & forcing for proc1"
bitfld.long 0x14 31. "GPIO47_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 30. "GPIO47_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 29. "GPIO47_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 28. "GPIO47_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 27. "GPIO46_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 26. "GPIO46_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 25. "GPIO46_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 24. "GPIO46_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 23. "GPIO45_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 22. "GPIO45_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 21. "GPIO45_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 20. "GPIO45_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 19. "GPIO44_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 18. "GPIO44_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 17. "GPIO44_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 16. "GPIO44_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 15. "GPIO43_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 14. "GPIO43_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 13. "GPIO43_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 12. "GPIO43_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 11. "GPIO42_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 10. "GPIO42_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 9. "GPIO42_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 8. "GPIO42_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 7. "GPIO41_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 6. "GPIO41_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 5. "GPIO41_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 4. "GPIO41_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 3. "GPIO40_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 2. "GPIO40_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 1. "GPIO40_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 0. "GPIO40_LEVEL_LOW" "0,1"
group.long 0x2D8++0x2F
line.long 0x0 "DORMANT_WAKE_INTE0,Interrupt Enable for dormant_wake"
bitfld.long 0x0 31. "GPIO7_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 30. "GPIO7_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 29. "GPIO7_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 28. "GPIO7_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 27. "GPIO6_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 26. "GPIO6_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 25. "GPIO6_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 24. "GPIO6_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 23. "GPIO5_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 22. "GPIO5_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 21. "GPIO5_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 20. "GPIO5_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 19. "GPIO4_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 18. "GPIO4_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 17. "GPIO4_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 16. "GPIO4_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 15. "GPIO3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 14. "GPIO3_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 13. "GPIO3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 12. "GPIO3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 11. "GPIO2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 10. "GPIO2_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 9. "GPIO2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 8. "GPIO2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 7. "GPIO1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 6. "GPIO1_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 5. "GPIO1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 4. "GPIO1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 3. "GPIO0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 2. "GPIO0_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 1. "GPIO0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 0. "GPIO0_LEVEL_LOW" "0,1"
line.long 0x4 "DORMANT_WAKE_INTE1,Interrupt Enable for dormant_wake"
bitfld.long 0x4 31. "GPIO15_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 30. "GPIO15_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 29. "GPIO15_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 28. "GPIO15_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 27. "GPIO14_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 26. "GPIO14_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 25. "GPIO14_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 24. "GPIO14_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 23. "GPIO13_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 22. "GPIO13_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 21. "GPIO13_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 20. "GPIO13_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 19. "GPIO12_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 18. "GPIO12_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 17. "GPIO12_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 16. "GPIO12_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 15. "GPIO11_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 14. "GPIO11_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 13. "GPIO11_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 12. "GPIO11_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 11. "GPIO10_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 10. "GPIO10_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 9. "GPIO10_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 8. "GPIO10_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 7. "GPIO9_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 6. "GPIO9_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 5. "GPIO9_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 4. "GPIO9_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 3. "GPIO8_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 2. "GPIO8_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 1. "GPIO8_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 0. "GPIO8_LEVEL_LOW" "0,1"
line.long 0x8 "DORMANT_WAKE_INTE2,Interrupt Enable for dormant_wake"
bitfld.long 0x8 31. "GPIO23_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 30. "GPIO23_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 29. "GPIO23_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 28. "GPIO23_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 27. "GPIO22_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 26. "GPIO22_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 25. "GPIO22_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 24. "GPIO22_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 23. "GPIO21_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 22. "GPIO21_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 21. "GPIO21_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 20. "GPIO21_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 19. "GPIO20_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 18. "GPIO20_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 17. "GPIO20_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 16. "GPIO20_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 15. "GPIO19_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 14. "GPIO19_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 13. "GPIO19_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 12. "GPIO19_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 11. "GPIO18_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 10. "GPIO18_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 9. "GPIO18_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 8. "GPIO18_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 7. "GPIO17_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 6. "GPIO17_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 5. "GPIO17_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 4. "GPIO17_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 3. "GPIO16_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 2. "GPIO16_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 1. "GPIO16_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 0. "GPIO16_LEVEL_LOW" "0,1"
line.long 0xC "DORMANT_WAKE_INTE3,Interrupt Enable for dormant_wake"
bitfld.long 0xC 31. "GPIO31_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 30. "GPIO31_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 29. "GPIO31_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 28. "GPIO31_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 27. "GPIO30_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 26. "GPIO30_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 25. "GPIO30_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 24. "GPIO30_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 23. "GPIO29_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 22. "GPIO29_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 21. "GPIO29_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 20. "GPIO29_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 19. "GPIO28_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 18. "GPIO28_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 17. "GPIO28_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 16. "GPIO28_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 15. "GPIO27_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 14. "GPIO27_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 13. "GPIO27_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 12. "GPIO27_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 11. "GPIO26_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 10. "GPIO26_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 9. "GPIO26_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 8. "GPIO26_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 7. "GPIO25_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 6. "GPIO25_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 5. "GPIO25_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 4. "GPIO25_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 3. "GPIO24_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 2. "GPIO24_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 1. "GPIO24_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 0. "GPIO24_LEVEL_LOW" "0,1"
line.long 0x10 "DORMANT_WAKE_INTE4,Interrupt Enable for dormant_wake"
bitfld.long 0x10 31. "GPIO39_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 30. "GPIO39_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 29. "GPIO39_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 28. "GPIO39_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 27. "GPIO38_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 26. "GPIO38_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 25. "GPIO38_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 24. "GPIO38_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 23. "GPIO37_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 22. "GPIO37_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 21. "GPIO37_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 20. "GPIO37_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 19. "GPIO36_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 18. "GPIO36_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 17. "GPIO36_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 16. "GPIO36_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 15. "GPIO35_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 14. "GPIO35_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 13. "GPIO35_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 12. "GPIO35_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 11. "GPIO34_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 10. "GPIO34_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 9. "GPIO34_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 8. "GPIO34_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 7. "GPIO33_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 6. "GPIO33_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 5. "GPIO33_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 4. "GPIO33_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 3. "GPIO32_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 2. "GPIO32_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 1. "GPIO32_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 0. "GPIO32_LEVEL_LOW" "0,1"
line.long 0x14 "DORMANT_WAKE_INTE5,Interrupt Enable for dormant_wake"
bitfld.long 0x14 31. "GPIO47_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 30. "GPIO47_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 29. "GPIO47_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 28. "GPIO47_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 27. "GPIO46_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 26. "GPIO46_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 25. "GPIO46_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 24. "GPIO46_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 23. "GPIO45_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 22. "GPIO45_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 21. "GPIO45_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 20. "GPIO45_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 19. "GPIO44_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 18. "GPIO44_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 17. "GPIO44_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 16. "GPIO44_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 15. "GPIO43_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 14. "GPIO43_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 13. "GPIO43_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 12. "GPIO43_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 11. "GPIO42_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 10. "GPIO42_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 9. "GPIO42_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 8. "GPIO42_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 7. "GPIO41_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 6. "GPIO41_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 5. "GPIO41_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 4. "GPIO41_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 3. "GPIO40_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 2. "GPIO40_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 1. "GPIO40_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 0. "GPIO40_LEVEL_LOW" "0,1"
line.long 0x18 "DORMANT_WAKE_INTF0,Interrupt Force for dormant_wake"
bitfld.long 0x18 31. "GPIO7_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 30. "GPIO7_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 29. "GPIO7_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 28. "GPIO7_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 27. "GPIO6_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 26. "GPIO6_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 25. "GPIO6_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 24. "GPIO6_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 23. "GPIO5_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 22. "GPIO5_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 21. "GPIO5_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 20. "GPIO5_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 19. "GPIO4_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 18. "GPIO4_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 17. "GPIO4_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 16. "GPIO4_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 15. "GPIO3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 14. "GPIO3_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 13. "GPIO3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 12. "GPIO3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 11. "GPIO2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 10. "GPIO2_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 9. "GPIO2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 8. "GPIO2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 7. "GPIO1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 6. "GPIO1_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 5. "GPIO1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 4. "GPIO1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x18 3. "GPIO0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x18 2. "GPIO0_EDGE_LOW" "0,1"
newline
bitfld.long 0x18 1. "GPIO0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x18 0. "GPIO0_LEVEL_LOW" "0,1"
line.long 0x1C "DORMANT_WAKE_INTF1,Interrupt Force for dormant_wake"
bitfld.long 0x1C 31. "GPIO15_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 30. "GPIO15_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 29. "GPIO15_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 28. "GPIO15_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 27. "GPIO14_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 26. "GPIO14_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 25. "GPIO14_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 24. "GPIO14_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 23. "GPIO13_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 22. "GPIO13_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 21. "GPIO13_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 20. "GPIO13_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 19. "GPIO12_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 18. "GPIO12_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 17. "GPIO12_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 16. "GPIO12_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 15. "GPIO11_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 14. "GPIO11_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 13. "GPIO11_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 12. "GPIO11_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 11. "GPIO10_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 10. "GPIO10_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 9. "GPIO10_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 8. "GPIO10_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 7. "GPIO9_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 6. "GPIO9_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 5. "GPIO9_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 4. "GPIO9_LEVEL_LOW" "0,1"
newline
bitfld.long 0x1C 3. "GPIO8_EDGE_HIGH" "0,1"
newline
bitfld.long 0x1C 2. "GPIO8_EDGE_LOW" "0,1"
newline
bitfld.long 0x1C 1. "GPIO8_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x1C 0. "GPIO8_LEVEL_LOW" "0,1"
line.long 0x20 "DORMANT_WAKE_INTF2,Interrupt Force for dormant_wake"
bitfld.long 0x20 31. "GPIO23_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 30. "GPIO23_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 29. "GPIO23_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 28. "GPIO23_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 27. "GPIO22_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 26. "GPIO22_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 25. "GPIO22_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 24. "GPIO22_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 23. "GPIO21_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 22. "GPIO21_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 21. "GPIO21_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 20. "GPIO21_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 19. "GPIO20_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 18. "GPIO20_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 17. "GPIO20_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 16. "GPIO20_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 15. "GPIO19_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 14. "GPIO19_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 13. "GPIO19_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 12. "GPIO19_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 11. "GPIO18_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 10. "GPIO18_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 9. "GPIO18_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 8. "GPIO18_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 7. "GPIO17_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 6. "GPIO17_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 5. "GPIO17_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 4. "GPIO17_LEVEL_LOW" "0,1"
newline
bitfld.long 0x20 3. "GPIO16_EDGE_HIGH" "0,1"
newline
bitfld.long 0x20 2. "GPIO16_EDGE_LOW" "0,1"
newline
bitfld.long 0x20 1. "GPIO16_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x20 0. "GPIO16_LEVEL_LOW" "0,1"
line.long 0x24 "DORMANT_WAKE_INTF3,Interrupt Force for dormant_wake"
bitfld.long 0x24 31. "GPIO31_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 30. "GPIO31_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 29. "GPIO31_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 28. "GPIO31_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 27. "GPIO30_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 26. "GPIO30_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 25. "GPIO30_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 24. "GPIO30_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 23. "GPIO29_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 22. "GPIO29_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 21. "GPIO29_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 20. "GPIO29_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 19. "GPIO28_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 18. "GPIO28_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 17. "GPIO28_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 16. "GPIO28_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 15. "GPIO27_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 14. "GPIO27_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 13. "GPIO27_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 12. "GPIO27_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 11. "GPIO26_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 10. "GPIO26_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 9. "GPIO26_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 8. "GPIO26_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 7. "GPIO25_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 6. "GPIO25_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 5. "GPIO25_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 4. "GPIO25_LEVEL_LOW" "0,1"
newline
bitfld.long 0x24 3. "GPIO24_EDGE_HIGH" "0,1"
newline
bitfld.long 0x24 2. "GPIO24_EDGE_LOW" "0,1"
newline
bitfld.long 0x24 1. "GPIO24_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x24 0. "GPIO24_LEVEL_LOW" "0,1"
line.long 0x28 "DORMANT_WAKE_INTF4,Interrupt Force for dormant_wake"
bitfld.long 0x28 31. "GPIO39_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 30. "GPIO39_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 29. "GPIO39_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 28. "GPIO39_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 27. "GPIO38_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 26. "GPIO38_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 25. "GPIO38_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 24. "GPIO38_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 23. "GPIO37_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 22. "GPIO37_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 21. "GPIO37_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 20. "GPIO37_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 19. "GPIO36_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 18. "GPIO36_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 17. "GPIO36_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 16. "GPIO36_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 15. "GPIO35_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 14. "GPIO35_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 13. "GPIO35_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 12. "GPIO35_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 11. "GPIO34_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 10. "GPIO34_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 9. "GPIO34_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 8. "GPIO34_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 7. "GPIO33_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 6. "GPIO33_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 5. "GPIO33_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 4. "GPIO33_LEVEL_LOW" "0,1"
newline
bitfld.long 0x28 3. "GPIO32_EDGE_HIGH" "0,1"
newline
bitfld.long 0x28 2. "GPIO32_EDGE_LOW" "0,1"
newline
bitfld.long 0x28 1. "GPIO32_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x28 0. "GPIO32_LEVEL_LOW" "0,1"
line.long 0x2C "DORMANT_WAKE_INTF5,Interrupt Force for dormant_wake"
bitfld.long 0x2C 31. "GPIO47_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 30. "GPIO47_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 29. "GPIO47_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 28. "GPIO47_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 27. "GPIO46_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 26. "GPIO46_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 25. "GPIO46_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 24. "GPIO46_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 23. "GPIO45_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 22. "GPIO45_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 21. "GPIO45_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 20. "GPIO45_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 19. "GPIO44_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 18. "GPIO44_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 17. "GPIO44_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 16. "GPIO44_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 15. "GPIO43_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 14. "GPIO43_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 13. "GPIO43_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 12. "GPIO43_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 11. "GPIO42_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 10. "GPIO42_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 9. "GPIO42_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 8. "GPIO42_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 7. "GPIO41_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 6. "GPIO41_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 5. "GPIO41_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 4. "GPIO41_LEVEL_LOW" "0,1"
newline
bitfld.long 0x2C 3. "GPIO40_EDGE_HIGH" "0,1"
newline
bitfld.long 0x2C 2. "GPIO40_EDGE_LOW" "0,1"
newline
bitfld.long 0x2C 1. "GPIO40_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x2C 0. "GPIO40_LEVEL_LOW" "0,1"
rgroup.long 0x308++0x17
line.long 0x0 "DORMANT_WAKE_INTS0,Interrupt status after masking & forcing for dormant_wake"
bitfld.long 0x0 31. "GPIO7_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 30. "GPIO7_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 29. "GPIO7_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 28. "GPIO7_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 27. "GPIO6_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 26. "GPIO6_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 25. "GPIO6_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 24. "GPIO6_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 23. "GPIO5_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 22. "GPIO5_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 21. "GPIO5_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 20. "GPIO5_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 19. "GPIO4_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 18. "GPIO4_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 17. "GPIO4_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 16. "GPIO4_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 15. "GPIO3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 14. "GPIO3_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 13. "GPIO3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 12. "GPIO3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 11. "GPIO2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 10. "GPIO2_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 9. "GPIO2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 8. "GPIO2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 7. "GPIO1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 6. "GPIO1_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 5. "GPIO1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 4. "GPIO1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 3. "GPIO0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 2. "GPIO0_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 1. "GPIO0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 0. "GPIO0_LEVEL_LOW" "0,1"
line.long 0x4 "DORMANT_WAKE_INTS1,Interrupt status after masking & forcing for dormant_wake"
bitfld.long 0x4 31. "GPIO15_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 30. "GPIO15_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 29. "GPIO15_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 28. "GPIO15_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 27. "GPIO14_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 26. "GPIO14_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 25. "GPIO14_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 24. "GPIO14_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 23. "GPIO13_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 22. "GPIO13_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 21. "GPIO13_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 20. "GPIO13_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 19. "GPIO12_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 18. "GPIO12_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 17. "GPIO12_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 16. "GPIO12_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 15. "GPIO11_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 14. "GPIO11_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 13. "GPIO11_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 12. "GPIO11_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 11. "GPIO10_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 10. "GPIO10_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 9. "GPIO10_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 8. "GPIO10_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 7. "GPIO9_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 6. "GPIO9_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 5. "GPIO9_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 4. "GPIO9_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 3. "GPIO8_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 2. "GPIO8_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 1. "GPIO8_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 0. "GPIO8_LEVEL_LOW" "0,1"
line.long 0x8 "DORMANT_WAKE_INTS2,Interrupt status after masking & forcing for dormant_wake"
bitfld.long 0x8 31. "GPIO23_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 30. "GPIO23_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 29. "GPIO23_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 28. "GPIO23_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 27. "GPIO22_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 26. "GPIO22_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 25. "GPIO22_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 24. "GPIO22_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 23. "GPIO21_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 22. "GPIO21_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 21. "GPIO21_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 20. "GPIO21_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 19. "GPIO20_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 18. "GPIO20_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 17. "GPIO20_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 16. "GPIO20_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 15. "GPIO19_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 14. "GPIO19_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 13. "GPIO19_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 12. "GPIO19_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 11. "GPIO18_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 10. "GPIO18_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 9. "GPIO18_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 8. "GPIO18_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 7. "GPIO17_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 6. "GPIO17_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 5. "GPIO17_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 4. "GPIO17_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 3. "GPIO16_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 2. "GPIO16_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 1. "GPIO16_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 0. "GPIO16_LEVEL_LOW" "0,1"
line.long 0xC "DORMANT_WAKE_INTS3,Interrupt status after masking & forcing for dormant_wake"
bitfld.long 0xC 31. "GPIO31_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 30. "GPIO31_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 29. "GPIO31_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 28. "GPIO31_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 27. "GPIO30_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 26. "GPIO30_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 25. "GPIO30_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 24. "GPIO30_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 23. "GPIO29_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 22. "GPIO29_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 21. "GPIO29_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 20. "GPIO29_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 19. "GPIO28_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 18. "GPIO28_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 17. "GPIO28_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 16. "GPIO28_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 15. "GPIO27_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 14. "GPIO27_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 13. "GPIO27_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 12. "GPIO27_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 11. "GPIO26_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 10. "GPIO26_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 9. "GPIO26_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 8. "GPIO26_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 7. "GPIO25_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 6. "GPIO25_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 5. "GPIO25_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 4. "GPIO25_LEVEL_LOW" "0,1"
newline
bitfld.long 0xC 3. "GPIO24_EDGE_HIGH" "0,1"
newline
bitfld.long 0xC 2. "GPIO24_EDGE_LOW" "0,1"
newline
bitfld.long 0xC 1. "GPIO24_LEVEL_HIGH" "0,1"
newline
bitfld.long 0xC 0. "GPIO24_LEVEL_LOW" "0,1"
line.long 0x10 "DORMANT_WAKE_INTS4,Interrupt status after masking & forcing for dormant_wake"
bitfld.long 0x10 31. "GPIO39_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 30. "GPIO39_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 29. "GPIO39_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 28. "GPIO39_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 27. "GPIO38_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 26. "GPIO38_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 25. "GPIO38_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 24. "GPIO38_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 23. "GPIO37_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 22. "GPIO37_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 21. "GPIO37_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 20. "GPIO37_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 19. "GPIO36_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 18. "GPIO36_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 17. "GPIO36_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 16. "GPIO36_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 15. "GPIO35_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 14. "GPIO35_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 13. "GPIO35_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 12. "GPIO35_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 11. "GPIO34_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 10. "GPIO34_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 9. "GPIO34_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 8. "GPIO34_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 7. "GPIO33_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 6. "GPIO33_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 5. "GPIO33_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 4. "GPIO33_LEVEL_LOW" "0,1"
newline
bitfld.long 0x10 3. "GPIO32_EDGE_HIGH" "0,1"
newline
bitfld.long 0x10 2. "GPIO32_EDGE_LOW" "0,1"
newline
bitfld.long 0x10 1. "GPIO32_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x10 0. "GPIO32_LEVEL_LOW" "0,1"
line.long 0x14 "DORMANT_WAKE_INTS5,Interrupt status after masking & forcing for dormant_wake"
bitfld.long 0x14 31. "GPIO47_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 30. "GPIO47_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 29. "GPIO47_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 28. "GPIO47_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 27. "GPIO46_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 26. "GPIO46_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 25. "GPIO46_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 24. "GPIO46_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 23. "GPIO45_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 22. "GPIO45_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 21. "GPIO45_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 20. "GPIO45_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 19. "GPIO44_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 18. "GPIO44_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 17. "GPIO44_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 16. "GPIO44_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 15. "GPIO43_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 14. "GPIO43_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 13. "GPIO43_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 12. "GPIO43_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 11. "GPIO42_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 10. "GPIO42_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 9. "GPIO42_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 8. "GPIO42_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 7. "GPIO41_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 6. "GPIO41_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 5. "GPIO41_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 4. "GPIO41_LEVEL_LOW" "0,1"
newline
bitfld.long 0x14 3. "GPIO40_EDGE_HIGH" "0,1"
newline
bitfld.long 0x14 2. "GPIO40_EDGE_LOW" "0,1"
newline
bitfld.long 0x14 1. "GPIO40_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x14 0. "GPIO40_LEVEL_LOW" "0,1"
tree.end
tree "IO_QSPI"
base ad:0x40030000
rgroup.long 0x0++0x3
line.long 0x0 "USBPHY_DP_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x4++0x3
line.long 0x0 "USBPHY_DP_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x8++0x3
line.long 0x0 "USBPHY_DM_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0xC++0x3
line.long 0x0 "USBPHY_DM_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x10++0x3
line.long 0x0 "GPIO_QSPI_SCLK_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x14++0x3
line.long 0x0 "GPIO_QSPI_SCLK_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x18++0x3
line.long 0x0 "GPIO_QSPI_SS_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x1C++0x3
line.long 0x0 "GPIO_QSPI_SS_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x20++0x3
line.long 0x0 "GPIO_QSPI_SD0_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x24++0x3
line.long 0x0 "GPIO_QSPI_SD0_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x28++0x3
line.long 0x0 "GPIO_QSPI_SD1_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x2C++0x3
line.long 0x0 "GPIO_QSPI_SD1_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x30++0x3
line.long 0x0 "GPIO_QSPI_SD2_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x34++0x3
line.long 0x0 "GPIO_QSPI_SD2_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x38++0x3
line.long 0x0 "GPIO_QSPI_SD3_STATUS"
bitfld.long 0x0 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1"
newline
bitfld.long 0x0 17. "INFROMPAD,input signal from pad before filtering and override are applied" "0,1"
newline
bitfld.long 0x0 13. "OETOPAD,output enable to pad after register override is applied" "0,1"
newline
bitfld.long 0x0 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1"
group.long 0x3C++0x3
line.long 0x0 "GPIO_QSPI_SD3_CTRL"
bitfld.long 0x0 28.--29. "IRQOVER" "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high"
newline
bitfld.long 0x0 16.--17. "INOVER" "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high"
newline
bitfld.long 0x0 14.--15. "OEOVER" "0: drive output enable from peripheral signal..,1: drive output enable from inverse of peripheral..,2: disable output,3: enable output"
newline
bitfld.long 0x0 12.--13. "OUTOVER" "0: drive output from peripheral signal selected by..,1: drive output from inverse of peripheral signal..,2: drive output low,3: drive output high"
newline
hexmask.long.byte 0x0 0.--4. 1. "FUNCSEL,0-31 -> selects pin function according to the gpio table"
rgroup.long 0x200++0x17
line.long 0x0 "IRQSUMMARY_PROC0_SECURE"
bitfld.long 0x0 7. "GPIO_QSPI_SD3" "0,1"
newline
bitfld.long 0x0 6. "GPIO_QSPI_SD2" "0,1"
newline
bitfld.long 0x0 5. "GPIO_QSPI_SD1" "0,1"
newline
bitfld.long 0x0 4. "GPIO_QSPI_SD0" "0,1"
newline
bitfld.long 0x0 3. "GPIO_QSPI_SS" "0,1"
newline
bitfld.long 0x0 2. "GPIO_QSPI_SCLK" "0,1"
newline
bitfld.long 0x0 1. "USBPHY_DM" "0,1"
newline
bitfld.long 0x0 0. "USBPHY_DP" "0,1"
line.long 0x4 "IRQSUMMARY_PROC0_NONSECURE"
bitfld.long 0x4 7. "GPIO_QSPI_SD3" "0,1"
newline
bitfld.long 0x4 6. "GPIO_QSPI_SD2" "0,1"
newline
bitfld.long 0x4 5. "GPIO_QSPI_SD1" "0,1"
newline
bitfld.long 0x4 4. "GPIO_QSPI_SD0" "0,1"
newline
bitfld.long 0x4 3. "GPIO_QSPI_SS" "0,1"
newline
bitfld.long 0x4 2. "GPIO_QSPI_SCLK" "0,1"
newline
bitfld.long 0x4 1. "USBPHY_DM" "0,1"
newline
bitfld.long 0x4 0. "USBPHY_DP" "0,1"
line.long 0x8 "IRQSUMMARY_PROC1_SECURE"
bitfld.long 0x8 7. "GPIO_QSPI_SD3" "0,1"
newline
bitfld.long 0x8 6. "GPIO_QSPI_SD2" "0,1"
newline
bitfld.long 0x8 5. "GPIO_QSPI_SD1" "0,1"
newline
bitfld.long 0x8 4. "GPIO_QSPI_SD0" "0,1"
newline
bitfld.long 0x8 3. "GPIO_QSPI_SS" "0,1"
newline
bitfld.long 0x8 2. "GPIO_QSPI_SCLK" "0,1"
newline
bitfld.long 0x8 1. "USBPHY_DM" "0,1"
newline
bitfld.long 0x8 0. "USBPHY_DP" "0,1"
line.long 0xC "IRQSUMMARY_PROC1_NONSECURE"
bitfld.long 0xC 7. "GPIO_QSPI_SD3" "0,1"
newline
bitfld.long 0xC 6. "GPIO_QSPI_SD2" "0,1"
newline
bitfld.long 0xC 5. "GPIO_QSPI_SD1" "0,1"
newline
bitfld.long 0xC 4. "GPIO_QSPI_SD0" "0,1"
newline
bitfld.long 0xC 3. "GPIO_QSPI_SS" "0,1"
newline
bitfld.long 0xC 2. "GPIO_QSPI_SCLK" "0,1"
newline
bitfld.long 0xC 1. "USBPHY_DM" "0,1"
newline
bitfld.long 0xC 0. "USBPHY_DP" "0,1"
line.long 0x10 "IRQSUMMARY_DORMANT_WAKE_SECURE"
bitfld.long 0x10 7. "GPIO_QSPI_SD3" "0,1"
newline
bitfld.long 0x10 6. "GPIO_QSPI_SD2" "0,1"
newline
bitfld.long 0x10 5. "GPIO_QSPI_SD1" "0,1"
newline
bitfld.long 0x10 4. "GPIO_QSPI_SD0" "0,1"
newline
bitfld.long 0x10 3. "GPIO_QSPI_SS" "0,1"
newline
bitfld.long 0x10 2. "GPIO_QSPI_SCLK" "0,1"
newline
bitfld.long 0x10 1. "USBPHY_DM" "0,1"
newline
bitfld.long 0x10 0. "USBPHY_DP" "0,1"
line.long 0x14 "IRQSUMMARY_DORMANT_WAKE_NONSECURE"
bitfld.long 0x14 7. "GPIO_QSPI_SD3" "0,1"
newline
bitfld.long 0x14 6. "GPIO_QSPI_SD2" "0,1"
newline
bitfld.long 0x14 5. "GPIO_QSPI_SD1" "0,1"
newline
bitfld.long 0x14 4. "GPIO_QSPI_SD0" "0,1"
newline
bitfld.long 0x14 3. "GPIO_QSPI_SS" "0,1"
newline
bitfld.long 0x14 2. "GPIO_QSPI_SCLK" "0,1"
newline
bitfld.long 0x14 1. "USBPHY_DM" "0,1"
newline
bitfld.long 0x14 0. "USBPHY_DP" "0,1"
group.long 0x218++0xB
line.long 0x0 "INTR,Raw Interrupts"
eventfld.long 0x0 31. "GPIO_QSPI_SD3_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 30. "GPIO_QSPI_SD3_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 29. "GPIO_QSPI_SD3_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 28. "GPIO_QSPI_SD3_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 27. "GPIO_QSPI_SD2_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 26. "GPIO_QSPI_SD2_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 25. "GPIO_QSPI_SD2_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 24. "GPIO_QSPI_SD2_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 23. "GPIO_QSPI_SD1_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 22. "GPIO_QSPI_SD1_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 21. "GPIO_QSPI_SD1_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 20. "GPIO_QSPI_SD1_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 19. "GPIO_QSPI_SD0_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 18. "GPIO_QSPI_SD0_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 17. "GPIO_QSPI_SD0_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 16. "GPIO_QSPI_SD0_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 15. "GPIO_QSPI_SS_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 14. "GPIO_QSPI_SS_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 13. "GPIO_QSPI_SS_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 12. "GPIO_QSPI_SS_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 11. "GPIO_QSPI_SCLK_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 10. "GPIO_QSPI_SCLK_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 9. "GPIO_QSPI_SCLK_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 8. "GPIO_QSPI_SCLK_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 7. "USBPHY_DM_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 6. "USBPHY_DM_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 5. "USBPHY_DM_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 4. "USBPHY_DM_LEVEL_LOW" "0,1"
newline
eventfld.long 0x0 3. "USBPHY_DP_EDGE_HIGH" "0,1"
newline
eventfld.long 0x0 2. "USBPHY_DP_EDGE_LOW" "0,1"
newline
rbitfld.long 0x0 1. "USBPHY_DP_LEVEL_HIGH" "0,1"
newline
rbitfld.long 0x0 0. "USBPHY_DP_LEVEL_LOW" "0,1"
line.long 0x4 "PROC0_INTE,Interrupt Enable for proc0"
bitfld.long 0x4 31. "GPIO_QSPI_SD3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 30. "GPIO_QSPI_SD3_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 29. "GPIO_QSPI_SD3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 28. "GPIO_QSPI_SD3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 27. "GPIO_QSPI_SD2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 26. "GPIO_QSPI_SD2_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 25. "GPIO_QSPI_SD2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 24. "GPIO_QSPI_SD2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 23. "GPIO_QSPI_SD1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 22. "GPIO_QSPI_SD1_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 21. "GPIO_QSPI_SD1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 20. "GPIO_QSPI_SD1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 19. "GPIO_QSPI_SD0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 18. "GPIO_QSPI_SD0_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 17. "GPIO_QSPI_SD0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 16. "GPIO_QSPI_SD0_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 15. "GPIO_QSPI_SS_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 14. "GPIO_QSPI_SS_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 13. "GPIO_QSPI_SS_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 12. "GPIO_QSPI_SS_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 11. "GPIO_QSPI_SCLK_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 10. "GPIO_QSPI_SCLK_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 9. "GPIO_QSPI_SCLK_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 8. "GPIO_QSPI_SCLK_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 7. "USBPHY_DM_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 6. "USBPHY_DM_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 5. "USBPHY_DM_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 4. "USBPHY_DM_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 3. "USBPHY_DP_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 2. "USBPHY_DP_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 1. "USBPHY_DP_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 0. "USBPHY_DP_LEVEL_LOW" "0,1"
line.long 0x8 "PROC0_INTF,Interrupt Force for proc0"
bitfld.long 0x8 31. "GPIO_QSPI_SD3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 30. "GPIO_QSPI_SD3_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 29. "GPIO_QSPI_SD3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 28. "GPIO_QSPI_SD3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 27. "GPIO_QSPI_SD2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 26. "GPIO_QSPI_SD2_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 25. "GPIO_QSPI_SD2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 24. "GPIO_QSPI_SD2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 23. "GPIO_QSPI_SD1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 22. "GPIO_QSPI_SD1_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 21. "GPIO_QSPI_SD1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 20. "GPIO_QSPI_SD1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 19. "GPIO_QSPI_SD0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 18. "GPIO_QSPI_SD0_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 17. "GPIO_QSPI_SD0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 16. "GPIO_QSPI_SD0_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 15. "GPIO_QSPI_SS_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 14. "GPIO_QSPI_SS_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 13. "GPIO_QSPI_SS_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 12. "GPIO_QSPI_SS_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 11. "GPIO_QSPI_SCLK_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 10. "GPIO_QSPI_SCLK_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 9. "GPIO_QSPI_SCLK_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 8. "GPIO_QSPI_SCLK_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 7. "USBPHY_DM_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 6. "USBPHY_DM_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 5. "USBPHY_DM_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 4. "USBPHY_DM_LEVEL_LOW" "0,1"
newline
bitfld.long 0x8 3. "USBPHY_DP_EDGE_HIGH" "0,1"
newline
bitfld.long 0x8 2. "USBPHY_DP_EDGE_LOW" "0,1"
newline
bitfld.long 0x8 1. "USBPHY_DP_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x8 0. "USBPHY_DP_LEVEL_LOW" "0,1"
rgroup.long 0x224++0x3
line.long 0x0 "PROC0_INTS,Interrupt status after masking & forcing for proc0"
bitfld.long 0x0 31. "GPIO_QSPI_SD3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 30. "GPIO_QSPI_SD3_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 29. "GPIO_QSPI_SD3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 28. "GPIO_QSPI_SD3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 27. "GPIO_QSPI_SD2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 26. "GPIO_QSPI_SD2_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 25. "GPIO_QSPI_SD2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 24. "GPIO_QSPI_SD2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 23. "GPIO_QSPI_SD1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 22. "GPIO_QSPI_SD1_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 21. "GPIO_QSPI_SD1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 20. "GPIO_QSPI_SD1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 19. "GPIO_QSPI_SD0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 18. "GPIO_QSPI_SD0_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 17. "GPIO_QSPI_SD0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 16. "GPIO_QSPI_SD0_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 15. "GPIO_QSPI_SS_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 14. "GPIO_QSPI_SS_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 13. "GPIO_QSPI_SS_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 12. "GPIO_QSPI_SS_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 11. "GPIO_QSPI_SCLK_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 10. "GPIO_QSPI_SCLK_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 9. "GPIO_QSPI_SCLK_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 8. "GPIO_QSPI_SCLK_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 7. "USBPHY_DM_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 6. "USBPHY_DM_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 5. "USBPHY_DM_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 4. "USBPHY_DM_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 3. "USBPHY_DP_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 2. "USBPHY_DP_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 1. "USBPHY_DP_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 0. "USBPHY_DP_LEVEL_LOW" "0,1"
group.long 0x228++0x7
line.long 0x0 "PROC1_INTE,Interrupt Enable for proc1"
bitfld.long 0x0 31. "GPIO_QSPI_SD3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 30. "GPIO_QSPI_SD3_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 29. "GPIO_QSPI_SD3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 28. "GPIO_QSPI_SD3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 27. "GPIO_QSPI_SD2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 26. "GPIO_QSPI_SD2_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 25. "GPIO_QSPI_SD2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 24. "GPIO_QSPI_SD2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 23. "GPIO_QSPI_SD1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 22. "GPIO_QSPI_SD1_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 21. "GPIO_QSPI_SD1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 20. "GPIO_QSPI_SD1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 19. "GPIO_QSPI_SD0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 18. "GPIO_QSPI_SD0_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 17. "GPIO_QSPI_SD0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 16. "GPIO_QSPI_SD0_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 15. "GPIO_QSPI_SS_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 14. "GPIO_QSPI_SS_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 13. "GPIO_QSPI_SS_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 12. "GPIO_QSPI_SS_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 11. "GPIO_QSPI_SCLK_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 10. "GPIO_QSPI_SCLK_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 9. "GPIO_QSPI_SCLK_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 8. "GPIO_QSPI_SCLK_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 7. "USBPHY_DM_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 6. "USBPHY_DM_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 5. "USBPHY_DM_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 4. "USBPHY_DM_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 3. "USBPHY_DP_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 2. "USBPHY_DP_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 1. "USBPHY_DP_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 0. "USBPHY_DP_LEVEL_LOW" "0,1"
line.long 0x4 "PROC1_INTF,Interrupt Force for proc1"
bitfld.long 0x4 31. "GPIO_QSPI_SD3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 30. "GPIO_QSPI_SD3_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 29. "GPIO_QSPI_SD3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 28. "GPIO_QSPI_SD3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 27. "GPIO_QSPI_SD2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 26. "GPIO_QSPI_SD2_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 25. "GPIO_QSPI_SD2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 24. "GPIO_QSPI_SD2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 23. "GPIO_QSPI_SD1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 22. "GPIO_QSPI_SD1_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 21. "GPIO_QSPI_SD1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 20. "GPIO_QSPI_SD1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 19. "GPIO_QSPI_SD0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 18. "GPIO_QSPI_SD0_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 17. "GPIO_QSPI_SD0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 16. "GPIO_QSPI_SD0_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 15. "GPIO_QSPI_SS_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 14. "GPIO_QSPI_SS_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 13. "GPIO_QSPI_SS_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 12. "GPIO_QSPI_SS_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 11. "GPIO_QSPI_SCLK_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 10. "GPIO_QSPI_SCLK_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 9. "GPIO_QSPI_SCLK_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 8. "GPIO_QSPI_SCLK_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 7. "USBPHY_DM_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 6. "USBPHY_DM_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 5. "USBPHY_DM_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 4. "USBPHY_DM_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 3. "USBPHY_DP_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 2. "USBPHY_DP_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 1. "USBPHY_DP_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 0. "USBPHY_DP_LEVEL_LOW" "0,1"
rgroup.long 0x230++0x3
line.long 0x0 "PROC1_INTS,Interrupt status after masking & forcing for proc1"
bitfld.long 0x0 31. "GPIO_QSPI_SD3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 30. "GPIO_QSPI_SD3_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 29. "GPIO_QSPI_SD3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 28. "GPIO_QSPI_SD3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 27. "GPIO_QSPI_SD2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 26. "GPIO_QSPI_SD2_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 25. "GPIO_QSPI_SD2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 24. "GPIO_QSPI_SD2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 23. "GPIO_QSPI_SD1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 22. "GPIO_QSPI_SD1_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 21. "GPIO_QSPI_SD1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 20. "GPIO_QSPI_SD1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 19. "GPIO_QSPI_SD0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 18. "GPIO_QSPI_SD0_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 17. "GPIO_QSPI_SD0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 16. "GPIO_QSPI_SD0_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 15. "GPIO_QSPI_SS_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 14. "GPIO_QSPI_SS_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 13. "GPIO_QSPI_SS_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 12. "GPIO_QSPI_SS_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 11. "GPIO_QSPI_SCLK_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 10. "GPIO_QSPI_SCLK_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 9. "GPIO_QSPI_SCLK_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 8. "GPIO_QSPI_SCLK_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 7. "USBPHY_DM_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 6. "USBPHY_DM_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 5. "USBPHY_DM_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 4. "USBPHY_DM_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 3. "USBPHY_DP_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 2. "USBPHY_DP_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 1. "USBPHY_DP_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 0. "USBPHY_DP_LEVEL_LOW" "0,1"
group.long 0x234++0x7
line.long 0x0 "DORMANT_WAKE_INTE,Interrupt Enable for dormant_wake"
bitfld.long 0x0 31. "GPIO_QSPI_SD3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 30. "GPIO_QSPI_SD3_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 29. "GPIO_QSPI_SD3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 28. "GPIO_QSPI_SD3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 27. "GPIO_QSPI_SD2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 26. "GPIO_QSPI_SD2_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 25. "GPIO_QSPI_SD2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 24. "GPIO_QSPI_SD2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 23. "GPIO_QSPI_SD1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 22. "GPIO_QSPI_SD1_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 21. "GPIO_QSPI_SD1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 20. "GPIO_QSPI_SD1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 19. "GPIO_QSPI_SD0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 18. "GPIO_QSPI_SD0_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 17. "GPIO_QSPI_SD0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 16. "GPIO_QSPI_SD0_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 15. "GPIO_QSPI_SS_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 14. "GPIO_QSPI_SS_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 13. "GPIO_QSPI_SS_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 12. "GPIO_QSPI_SS_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 11. "GPIO_QSPI_SCLK_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 10. "GPIO_QSPI_SCLK_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 9. "GPIO_QSPI_SCLK_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 8. "GPIO_QSPI_SCLK_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 7. "USBPHY_DM_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 6. "USBPHY_DM_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 5. "USBPHY_DM_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 4. "USBPHY_DM_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 3. "USBPHY_DP_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 2. "USBPHY_DP_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 1. "USBPHY_DP_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 0. "USBPHY_DP_LEVEL_LOW" "0,1"
line.long 0x4 "DORMANT_WAKE_INTF,Interrupt Force for dormant_wake"
bitfld.long 0x4 31. "GPIO_QSPI_SD3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 30. "GPIO_QSPI_SD3_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 29. "GPIO_QSPI_SD3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 28. "GPIO_QSPI_SD3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 27. "GPIO_QSPI_SD2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 26. "GPIO_QSPI_SD2_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 25. "GPIO_QSPI_SD2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 24. "GPIO_QSPI_SD2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 23. "GPIO_QSPI_SD1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 22. "GPIO_QSPI_SD1_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 21. "GPIO_QSPI_SD1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 20. "GPIO_QSPI_SD1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 19. "GPIO_QSPI_SD0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 18. "GPIO_QSPI_SD0_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 17. "GPIO_QSPI_SD0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 16. "GPIO_QSPI_SD0_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 15. "GPIO_QSPI_SS_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 14. "GPIO_QSPI_SS_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 13. "GPIO_QSPI_SS_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 12. "GPIO_QSPI_SS_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 11. "GPIO_QSPI_SCLK_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 10. "GPIO_QSPI_SCLK_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 9. "GPIO_QSPI_SCLK_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 8. "GPIO_QSPI_SCLK_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 7. "USBPHY_DM_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 6. "USBPHY_DM_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 5. "USBPHY_DM_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 4. "USBPHY_DM_LEVEL_LOW" "0,1"
newline
bitfld.long 0x4 3. "USBPHY_DP_EDGE_HIGH" "0,1"
newline
bitfld.long 0x4 2. "USBPHY_DP_EDGE_LOW" "0,1"
newline
bitfld.long 0x4 1. "USBPHY_DP_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x4 0. "USBPHY_DP_LEVEL_LOW" "0,1"
rgroup.long 0x23C++0x3
line.long 0x0 "DORMANT_WAKE_INTS,Interrupt status after masking & forcing for dormant_wake"
bitfld.long 0x0 31. "GPIO_QSPI_SD3_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 30. "GPIO_QSPI_SD3_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 29. "GPIO_QSPI_SD3_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 28. "GPIO_QSPI_SD3_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 27. "GPIO_QSPI_SD2_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 26. "GPIO_QSPI_SD2_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 25. "GPIO_QSPI_SD2_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 24. "GPIO_QSPI_SD2_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 23. "GPIO_QSPI_SD1_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 22. "GPIO_QSPI_SD1_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 21. "GPIO_QSPI_SD1_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 20. "GPIO_QSPI_SD1_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 19. "GPIO_QSPI_SD0_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 18. "GPIO_QSPI_SD0_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 17. "GPIO_QSPI_SD0_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 16. "GPIO_QSPI_SD0_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 15. "GPIO_QSPI_SS_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 14. "GPIO_QSPI_SS_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 13. "GPIO_QSPI_SS_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 12. "GPIO_QSPI_SS_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 11. "GPIO_QSPI_SCLK_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 10. "GPIO_QSPI_SCLK_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 9. "GPIO_QSPI_SCLK_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 8. "GPIO_QSPI_SCLK_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 7. "USBPHY_DM_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 6. "USBPHY_DM_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 5. "USBPHY_DM_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 4. "USBPHY_DM_LEVEL_LOW" "0,1"
newline
bitfld.long 0x0 3. "USBPHY_DP_EDGE_HIGH" "0,1"
newline
bitfld.long 0x0 2. "USBPHY_DP_EDGE_LOW" "0,1"
newline
bitfld.long 0x0 1. "USBPHY_DP_LEVEL_HIGH" "0,1"
newline
bitfld.long 0x0 0. "USBPHY_DP_LEVEL_LOW" "0,1"
tree.end
tree.end
tree "PADS (PAD Control)"
tree "PADS_BANK0"
base ad:0x40038000
group.long 0x0++0xCB
line.long 0x0 "VOLTAGE_SELECT,Voltage select. Per bank control"
bitfld.long 0x0 0. "VOLTAGE_SELECT" "0: Set voltage to 3.3V (DVDD >= 2V5),1: Set voltage to 1.8V (DVDD <= 1V8)"
line.long 0x4 "GPIO0"
bitfld.long 0x4 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x4 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x4 6. "IE,Input enable" "0,1"
bitfld.long 0x4 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x4 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x4 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x4 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x4 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x8 "GPIO1"
bitfld.long 0x8 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x8 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x8 6. "IE,Input enable" "0,1"
bitfld.long 0x8 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x8 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x8 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x8 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x8 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xC "GPIO2"
bitfld.long 0xC 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xC 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xC 6. "IE,Input enable" "0,1"
bitfld.long 0xC 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xC 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xC 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xC 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xC 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x10 "GPIO3"
bitfld.long 0x10 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x10 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x10 6. "IE,Input enable" "0,1"
bitfld.long 0x10 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x10 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x10 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x10 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x10 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x14 "GPIO4"
bitfld.long 0x14 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x14 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x14 6. "IE,Input enable" "0,1"
bitfld.long 0x14 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x14 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x14 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x14 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x14 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x18 "GPIO5"
bitfld.long 0x18 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x18 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x18 6. "IE,Input enable" "0,1"
bitfld.long 0x18 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x18 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x18 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x18 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x18 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x1C "GPIO6"
bitfld.long 0x1C 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x1C 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x1C 6. "IE,Input enable" "0,1"
bitfld.long 0x1C 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x1C 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x1C 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x1C 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x1C 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x20 "GPIO7"
bitfld.long 0x20 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x20 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x20 6. "IE,Input enable" "0,1"
bitfld.long 0x20 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x20 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x20 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x20 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x20 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x24 "GPIO8"
bitfld.long 0x24 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x24 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x24 6. "IE,Input enable" "0,1"
bitfld.long 0x24 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x24 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x24 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x24 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x24 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x28 "GPIO9"
bitfld.long 0x28 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x28 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x28 6. "IE,Input enable" "0,1"
bitfld.long 0x28 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x28 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x28 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x28 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x28 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x2C "GPIO10"
bitfld.long 0x2C 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x2C 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x2C 6. "IE,Input enable" "0,1"
bitfld.long 0x2C 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x2C 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x2C 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x2C 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x2C 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x30 "GPIO11"
bitfld.long 0x30 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x30 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x30 6. "IE,Input enable" "0,1"
bitfld.long 0x30 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x30 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x30 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x30 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x30 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x34 "GPIO12"
bitfld.long 0x34 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x34 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x34 6. "IE,Input enable" "0,1"
bitfld.long 0x34 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x34 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x34 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x34 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x34 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x38 "GPIO13"
bitfld.long 0x38 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x38 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x38 6. "IE,Input enable" "0,1"
bitfld.long 0x38 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x38 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x38 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x38 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x38 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x3C "GPIO14"
bitfld.long 0x3C 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x3C 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x3C 6. "IE,Input enable" "0,1"
bitfld.long 0x3C 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x3C 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x3C 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x3C 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x3C 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x40 "GPIO15"
bitfld.long 0x40 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x40 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x40 6. "IE,Input enable" "0,1"
bitfld.long 0x40 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x40 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x40 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x40 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x40 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x44 "GPIO16"
bitfld.long 0x44 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x44 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x44 6. "IE,Input enable" "0,1"
bitfld.long 0x44 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x44 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x44 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x44 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x44 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x48 "GPIO17"
bitfld.long 0x48 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x48 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x48 6. "IE,Input enable" "0,1"
bitfld.long 0x48 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x48 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x48 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x48 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x48 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x4C "GPIO18"
bitfld.long 0x4C 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x4C 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x4C 6. "IE,Input enable" "0,1"
bitfld.long 0x4C 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x4C 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x4C 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x4C 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x4C 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x50 "GPIO19"
bitfld.long 0x50 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x50 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x50 6. "IE,Input enable" "0,1"
bitfld.long 0x50 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x50 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x50 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x50 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x50 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x54 "GPIO20"
bitfld.long 0x54 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x54 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x54 6. "IE,Input enable" "0,1"
bitfld.long 0x54 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x54 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x54 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x54 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x54 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x58 "GPIO21"
bitfld.long 0x58 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x58 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x58 6. "IE,Input enable" "0,1"
bitfld.long 0x58 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x58 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x58 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x58 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x58 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x5C "GPIO22"
bitfld.long 0x5C 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x5C 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x5C 6. "IE,Input enable" "0,1"
bitfld.long 0x5C 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x5C 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x5C 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x5C 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x5C 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x60 "GPIO23"
bitfld.long 0x60 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x60 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x60 6. "IE,Input enable" "0,1"
bitfld.long 0x60 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x60 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x60 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x60 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x60 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x64 "GPIO24"
bitfld.long 0x64 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x64 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x64 6. "IE,Input enable" "0,1"
bitfld.long 0x64 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x64 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x64 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x64 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x64 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x68 "GPIO25"
bitfld.long 0x68 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x68 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x68 6. "IE,Input enable" "0,1"
bitfld.long 0x68 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x68 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x68 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x68 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x68 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x6C "GPIO26"
bitfld.long 0x6C 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x6C 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x6C 6. "IE,Input enable" "0,1"
bitfld.long 0x6C 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x6C 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x6C 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x6C 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x6C 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x70 "GPIO27"
bitfld.long 0x70 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x70 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x70 6. "IE,Input enable" "0,1"
bitfld.long 0x70 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x70 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x70 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x70 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x70 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x74 "GPIO28"
bitfld.long 0x74 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x74 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x74 6. "IE,Input enable" "0,1"
bitfld.long 0x74 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x74 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x74 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x74 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x74 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x78 "GPIO29"
bitfld.long 0x78 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x78 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x78 6. "IE,Input enable" "0,1"
bitfld.long 0x78 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x78 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x78 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x78 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x78 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x7C "GPIO30"
bitfld.long 0x7C 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x7C 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x7C 6. "IE,Input enable" "0,1"
bitfld.long 0x7C 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x7C 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x7C 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x7C 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x7C 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x80 "GPIO31"
bitfld.long 0x80 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x80 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x80 6. "IE,Input enable" "0,1"
bitfld.long 0x80 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x80 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x80 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x80 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x80 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x84 "GPIO32"
bitfld.long 0x84 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x84 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x84 6. "IE,Input enable" "0,1"
bitfld.long 0x84 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x84 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x84 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x84 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x84 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x88 "GPIO33"
bitfld.long 0x88 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x88 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x88 6. "IE,Input enable" "0,1"
bitfld.long 0x88 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x88 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x88 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x88 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x88 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x8C "GPIO34"
bitfld.long 0x8C 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x8C 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x8C 6. "IE,Input enable" "0,1"
bitfld.long 0x8C 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x8C 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x8C 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x8C 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x8C 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x90 "GPIO35"
bitfld.long 0x90 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x90 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x90 6. "IE,Input enable" "0,1"
bitfld.long 0x90 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x90 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x90 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x90 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x90 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x94 "GPIO36"
bitfld.long 0x94 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x94 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x94 6. "IE,Input enable" "0,1"
bitfld.long 0x94 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x94 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x94 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x94 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x94 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x98 "GPIO37"
bitfld.long 0x98 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x98 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x98 6. "IE,Input enable" "0,1"
bitfld.long 0x98 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x98 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x98 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x98 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x98 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x9C "GPIO38"
bitfld.long 0x9C 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x9C 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x9C 6. "IE,Input enable" "0,1"
bitfld.long 0x9C 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x9C 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x9C 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x9C 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x9C 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xA0 "GPIO39"
bitfld.long 0xA0 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xA0 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xA0 6. "IE,Input enable" "0,1"
bitfld.long 0xA0 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xA0 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xA0 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xA0 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xA0 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xA4 "GPIO40"
bitfld.long 0xA4 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xA4 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xA4 6. "IE,Input enable" "0,1"
bitfld.long 0xA4 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xA4 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xA4 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xA4 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xA4 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xA8 "GPIO41"
bitfld.long 0xA8 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xA8 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xA8 6. "IE,Input enable" "0,1"
bitfld.long 0xA8 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xA8 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xA8 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xA8 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xA8 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xAC "GPIO42"
bitfld.long 0xAC 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xAC 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xAC 6. "IE,Input enable" "0,1"
bitfld.long 0xAC 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xAC 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xAC 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xAC 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xAC 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xB0 "GPIO43"
bitfld.long 0xB0 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xB0 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xB0 6. "IE,Input enable" "0,1"
bitfld.long 0xB0 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xB0 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xB0 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xB0 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xB0 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xB4 "GPIO44"
bitfld.long 0xB4 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xB4 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xB4 6. "IE,Input enable" "0,1"
bitfld.long 0xB4 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xB4 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xB4 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xB4 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xB4 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xB8 "GPIO45"
bitfld.long 0xB8 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xB8 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xB8 6. "IE,Input enable" "0,1"
bitfld.long 0xB8 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xB8 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xB8 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xB8 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xB8 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xBC "GPIO46"
bitfld.long 0xBC 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xBC 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xBC 6. "IE,Input enable" "0,1"
bitfld.long 0xBC 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xBC 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xBC 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xBC 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xBC 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xC0 "GPIO47"
bitfld.long 0xC0 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xC0 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xC0 6. "IE,Input enable" "0,1"
bitfld.long 0xC0 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xC0 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xC0 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xC0 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xC0 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xC4 "SWCLK"
bitfld.long 0xC4 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xC4 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xC4 6. "IE,Input enable" "0,1"
bitfld.long 0xC4 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xC4 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xC4 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xC4 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xC4 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xC8 "SWD"
bitfld.long 0xC8 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xC8 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xC8 6. "IE,Input enable" "0,1"
bitfld.long 0xC8 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xC8 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xC8 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xC8 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xC8 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
tree.end
tree "PADS_QSPI"
base ad:0x40040000
group.long 0x0++0x1B
line.long 0x0 "VOLTAGE_SELECT,Voltage select. Per bank control"
bitfld.long 0x0 0. "VOLTAGE_SELECT" "0: Set voltage to 3.3V (DVDD >= 2V5),1: Set voltage to 1.8V (DVDD <= 1V8)"
line.long 0x4 "GPIO_QSPI_SCLK"
bitfld.long 0x4 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x4 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x4 6. "IE,Input enable" "0,1"
bitfld.long 0x4 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x4 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x4 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x4 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x4 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x8 "GPIO_QSPI_SD0"
bitfld.long 0x8 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x8 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x8 6. "IE,Input enable" "0,1"
bitfld.long 0x8 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x8 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x8 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x8 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x8 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0xC "GPIO_QSPI_SD1"
bitfld.long 0xC 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0xC 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0xC 6. "IE,Input enable" "0,1"
bitfld.long 0xC 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0xC 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0xC 2. "PDE,Pull down enable" "0,1"
bitfld.long 0xC 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0xC 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x10 "GPIO_QSPI_SD2"
bitfld.long 0x10 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x10 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x10 6. "IE,Input enable" "0,1"
bitfld.long 0x10 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x10 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x10 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x10 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x10 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x14 "GPIO_QSPI_SD3"
bitfld.long 0x14 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x14 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x14 6. "IE,Input enable" "0,1"
bitfld.long 0x14 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x14 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x14 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x14 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x14 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
line.long 0x18 "GPIO_QSPI_SS"
bitfld.long 0x18 8. "ISO,Pad isolation control. Remove this once the pad is configured by software." "0,1"
bitfld.long 0x18 7. "OD,Output disable. Has priority over output enable from peripherals" "0,1"
bitfld.long 0x18 6. "IE,Input enable" "0,1"
bitfld.long 0x18 4.--5. "DRIVE,Drive strength." "0,1,2,3"
bitfld.long 0x18 3. "PUE,Pull up enable" "0,1"
newline
bitfld.long 0x18 2. "PDE,Pull down enable" "0,1"
bitfld.long 0x18 1. "SCHMITT,Enable schmitt trigger" "0,1"
bitfld.long 0x18 0. "SLEWFAST,Slew rate control. 1 = Fast 0 = Slow" "0: Slow,1: Fast"
tree.end
tree.end
tree "SIO (Single-Cycle IO)"
tree "SIO"
base ad:0xD0000000
rgroup.long 0x0++0xB
line.long 0x0 "CPUID,Processor core identifier"
hexmask.long 0x0 0.--31. 1. "CPUID,Value is 0 when read from processor core 0 and 1 when read from processor core 1."
line.long 0x4 "GPIO_IN,Input value for GPIO0...31."
hexmask.long 0x4 0.--31. 1. "GPIO_IN"
line.long 0x8 "GPIO_HI_IN,Input value on GPIO32...47. QSPI IOs and USB pins"
hexmask.long.byte 0x8 28.--31. 1. "QSPI_SD,Input value on QSPI SD0 (MOSI) SD1 (MISO) SD2 and SD3 pins"
bitfld.long 0x8 27. "QSPI_CSN,Input value on QSPI CSn pin" "0,1"
bitfld.long 0x8 26. "QSPI_SCK,Input value on QSPI SCK pin" "0,1"
newline
bitfld.long 0x8 25. "USB_DM,Input value on USB D- pin" "0,1"
bitfld.long 0x8 24. "USB_DP,Input value on USB D+ pin" "0,1"
hexmask.long.word 0x8 0.--15. 1. "GPIO,Input value on GPIO32...47"
group.long 0x10++0x7
line.long 0x0 "GPIO_OUT,GPIO0...31 output value"
hexmask.long 0x0 0.--31. 1. "GPIO_OUT,Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written NOT the input value from the pins."
line.long 0x4 "GPIO_HI_OUT,Output value for GPIO32...47. QSPI IOs and USB pins."
hexmask.long.byte 0x4 28.--31. 1. "QSPI_SD,Output value for QSPI SD0 (MOSI) SD1 (MISO) SD2 and SD3 pins"
bitfld.long 0x4 27. "QSPI_CSN,Output value for QSPI CSn pin" "0,1"
bitfld.long 0x4 26. "QSPI_SCK,Output value for QSPI SCK pin" "0,1"
newline
bitfld.long 0x4 25. "USB_DM,Output value for USB D- pin" "0,1"
bitfld.long 0x4 24. "USB_DP,Output value for USB D+ pin" "0,1"
hexmask.long.word 0x4 0.--15. 1. "GPIO,Output value for GPIO32...47"
wgroup.long 0x18++0x17
line.long 0x0 "GPIO_OUT_SET,GPIO0...31 output value set"
hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Perform an atomic bit-set on GPIO_OUT i.e. `GPIO_OUT |= wdata`"
line.long 0x4 "GPIO_HI_OUT_SET,Output value set for GPIO32..47. QSPI IOs and USB pins."
hexmask.long.byte 0x4 28.--31. 1. "QSPI_SD"
bitfld.long 0x4 27. "QSPI_CSN" "0,1"
bitfld.long 0x4 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0x4 25. "USB_DM" "0,1"
bitfld.long 0x4 24. "USB_DP" "0,1"
hexmask.long.word 0x4 0.--15. 1. "GPIO"
line.long 0x8 "GPIO_OUT_CLR,GPIO0...31 output value clear"
hexmask.long 0x8 0.--31. 1. "GPIO_OUT_CLR,Perform an atomic bit-clear on GPIO_OUT i.e. `GPIO_OUT &= ~wdata`"
line.long 0xC "GPIO_HI_OUT_CLR,Output value clear for GPIO32..47. QSPI IOs and USB pins."
hexmask.long.byte 0xC 28.--31. 1. "QSPI_SD"
bitfld.long 0xC 27. "QSPI_CSN" "0,1"
bitfld.long 0xC 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0xC 25. "USB_DM" "0,1"
bitfld.long 0xC 24. "USB_DP" "0,1"
hexmask.long.word 0xC 0.--15. 1. "GPIO"
line.long 0x10 "GPIO_OUT_XOR,GPIO0...31 output value XOR"
hexmask.long 0x10 0.--31. 1. "GPIO_OUT_XOR,Perform an atomic bitwise XOR on GPIO_OUT i.e. `GPIO_OUT ^= wdata`"
line.long 0x14 "GPIO_HI_OUT_XOR,Output value XOR for GPIO32..47. QSPI IOs and USB pins."
hexmask.long.byte 0x14 28.--31. 1. "QSPI_SD"
bitfld.long 0x14 27. "QSPI_CSN" "0,1"
bitfld.long 0x14 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0x14 25. "USB_DM" "0,1"
bitfld.long 0x14 24. "USB_DP" "0,1"
hexmask.long.word 0x14 0.--15. 1. "GPIO"
group.long 0x30++0x7
line.long 0x0 "GPIO_OE,GPIO0...31 output enable"
hexmask.long 0x0 0.--31. 1. "GPIO_OE,Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written."
line.long 0x4 "GPIO_HI_OE,Output enable value for GPIO32...47. QSPI IOs and USB pins."
hexmask.long.byte 0x4 28.--31. 1. "QSPI_SD,Output enable value for QSPI SD0 (MOSI) SD1 (MISO) SD2 and SD3 pins"
bitfld.long 0x4 27. "QSPI_CSN,Output enable value for QSPI CSn pin" "0,1"
bitfld.long 0x4 26. "QSPI_SCK,Output enable value for QSPI SCK pin" "0,1"
newline
bitfld.long 0x4 25. "USB_DM,Output enable value for USB D- pin" "0,1"
bitfld.long 0x4 24. "USB_DP,Output enable value for USB D+ pin" "0,1"
hexmask.long.word 0x4 0.--15. 1. "GPIO,Output enable value for GPIO32...47"
wgroup.long 0x38++0x17
line.long 0x0 "GPIO_OE_SET,GPIO0...31 output enable set"
hexmask.long 0x0 0.--31. 1. "GPIO_OE_SET,Perform an atomic bit-set on GPIO_OE i.e. `GPIO_OE |= wdata`"
line.long 0x4 "GPIO_HI_OE_SET,Output enable set for GPIO32...47. QSPI IOs and USB pins."
hexmask.long.byte 0x4 28.--31. 1. "QSPI_SD"
bitfld.long 0x4 27. "QSPI_CSN" "0,1"
bitfld.long 0x4 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0x4 25. "USB_DM" "0,1"
bitfld.long 0x4 24. "USB_DP" "0,1"
hexmask.long.word 0x4 0.--15. 1. "GPIO"
line.long 0x8 "GPIO_OE_CLR,GPIO0...31 output enable clear"
hexmask.long 0x8 0.--31. 1. "GPIO_OE_CLR,Perform an atomic bit-clear on GPIO_OE i.e. `GPIO_OE &= ~wdata`"
line.long 0xC "GPIO_HI_OE_CLR,Output enable clear for GPIO32...47. QSPI IOs and USB pins."
hexmask.long.byte 0xC 28.--31. 1. "QSPI_SD"
bitfld.long 0xC 27. "QSPI_CSN" "0,1"
bitfld.long 0xC 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0xC 25. "USB_DM" "0,1"
bitfld.long 0xC 24. "USB_DP" "0,1"
hexmask.long.word 0xC 0.--15. 1. "GPIO"
line.long 0x10 "GPIO_OE_XOR,GPIO0...31 output enable XOR"
hexmask.long 0x10 0.--31. 1. "GPIO_OE_XOR,Perform an atomic bitwise XOR on GPIO_OE i.e. `GPIO_OE ^= wdata`"
line.long 0x14 "GPIO_HI_OE_XOR,Output enable XOR for GPIO32...47. QSPI IOs and USB pins."
hexmask.long.byte 0x14 28.--31. 1. "QSPI_SD"
bitfld.long 0x14 27. "QSPI_CSN" "0,1"
bitfld.long 0x14 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0x14 25. "USB_DM" "0,1"
bitfld.long 0x14 24. "USB_DP" "0,1"
hexmask.long.word 0x14 0.--15. 1. "GPIO"
group.long 0x50++0x3
line.long 0x0 "FIFO_ST,Status register for inter-core FIFOs (mailboxes)."
eventfld.long 0x0 3. "ROE,Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO." "0,1"
eventfld.long 0x0 2. "WOF,Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO." "0,1"
rbitfld.long 0x0 1. "RDY,Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)" "0,1"
newline
rbitfld.long 0x0 0. "VLD,Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)" "0,1"
wgroup.long 0x54++0x3
line.long 0x0 "FIFO_WR,Write access to this core's TX FIFO"
hexmask.long 0x0 0.--31. 1. "FIFO_WR"
rgroup.long 0x58++0x7
line.long 0x0 "FIFO_RD,Read access to this core's RX FIFO"
hexmask.long 0x0 0.--31. 1. "FIFO_RD"
line.long 0x4 "SPINLOCK_ST,Spinlock state"
hexmask.long 0x4 0.--31. 1. "SPINLOCK_ST"
group.long 0x80++0x13
line.long 0x0 "INTERP0_ACCUM0,Read/write access to accumulator 0"
hexmask.long 0x0 0.--31. 1. "INTERP0_ACCUM0"
line.long 0x4 "INTERP0_ACCUM1,Read/write access to accumulator 1"
hexmask.long 0x4 0.--31. 1. "INTERP0_ACCUM1"
line.long 0x8 "INTERP0_BASE0,Read/write access to BASE0 register."
hexmask.long 0x8 0.--31. 1. "INTERP0_BASE0"
line.long 0xC "INTERP0_BASE1,Read/write access to BASE1 register."
hexmask.long 0xC 0.--31. 1. "INTERP0_BASE1"
line.long 0x10 "INTERP0_BASE2,Read/write access to BASE2 register."
hexmask.long 0x10 0.--31. 1. "INTERP0_BASE2"
rgroup.long 0x94++0x17
line.long 0x0 "INTERP0_POP_LANE0,Read LANE0 result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x0 0.--31. 1. "INTERP0_POP_LANE0"
line.long 0x4 "INTERP0_POP_LANE1,Read LANE1 result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x4 0.--31. 1. "INTERP0_POP_LANE1"
line.long 0x8 "INTERP0_POP_FULL,Read FULL result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x8 0.--31. 1. "INTERP0_POP_FULL"
line.long 0xC "INTERP0_PEEK_LANE0,Read LANE0 result. without altering any internal state (PEEK)."
hexmask.long 0xC 0.--31. 1. "INTERP0_PEEK_LANE0"
line.long 0x10 "INTERP0_PEEK_LANE1,Read LANE1 result. without altering any internal state (PEEK)."
hexmask.long 0x10 0.--31. 1. "INTERP0_PEEK_LANE1"
line.long 0x14 "INTERP0_PEEK_FULL,Read FULL result. without altering any internal state (PEEK)."
hexmask.long 0x14 0.--31. 1. "INTERP0_PEEK_FULL"
group.long 0xAC++0xF
line.long 0x0 "INTERP0_CTRL_LANE0,Control register for lane 0"
rbitfld.long 0x0 25. "OVERF,Set if either OVERF0 or OVERF1 is set." "0,1"
rbitfld.long 0x0 24. "OVERF1,Indicates if any masked-off MSBs in ACCUM1 are set." "0,1"
rbitfld.long 0x0 23. "OVERF0,Indicates if any masked-off MSBs in ACCUM0 are set." "0,1"
newline
bitfld.long 0x0 21. "BLEND,Only present on INTERP0 on each core. If BLEND mode is enabled:" "0,1"
bitfld.long 0x0 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus." "0,1,2,3"
bitfld.long 0x0 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE0 result. This does not affect FULL result." "0,1"
newline
bitfld.long 0x0 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP." "0,1"
bitfld.long 0x0 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware." "0,1"
bitfld.long 0x0 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits" "0,1"
newline
hexmask.long.byte 0x0 10.--14. 1. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x0 5.--9. 1. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x0 0.--4. 1. "SHIFT,Right-rotate applied to accumulator before masking. By appropriately configuring the masks left and right shifts can be synthesised."
line.long 0x4 "INTERP0_CTRL_LANE1,Control register for lane 1"
bitfld.long 0x4 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus." "0,1,2,3"
bitfld.long 0x4 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE1 result. This does not affect FULL result." "0,1"
bitfld.long 0x4 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP." "0,1"
newline
bitfld.long 0x4 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware." "0,1"
bitfld.long 0x4 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits" "0,1"
hexmask.long.byte 0x4 10.--14. 1. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)"
newline
hexmask.long.byte 0x4 5.--9. 1. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x4 0.--4. 1. "SHIFT,Right-rotate applied to accumulator before masking. By appropriately configuring the masks left and right shifts can be synthesised."
line.long 0x8 "INTERP0_ACCUM0_ADD,Values written here are atomically added to ACCUM0"
hexmask.long.tbyte 0x8 0.--23. 1. "INTERP0_ACCUM0_ADD"
line.long 0xC "INTERP0_ACCUM1_ADD,Values written here are atomically added to ACCUM1"
hexmask.long.tbyte 0xC 0.--23. 1. "INTERP0_ACCUM1_ADD"
wgroup.long 0xBC++0x3
line.long 0x0 "INTERP0_BASE_1AND0,On write. the lower 16 bits go to BASE0. upper bits to BASE1 simultaneously."
hexmask.long 0x0 0.--31. 1. "INTERP0_BASE_1AND0"
group.long 0xC0++0x13
line.long 0x0 "INTERP1_ACCUM0,Read/write access to accumulator 0"
hexmask.long 0x0 0.--31. 1. "INTERP1_ACCUM0"
line.long 0x4 "INTERP1_ACCUM1,Read/write access to accumulator 1"
hexmask.long 0x4 0.--31. 1. "INTERP1_ACCUM1"
line.long 0x8 "INTERP1_BASE0,Read/write access to BASE0 register."
hexmask.long 0x8 0.--31. 1. "INTERP1_BASE0"
line.long 0xC "INTERP1_BASE1,Read/write access to BASE1 register."
hexmask.long 0xC 0.--31. 1. "INTERP1_BASE1"
line.long 0x10 "INTERP1_BASE2,Read/write access to BASE2 register."
hexmask.long 0x10 0.--31. 1. "INTERP1_BASE2"
rgroup.long 0xD4++0x17
line.long 0x0 "INTERP1_POP_LANE0,Read LANE0 result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x0 0.--31. 1. "INTERP1_POP_LANE0"
line.long 0x4 "INTERP1_POP_LANE1,Read LANE1 result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x4 0.--31. 1. "INTERP1_POP_LANE1"
line.long 0x8 "INTERP1_POP_FULL,Read FULL result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x8 0.--31. 1. "INTERP1_POP_FULL"
line.long 0xC "INTERP1_PEEK_LANE0,Read LANE0 result. without altering any internal state (PEEK)."
hexmask.long 0xC 0.--31. 1. "INTERP1_PEEK_LANE0"
line.long 0x10 "INTERP1_PEEK_LANE1,Read LANE1 result. without altering any internal state (PEEK)."
hexmask.long 0x10 0.--31. 1. "INTERP1_PEEK_LANE1"
line.long 0x14 "INTERP1_PEEK_FULL,Read FULL result. without altering any internal state (PEEK)."
hexmask.long 0x14 0.--31. 1. "INTERP1_PEEK_FULL"
group.long 0xEC++0xF
line.long 0x0 "INTERP1_CTRL_LANE0,Control register for lane 0"
rbitfld.long 0x0 25. "OVERF,Set if either OVERF0 or OVERF1 is set." "0,1"
rbitfld.long 0x0 24. "OVERF1,Indicates if any masked-off MSBs in ACCUM1 are set." "0,1"
rbitfld.long 0x0 23. "OVERF0,Indicates if any masked-off MSBs in ACCUM0 are set." "0,1"
newline
bitfld.long 0x0 22. "CLAMP,Only present on INTERP1 on each core. If CLAMP mode is enabled:" "0,1"
bitfld.long 0x0 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus." "0,1,2,3"
bitfld.long 0x0 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE0 result. This does not affect FULL result." "0,1"
newline
bitfld.long 0x0 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP." "0,1"
bitfld.long 0x0 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware." "0,1"
bitfld.long 0x0 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits" "0,1"
newline
hexmask.long.byte 0x0 10.--14. 1. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x0 5.--9. 1. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x0 0.--4. 1. "SHIFT,Right-rotate applied to accumulator before masking. By appropriately configuring the masks left and right shifts can be synthesised."
line.long 0x4 "INTERP1_CTRL_LANE1,Control register for lane 1"
bitfld.long 0x4 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus." "0,1,2,3"
bitfld.long 0x4 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE1 result. This does not affect FULL result." "0,1"
bitfld.long 0x4 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP." "0,1"
newline
bitfld.long 0x4 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware." "0,1"
bitfld.long 0x4 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits" "0,1"
hexmask.long.byte 0x4 10.--14. 1. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)"
newline
hexmask.long.byte 0x4 5.--9. 1. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x4 0.--4. 1. "SHIFT,Right-rotate applied to accumulator before masking. By appropriately configuring the masks left and right shifts can be synthesised."
line.long 0x8 "INTERP1_ACCUM0_ADD,Values written here are atomically added to ACCUM0"
hexmask.long.tbyte 0x8 0.--23. 1. "INTERP1_ACCUM0_ADD"
line.long 0xC "INTERP1_ACCUM1_ADD,Values written here are atomically added to ACCUM1"
hexmask.long.tbyte 0xC 0.--23. 1. "INTERP1_ACCUM1_ADD"
wgroup.long 0xFC++0x3
line.long 0x0 "INTERP1_BASE_1AND0,On write. the lower 16 bits go to BASE0. upper bits to BASE1 simultaneously."
hexmask.long 0x0 0.--31. 1. "INTERP1_BASE_1AND0"
group.long 0x100++0x93
line.long 0x0 "SPINLOCK0,Reading from a spinlock address will:"
hexmask.long 0x0 0.--31. 1. "SPINLOCK0"
line.long 0x4 "SPINLOCK1,Reading from a spinlock address will:"
hexmask.long 0x4 0.--31. 1. "SPINLOCK1"
line.long 0x8 "SPINLOCK2,Reading from a spinlock address will:"
hexmask.long 0x8 0.--31. 1. "SPINLOCK2"
line.long 0xC "SPINLOCK3,Reading from a spinlock address will:"
hexmask.long 0xC 0.--31. 1. "SPINLOCK3"
line.long 0x10 "SPINLOCK4,Reading from a spinlock address will:"
hexmask.long 0x10 0.--31. 1. "SPINLOCK4"
line.long 0x14 "SPINLOCK5,Reading from a spinlock address will:"
hexmask.long 0x14 0.--31. 1. "SPINLOCK5"
line.long 0x18 "SPINLOCK6,Reading from a spinlock address will:"
hexmask.long 0x18 0.--31. 1. "SPINLOCK6"
line.long 0x1C "SPINLOCK7,Reading from a spinlock address will:"
hexmask.long 0x1C 0.--31. 1. "SPINLOCK7"
line.long 0x20 "SPINLOCK8,Reading from a spinlock address will:"
hexmask.long 0x20 0.--31. 1. "SPINLOCK8"
line.long 0x24 "SPINLOCK9,Reading from a spinlock address will:"
hexmask.long 0x24 0.--31. 1. "SPINLOCK9"
line.long 0x28 "SPINLOCK10,Reading from a spinlock address will:"
hexmask.long 0x28 0.--31. 1. "SPINLOCK10"
line.long 0x2C "SPINLOCK11,Reading from a spinlock address will:"
hexmask.long 0x2C 0.--31. 1. "SPINLOCK11"
line.long 0x30 "SPINLOCK12,Reading from a spinlock address will:"
hexmask.long 0x30 0.--31. 1. "SPINLOCK12"
line.long 0x34 "SPINLOCK13,Reading from a spinlock address will:"
hexmask.long 0x34 0.--31. 1. "SPINLOCK13"
line.long 0x38 "SPINLOCK14,Reading from a spinlock address will:"
hexmask.long 0x38 0.--31. 1. "SPINLOCK14"
line.long 0x3C "SPINLOCK15,Reading from a spinlock address will:"
hexmask.long 0x3C 0.--31. 1. "SPINLOCK15"
line.long 0x40 "SPINLOCK16,Reading from a spinlock address will:"
hexmask.long 0x40 0.--31. 1. "SPINLOCK16"
line.long 0x44 "SPINLOCK17,Reading from a spinlock address will:"
hexmask.long 0x44 0.--31. 1. "SPINLOCK17"
line.long 0x48 "SPINLOCK18,Reading from a spinlock address will:"
hexmask.long 0x48 0.--31. 1. "SPINLOCK18"
line.long 0x4C "SPINLOCK19,Reading from a spinlock address will:"
hexmask.long 0x4C 0.--31. 1. "SPINLOCK19"
line.long 0x50 "SPINLOCK20,Reading from a spinlock address will:"
hexmask.long 0x50 0.--31. 1. "SPINLOCK20"
line.long 0x54 "SPINLOCK21,Reading from a spinlock address will:"
hexmask.long 0x54 0.--31. 1. "SPINLOCK21"
line.long 0x58 "SPINLOCK22,Reading from a spinlock address will:"
hexmask.long 0x58 0.--31. 1. "SPINLOCK22"
line.long 0x5C "SPINLOCK23,Reading from a spinlock address will:"
hexmask.long 0x5C 0.--31. 1. "SPINLOCK23"
line.long 0x60 "SPINLOCK24,Reading from a spinlock address will:"
hexmask.long 0x60 0.--31. 1. "SPINLOCK24"
line.long 0x64 "SPINLOCK25,Reading from a spinlock address will:"
hexmask.long 0x64 0.--31. 1. "SPINLOCK25"
line.long 0x68 "SPINLOCK26,Reading from a spinlock address will:"
hexmask.long 0x68 0.--31. 1. "SPINLOCK26"
line.long 0x6C "SPINLOCK27,Reading from a spinlock address will:"
hexmask.long 0x6C 0.--31. 1. "SPINLOCK27"
line.long 0x70 "SPINLOCK28,Reading from a spinlock address will:"
hexmask.long 0x70 0.--31. 1. "SPINLOCK28"
line.long 0x74 "SPINLOCK29,Reading from a spinlock address will:"
hexmask.long 0x74 0.--31. 1. "SPINLOCK29"
line.long 0x78 "SPINLOCK30,Reading from a spinlock address will:"
hexmask.long 0x78 0.--31. 1. "SPINLOCK30"
line.long 0x7C "SPINLOCK31,Reading from a spinlock address will:"
hexmask.long 0x7C 0.--31. 1. "SPINLOCK31"
line.long 0x80 "DOORBELL_OUT_SET,Trigger a doorbell interrupt on the opposite core."
hexmask.long.byte 0x80 0.--7. 1. "DOORBELL_OUT_SET"
line.long 0x84 "DOORBELL_OUT_CLR,Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes."
hexmask.long.byte 0x84 0.--7. 1. "DOORBELL_OUT_CLR"
line.long 0x88 "DOORBELL_IN_SET,Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core."
hexmask.long.byte 0x88 0.--7. 1. "DOORBELL_IN_SET"
line.long 0x8C "DOORBELL_IN_CLR,Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1."
hexmask.long.byte 0x8C 0.--7. 1. "DOORBELL_IN_CLR"
line.long 0x90 "PERI_NONSEC,Detach certain core-local peripherals from Secure SIO. and attach them to Non-secure SIO. so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO..."
bitfld.long 0x90 5. "TMDS,IF 1 detach TMDS encoder (of this core) from the Secure SIO and attach to the Non-secure SIO." "0,1"
bitfld.long 0x90 1. "INTERP1,If 1 detach interpolator 1 (of this core) from the Secure SIO and attach to the Non-secure SIO." "0,1"
bitfld.long 0x90 0. "INTERP0,If 1 detach interpolator 0 (of this core) from the Secure SIO and attach to the Non-secure SIO." "0,1"
group.long 0x1A0++0x7
line.long 0x0 "RISCV_SOFTIRQ,Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores."
bitfld.long 0x0 9. "CORE1_CLR,Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag." "0,1"
bitfld.long 0x0 8. "CORE0_CLR,Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag." "0,1"
bitfld.long 0x0 1. "CORE1_SET,Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag." "0,1"
newline
bitfld.long 0x0 0. "CORE0_SET,Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag." "0,1"
line.long 0x4 "MTIME_CTRL,Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO. so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode."
bitfld.long 0x4 3. "DBGPAUSE_CORE1,If 1 the timer pauses when core 1 is in the debug halt state." "0,1"
bitfld.long 0x4 2. "DBGPAUSE_CORE0,If 1 the timer pauses when core 0 is in the debug halt state." "0,1"
bitfld.long 0x4 1. "FULLSPEED,If 1 increment the timer every cycle (i.e. run directly from the system clock) rather than incrementing on the system-level timer tick input." "0,1"
newline
bitfld.long 0x4 0. "EN,Timer enable bit. When 0 the timer will not increment automatically." "0,1"
group.long 0x1B0++0x13
line.long 0x0 "MTIME,Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle. core 1 takes precedence."
hexmask.long 0x0 0.--31. 1. "MTIME"
line.long 0x4 "MTIMEH,Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle. core 1 takes precedence."
hexmask.long 0x4 0.--31. 1. "MTIMEH"
line.long 0x8 "MTIMECMP,Low half of RISC-V Machine-mode timer comparator. This register is core-local. i.e.. each core gets a copy of this register. with the comparison result routed to its own interrupt line."
hexmask.long 0x8 0.--31. 1. "MTIMECMP"
line.long 0xC "MTIMECMPH,High half of RISC-V Machine-mode timer comparator. This register is core-local."
hexmask.long 0xC 0.--31. 1. "MTIMECMPH"
line.long 0x10 "TMDS_CTRL,Control register for TMDS encoder."
bitfld.long 0x10 28. "CLEAR_BALANCE,Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline." "0,1"
bitfld.long 0x10 27. "PIX2_NOSHIFT,When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register) the second encoder sees a shifted version of the colour data register." "0,1"
bitfld.long 0x10 24.--26. "PIX_SHIFT,Shift applied to the colour data register with each read of a POP alias register." "0: Do not shift the colour data register.,1: Shift the colour data register by 1 bit,2: Shift the colour data register by 2 bits,3: Shift the colour data register by 4 bits,4: Shift the colour data register by 8 bits,5: Shift the colour data register by 16 bits,?,?"
newline
bitfld.long 0x10 23. "INTERLEAVE,Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE." "0,1"
bitfld.long 0x10 18.--20. "L2_NBITS,Number of valid colour MSBs for lane 2 (1-8 bits encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 15.--17. "L1_NBITS,Number of valid colour MSBs for lane 1 (1-8 bits encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 12.--14. "L0_NBITS,Number of valid colour MSBs for lane 0 (1-8 bits encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 8.--11. 1. "L2_ROT,Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input."
hexmask.long.byte 0x10 4.--7. 1. "L1_ROT,Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input."
newline
hexmask.long.byte 0x10 0.--3. 1. "L0_ROT,Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input."
wgroup.long 0x1C4++0x3
line.long 0x0 "TMDS_WDATA,Write-only access to the TMDS colour data register."
hexmask.long 0x0 0.--31. 1. "TMDS_WDATA"
rgroup.long 0x1C8++0x1F
line.long 0x0 "TMDS_PEEK_SINGLE,Get the encoding of one pixel's worth of colour data. packed into a 32-bit value (3x10-bit symbols)."
hexmask.long 0x0 0.--31. 1. "TMDS_PEEK_SINGLE"
line.long 0x4 "TMDS_POP_SINGLE,Get the encoding of one pixel's worth of colour data. packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for.."
hexmask.long 0x4 0.--31. 1. "TMDS_POP_SINGLE"
line.long 0x8 "TMDS_PEEK_DOUBLE_L0,Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0x8 0.--31. 1. "TMDS_PEEK_DOUBLE_L0"
line.long 0xC "TMDS_POP_DOUBLE_L0,Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0xC 0.--31. 1. "TMDS_POP_DOUBLE_L0"
line.long 0x10 "TMDS_PEEK_DOUBLE_L1,Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0x10 0.--31. 1. "TMDS_PEEK_DOUBLE_L1"
line.long 0x14 "TMDS_POP_DOUBLE_L1,Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0x14 0.--31. 1. "TMDS_POP_DOUBLE_L1"
line.long 0x18 "TMDS_PEEK_DOUBLE_L2,Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0x18 0.--31. 1. "TMDS_PEEK_DOUBLE_L2"
line.long 0x1C "TMDS_POP_DOUBLE_L2,Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0x1C 0.--31. 1. "TMDS_POP_DOUBLE_L2"
tree.end
tree "SIO_NS"
base ad:0xD0020000
rgroup.long 0x0++0xB
line.long 0x0 "CPUID,Processor core identifier"
hexmask.long 0x0 0.--31. 1. "CPUID,Value is 0 when read from processor core 0 and 1 when read from processor core 1."
line.long 0x4 "GPIO_IN,Input value for GPIO0...31."
hexmask.long 0x4 0.--31. 1. "GPIO_IN"
line.long 0x8 "GPIO_HI_IN,Input value on GPIO32...47. QSPI IOs and USB pins"
hexmask.long.byte 0x8 28.--31. 1. "QSPI_SD,Input value on QSPI SD0 (MOSI) SD1 (MISO) SD2 and SD3 pins"
bitfld.long 0x8 27. "QSPI_CSN,Input value on QSPI CSn pin" "0,1"
bitfld.long 0x8 26. "QSPI_SCK,Input value on QSPI SCK pin" "0,1"
newline
bitfld.long 0x8 25. "USB_DM,Input value on USB D- pin" "0,1"
bitfld.long 0x8 24. "USB_DP,Input value on USB D+ pin" "0,1"
hexmask.long.word 0x8 0.--15. 1. "GPIO,Input value on GPIO32...47"
group.long 0x10++0x7
line.long 0x0 "GPIO_OUT,GPIO0...31 output value"
hexmask.long 0x0 0.--31. 1. "GPIO_OUT,Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written NOT the input value from the pins."
line.long 0x4 "GPIO_HI_OUT,Output value for GPIO32...47. QSPI IOs and USB pins."
hexmask.long.byte 0x4 28.--31. 1. "QSPI_SD,Output value for QSPI SD0 (MOSI) SD1 (MISO) SD2 and SD3 pins"
bitfld.long 0x4 27. "QSPI_CSN,Output value for QSPI CSn pin" "0,1"
bitfld.long 0x4 26. "QSPI_SCK,Output value for QSPI SCK pin" "0,1"
newline
bitfld.long 0x4 25. "USB_DM,Output value for USB D- pin" "0,1"
bitfld.long 0x4 24. "USB_DP,Output value for USB D+ pin" "0,1"
hexmask.long.word 0x4 0.--15. 1. "GPIO,Output value for GPIO32...47"
wgroup.long 0x18++0x17
line.long 0x0 "GPIO_OUT_SET,GPIO0...31 output value set"
hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Perform an atomic bit-set on GPIO_OUT i.e. `GPIO_OUT |= wdata`"
line.long 0x4 "GPIO_HI_OUT_SET,Output value set for GPIO32..47. QSPI IOs and USB pins."
hexmask.long.byte 0x4 28.--31. 1. "QSPI_SD"
bitfld.long 0x4 27. "QSPI_CSN" "0,1"
bitfld.long 0x4 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0x4 25. "USB_DM" "0,1"
bitfld.long 0x4 24. "USB_DP" "0,1"
hexmask.long.word 0x4 0.--15. 1. "GPIO"
line.long 0x8 "GPIO_OUT_CLR,GPIO0...31 output value clear"
hexmask.long 0x8 0.--31. 1. "GPIO_OUT_CLR,Perform an atomic bit-clear on GPIO_OUT i.e. `GPIO_OUT &= ~wdata`"
line.long 0xC "GPIO_HI_OUT_CLR,Output value clear for GPIO32..47. QSPI IOs and USB pins."
hexmask.long.byte 0xC 28.--31. 1. "QSPI_SD"
bitfld.long 0xC 27. "QSPI_CSN" "0,1"
bitfld.long 0xC 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0xC 25. "USB_DM" "0,1"
bitfld.long 0xC 24. "USB_DP" "0,1"
hexmask.long.word 0xC 0.--15. 1. "GPIO"
line.long 0x10 "GPIO_OUT_XOR,GPIO0...31 output value XOR"
hexmask.long 0x10 0.--31. 1. "GPIO_OUT_XOR,Perform an atomic bitwise XOR on GPIO_OUT i.e. `GPIO_OUT ^= wdata`"
line.long 0x14 "GPIO_HI_OUT_XOR,Output value XOR for GPIO32..47. QSPI IOs and USB pins."
hexmask.long.byte 0x14 28.--31. 1. "QSPI_SD"
bitfld.long 0x14 27. "QSPI_CSN" "0,1"
bitfld.long 0x14 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0x14 25. "USB_DM" "0,1"
bitfld.long 0x14 24. "USB_DP" "0,1"
hexmask.long.word 0x14 0.--15. 1. "GPIO"
group.long 0x30++0x7
line.long 0x0 "GPIO_OE,GPIO0...31 output enable"
hexmask.long 0x0 0.--31. 1. "GPIO_OE,Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written."
line.long 0x4 "GPIO_HI_OE,Output enable value for GPIO32...47. QSPI IOs and USB pins."
hexmask.long.byte 0x4 28.--31. 1. "QSPI_SD,Output enable value for QSPI SD0 (MOSI) SD1 (MISO) SD2 and SD3 pins"
bitfld.long 0x4 27. "QSPI_CSN,Output enable value for QSPI CSn pin" "0,1"
bitfld.long 0x4 26. "QSPI_SCK,Output enable value for QSPI SCK pin" "0,1"
newline
bitfld.long 0x4 25. "USB_DM,Output enable value for USB D- pin" "0,1"
bitfld.long 0x4 24. "USB_DP,Output enable value for USB D+ pin" "0,1"
hexmask.long.word 0x4 0.--15. 1. "GPIO,Output enable value for GPIO32...47"
wgroup.long 0x38++0x17
line.long 0x0 "GPIO_OE_SET,GPIO0...31 output enable set"
hexmask.long 0x0 0.--31. 1. "GPIO_OE_SET,Perform an atomic bit-set on GPIO_OE i.e. `GPIO_OE |= wdata`"
line.long 0x4 "GPIO_HI_OE_SET,Output enable set for GPIO32...47. QSPI IOs and USB pins."
hexmask.long.byte 0x4 28.--31. 1. "QSPI_SD"
bitfld.long 0x4 27. "QSPI_CSN" "0,1"
bitfld.long 0x4 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0x4 25. "USB_DM" "0,1"
bitfld.long 0x4 24. "USB_DP" "0,1"
hexmask.long.word 0x4 0.--15. 1. "GPIO"
line.long 0x8 "GPIO_OE_CLR,GPIO0...31 output enable clear"
hexmask.long 0x8 0.--31. 1. "GPIO_OE_CLR,Perform an atomic bit-clear on GPIO_OE i.e. `GPIO_OE &= ~wdata`"
line.long 0xC "GPIO_HI_OE_CLR,Output enable clear for GPIO32...47. QSPI IOs and USB pins."
hexmask.long.byte 0xC 28.--31. 1. "QSPI_SD"
bitfld.long 0xC 27. "QSPI_CSN" "0,1"
bitfld.long 0xC 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0xC 25. "USB_DM" "0,1"
bitfld.long 0xC 24. "USB_DP" "0,1"
hexmask.long.word 0xC 0.--15. 1. "GPIO"
line.long 0x10 "GPIO_OE_XOR,GPIO0...31 output enable XOR"
hexmask.long 0x10 0.--31. 1. "GPIO_OE_XOR,Perform an atomic bitwise XOR on GPIO_OE i.e. `GPIO_OE ^= wdata`"
line.long 0x14 "GPIO_HI_OE_XOR,Output enable XOR for GPIO32...47. QSPI IOs and USB pins."
hexmask.long.byte 0x14 28.--31. 1. "QSPI_SD"
bitfld.long 0x14 27. "QSPI_CSN" "0,1"
bitfld.long 0x14 26. "QSPI_SCK" "0,1"
newline
bitfld.long 0x14 25. "USB_DM" "0,1"
bitfld.long 0x14 24. "USB_DP" "0,1"
hexmask.long.word 0x14 0.--15. 1. "GPIO"
group.long 0x50++0x3
line.long 0x0 "FIFO_ST,Status register for inter-core FIFOs (mailboxes)."
eventfld.long 0x0 3. "ROE,Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO." "0,1"
eventfld.long 0x0 2. "WOF,Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO." "0,1"
rbitfld.long 0x0 1. "RDY,Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)" "0,1"
newline
rbitfld.long 0x0 0. "VLD,Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)" "0,1"
wgroup.long 0x54++0x3
line.long 0x0 "FIFO_WR,Write access to this core's TX FIFO"
hexmask.long 0x0 0.--31. 1. "FIFO_WR"
rgroup.long 0x58++0x7
line.long 0x0 "FIFO_RD,Read access to this core's RX FIFO"
hexmask.long 0x0 0.--31. 1. "FIFO_RD"
line.long 0x4 "SPINLOCK_ST,Spinlock state"
hexmask.long 0x4 0.--31. 1. "SPINLOCK_ST"
group.long 0x80++0x13
line.long 0x0 "INTERP0_ACCUM0,Read/write access to accumulator 0"
hexmask.long 0x0 0.--31. 1. "INTERP0_ACCUM0"
line.long 0x4 "INTERP0_ACCUM1,Read/write access to accumulator 1"
hexmask.long 0x4 0.--31. 1. "INTERP0_ACCUM1"
line.long 0x8 "INTERP0_BASE0,Read/write access to BASE0 register."
hexmask.long 0x8 0.--31. 1. "INTERP0_BASE0"
line.long 0xC "INTERP0_BASE1,Read/write access to BASE1 register."
hexmask.long 0xC 0.--31. 1. "INTERP0_BASE1"
line.long 0x10 "INTERP0_BASE2,Read/write access to BASE2 register."
hexmask.long 0x10 0.--31. 1. "INTERP0_BASE2"
rgroup.long 0x94++0x17
line.long 0x0 "INTERP0_POP_LANE0,Read LANE0 result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x0 0.--31. 1. "INTERP0_POP_LANE0"
line.long 0x4 "INTERP0_POP_LANE1,Read LANE1 result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x4 0.--31. 1. "INTERP0_POP_LANE1"
line.long 0x8 "INTERP0_POP_FULL,Read FULL result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x8 0.--31. 1. "INTERP0_POP_FULL"
line.long 0xC "INTERP0_PEEK_LANE0,Read LANE0 result. without altering any internal state (PEEK)."
hexmask.long 0xC 0.--31. 1. "INTERP0_PEEK_LANE0"
line.long 0x10 "INTERP0_PEEK_LANE1,Read LANE1 result. without altering any internal state (PEEK)."
hexmask.long 0x10 0.--31. 1. "INTERP0_PEEK_LANE1"
line.long 0x14 "INTERP0_PEEK_FULL,Read FULL result. without altering any internal state (PEEK)."
hexmask.long 0x14 0.--31. 1. "INTERP0_PEEK_FULL"
group.long 0xAC++0xF
line.long 0x0 "INTERP0_CTRL_LANE0,Control register for lane 0"
rbitfld.long 0x0 25. "OVERF,Set if either OVERF0 or OVERF1 is set." "0,1"
rbitfld.long 0x0 24. "OVERF1,Indicates if any masked-off MSBs in ACCUM1 are set." "0,1"
rbitfld.long 0x0 23. "OVERF0,Indicates if any masked-off MSBs in ACCUM0 are set." "0,1"
newline
bitfld.long 0x0 21. "BLEND,Only present on INTERP0 on each core. If BLEND mode is enabled:" "0,1"
bitfld.long 0x0 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus." "0,1,2,3"
bitfld.long 0x0 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE0 result. This does not affect FULL result." "0,1"
newline
bitfld.long 0x0 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP." "0,1"
bitfld.long 0x0 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware." "0,1"
bitfld.long 0x0 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits" "0,1"
newline
hexmask.long.byte 0x0 10.--14. 1. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x0 5.--9. 1. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x0 0.--4. 1. "SHIFT,Right-rotate applied to accumulator before masking. By appropriately configuring the masks left and right shifts can be synthesised."
line.long 0x4 "INTERP0_CTRL_LANE1,Control register for lane 1"
bitfld.long 0x4 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus." "0,1,2,3"
bitfld.long 0x4 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE1 result. This does not affect FULL result." "0,1"
bitfld.long 0x4 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP." "0,1"
newline
bitfld.long 0x4 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware." "0,1"
bitfld.long 0x4 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits" "0,1"
hexmask.long.byte 0x4 10.--14. 1. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)"
newline
hexmask.long.byte 0x4 5.--9. 1. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x4 0.--4. 1. "SHIFT,Right-rotate applied to accumulator before masking. By appropriately configuring the masks left and right shifts can be synthesised."
line.long 0x8 "INTERP0_ACCUM0_ADD,Values written here are atomically added to ACCUM0"
hexmask.long.tbyte 0x8 0.--23. 1. "INTERP0_ACCUM0_ADD"
line.long 0xC "INTERP0_ACCUM1_ADD,Values written here are atomically added to ACCUM1"
hexmask.long.tbyte 0xC 0.--23. 1. "INTERP0_ACCUM1_ADD"
wgroup.long 0xBC++0x3
line.long 0x0 "INTERP0_BASE_1AND0,On write. the lower 16 bits go to BASE0. upper bits to BASE1 simultaneously."
hexmask.long 0x0 0.--31. 1. "INTERP0_BASE_1AND0"
group.long 0xC0++0x13
line.long 0x0 "INTERP1_ACCUM0,Read/write access to accumulator 0"
hexmask.long 0x0 0.--31. 1. "INTERP1_ACCUM0"
line.long 0x4 "INTERP1_ACCUM1,Read/write access to accumulator 1"
hexmask.long 0x4 0.--31. 1. "INTERP1_ACCUM1"
line.long 0x8 "INTERP1_BASE0,Read/write access to BASE0 register."
hexmask.long 0x8 0.--31. 1. "INTERP1_BASE0"
line.long 0xC "INTERP1_BASE1,Read/write access to BASE1 register."
hexmask.long 0xC 0.--31. 1. "INTERP1_BASE1"
line.long 0x10 "INTERP1_BASE2,Read/write access to BASE2 register."
hexmask.long 0x10 0.--31. 1. "INTERP1_BASE2"
rgroup.long 0xD4++0x17
line.long 0x0 "INTERP1_POP_LANE0,Read LANE0 result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x0 0.--31. 1. "INTERP1_POP_LANE0"
line.long 0x4 "INTERP1_POP_LANE1,Read LANE1 result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x4 0.--31. 1. "INTERP1_POP_LANE1"
line.long 0x8 "INTERP1_POP_FULL,Read FULL result. and simultaneously write lane results to both accumulators (POP)."
hexmask.long 0x8 0.--31. 1. "INTERP1_POP_FULL"
line.long 0xC "INTERP1_PEEK_LANE0,Read LANE0 result. without altering any internal state (PEEK)."
hexmask.long 0xC 0.--31. 1. "INTERP1_PEEK_LANE0"
line.long 0x10 "INTERP1_PEEK_LANE1,Read LANE1 result. without altering any internal state (PEEK)."
hexmask.long 0x10 0.--31. 1. "INTERP1_PEEK_LANE1"
line.long 0x14 "INTERP1_PEEK_FULL,Read FULL result. without altering any internal state (PEEK)."
hexmask.long 0x14 0.--31. 1. "INTERP1_PEEK_FULL"
group.long 0xEC++0xF
line.long 0x0 "INTERP1_CTRL_LANE0,Control register for lane 0"
rbitfld.long 0x0 25. "OVERF,Set if either OVERF0 or OVERF1 is set." "0,1"
rbitfld.long 0x0 24. "OVERF1,Indicates if any masked-off MSBs in ACCUM1 are set." "0,1"
rbitfld.long 0x0 23. "OVERF0,Indicates if any masked-off MSBs in ACCUM0 are set." "0,1"
newline
bitfld.long 0x0 22. "CLAMP,Only present on INTERP1 on each core. If CLAMP mode is enabled:" "0,1"
bitfld.long 0x0 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus." "0,1,2,3"
bitfld.long 0x0 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE0 result. This does not affect FULL result." "0,1"
newline
bitfld.long 0x0 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP." "0,1"
bitfld.long 0x0 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware." "0,1"
bitfld.long 0x0 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits" "0,1"
newline
hexmask.long.byte 0x0 10.--14. 1. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x0 5.--9. 1. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x0 0.--4. 1. "SHIFT,Right-rotate applied to accumulator before masking. By appropriately configuring the masks left and right shifts can be synthesised."
line.long 0x4 "INTERP1_CTRL_LANE1,Control register for lane 1"
bitfld.long 0x4 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus." "0,1,2,3"
bitfld.long 0x4 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE1 result. This does not affect FULL result." "0,1"
bitfld.long 0x4 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP." "0,1"
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bitfld.long 0x4 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware." "0,1"
bitfld.long 0x4 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits" "0,1"
hexmask.long.byte 0x4 10.--14. 1. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)"
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hexmask.long.byte 0x4 5.--9. 1. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)"
hexmask.long.byte 0x4 0.--4. 1. "SHIFT,Right-rotate applied to accumulator before masking. By appropriately configuring the masks left and right shifts can be synthesised."
line.long 0x8 "INTERP1_ACCUM0_ADD,Values written here are atomically added to ACCUM0"
hexmask.long.tbyte 0x8 0.--23. 1. "INTERP1_ACCUM0_ADD"
line.long 0xC "INTERP1_ACCUM1_ADD,Values written here are atomically added to ACCUM1"
hexmask.long.tbyte 0xC 0.--23. 1. "INTERP1_ACCUM1_ADD"
wgroup.long 0xFC++0x3
line.long 0x0 "INTERP1_BASE_1AND0,On write. the lower 16 bits go to BASE0. upper bits to BASE1 simultaneously."
hexmask.long 0x0 0.--31. 1. "INTERP1_BASE_1AND0"
group.long 0x100++0x93
line.long 0x0 "SPINLOCK0,Reading from a spinlock address will:"
hexmask.long 0x0 0.--31. 1. "SPINLOCK0"
line.long 0x4 "SPINLOCK1,Reading from a spinlock address will:"
hexmask.long 0x4 0.--31. 1. "SPINLOCK1"
line.long 0x8 "SPINLOCK2,Reading from a spinlock address will:"
hexmask.long 0x8 0.--31. 1. "SPINLOCK2"
line.long 0xC "SPINLOCK3,Reading from a spinlock address will:"
hexmask.long 0xC 0.--31. 1. "SPINLOCK3"
line.long 0x10 "SPINLOCK4,Reading from a spinlock address will:"
hexmask.long 0x10 0.--31. 1. "SPINLOCK4"
line.long 0x14 "SPINLOCK5,Reading from a spinlock address will:"
hexmask.long 0x14 0.--31. 1. "SPINLOCK5"
line.long 0x18 "SPINLOCK6,Reading from a spinlock address will:"
hexmask.long 0x18 0.--31. 1. "SPINLOCK6"
line.long 0x1C "SPINLOCK7,Reading from a spinlock address will:"
hexmask.long 0x1C 0.--31. 1. "SPINLOCK7"
line.long 0x20 "SPINLOCK8,Reading from a spinlock address will:"
hexmask.long 0x20 0.--31. 1. "SPINLOCK8"
line.long 0x24 "SPINLOCK9,Reading from a spinlock address will:"
hexmask.long 0x24 0.--31. 1. "SPINLOCK9"
line.long 0x28 "SPINLOCK10,Reading from a spinlock address will:"
hexmask.long 0x28 0.--31. 1. "SPINLOCK10"
line.long 0x2C "SPINLOCK11,Reading from a spinlock address will:"
hexmask.long 0x2C 0.--31. 1. "SPINLOCK11"
line.long 0x30 "SPINLOCK12,Reading from a spinlock address will:"
hexmask.long 0x30 0.--31. 1. "SPINLOCK12"
line.long 0x34 "SPINLOCK13,Reading from a spinlock address will:"
hexmask.long 0x34 0.--31. 1. "SPINLOCK13"
line.long 0x38 "SPINLOCK14,Reading from a spinlock address will:"
hexmask.long 0x38 0.--31. 1. "SPINLOCK14"
line.long 0x3C "SPINLOCK15,Reading from a spinlock address will:"
hexmask.long 0x3C 0.--31. 1. "SPINLOCK15"
line.long 0x40 "SPINLOCK16,Reading from a spinlock address will:"
hexmask.long 0x40 0.--31. 1. "SPINLOCK16"
line.long 0x44 "SPINLOCK17,Reading from a spinlock address will:"
hexmask.long 0x44 0.--31. 1. "SPINLOCK17"
line.long 0x48 "SPINLOCK18,Reading from a spinlock address will:"
hexmask.long 0x48 0.--31. 1. "SPINLOCK18"
line.long 0x4C "SPINLOCK19,Reading from a spinlock address will:"
hexmask.long 0x4C 0.--31. 1. "SPINLOCK19"
line.long 0x50 "SPINLOCK20,Reading from a spinlock address will:"
hexmask.long 0x50 0.--31. 1. "SPINLOCK20"
line.long 0x54 "SPINLOCK21,Reading from a spinlock address will:"
hexmask.long 0x54 0.--31. 1. "SPINLOCK21"
line.long 0x58 "SPINLOCK22,Reading from a spinlock address will:"
hexmask.long 0x58 0.--31. 1. "SPINLOCK22"
line.long 0x5C "SPINLOCK23,Reading from a spinlock address will:"
hexmask.long 0x5C 0.--31. 1. "SPINLOCK23"
line.long 0x60 "SPINLOCK24,Reading from a spinlock address will:"
hexmask.long 0x60 0.--31. 1. "SPINLOCK24"
line.long 0x64 "SPINLOCK25,Reading from a spinlock address will:"
hexmask.long 0x64 0.--31. 1. "SPINLOCK25"
line.long 0x68 "SPINLOCK26,Reading from a spinlock address will:"
hexmask.long 0x68 0.--31. 1. "SPINLOCK26"
line.long 0x6C "SPINLOCK27,Reading from a spinlock address will:"
hexmask.long 0x6C 0.--31. 1. "SPINLOCK27"
line.long 0x70 "SPINLOCK28,Reading from a spinlock address will:"
hexmask.long 0x70 0.--31. 1. "SPINLOCK28"
line.long 0x74 "SPINLOCK29,Reading from a spinlock address will:"
hexmask.long 0x74 0.--31. 1. "SPINLOCK29"
line.long 0x78 "SPINLOCK30,Reading from a spinlock address will:"
hexmask.long 0x78 0.--31. 1. "SPINLOCK30"
line.long 0x7C "SPINLOCK31,Reading from a spinlock address will:"
hexmask.long 0x7C 0.--31. 1. "SPINLOCK31"
line.long 0x80 "DOORBELL_OUT_SET,Trigger a doorbell interrupt on the opposite core."
hexmask.long.byte 0x80 0.--7. 1. "DOORBELL_OUT_SET"
line.long 0x84 "DOORBELL_OUT_CLR,Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes."
hexmask.long.byte 0x84 0.--7. 1. "DOORBELL_OUT_CLR"
line.long 0x88 "DOORBELL_IN_SET,Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core."
hexmask.long.byte 0x88 0.--7. 1. "DOORBELL_IN_SET"
line.long 0x8C "DOORBELL_IN_CLR,Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1."
hexmask.long.byte 0x8C 0.--7. 1. "DOORBELL_IN_CLR"
line.long 0x90 "PERI_NONSEC,Detach certain core-local peripherals from Secure SIO. and attach them to Non-secure SIO. so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO..."
bitfld.long 0x90 5. "TMDS,IF 1 detach TMDS encoder (of this core) from the Secure SIO and attach to the Non-secure SIO." "0,1"
bitfld.long 0x90 1. "INTERP1,If 1 detach interpolator 1 (of this core) from the Secure SIO and attach to the Non-secure SIO." "0,1"
bitfld.long 0x90 0. "INTERP0,If 1 detach interpolator 0 (of this core) from the Secure SIO and attach to the Non-secure SIO." "0,1"
group.long 0x1A0++0x7
line.long 0x0 "RISCV_SOFTIRQ,Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores."
bitfld.long 0x0 9. "CORE1_CLR,Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag." "0,1"
bitfld.long 0x0 8. "CORE0_CLR,Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag." "0,1"
bitfld.long 0x0 1. "CORE1_SET,Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag." "0,1"
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bitfld.long 0x0 0. "CORE0_SET,Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag." "0,1"
line.long 0x4 "MTIME_CTRL,Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO. so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode."
bitfld.long 0x4 3. "DBGPAUSE_CORE1,If 1 the timer pauses when core 1 is in the debug halt state." "0,1"
bitfld.long 0x4 2. "DBGPAUSE_CORE0,If 1 the timer pauses when core 0 is in the debug halt state." "0,1"
bitfld.long 0x4 1. "FULLSPEED,If 1 increment the timer every cycle (i.e. run directly from the system clock) rather than incrementing on the system-level timer tick input." "0,1"
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bitfld.long 0x4 0. "EN,Timer enable bit. When 0 the timer will not increment automatically." "0,1"
group.long 0x1B0++0x13
line.long 0x0 "MTIME,Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle. core 1 takes precedence."
hexmask.long 0x0 0.--31. 1. "MTIME"
line.long 0x4 "MTIMEH,Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle. core 1 takes precedence."
hexmask.long 0x4 0.--31. 1. "MTIMEH"
line.long 0x8 "MTIMECMP,Low half of RISC-V Machine-mode timer comparator. This register is core-local. i.e.. each core gets a copy of this register. with the comparison result routed to its own interrupt line."
hexmask.long 0x8 0.--31. 1. "MTIMECMP"
line.long 0xC "MTIMECMPH,High half of RISC-V Machine-mode timer comparator. This register is core-local."
hexmask.long 0xC 0.--31. 1. "MTIMECMPH"
line.long 0x10 "TMDS_CTRL,Control register for TMDS encoder."
bitfld.long 0x10 28. "CLEAR_BALANCE,Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline." "0,1"
bitfld.long 0x10 27. "PIX2_NOSHIFT,When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register) the second encoder sees a shifted version of the colour data register." "0,1"
bitfld.long 0x10 24.--26. "PIX_SHIFT,Shift applied to the colour data register with each read of a POP alias register." "0: Do not shift the colour data register.,1: Shift the colour data register by 1 bit,2: Shift the colour data register by 2 bits,3: Shift the colour data register by 4 bits,4: Shift the colour data register by 8 bits,5: Shift the colour data register by 16 bits,?,?"
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bitfld.long 0x10 23. "INTERLEAVE,Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE." "0,1"
bitfld.long 0x10 18.--20. "L2_NBITS,Number of valid colour MSBs for lane 2 (1-8 bits encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 15.--17. "L1_NBITS,Number of valid colour MSBs for lane 1 (1-8 bits encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 12.--14. "L0_NBITS,Number of valid colour MSBs for lane 0 (1-8 bits encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 8.--11. 1. "L2_ROT,Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input."
hexmask.long.byte 0x10 4.--7. 1. "L1_ROT,Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input."
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hexmask.long.byte 0x10 0.--3. 1. "L0_ROT,Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input."
wgroup.long 0x1C4++0x3
line.long 0x0 "TMDS_WDATA,Write-only access to the TMDS colour data register."
hexmask.long 0x0 0.--31. 1. "TMDS_WDATA"
rgroup.long 0x1C8++0x1F
line.long 0x0 "TMDS_PEEK_SINGLE,Get the encoding of one pixel's worth of colour data. packed into a 32-bit value (3x10-bit symbols)."
hexmask.long 0x0 0.--31. 1. "TMDS_PEEK_SINGLE"
line.long 0x4 "TMDS_POP_SINGLE,Get the encoding of one pixel's worth of colour data. packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for.."
hexmask.long 0x4 0.--31. 1. "TMDS_POP_SINGLE"
line.long 0x8 "TMDS_PEEK_DOUBLE_L0,Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0x8 0.--31. 1. "TMDS_PEEK_DOUBLE_L0"
line.long 0xC "TMDS_POP_DOUBLE_L0,Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0xC 0.--31. 1. "TMDS_POP_DOUBLE_L0"
line.long 0x10 "TMDS_PEEK_DOUBLE_L1,Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0x10 0.--31. 1. "TMDS_PEEK_DOUBLE_L1"
line.long 0x14 "TMDS_POP_DOUBLE_L1,Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0x14 0.--31. 1. "TMDS_POP_DOUBLE_L1"
line.long 0x18 "TMDS_PEEK_DOUBLE_L2,Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0x18 0.--31. 1. "TMDS_PEEK_DOUBLE_L2"
line.long 0x1C "TMDS_POP_DOUBLE_L2,Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word."
hexmask.long 0x1C 0.--31. 1. "TMDS_POP_DOUBLE_L2"
tree.end
tree.end
tree.end
tree "HSTX (High-Speed Serial Transmit)"
base ad:0x0
tree "HSTX_CTRL"
base ad:0x400C0000
group.long 0x0++0x2B
line.long 0x0 "CSR"
hexmask.long.byte 0x0 28.--31. 1. "CLKDIV,Clock period of the generated clock measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts."
hexmask.long.byte 0x0 24.--27. 1. "CLKPHASE,Set the initial phase of the generated clock."
hexmask.long.byte 0x0 16.--20. 1. "N_SHIFTS,Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted *not* the total shift distance.)"
hexmask.long.byte 0x0 8.--12. 1. "SHIFT,How many bits to right-rotate the shift register by each cycle."
bitfld.long 0x0 5.--6. "COUPLED_SEL,Select which PIO to use for coupled mode operation." "0,1,2,3"
bitfld.long 0x0 4. "COUPLED_MODE,Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly." "?,1: 1 connection"
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bitfld.long 0x0 1. "EXPAND_EN,Enable the command expander. When 0 raw FIFO data is passed directly to the output shift register. When 1 the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register." "0,1"
bitfld.long 0x0 0. "EN,When EN is 1 the HSTX will shift out data as it appears in the FIFO. As long as there is data the HSTX shift register will shift once per clock cycle and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH." "0,1"
line.long 0x4 "BIT0,Data control register for output bit 0"
bitfld.long 0x4 17. "CLK,Connect this output to the generated clock rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set but INV can still be set to generate an antiphase clock." "0,1"
bitfld.long 0x4 16. "INV,Invert this data output (logical NOT)" "0,1"
hexmask.long.byte 0x4 8.--12. 1. "SEL_N,Shift register data bit select for the second half of the HSTX clock cycle"
hexmask.long.byte 0x4 0.--4. 1. "SEL_P,Shift register data bit select for the first half of the HSTX clock cycle"
line.long 0x8 "BIT1,Data control register for output bit 1"
bitfld.long 0x8 17. "CLK,Connect this output to the generated clock rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set but INV can still be set to generate an antiphase clock." "0,1"
bitfld.long 0x8 16. "INV,Invert this data output (logical NOT)" "0,1"
hexmask.long.byte 0x8 8.--12. 1. "SEL_N,Shift register data bit select for the second half of the HSTX clock cycle"
hexmask.long.byte 0x8 0.--4. 1. "SEL_P,Shift register data bit select for the first half of the HSTX clock cycle"
line.long 0xC "BIT2,Data control register for output bit 2"
bitfld.long 0xC 17. "CLK,Connect this output to the generated clock rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set but INV can still be set to generate an antiphase clock." "0,1"
bitfld.long 0xC 16. "INV,Invert this data output (logical NOT)" "0,1"
hexmask.long.byte 0xC 8.--12. 1. "SEL_N,Shift register data bit select for the second half of the HSTX clock cycle"
hexmask.long.byte 0xC 0.--4. 1. "SEL_P,Shift register data bit select for the first half of the HSTX clock cycle"
line.long 0x10 "BIT3,Data control register for output bit 3"
bitfld.long 0x10 17. "CLK,Connect this output to the generated clock rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set but INV can still be set to generate an antiphase clock." "0,1"
bitfld.long 0x10 16. "INV,Invert this data output (logical NOT)" "0,1"
hexmask.long.byte 0x10 8.--12. 1. "SEL_N,Shift register data bit select for the second half of the HSTX clock cycle"
hexmask.long.byte 0x10 0.--4. 1. "SEL_P,Shift register data bit select for the first half of the HSTX clock cycle"
line.long 0x14 "BIT4,Data control register for output bit 4"
bitfld.long 0x14 17. "CLK,Connect this output to the generated clock rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set but INV can still be set to generate an antiphase clock." "0,1"
bitfld.long 0x14 16. "INV,Invert this data output (logical NOT)" "0,1"
hexmask.long.byte 0x14 8.--12. 1. "SEL_N,Shift register data bit select for the second half of the HSTX clock cycle"
hexmask.long.byte 0x14 0.--4. 1. "SEL_P,Shift register data bit select for the first half of the HSTX clock cycle"
line.long 0x18 "BIT5,Data control register for output bit 5"
bitfld.long 0x18 17. "CLK,Connect this output to the generated clock rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set but INV can still be set to generate an antiphase clock." "0,1"
bitfld.long 0x18 16. "INV,Invert this data output (logical NOT)" "0,1"
hexmask.long.byte 0x18 8.--12. 1. "SEL_N,Shift register data bit select for the second half of the HSTX clock cycle"
hexmask.long.byte 0x18 0.--4. 1. "SEL_P,Shift register data bit select for the first half of the HSTX clock cycle"
line.long 0x1C "BIT6,Data control register for output bit 6"
bitfld.long 0x1C 17. "CLK,Connect this output to the generated clock rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set but INV can still be set to generate an antiphase clock." "0,1"
bitfld.long 0x1C 16. "INV,Invert this data output (logical NOT)" "0,1"
hexmask.long.byte 0x1C 8.--12. 1. "SEL_N,Shift register data bit select for the second half of the HSTX clock cycle"
hexmask.long.byte 0x1C 0.--4. 1. "SEL_P,Shift register data bit select for the first half of the HSTX clock cycle"
line.long 0x20 "BIT7,Data control register for output bit 7"
bitfld.long 0x20 17. "CLK,Connect this output to the generated clock rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set but INV can still be set to generate an antiphase clock." "0,1"
bitfld.long 0x20 16. "INV,Invert this data output (logical NOT)" "0,1"
hexmask.long.byte 0x20 8.--12. 1. "SEL_N,Shift register data bit select for the second half of the HSTX clock cycle"
hexmask.long.byte 0x20 0.--4. 1. "SEL_P,Shift register data bit select for the first half of the HSTX clock cycle"
line.long 0x24 "EXPAND_SHIFT,Configure the optional shifter inside the command expander"
hexmask.long.byte 0x24 24.--28. 1. "ENC_N_SHIFTS,Number of times to consume from the shift register before refilling it from the FIFO when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times."
hexmask.long.byte 0x24 16.--20. 1. "ENC_SHIFT,How many bits to right-rotate the shift register by each time data is pushed to the output shifter when the current command is an encoded data command (e.g. TMDS)."
hexmask.long.byte 0x24 8.--12. 1. "RAW_N_SHIFTS,Number of times to consume from the shift register before refilling it from the FIFO when the current command is a raw data command. A register value of 0 means shift 32 times."
hexmask.long.byte 0x24 0.--4. 1. "RAW_SHIFT,How many bits to right-rotate the shift register by each time data is pushed to the output shifter when the current command is a raw data command."
line.long 0x28 "EXPAND_TMDS,Configure the optional TMDS encoder inside the command expander"
bitfld.long 0x28 21.--23. "L2_NBITS" "0: 1 bit,1: 2 bits,2: 3 bits,3: 4 bits,4: 5 bits,5: 6 bits,6: 7 bits,7: 8 bits"
hexmask.long.byte 0x28 16.--20. 1. "L2_ROT,Right-rotate applied to the current shifter data before the lane 2 TMDS encoder."
bitfld.long 0x28 13.--15. "L1_NBITS" "0: 1 bit,1: 2 bits,2: 3 bits,3: 4 bits,4: 5 bits,5: 6 bits,6: 7 bits,7: 8 bits"
hexmask.long.byte 0x28 8.--12. 1. "L1_ROT,Right-rotate applied to the current shifter data before the lane 1 TMDS encoder."
bitfld.long 0x28 5.--7. "L0_NBITS" "0: 1 bit,1: 2 bits,2: 3 bits,3: 4 bits,4: 5 bits,5: 6 bits,6: 7 bits,7: 8 bits"
hexmask.long.byte 0x28 0.--4. 1. "L0_ROT,Right-rotate applied to the current shifter data before the lane 0 TMDS encoder."
tree.end
tree "HSTX_FIFO"
base ad:0x50600000
group.long 0x0++0x3
line.long 0x0 "STAT,FIFO status"
eventfld.long 0x0 10. "WOF,FIFO was written when full. Write 1 to clear." "0,1"
rbitfld.long 0x0 9. "EMPTY" "0,1"
rbitfld.long 0x0 8. "FULL" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "LEVEL"
wgroup.long 0x4++0x3
line.long 0x0 "FIFO,Write access to FIFO"
hexmask.long 0x0 0.--31. 1. "FIFO"
tree.end
tree.end
tree "I2C (Inter-Integrated Circuit)"
base ad:0x0
tree "I2C0"
base ad:0x40090000
group.long 0x0++0xB
line.long 0x0 "IC_CON,I2C Control Register. This register can be written only when the DW_apb_i2c is disabled. which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect."
rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,Master issues the STOP_DET interrupt irrespective of whether master is active or not" "0,1"
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bitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH as described in the IC_RX_FULL_HLD_BUS_EN parameter." "0: Overflow when RX_FIFO is full,1: Hold bus when RX_FIFO is full"
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bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation of the TX_EMPTY interrupt as described in the IC_RAW_INTR_STAT register." "0: Default behaviour of TX_EMPTY interrupt,1: Controlled generation of TX_EMPTY interrupt"
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bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled which means once the presetn signal is applied then this bit is set and the slave is disabled." "0: Slave mode is enabled,1: Slave mode is disabled"
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bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled the.." "0: Master restart disabled,1: Master restart enabled"
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bitfld.long 0x0 4. "IC_10BITADDR_MASTER,Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing only the lower 7 bits.." "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed.." "?,1: standard mode,2: fast mode,3: high speed mode"
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bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: Master mode is disabled,1: Master mode is enabled"
line.long 0x4 "IC_TAR,I2C Target Address Register"
bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
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bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0 then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call only.." "0: General Call Address,1: START BYTE Reset value: 0x0"
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hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When transmitting a General Call these bits are ignored. To generate a START BYTE the CPU needs to write only once into these bits."
line.long 0x8 "IC_SAR,I2C Slave Address Register"
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing only IC_SAR[6:0] is used."
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO."
rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode." "0: Sequential data byte received,1: Non sequential data byte received"
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bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0: Don't Issue RESTART before this command,1: Issue RESTART before this command"
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bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0: Don't Issue STOP after this command,1: Issue STOP after this command"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master." "0: Master Write Command,1: Master Read Command"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read bits 7:0 (DAT) are ignored by the DW_apb_i2c. However when you read this register these bits return the.."
line.long 0x4 "IC_SS_SCL_HCNT,Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information refer to 'IC_CLK Frequency Configuration'."
line.long 0x8 "IC_SS_SCL_LCNT,Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information refer to 'IC_CLK Frequency Configuration'"
line.long 0xC "IC_FS_SCL_HCNT,Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code.."
line.long 0x10 "IC_FS_SCL_LCNT,Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or.."
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,I2C Interrupt Status Register"
bitfld.long 0x0 12. "R_RESTART_DET,See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit." "0: R_RESTART_DET interrupt is inactive,1: R_RESTART_DET interrupt is active"
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bitfld.long 0x0 11. "R_GEN_CALL,See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit." "0: R_GEN_CALL interrupt is inactive,1: R_GEN_CALL interrupt is active"
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bitfld.long 0x0 10. "R_START_DET,See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit." "0: R_START_DET interrupt is inactive,1: R_START_DET interrupt is active"
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bitfld.long 0x0 9. "R_STOP_DET,See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit." "0: R_STOP_DET interrupt is inactive,1: R_STOP_DET interrupt is active"
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bitfld.long 0x0 8. "R_ACTIVITY,See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit." "0: R_ACTIVITY interrupt is inactive,1: R_ACTIVITY interrupt is active"
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bitfld.long 0x0 7. "R_RX_DONE,See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit." "0: R_RX_DONE interrupt is inactive,1: R_RX_DONE interrupt is active"
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bitfld.long 0x0 6. "R_TX_ABRT,See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit." "0: R_TX_ABRT interrupt is inactive,1: R_TX_ABRT interrupt is active"
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bitfld.long 0x0 5. "R_RD_REQ,See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit." "0: R_RD_REQ interrupt is inactive,1: R_RD_REQ interrupt is active"
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bitfld.long 0x0 4. "R_TX_EMPTY,See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit." "0: R_TX_EMPTY interrupt is inactive,1: R_TX_EMPTY interrupt is active"
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bitfld.long 0x0 3. "R_TX_OVER,See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit." "0: R_TX_OVER interrupt is inactive,1: R_TX_OVER interrupt is active"
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bitfld.long 0x0 2. "R_RX_FULL,See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit." "0: R_RX_FULL interrupt is inactive,1: R_RX_FULL interrupt is active"
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bitfld.long 0x0 1. "R_RX_OVER,See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit." "0: R_RX_OVER interrupt is inactive,1: R_RX_OVER interrupt is active"
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bitfld.long 0x0 0. "R_RX_UNDER,See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit." "0: RX_UNDER interrupt is inactive,1: RX_UNDER interrupt is active"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,I2C Interrupt Mask Register."
bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0: RESTART_DET interrupt is masked,1: RESTART_DET interrupt is unmasked"
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bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0: GEN_CALL interrupt is masked,1: GEN_CALL interrupt is unmasked"
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bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0: START_DET interrupt is masked,1: START_DET interrupt is unmasked"
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bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0: STOP_DET interrupt is masked,1: STOP_DET interrupt is unmasked"
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bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0: ACTIVITY interrupt is masked,1: ACTIVITY interrupt is unmasked"
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bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0: RX_DONE interrupt is masked,1: RX_DONE interrupt is unmasked"
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bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0: TX_ABORT interrupt is masked,1: TX_ABORT interrupt is unmasked"
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bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0: RD_REQ interrupt is masked,1: RD_REQ interrupt is unmasked"
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bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0: TX_EMPTY interrupt is masked,1: TX_EMPTY interrupt is unmasked"
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bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0: TX_OVER interrupt is masked,1: TX_OVER interrupt is unmasked"
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bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0: RX_FULL interrupt is masked,1: RX_FULL interrupt is unmasked"
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bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0: RX_OVER interrupt is masked,1: RX_OVER interrupt is unmasked"
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bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0: RX_UNDER interrupt is masked,1: RX_UNDER interrupt is unmasked"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,I2C Raw Interrupt Status Register"
bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1." "0: RESTART_DET interrupt is inactive,1: RESTART_DET interrupt is active"
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bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx.." "0: GEN_CALL interrupt is inactive,1: GEN_CALL interrupt is active"
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bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode." "0: START_DET interrupt is inactive,1: START_DET interrupt is active"
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bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode." "0: STOP_DET interrupt is inactive,1: STOP_DET interrupt is active"
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bitfld.long 0x0 8. "ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set .." "0: RAW_INTR_ACTIVITY interrupt is inactive,1: RAW_INTR_ACTIVITY interrupt is active"
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bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission indicating that the transmission is done." "0: RX_DONE interrupt is inactive,1: RX_DONE interrupt is active"
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bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave and is referred to as a 'transmit abort'." "0: TX_ABRT interrupt is inactive,1: TX_ABRT interrupt is active"
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bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced which means that the slave has.." "0: RD_REQ interrupt is inactive,1: RD_REQ interrupt is active"
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bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL.." "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
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bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled this bit keeps its level until the master or.." "0: TX_OVER interrupt is inactive,1: TX_OVER interrupt is active"
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bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0) the RX FIFO is flushed.." "0: RX_FULL interrupt is inactive,1: RX_FULL interrupt is active"
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bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this but any data bytes received after the FIFO is full are lost. If the module is.." "0: RX_OVER interrupt is inactive,1: RX_OVER interrupt is active"
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bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0) this bit keeps its level until the master or slave state machines go into idle and.." "0: RX_UNDER interrupt is inactive,1: RX_UNDER interrupt is active"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,I2C Receive FIFO Threshold Register"
hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level."
line.long 0x4 "IC_TX_TL,I2C Transmit FIFO Threshold Register"
hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level."
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Clear Combined and Individual Interrupt Register"
bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE.." "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Clear RX_UNDER Interrupt Register"
bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Clear RX_OVER Interrupt Register"
bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0xC "IC_CLR_TX_OVER,Clear TX_OVER Interrupt Register"
bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Clear RD_REQ Interrupt Register"
bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Clear TX_ABRT Interrupt Register"
bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state allowing more writes to the TX FIFO. Refer to Bit 9.." "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Clear RX_DONE Interrupt Register"
bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Clear ACTIVITY Interrupt Register"
bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is.." "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Clear STOP_DET Interrupt Register"
bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x24 "IC_CLR_START_DET,Clear START_DET Interrupt Register"
bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Clear GEN_CALL Interrupt Register"
bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register." "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,I2C Enable Register"
bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically as soon as the first data is available in the Tx FIFO. Note: To block.." "0: The transmission of data starts on I2C bus..,1: Blocks the transmission of data on I2C bus even.."
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bitfld.long 0x0 1. "ABORT,When set the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when.." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress The software can.."
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bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However it is important that care be taken to ensure.." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c Software can disable.."
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,I2C Status Register"
bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave.." "0: Slave FSM is in IDLE state so the Slave part of..,1: Slave FSM is not in IDLE state so the Slave part.."
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bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the.." "0: Master FSM is in IDLE state so the Master part..,1: Master FSM is not in IDLE state so the Master.."
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bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full. When the receive FIFO is completely full this bit is set. When the receive FIFO contains one or more empty location this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0" "0: Receive FIFO is not full,1: Receive FIFO is full Reset value: 0x0"
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bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0" "0: Receive FIFO is empty,1: Receive FIFO is not empty Reset value: 0x0"
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bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty. When the transmit FIFO is completely empty this bit is set. When it contains one or more valid entries this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit.." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty Reset value: 0x1"
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bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1" "0: Transmit FIFO is full,1: Transmit FIFO is not full Reset value: 0x1"
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bitfld.long 0x0 0. "ACTIVITY,I2C Activity Status. Reset value: 0x0" "0: I2C is idle,1: I2C is active"
line.long 0x4 "IC_TXFLR,I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is. TX_ABRT bit is set in the IC_RAW_INTR_STAT.."
hexmask.long.byte 0x4 0.--4. 1. "TXFLR,Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO."
line.long 0x8 "IC_RXFLR,I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in.."
hexmask.long.byte 0x8 0.--4. 1. "RXFLR,Receive FIFO Level. Contains the number of valid data entries in the receive FIFO."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time in units of ic_clk period when DW_apb_i2c acts as a receiver."
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hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time in units of ic_clk period when DW_apb_i2c acts as a transmitter."
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled."
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bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])" "0: Transfer abort detected by master- scenario not..,1: Transfer abort detected by master"
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bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register." "0: Slave trying to transmit to remote master in..,1: When the processor side responds to a slave mode.."
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bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus something could go wrong on the bus. This is.." "0: Slave lost arbitration to remote master-..,1: Slave lost arbitration to remote master"
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bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,This field specifies that the Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO." "0: Slave flushes existing data in TX-FIFO upon..,1: Slave flushes existing data in TX-FIFO upon.."
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bitfld.long 0x0 12. "ARB_LOST,This field specifies that the Master has lost arbitration or if IC_TX_ABRT_SOURCE[14] is also set then the slave transmitter has lost arbitration." "0: Master or Slave-Transmitter lost arbitration-..,1: Master or Slave-Transmitter lost arbitration"
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bitfld.long 0x0 11. "ABRT_MASTER_DIS,This field indicates that the User tries to initiate a Master operation with the Master mode disabled." "0: User initiating master operation when MASTER..,1: User initiating master operation when MASTER.."
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bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode." "0: Master not trying to read in 10Bit addressing..,1: Master trying to read in 10Bit addressing mode.."
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bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1) the SPECIAL bit must be cleared (IC_TAR[11]) or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the.." "0: User trying to send START byte when RESTART..,1: User trying to send START byte when RESTART.."
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bitfld.long 0x0 8. "ABRT_HS_NORSTRT,This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode." "0: User trying to switch Master to HS mode when..,1: User trying to switch Master to HS mode when.."
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bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior)." "0: ACK detected for START byte- scenario not present,1: ACK detected for START byte"
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bitfld.long 0x0 6. "ABRT_HS_ACKDET,This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior)." "0: HS Master code ACKed in HS Mode- scenario not..,1: HS Master code ACKed in HS Mode"
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bitfld.long 0x0 5. "ABRT_GCALL_READ,This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1)." "0: GCALL is followed by read from bus-scenario not..,1: GCALL is followed by read from bus"
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bitfld.long 0x0 4. "ABRT_GCALL_NOACK,This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call." "0: GCALL not ACKed by any slave-scenario not present,1: GCALL not ACKed by any slave"
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bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,This field indicates the master-mode only bit. When the master receives an acknowledgement for the address but when it sends data byte(s) following the address it did not receive an acknowledge from the remote slave(s)." "0: Transmitted data non-ACKed by addressed..,1: Transmitted data not ACKed by addressed slave"
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bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave." "0: This abort is not generated,1: Byte 2 of 10Bit Address not ACKed by any slave"
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bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave." "0: This abort is not generated,1: Byte 1 of 10Bit Address not ACKed by any slave"
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bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave." "0: This abort is not generated,1: This abort is generated because of NOACK for.."
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Generate Slave Data NACK Register"
bitfld.long 0x0 0. "NACK,Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1 it can only generate a NACK after a data byte is received; hence the data transfer is aborted and the data received is not.." "0: generate NACK/ACK normally Reset value: 0x0,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,DMA Control Register"
bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0" "0: transmit FIFO DMA channel disabled,1: Transmit FIFO DMA channel enabled"
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bitfld.long 0x4 0. "RDMAE,Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0" "0: Receive FIFO DMA channel disabled,1: Receive FIFO DMA channel enabled"
line.long 0x8 "IC_DMA_TDLR,DMA Transmit Data Level Register"
hexmask.long.byte 0x8 0.--3. 1. "DMATDL,Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO.."
line.long 0xC "IC_DMA_RDLR,I2C Receive Data Level Register"
hexmask.long.byte 0xC 0.--3. 1. "DMARDL,Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or.."
line.long 0x10 "IC_SDA_SETUP,I2C SDA Setup Register"
hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup. It is recommended that if the required delay is 1000ns then for an ic_clk frequency of 10 MHz IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."
line.long 0x14 "IC_ACK_GENERAL_CALL,I2C ACK General Call Register"
bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call. When set to 1 DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise DW_apb_i2c responds with a NACK (by negating ic_data_oe)." "0: Generate NACK for a General Call,1: Generate ACK for a General Call"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,I2C Enable Status Register"
bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1 DW_apb_i2c is deemed.." "0: Slave RX Data is not lost,1: Slave RX Data is lost"
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bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to.." "0: Slave is disabled when it is idle,1: Slave is disabled when it is active"
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bitfld.long 0x0 0. "IC_EN,ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1 DW_apb_i2c is deemed to be in an enabled state. - When read as 0 DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit.." "0: I2C disabled,1: I2C enabled"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,I2C SS. FS or FM+ spike suppression limit"
hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration measured in ic_clk cycles of the longest spike in the SCL or SDA lines that will be filtered out by the.."
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Clear RESTART_DET Interrupt Register"
bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register." "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Component Parameter Register 1"
hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,TX Buffer Depth = 16"
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hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,RX Buffer Depth = 16"
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bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,Encoded parameters not visible" "0,1"
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bitfld.long 0x0 6. "HAS_DMA,DMA handshaking signals are enabled" "0,1"
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bitfld.long 0x0 5. "INTR_IO,COMBINED Interrupt outputs" "0,1"
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bitfld.long 0x0 4. "HC_COUNT_VALUES,Programmable count values for each mode." "0,1"
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bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,MAX SPEED MODE = FAST MODE" "0,1,2,3"
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bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,APB data bus width is 32 bits" "0,1,2,3"
line.long 0x4 "IC_COMP_VERSION,I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION"
line.long 0x8 "IC_COMP_TYPE,I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number."
tree.end
tree "I2C1"
base ad:0x40098000
group.long 0x0++0xB
line.long 0x0 "IC_CON,I2C Control Register. This register can be written only when the DW_apb_i2c is disabled. which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect."
rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,Master issues the STOP_DET interrupt irrespective of whether master is active or not" "0,1"
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bitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH as described in the IC_RX_FULL_HLD_BUS_EN parameter." "0: Overflow when RX_FIFO is full,1: Hold bus when RX_FIFO is full"
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bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation of the TX_EMPTY interrupt as described in the IC_RAW_INTR_STAT register." "0: Default behaviour of TX_EMPTY interrupt,1: Controlled generation of TX_EMPTY interrupt"
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bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled which means once the presetn signal is applied then this bit is set and the slave is disabled." "0: Slave mode is enabled,1: Slave mode is disabled"
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bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled the.." "0: Master restart disabled,1: Master restart enabled"
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bitfld.long 0x0 4. "IC_10BITADDR_MASTER,Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing only the lower 7 bits.." "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed.." "?,1: standard mode,2: fast mode,3: high speed mode"
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bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: Master mode is disabled,1: Master mode is enabled"
line.long 0x4 "IC_TAR,I2C Target Address Register"
bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
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bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0 then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call only.." "0: General Call Address,1: START BYTE Reset value: 0x0"
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hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When transmitting a General Call these bits are ignored. To generate a START BYTE the CPU needs to write only once into these bits."
line.long 0x8 "IC_SAR,I2C Slave Address Register"
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing only IC_SAR[6:0] is used."
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO."
rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode." "0: Sequential data byte received,1: Non sequential data byte received"
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bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0: Don't Issue RESTART before this command,1: Issue RESTART before this command"
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bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0: Don't Issue STOP after this command,1: Issue STOP after this command"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master." "0: Master Write Command,1: Master Read Command"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read bits 7:0 (DAT) are ignored by the DW_apb_i2c. However when you read this register these bits return the.."
line.long 0x4 "IC_SS_SCL_HCNT,Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information refer to 'IC_CLK Frequency Configuration'."
line.long 0x8 "IC_SS_SCL_LCNT,Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information refer to 'IC_CLK Frequency Configuration'"
line.long 0xC "IC_FS_SCL_HCNT,Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code.."
line.long 0x10 "IC_FS_SCL_LCNT,Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or.."
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,I2C Interrupt Status Register"
bitfld.long 0x0 12. "R_RESTART_DET,See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit." "0: R_RESTART_DET interrupt is inactive,1: R_RESTART_DET interrupt is active"
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bitfld.long 0x0 11. "R_GEN_CALL,See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit." "0: R_GEN_CALL interrupt is inactive,1: R_GEN_CALL interrupt is active"
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bitfld.long 0x0 10. "R_START_DET,See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit." "0: R_START_DET interrupt is inactive,1: R_START_DET interrupt is active"
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bitfld.long 0x0 9. "R_STOP_DET,See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit." "0: R_STOP_DET interrupt is inactive,1: R_STOP_DET interrupt is active"
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bitfld.long 0x0 8. "R_ACTIVITY,See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit." "0: R_ACTIVITY interrupt is inactive,1: R_ACTIVITY interrupt is active"
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bitfld.long 0x0 7. "R_RX_DONE,See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit." "0: R_RX_DONE interrupt is inactive,1: R_RX_DONE interrupt is active"
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bitfld.long 0x0 6. "R_TX_ABRT,See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit." "0: R_TX_ABRT interrupt is inactive,1: R_TX_ABRT interrupt is active"
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bitfld.long 0x0 5. "R_RD_REQ,See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit." "0: R_RD_REQ interrupt is inactive,1: R_RD_REQ interrupt is active"
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bitfld.long 0x0 4. "R_TX_EMPTY,See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit." "0: R_TX_EMPTY interrupt is inactive,1: R_TX_EMPTY interrupt is active"
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bitfld.long 0x0 3. "R_TX_OVER,See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit." "0: R_TX_OVER interrupt is inactive,1: R_TX_OVER interrupt is active"
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bitfld.long 0x0 2. "R_RX_FULL,See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit." "0: R_RX_FULL interrupt is inactive,1: R_RX_FULL interrupt is active"
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bitfld.long 0x0 1. "R_RX_OVER,See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit." "0: R_RX_OVER interrupt is inactive,1: R_RX_OVER interrupt is active"
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bitfld.long 0x0 0. "R_RX_UNDER,See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit." "0: RX_UNDER interrupt is inactive,1: RX_UNDER interrupt is active"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,I2C Interrupt Mask Register."
bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0: RESTART_DET interrupt is masked,1: RESTART_DET interrupt is unmasked"
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bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0: GEN_CALL interrupt is masked,1: GEN_CALL interrupt is unmasked"
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bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0: START_DET interrupt is masked,1: START_DET interrupt is unmasked"
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bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0: STOP_DET interrupt is masked,1: STOP_DET interrupt is unmasked"
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bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0: ACTIVITY interrupt is masked,1: ACTIVITY interrupt is unmasked"
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bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0: RX_DONE interrupt is masked,1: RX_DONE interrupt is unmasked"
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bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0: TX_ABORT interrupt is masked,1: TX_ABORT interrupt is unmasked"
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bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0: RD_REQ interrupt is masked,1: RD_REQ interrupt is unmasked"
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bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0: TX_EMPTY interrupt is masked,1: TX_EMPTY interrupt is unmasked"
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bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0: TX_OVER interrupt is masked,1: TX_OVER interrupt is unmasked"
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bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0: RX_FULL interrupt is masked,1: RX_FULL interrupt is unmasked"
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bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0: RX_OVER interrupt is masked,1: RX_OVER interrupt is unmasked"
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bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0: RX_UNDER interrupt is masked,1: RX_UNDER interrupt is unmasked"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,I2C Raw Interrupt Status Register"
bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1." "0: RESTART_DET interrupt is inactive,1: RESTART_DET interrupt is active"
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bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx.." "0: GEN_CALL interrupt is inactive,1: GEN_CALL interrupt is active"
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bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode." "0: START_DET interrupt is inactive,1: START_DET interrupt is active"
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bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode." "0: STOP_DET interrupt is inactive,1: STOP_DET interrupt is active"
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bitfld.long 0x0 8. "ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set .." "0: RAW_INTR_ACTIVITY interrupt is inactive,1: RAW_INTR_ACTIVITY interrupt is active"
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bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission indicating that the transmission is done." "0: RX_DONE interrupt is inactive,1: RX_DONE interrupt is active"
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bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave and is referred to as a 'transmit abort'." "0: TX_ABRT interrupt is inactive,1: TX_ABRT interrupt is active"
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bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced which means that the slave has.." "0: RD_REQ interrupt is inactive,1: RD_REQ interrupt is active"
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bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL.." "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
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bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled this bit keeps its level until the master or.." "0: TX_OVER interrupt is inactive,1: TX_OVER interrupt is active"
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bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0) the RX FIFO is flushed.." "0: RX_FULL interrupt is inactive,1: RX_FULL interrupt is active"
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bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this but any data bytes received after the FIFO is full are lost. If the module is.." "0: RX_OVER interrupt is inactive,1: RX_OVER interrupt is active"
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bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0) this bit keeps its level until the master or slave state machines go into idle and.." "0: RX_UNDER interrupt is inactive,1: RX_UNDER interrupt is active"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,I2C Receive FIFO Threshold Register"
hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level."
line.long 0x4 "IC_TX_TL,I2C Transmit FIFO Threshold Register"
hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level."
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Clear Combined and Individual Interrupt Register"
bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE.." "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Clear RX_UNDER Interrupt Register"
bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Clear RX_OVER Interrupt Register"
bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0xC "IC_CLR_TX_OVER,Clear TX_OVER Interrupt Register"
bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Clear RD_REQ Interrupt Register"
bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Clear TX_ABRT Interrupt Register"
bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state allowing more writes to the TX FIFO. Refer to Bit 9.." "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Clear RX_DONE Interrupt Register"
bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Clear ACTIVITY Interrupt Register"
bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is.." "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Clear STOP_DET Interrupt Register"
bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x24 "IC_CLR_START_DET,Clear START_DET Interrupt Register"
bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register." "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Clear GEN_CALL Interrupt Register"
bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register." "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,I2C Enable Register"
bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically as soon as the first data is available in the Tx FIFO. Note: To block.." "0: The transmission of data starts on I2C bus..,1: Blocks the transmission of data on I2C bus even.."
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bitfld.long 0x0 1. "ABORT,When set the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when.." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress The software can.."
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bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However it is important that care be taken to ensure.." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c Software can disable.."
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,I2C Status Register"
bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave.." "0: Slave FSM is in IDLE state so the Slave part of..,1: Slave FSM is not in IDLE state so the Slave part.."
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bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the.." "0: Master FSM is in IDLE state so the Master part..,1: Master FSM is not in IDLE state so the Master.."
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bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full. When the receive FIFO is completely full this bit is set. When the receive FIFO contains one or more empty location this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0" "0: Receive FIFO is not full,1: Receive FIFO is full Reset value: 0x0"
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bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0" "0: Receive FIFO is empty,1: Receive FIFO is not empty Reset value: 0x0"
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bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty. When the transmit FIFO is completely empty this bit is set. When it contains one or more valid entries this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit.." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty Reset value: 0x1"
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bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1" "0: Transmit FIFO is full,1: Transmit FIFO is not full Reset value: 0x1"
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bitfld.long 0x0 0. "ACTIVITY,I2C Activity Status. Reset value: 0x0" "0: I2C is idle,1: I2C is active"
line.long 0x4 "IC_TXFLR,I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is. TX_ABRT bit is set in the IC_RAW_INTR_STAT.."
hexmask.long.byte 0x4 0.--4. 1. "TXFLR,Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO."
line.long 0x8 "IC_RXFLR,I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in.."
hexmask.long.byte 0x8 0.--4. 1. "RXFLR,Receive FIFO Level. Contains the number of valid data entries in the receive FIFO."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time in units of ic_clk period when DW_apb_i2c acts as a receiver."
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hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time in units of ic_clk period when DW_apb_i2c acts as a transmitter."
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled."
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bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])" "0: Transfer abort detected by master- scenario not..,1: Transfer abort detected by master"
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bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register." "0: Slave trying to transmit to remote master in..,1: When the processor side responds to a slave mode.."
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bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus something could go wrong on the bus. This is.." "0: Slave lost arbitration to remote master-..,1: Slave lost arbitration to remote master"
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bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,This field specifies that the Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO." "0: Slave flushes existing data in TX-FIFO upon..,1: Slave flushes existing data in TX-FIFO upon.."
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bitfld.long 0x0 12. "ARB_LOST,This field specifies that the Master has lost arbitration or if IC_TX_ABRT_SOURCE[14] is also set then the slave transmitter has lost arbitration." "0: Master or Slave-Transmitter lost arbitration-..,1: Master or Slave-Transmitter lost arbitration"
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bitfld.long 0x0 11. "ABRT_MASTER_DIS,This field indicates that the User tries to initiate a Master operation with the Master mode disabled." "0: User initiating master operation when MASTER..,1: User initiating master operation when MASTER.."
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bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode." "0: Master not trying to read in 10Bit addressing..,1: Master trying to read in 10Bit addressing mode.."
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bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1) the SPECIAL bit must be cleared (IC_TAR[11]) or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the.." "0: User trying to send START byte when RESTART..,1: User trying to send START byte when RESTART.."
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bitfld.long 0x0 8. "ABRT_HS_NORSTRT,This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode." "0: User trying to switch Master to HS mode when..,1: User trying to switch Master to HS mode when.."
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bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior)." "0: ACK detected for START byte- scenario not present,1: ACK detected for START byte"
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bitfld.long 0x0 6. "ABRT_HS_ACKDET,This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior)." "0: HS Master code ACKed in HS Mode- scenario not..,1: HS Master code ACKed in HS Mode"
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bitfld.long 0x0 5. "ABRT_GCALL_READ,This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1)." "0: GCALL is followed by read from bus-scenario not..,1: GCALL is followed by read from bus"
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bitfld.long 0x0 4. "ABRT_GCALL_NOACK,This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call." "0: GCALL not ACKed by any slave-scenario not present,1: GCALL not ACKed by any slave"
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bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,This field indicates the master-mode only bit. When the master receives an acknowledgement for the address but when it sends data byte(s) following the address it did not receive an acknowledge from the remote slave(s)." "0: Transmitted data non-ACKed by addressed..,1: Transmitted data not ACKed by addressed slave"
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bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave." "0: This abort is not generated,1: Byte 2 of 10Bit Address not ACKed by any slave"
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bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave." "0: This abort is not generated,1: Byte 1 of 10Bit Address not ACKed by any slave"
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bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave." "0: This abort is not generated,1: This abort is generated because of NOACK for.."
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Generate Slave Data NACK Register"
bitfld.long 0x0 0. "NACK,Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1 it can only generate a NACK after a data byte is received; hence the data transfer is aborted and the data received is not.." "0: generate NACK/ACK normally Reset value: 0x0,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,DMA Control Register"
bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0" "0: transmit FIFO DMA channel disabled,1: Transmit FIFO DMA channel enabled"
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bitfld.long 0x4 0. "RDMAE,Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0" "0: Receive FIFO DMA channel disabled,1: Receive FIFO DMA channel enabled"
line.long 0x8 "IC_DMA_TDLR,DMA Transmit Data Level Register"
hexmask.long.byte 0x8 0.--3. 1. "DMATDL,Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO.."
line.long 0xC "IC_DMA_RDLR,I2C Receive Data Level Register"
hexmask.long.byte 0xC 0.--3. 1. "DMARDL,Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or.."
line.long 0x10 "IC_SDA_SETUP,I2C SDA Setup Register"
hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup. It is recommended that if the required delay is 1000ns then for an ic_clk frequency of 10 MHz IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."
line.long 0x14 "IC_ACK_GENERAL_CALL,I2C ACK General Call Register"
bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call. When set to 1 DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise DW_apb_i2c responds with a NACK (by negating ic_data_oe)." "0: Generate NACK for a General Call,1: Generate ACK for a General Call"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,I2C Enable Status Register"
bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1 DW_apb_i2c is deemed.." "0: Slave RX Data is not lost,1: Slave RX Data is lost"
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bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to.." "0: Slave is disabled when it is idle,1: Slave is disabled when it is active"
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bitfld.long 0x0 0. "IC_EN,ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1 DW_apb_i2c is deemed to be in an enabled state. - When read as 0 DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit.." "0: I2C disabled,1: I2C enabled"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,I2C SS. FS or FM+ spike suppression limit"
hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration measured in ic_clk cycles of the longest spike in the SCL or SDA lines that will be filtered out by the.."
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Clear RESTART_DET Interrupt Register"
bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register." "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Component Parameter Register 1"
hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,TX Buffer Depth = 16"
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hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,RX Buffer Depth = 16"
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bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,Encoded parameters not visible" "0,1"
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bitfld.long 0x0 6. "HAS_DMA,DMA handshaking signals are enabled" "0,1"
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bitfld.long 0x0 5. "INTR_IO,COMBINED Interrupt outputs" "0,1"
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bitfld.long 0x0 4. "HC_COUNT_VALUES,Programmable count values for each mode." "0,1"
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bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,MAX SPEED MODE = FAST MODE" "0,1,2,3"
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bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,APB data bus width is 32 bits" "0,1,2,3"
line.long 0x4 "IC_COMP_VERSION,I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION"
line.long 0x8 "IC_COMP_TYPE,I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number."
tree.end
tree.end
tree "OTP (One-Time-Programmable Storage)"
base ad:0x0
tree "OTP"
base ad:0x40120000
group.long 0x0++0x113
line.long 0x0 "SW_LOCK0,Software lock register for page 0."
bitfld.long 0x0 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x0 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x4 "SW_LOCK1,Software lock register for page 1."
bitfld.long 0x4 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x4 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x8 "SW_LOCK2,Software lock register for page 2."
bitfld.long 0x8 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x8 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xC "SW_LOCK3,Software lock register for page 3."
bitfld.long 0xC 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xC 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x10 "SW_LOCK4,Software lock register for page 4."
bitfld.long 0x10 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x10 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x14 "SW_LOCK5,Software lock register for page 5."
bitfld.long 0x14 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x14 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x18 "SW_LOCK6,Software lock register for page 6."
bitfld.long 0x18 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x18 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x1C "SW_LOCK7,Software lock register for page 7."
bitfld.long 0x1C 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x1C 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x20 "SW_LOCK8,Software lock register for page 8."
bitfld.long 0x20 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x20 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x24 "SW_LOCK9,Software lock register for page 9."
bitfld.long 0x24 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x24 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x28 "SW_LOCK10,Software lock register for page 10."
bitfld.long 0x28 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x28 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x2C "SW_LOCK11,Software lock register for page 11."
bitfld.long 0x2C 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x2C 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x30 "SW_LOCK12,Software lock register for page 12."
bitfld.long 0x30 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x30 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x34 "SW_LOCK13,Software lock register for page 13."
bitfld.long 0x34 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x34 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x38 "SW_LOCK14,Software lock register for page 14."
bitfld.long 0x38 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x38 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x3C "SW_LOCK15,Software lock register for page 15."
bitfld.long 0x3C 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x3C 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x40 "SW_LOCK16,Software lock register for page 16."
bitfld.long 0x40 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x40 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x44 "SW_LOCK17,Software lock register for page 17."
bitfld.long 0x44 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x44 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x48 "SW_LOCK18,Software lock register for page 18."
bitfld.long 0x48 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x48 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x4C "SW_LOCK19,Software lock register for page 19."
bitfld.long 0x4C 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x4C 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x50 "SW_LOCK20,Software lock register for page 20."
bitfld.long 0x50 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x50 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x54 "SW_LOCK21,Software lock register for page 21."
bitfld.long 0x54 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x54 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x58 "SW_LOCK22,Software lock register for page 22."
bitfld.long 0x58 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x58 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x5C "SW_LOCK23,Software lock register for page 23."
bitfld.long 0x5C 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x5C 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x60 "SW_LOCK24,Software lock register for page 24."
bitfld.long 0x60 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x60 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x64 "SW_LOCK25,Software lock register for page 25."
bitfld.long 0x64 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x64 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x68 "SW_LOCK26,Software lock register for page 26."
bitfld.long 0x68 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x68 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x6C "SW_LOCK27,Software lock register for page 27."
bitfld.long 0x6C 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x6C 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x70 "SW_LOCK28,Software lock register for page 28."
bitfld.long 0x70 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x70 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x74 "SW_LOCK29,Software lock register for page 29."
bitfld.long 0x74 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x74 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x78 "SW_LOCK30,Software lock register for page 30."
bitfld.long 0x78 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x78 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x7C "SW_LOCK31,Software lock register for page 31."
bitfld.long 0x7C 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x7C 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x80 "SW_LOCK32,Software lock register for page 32."
bitfld.long 0x80 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x80 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x84 "SW_LOCK33,Software lock register for page 33."
bitfld.long 0x84 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x84 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x88 "SW_LOCK34,Software lock register for page 34."
bitfld.long 0x88 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x88 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x8C "SW_LOCK35,Software lock register for page 35."
bitfld.long 0x8C 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x8C 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x90 "SW_LOCK36,Software lock register for page 36."
bitfld.long 0x90 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x90 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x94 "SW_LOCK37,Software lock register for page 37."
bitfld.long 0x94 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x94 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x98 "SW_LOCK38,Software lock register for page 38."
bitfld.long 0x98 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x98 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x9C "SW_LOCK39,Software lock register for page 39."
bitfld.long 0x9C 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0x9C 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xA0 "SW_LOCK40,Software lock register for page 40."
bitfld.long 0xA0 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xA0 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xA4 "SW_LOCK41,Software lock register for page 41."
bitfld.long 0xA4 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xA4 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xA8 "SW_LOCK42,Software lock register for page 42."
bitfld.long 0xA8 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xA8 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xAC "SW_LOCK43,Software lock register for page 43."
bitfld.long 0xAC 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xAC 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xB0 "SW_LOCK44,Software lock register for page 44."
bitfld.long 0xB0 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xB0 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xB4 "SW_LOCK45,Software lock register for page 45."
bitfld.long 0xB4 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xB4 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xB8 "SW_LOCK46,Software lock register for page 46."
bitfld.long 0xB8 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xB8 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xBC "SW_LOCK47,Software lock register for page 47."
bitfld.long 0xBC 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xBC 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xC0 "SW_LOCK48,Software lock register for page 48."
bitfld.long 0xC0 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xC0 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xC4 "SW_LOCK49,Software lock register for page 49."
bitfld.long 0xC4 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xC4 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xC8 "SW_LOCK50,Software lock register for page 50."
bitfld.long 0xC8 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xC8 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xCC "SW_LOCK51,Software lock register for page 51."
bitfld.long 0xCC 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xCC 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xD0 "SW_LOCK52,Software lock register for page 52."
bitfld.long 0xD0 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xD0 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xD4 "SW_LOCK53,Software lock register for page 53."
bitfld.long 0xD4 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xD4 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xD8 "SW_LOCK54,Software lock register for page 54."
bitfld.long 0xD8 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xD8 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xDC "SW_LOCK55,Software lock register for page 55."
bitfld.long 0xDC 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xDC 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xE0 "SW_LOCK56,Software lock register for page 56."
bitfld.long 0xE0 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xE0 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xE4 "SW_LOCK57,Software lock register for page 57."
bitfld.long 0xE4 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xE4 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xE8 "SW_LOCK58,Software lock register for page 58."
bitfld.long 0xE8 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xE8 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xEC "SW_LOCK59,Software lock register for page 59."
bitfld.long 0xEC 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xEC 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xF0 "SW_LOCK60,Software lock register for page 60."
bitfld.long 0xF0 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xF0 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xF4 "SW_LOCK61,Software lock register for page 61."
bitfld.long 0xF4 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xF4 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xF8 "SW_LOCK62,Software lock register for page 62."
bitfld.long 0xF8 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xF8 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0xFC "SW_LOCK63,Software lock register for page 63."
bitfld.long 0xFC 2.--3. "NSEC,Non-secure lock status. Writes are OR'd with the current value." "0,1,2,3"
bitfld.long 0xFC 0.--1. "SEC,Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code." "0,1,2,3"
line.long 0x100 "SBPI_INSTR,Dispatch instructions to the SBPI interface. used for programming the OTP fuses."
bitfld.long 0x100 30. "EXEC,Execute instruction" "0,1"
bitfld.long 0x100 29. "IS_WR,Payload type is write" "0,1"
newline
bitfld.long 0x100 28. "HAS_PAYLOAD,Instruction has payload (data to be written or to be read)" "0,1"
hexmask.long.byte 0x100 24.--27. 1. "PAYLOAD_SIZE_M1,Instruction payload size in bytes minus 1"
newline
hexmask.long.byte 0x100 16.--23. 1. "TARGET,Instruction target it can be PMC (0x3a) or DAP (0x02)"
hexmask.long.byte 0x100 8.--15. 1. "CMD"
newline
hexmask.long.byte 0x100 0.--7. 1. "SHORT_WDATA,wdata to be used only when payload_size_m1=0"
line.long 0x104 "SBPI_WDATA_0,SBPI write payload bytes 3..0"
hexmask.long 0x104 0.--31. 1. "SBPI_WDATA_0"
line.long 0x108 "SBPI_WDATA_1,SBPI write payload bytes 7..4"
hexmask.long 0x108 0.--31. 1. "SBPI_WDATA_1"
line.long 0x10C "SBPI_WDATA_2,SBPI write payload bytes 11..8"
hexmask.long 0x10C 0.--31. 1. "SBPI_WDATA_2"
line.long 0x110 "SBPI_WDATA_3,SBPI write payload bytes 15..12"
hexmask.long 0x110 0.--31. 1. "SBPI_WDATA_3"
rgroup.long 0x114++0xF
line.long 0x0 "SBPI_RDATA_0,Read payload bytes 3..0. Once read. the data in the register will automatically clear to 0."
hexmask.long 0x0 0.--31. 1. "SBPI_RDATA_0"
line.long 0x4 "SBPI_RDATA_1,Read payload bytes 7..4. Once read. the data in the register will automatically clear to 0."
hexmask.long 0x4 0.--31. 1. "SBPI_RDATA_1"
line.long 0x8 "SBPI_RDATA_2,Read payload bytes 11..8. Once read. the data in the register will automatically clear to 0."
hexmask.long 0x8 0.--31. 1. "SBPI_RDATA_2"
line.long 0xC "SBPI_RDATA_3,Read payload bytes 15..12. Once read. the data in the register will automatically clear to 0."
hexmask.long 0xC 0.--31. 1. "SBPI_RDATA_3"
group.long 0x124++0xB
line.long 0x0 "SBPI_STATUS"
hexmask.long.byte 0x0 16.--23. 1. "MISO,SBPI MISO (master in - slave out): response from SBPI"
rbitfld.long 0x0 12. "FLAG,SBPI flag" "0,1"
newline
eventfld.long 0x0 8. "INSTR_MISS,Last instruction missed (dropped) as the previous has not finished running" "0,1"
eventfld.long 0x0 4. "INSTR_DONE,Last instruction done" "0,1"
newline
eventfld.long 0x0 0. "RDATA_VLD,Read command has returned data" "0,1"
line.long 0x4 "USR,Controls for APB data read interface (USER interface)"
bitfld.long 0x4 4. "PD,Power-down; 1 disables current reference. Must be 0 to read data from the OTP." "0,1"
bitfld.long 0x4 0. "DCTRL,1 enables USER interface; 0 disables USER interface (enables SBPI)." "0,1"
line.long 0x8 "DBG,Debug for OTP power-on state machine"
rbitfld.long 0x8 12. "CUSTOMER_RMA_FLAG,The chip is in RMA mode" "0,1"
hexmask.long.byte 0x8 4.--7. 1. "PSM_STATE,Monitor the PSM FSM's state"
newline
rbitfld.long 0x8 3. "ROSC_UP,Ring oscillator is up and running" "0,1"
eventfld.long 0x8 2. "ROSC_UP_SEEN,Ring oscillator was seen up and running" "0,1"
newline
rbitfld.long 0x8 1. "BOOT_DONE,PSM boot done status flag" "0,1"
rbitfld.long 0x8 0. "PSM_DONE,PSM done status flag" "0,1"
group.long 0x134++0x3
line.long 0x0 "BIST,During BIST. count address locations that have at least one leaky bit"
rbitfld.long 0x0 30. "CNT_FAIL,Flag if the count of address locations with at least one leaky bit exceeds cnt_max" "0,1"
bitfld.long 0x0 29. "CNT_CLR,Clear counter before use" "0,1"
newline
bitfld.long 0x0 28. "CNT_ENA,Enable the counter before the BIST function is initiated" "0,1"
hexmask.long.word 0x0 16.--27. 1. "CNT_MAX,The cnt_fail flag will be set if the number of leaky locations exceeds this number"
newline
hexmask.long.word 0x0 0.--12. 1. "CNT,Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option."
wgroup.long 0x138++0xF
line.long 0x0 "CRT_KEY_W0,Word 0 (bits 31..0) of the key. Write only. read returns 0x0"
hexmask.long 0x0 0.--31. 1. "CRT_KEY_W0"
line.long 0x4 "CRT_KEY_W1,Word 1 (bits 63..32) of the key. Write only. read returns 0x0"
hexmask.long 0x4 0.--31. 1. "CRT_KEY_W1"
line.long 0x8 "CRT_KEY_W2,Word 2 (bits 95..64) of the key. Write only. read returns 0x0"
hexmask.long 0x8 0.--31. 1. "CRT_KEY_W2"
line.long 0xC "CRT_KEY_W3,Word 3 (bits 127..96) of the key. Write only. read returns 0x0"
hexmask.long 0xC 0.--31. 1. "CRT_KEY_W3"
rgroup.long 0x148++0x7
line.long 0x0 "CRITICAL,Quickly check values of critical flags read during boot up"
bitfld.long 0x0 17. "RISCV_DISABLE" "0,1"
bitfld.long 0x0 16. "ARM_DISABLE" "0,1"
newline
bitfld.long 0x0 5.--6. "GLITCH_DETECTOR_SENS" "0,1,2,3"
bitfld.long 0x0 4. "GLITCH_DETECTOR_ENABLE" "0,1"
newline
bitfld.long 0x0 3. "DEFAULT_ARCHSEL" "0,1"
bitfld.long 0x0 2. "DEBUG_DISABLE" "0,1"
newline
bitfld.long 0x0 1. "SECURE_DEBUG_DISABLE" "0,1"
bitfld.long 0x0 0. "SECURE_BOOT_ENABLE" "0,1"
line.long 0x4 "KEY_VALID,Which keys were valid (enrolled) at boot time"
hexmask.long.byte 0x4 0.--7. 1. "KEY_VALID"
group.long 0x150++0xB
line.long 0x0 "DEBUGEN,Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE). OR if a debug key is marked valid in OTP. and the matching key value has.."
bitfld.long 0x0 8. "MISC,Enable other debug components. Specifically the CTI and the APB-AP used to access the RISC-V Debug Module." "0,1"
bitfld.long 0x0 3. "PROC1_SECURE,Permit core 1's Mem-AP to generate Secure accesses assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN)." "0,1"
newline
bitfld.long 0x0 2. "PROC1,Enable core 1's Mem-AP if it is currently disabled." "0,1"
bitfld.long 0x0 1. "PROC0_SECURE,Permit core 0's Mem-AP to generate Secure accesses assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN)." "0,1"
newline
bitfld.long 0x0 0. "PROC0,Enable core 0's Mem-AP if it is currently disabled." "0,1"
line.long 0x4 "DEBUGEN_LOCK,Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset."
bitfld.long 0x4 8. "MISC,Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set." "0,1"
bitfld.long 0x4 3. "PROC1_SECURE,Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set." "0,1"
newline
bitfld.long 0x4 2. "PROC1,Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set." "0,1"
bitfld.long 0x4 1. "PROC0_SECURE,Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set." "0,1"
newline
bitfld.long 0x4 0. "PROC0,Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set." "0,1"
line.long 0x8 "ARCHSEL,Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags."
bitfld.long 0x8 1. "CORE1,Select architecture for core 1." "0: Switch core 1 to Arm (Cortex-M33),1: Switch core 1 to RISC-V (Hazard3)"
bitfld.long 0x8 0. "CORE0,Select architecture for core 0." "0: Switch core 0 to Arm (Cortex-M33),1: Switch core 0 to RISC-V (Hazard3)"
rgroup.long 0x15C++0x3
line.long 0x0 "ARCHSEL_STATUS,Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released. at which point the corresponding bit in this register will also update."
bitfld.long 0x0 1. "CORE1,Current architecture for core 0. Updated on processor warm reset." "0: Core 1 is currently Arm (Cortex-M33),1: Core 1 is currently RISC-V (Hazard3)"
bitfld.long 0x0 0. "CORE0,Current architecture for core 0. Updated on processor warm reset." "0: Core 0 is currently Arm (Cortex-M33),1: Core 0 is currently RISC-V (Hazard3)"
group.long 0x160++0xF
line.long 0x0 "BOOTDIS,Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up."
bitfld.long 0x0 1. "NEXT,This flag always ORs writes into its current contents. It can be set but not cleared by software." "0,1"
eventfld.long 0x0 0. "NOW,When the core is powered down the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW and BOOTDIS_NEXT is cleared." "0,1"
line.long 0x4 "INTR,Raw Interrupts"
eventfld.long 0x4 4. "APB_RD_NSEC_FAIL" "0,1"
eventfld.long 0x4 3. "APB_RD_SEC_FAIL" "0,1"
newline
eventfld.long 0x4 2. "APB_DCTRL_FAIL" "0,1"
eventfld.long 0x4 1. "SBPI_WR_FAIL" "0,1"
newline
rbitfld.long 0x4 0. "SBPI_FLAG_N" "0,1"
line.long 0x8 "INTE,Interrupt Enable"
bitfld.long 0x8 4. "APB_RD_NSEC_FAIL" "0,1"
bitfld.long 0x8 3. "APB_RD_SEC_FAIL" "0,1"
newline
bitfld.long 0x8 2. "APB_DCTRL_FAIL" "0,1"
bitfld.long 0x8 1. "SBPI_WR_FAIL" "0,1"
newline
bitfld.long 0x8 0. "SBPI_FLAG_N" "0,1"
line.long 0xC "INTF,Interrupt Force"
bitfld.long 0xC 4. "APB_RD_NSEC_FAIL" "0,1"
bitfld.long 0xC 3. "APB_RD_SEC_FAIL" "0,1"
newline
bitfld.long 0xC 2. "APB_DCTRL_FAIL" "0,1"
bitfld.long 0xC 1. "SBPI_WR_FAIL" "0,1"
newline
bitfld.long 0xC 0. "SBPI_FLAG_N" "0,1"
rgroup.long 0x170++0x3
line.long 0x0 "INTS,Interrupt status after masking & forcing"
bitfld.long 0x0 4. "APB_RD_NSEC_FAIL" "0,1"
bitfld.long 0x0 3. "APB_RD_SEC_FAIL" "0,1"
newline
bitfld.long 0x0 2. "APB_DCTRL_FAIL" "0,1"
bitfld.long 0x0 1. "SBPI_WR_FAIL" "0,1"
newline
bitfld.long 0x0 0. "SBPI_FLAG_N" "0,1"
tree.end
tree "OTP_DATA"
base ad:0x40130000
rgroup.word 0x0++0x17
line.word 0x0 "CHIPID0,Bits 15:0 of public device ID. (ECC)"
hexmask.word 0x0 0.--15. 1. "CHIPID0"
line.word 0x2 "CHIPID1,Bits 31:16 of public device ID (ECC)"
hexmask.word 0x2 0.--15. 1. "CHIPID1"
line.word 0x4 "CHIPID2,Bits 47:32 of public device ID (ECC)"
hexmask.word 0x4 0.--15. 1. "CHIPID2"
line.word 0x6 "CHIPID3,Bits 63:48 of public device ID (ECC)"
hexmask.word 0x6 0.--15. 1. "CHIPID3"
line.word 0x8 "RANDID0,Bits 15:0 of private per-device random number (ECC)"
hexmask.word 0x8 0.--15. 1. "RANDID0"
line.word 0xA "RANDID1,Bits 31:16 of private per-device random number (ECC)"
hexmask.word 0xA 0.--15. 1. "RANDID1"
line.word 0xC "RANDID2,Bits 47:32 of private per-device random number (ECC)"
hexmask.word 0xC 0.--15. 1. "RANDID2"
line.word 0xE "RANDID3,Bits 63:48 of private per-device random number (ECC)"
hexmask.word 0xE 0.--15. 1. "RANDID3"
line.word 0x10 "RANDID4,Bits 79:64 of private per-device random number (ECC)"
hexmask.word 0x10 0.--15. 1. "RANDID4"
line.word 0x12 "RANDID5,Bits 95:80 of private per-device random number (ECC)"
hexmask.word 0x12 0.--15. 1. "RANDID5"
line.word 0x14 "RANDID6,Bits 111:96 of private per-device random number (ECC)"
hexmask.word 0x14 0.--15. 1. "RANDID6"
line.word 0x16 "RANDID7,Bits 127:112 of private per-device random number (ECC)"
hexmask.word 0x16 0.--15. 1. "RANDID7"
rgroup.word 0x20++0x3
line.word 0x0 "ROSC_CALIB,Ring oscillator frequency in kHz. measured during manufacturing (ECC)"
hexmask.word 0x0 0.--15. 1. "ROSC_CALIB"
line.word 0x2 "LPOSC_CALIB,Low-power oscillator frequency in Hz. measured during manufacturing (ECC)"
hexmask.word 0x2 0.--15. 1. "LPOSC_CALIB"
rgroup.word 0x30++0x1
line.word 0x0 "NUM_GPIOS,The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package. and 30 in the QFN60 package. (ECC)"
hexmask.word.byte 0x0 0.--7. 1. "NUM_GPIOS"
rgroup.word 0x6C++0x3
line.word 0x0 "INFO_CRC0,Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7. input reflected. output reflected. seed all-ones. final XOR all-ones) (ECC)"
hexmask.word 0x0 0.--15. 1. "INFO_CRC0"
line.word 0x2 "INFO_CRC1,Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"
hexmask.word 0x2 0.--15. 1. "INFO_CRC1"
rgroup.word 0xA8++0x9
line.word 0x0 "FLASH_DEVINFO,Stores information about external flash device(s). (ECC)"
hexmask.word.byte 0x0 12.--15. 1. "CS1_SIZE,The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff)."
hexmask.word.byte 0x0 8.--11. 1. "CS0_SIZE,The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff)."
bitfld.word 0x0 7. "D8H_ERASE_SUPPORTED,If true all attached devices are assumed to support (or ignore in the case of PSRAM) a block erase command with a command prefix of D8h an erase size of 64 kiB and a 24-bit address. Almost all 25-series flash devices support this.." "0,1"
hexmask.word.byte 0x0 0.--5. 1. "CS1_GPIO,Indicate a GPIO number to be used for the secondary flash chip select (CS1) which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0 as the primary chip select has.."
line.word 0x2 "FLASH_PARTITION_SLOT_SIZE,Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS. the size is 4096 * (value + 1)"
hexmask.word 0x2 0.--15. 1. "FLASH_PARTITION_SLOT_SIZE"
line.word 0x4 "BOOTSEL_LED_CFG,Pin configuration for LED status. used by USB bootloader. (ECC)"
bitfld.word 0x4 8. "ACTIVELOW,LED is active-low. (Default: active-high.)" "0,1"
hexmask.word.byte 0x4 0.--5. 1. "PIN,GPIO index to use for bootloader activity LED."
line.word 0x6 "BOOTSEL_PLL_CFG,Optional PLL configuration for BOOTSEL mode. (ECC)"
bitfld.word 0x6 15. "REFDIV,PLL reference divisor minus one." "0,1"
bitfld.word 0x6 12.--14. "POSTDIV2,PLL post-divide 2 divisor in the range 1..7 inclusive." "0,1,2,3,4,5,6,7"
bitfld.word 0x6 9.--11. "POSTDIV1,PLL post-divide 1 divisor in the range 1..7 inclusive." "0,1,2,3,4,5,6,7"
hexmask.word 0x6 0.--8. 1. "FBDIV,PLL feedback divisor in the range 16..320 inclusive."
line.word 0x8 "BOOTSEL_XOSC_CFG,Non-default crystal oscillator configuration for the USB bootloader. (ECC)"
bitfld.word 0x8 14.--15. "RANGE,Value of the XOSC_CTRL_FREQ_RANGE register." "0,1,2,3"
hexmask.word 0x8 0.--13. 1. "STARTUP,Value of the XOSC_STARTUP register"
rgroup.word 0xB8++0x1
line.word 0x0 "USB_WHITE_LABEL_ADDR,Row index of the USB_WHITE_LABEL structure within OTP (ECC)"
hexmask.word 0x0 0.--15. 1. "USB_WHITE_LABEL_ADDR"
rgroup.word 0xBC++0x7
line.word 0x0 "OTPBOOT_SRC,OTP start row for the OTP boot image. (ECC)"
hexmask.word 0x0 0.--15. 1. "OTPBOOT_SRC"
line.word 0x2 "OTPBOOT_LEN,Length in rows of the OTP boot image. (ECC)"
hexmask.word 0x2 0.--15. 1. "OTPBOOT_LEN"
line.word 0x4 "OTPBOOT_DST0,Bits 15:0 of the OTP boot image load destination (and entry point). (ECC)"
hexmask.word 0x4 0.--15. 1. "OTPBOOT_DST0"
line.word 0x6 "OTPBOOT_DST1,Bits 31:16 of the OTP boot image load destination (and entry point). (ECC)"
hexmask.word 0x6 0.--15. 1. "OTPBOOT_DST1"
rgroup.word 0x100++0x7F
line.word 0x0 "BOOTKEY0_0,Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x0 0.--15. 1. "BOOTKEY0_0"
line.word 0x2 "BOOTKEY0_1,Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x2 0.--15. 1. "BOOTKEY0_1"
line.word 0x4 "BOOTKEY0_2,Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x4 0.--15. 1. "BOOTKEY0_2"
line.word 0x6 "BOOTKEY0_3,Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x6 0.--15. 1. "BOOTKEY0_3"
line.word 0x8 "BOOTKEY0_4,Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x8 0.--15. 1. "BOOTKEY0_4"
line.word 0xA "BOOTKEY0_5,Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0xA 0.--15. 1. "BOOTKEY0_5"
line.word 0xC "BOOTKEY0_6,Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0xC 0.--15. 1. "BOOTKEY0_6"
line.word 0xE "BOOTKEY0_7,Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0xE 0.--15. 1. "BOOTKEY0_7"
line.word 0x10 "BOOTKEY0_8,Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x10 0.--15. 1. "BOOTKEY0_8"
line.word 0x12 "BOOTKEY0_9,Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x12 0.--15. 1. "BOOTKEY0_9"
line.word 0x14 "BOOTKEY0_10,Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x14 0.--15. 1. "BOOTKEY0_10"
line.word 0x16 "BOOTKEY0_11,Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x16 0.--15. 1. "BOOTKEY0_11"
line.word 0x18 "BOOTKEY0_12,Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x18 0.--15. 1. "BOOTKEY0_12"
line.word 0x1A "BOOTKEY0_13,Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x1A 0.--15. 1. "BOOTKEY0_13"
line.word 0x1C "BOOTKEY0_14,Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x1C 0.--15. 1. "BOOTKEY0_14"
line.word 0x1E "BOOTKEY0_15,Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"
hexmask.word 0x1E 0.--15. 1. "BOOTKEY0_15"
line.word 0x20 "BOOTKEY1_0,Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x20 0.--15. 1. "BOOTKEY1_0"
line.word 0x22 "BOOTKEY1_1,Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x22 0.--15. 1. "BOOTKEY1_1"
line.word 0x24 "BOOTKEY1_2,Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x24 0.--15. 1. "BOOTKEY1_2"
line.word 0x26 "BOOTKEY1_3,Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x26 0.--15. 1. "BOOTKEY1_3"
line.word 0x28 "BOOTKEY1_4,Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x28 0.--15. 1. "BOOTKEY1_4"
line.word 0x2A "BOOTKEY1_5,Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x2A 0.--15. 1. "BOOTKEY1_5"
line.word 0x2C "BOOTKEY1_6,Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x2C 0.--15. 1. "BOOTKEY1_6"
line.word 0x2E "BOOTKEY1_7,Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x2E 0.--15. 1. "BOOTKEY1_7"
line.word 0x30 "BOOTKEY1_8,Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x30 0.--15. 1. "BOOTKEY1_8"
line.word 0x32 "BOOTKEY1_9,Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x32 0.--15. 1. "BOOTKEY1_9"
line.word 0x34 "BOOTKEY1_10,Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x34 0.--15. 1. "BOOTKEY1_10"
line.word 0x36 "BOOTKEY1_11,Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x36 0.--15. 1. "BOOTKEY1_11"
line.word 0x38 "BOOTKEY1_12,Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x38 0.--15. 1. "BOOTKEY1_12"
line.word 0x3A "BOOTKEY1_13,Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x3A 0.--15. 1. "BOOTKEY1_13"
line.word 0x3C "BOOTKEY1_14,Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x3C 0.--15. 1. "BOOTKEY1_14"
line.word 0x3E "BOOTKEY1_15,Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"
hexmask.word 0x3E 0.--15. 1. "BOOTKEY1_15"
line.word 0x40 "BOOTKEY2_0,Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x40 0.--15. 1. "BOOTKEY2_0"
line.word 0x42 "BOOTKEY2_1,Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x42 0.--15. 1. "BOOTKEY2_1"
line.word 0x44 "BOOTKEY2_2,Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x44 0.--15. 1. "BOOTKEY2_2"
line.word 0x46 "BOOTKEY2_3,Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x46 0.--15. 1. "BOOTKEY2_3"
line.word 0x48 "BOOTKEY2_4,Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x48 0.--15. 1. "BOOTKEY2_4"
line.word 0x4A "BOOTKEY2_5,Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x4A 0.--15. 1. "BOOTKEY2_5"
line.word 0x4C "BOOTKEY2_6,Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x4C 0.--15. 1. "BOOTKEY2_6"
line.word 0x4E "BOOTKEY2_7,Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x4E 0.--15. 1. "BOOTKEY2_7"
line.word 0x50 "BOOTKEY2_8,Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x50 0.--15. 1. "BOOTKEY2_8"
line.word 0x52 "BOOTKEY2_9,Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x52 0.--15. 1. "BOOTKEY2_9"
line.word 0x54 "BOOTKEY2_10,Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x54 0.--15. 1. "BOOTKEY2_10"
line.word 0x56 "BOOTKEY2_11,Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x56 0.--15. 1. "BOOTKEY2_11"
line.word 0x58 "BOOTKEY2_12,Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x58 0.--15. 1. "BOOTKEY2_12"
line.word 0x5A "BOOTKEY2_13,Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x5A 0.--15. 1. "BOOTKEY2_13"
line.word 0x5C "BOOTKEY2_14,Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x5C 0.--15. 1. "BOOTKEY2_14"
line.word 0x5E "BOOTKEY2_15,Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"
hexmask.word 0x5E 0.--15. 1. "BOOTKEY2_15"
line.word 0x60 "BOOTKEY3_0,Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x60 0.--15. 1. "BOOTKEY3_0"
line.word 0x62 "BOOTKEY3_1,Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x62 0.--15. 1. "BOOTKEY3_1"
line.word 0x64 "BOOTKEY3_2,Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x64 0.--15. 1. "BOOTKEY3_2"
line.word 0x66 "BOOTKEY3_3,Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x66 0.--15. 1. "BOOTKEY3_3"
line.word 0x68 "BOOTKEY3_4,Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x68 0.--15. 1. "BOOTKEY3_4"
line.word 0x6A "BOOTKEY3_5,Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x6A 0.--15. 1. "BOOTKEY3_5"
line.word 0x6C "BOOTKEY3_6,Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x6C 0.--15. 1. "BOOTKEY3_6"
line.word 0x6E "BOOTKEY3_7,Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x6E 0.--15. 1. "BOOTKEY3_7"
line.word 0x70 "BOOTKEY3_8,Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x70 0.--15. 1. "BOOTKEY3_8"
line.word 0x72 "BOOTKEY3_9,Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x72 0.--15. 1. "BOOTKEY3_9"
line.word 0x74 "BOOTKEY3_10,Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x74 0.--15. 1. "BOOTKEY3_10"
line.word 0x76 "BOOTKEY3_11,Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x76 0.--15. 1. "BOOTKEY3_11"
line.word 0x78 "BOOTKEY3_12,Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x78 0.--15. 1. "BOOTKEY3_12"
line.word 0x7A "BOOTKEY3_13,Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x7A 0.--15. 1. "BOOTKEY3_13"
line.word 0x7C "BOOTKEY3_14,Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x7C 0.--15. 1. "BOOTKEY3_14"
line.word 0x7E "BOOTKEY3_15,Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"
hexmask.word 0x7E 0.--15. 1. "BOOTKEY3_15"
rgroup.word 0x1E90++0x5F
line.word 0x0 "KEY1_0,Bits 15:0 of OTP access key 1 (ECC)"
hexmask.word 0x0 0.--15. 1. "KEY1_0"
line.word 0x2 "KEY1_1,Bits 31:16 of OTP access key 1 (ECC)"
hexmask.word 0x2 0.--15. 1. "KEY1_1"
line.word 0x4 "KEY1_2,Bits 47:32 of OTP access key 1 (ECC)"
hexmask.word 0x4 0.--15. 1. "KEY1_2"
line.word 0x6 "KEY1_3,Bits 63:48 of OTP access key 1 (ECC)"
hexmask.word 0x6 0.--15. 1. "KEY1_3"
line.word 0x8 "KEY1_4,Bits 79:64 of OTP access key 1 (ECC)"
hexmask.word 0x8 0.--15. 1. "KEY1_4"
line.word 0xA "KEY1_5,Bits 95:80 of OTP access key 1 (ECC)"
hexmask.word 0xA 0.--15. 1. "KEY1_5"
line.word 0xC "KEY1_6,Bits 111:96 of OTP access key 1 (ECC)"
hexmask.word 0xC 0.--15. 1. "KEY1_6"
line.word 0xE "KEY1_7,Bits 127:112 of OTP access key 1 (ECC)"
hexmask.word 0xE 0.--15. 1. "KEY1_7"
line.word 0x10 "KEY2_0,Bits 15:0 of OTP access key 2 (ECC)"
hexmask.word 0x10 0.--15. 1. "KEY2_0"
line.word 0x12 "KEY2_1,Bits 31:16 of OTP access key 2 (ECC)"
hexmask.word 0x12 0.--15. 1. "KEY2_1"
line.word 0x14 "KEY2_2,Bits 47:32 of OTP access key 2 (ECC)"
hexmask.word 0x14 0.--15. 1. "KEY2_2"
line.word 0x16 "KEY2_3,Bits 63:48 of OTP access key 2 (ECC)"
hexmask.word 0x16 0.--15. 1. "KEY2_3"
line.word 0x18 "KEY2_4,Bits 79:64 of OTP access key 2 (ECC)"
hexmask.word 0x18 0.--15. 1. "KEY2_4"
line.word 0x1A "KEY2_5,Bits 95:80 of OTP access key 2 (ECC)"
hexmask.word 0x1A 0.--15. 1. "KEY2_5"
line.word 0x1C "KEY2_6,Bits 111:96 of OTP access key 2 (ECC)"
hexmask.word 0x1C 0.--15. 1. "KEY2_6"
line.word 0x1E "KEY2_7,Bits 127:112 of OTP access key 2 (ECC)"
hexmask.word 0x1E 0.--15. 1. "KEY2_7"
line.word 0x20 "KEY3_0,Bits 15:0 of OTP access key 3 (ECC)"
hexmask.word 0x20 0.--15. 1. "KEY3_0"
line.word 0x22 "KEY3_1,Bits 31:16 of OTP access key 3 (ECC)"
hexmask.word 0x22 0.--15. 1. "KEY3_1"
line.word 0x24 "KEY3_2,Bits 47:32 of OTP access key 3 (ECC)"
hexmask.word 0x24 0.--15. 1. "KEY3_2"
line.word 0x26 "KEY3_3,Bits 63:48 of OTP access key 3 (ECC)"
hexmask.word 0x26 0.--15. 1. "KEY3_3"
line.word 0x28 "KEY3_4,Bits 79:64 of OTP access key 3 (ECC)"
hexmask.word 0x28 0.--15. 1. "KEY3_4"
line.word 0x2A "KEY3_5,Bits 95:80 of OTP access key 3 (ECC)"
hexmask.word 0x2A 0.--15. 1. "KEY3_5"
line.word 0x2C "KEY3_6,Bits 111:96 of OTP access key 3 (ECC)"
hexmask.word 0x2C 0.--15. 1. "KEY3_6"
line.word 0x2E "KEY3_7,Bits 127:112 of OTP access key 3 (ECC)"
hexmask.word 0x2E 0.--15. 1. "KEY3_7"
line.word 0x30 "KEY4_0,Bits 15:0 of OTP access key 4 (ECC)"
hexmask.word 0x30 0.--15. 1. "KEY4_0"
line.word 0x32 "KEY4_1,Bits 31:16 of OTP access key 4 (ECC)"
hexmask.word 0x32 0.--15. 1. "KEY4_1"
line.word 0x34 "KEY4_2,Bits 47:32 of OTP access key 4 (ECC)"
hexmask.word 0x34 0.--15. 1. "KEY4_2"
line.word 0x36 "KEY4_3,Bits 63:48 of OTP access key 4 (ECC)"
hexmask.word 0x36 0.--15. 1. "KEY4_3"
line.word 0x38 "KEY4_4,Bits 79:64 of OTP access key 4 (ECC)"
hexmask.word 0x38 0.--15. 1. "KEY4_4"
line.word 0x3A "KEY4_5,Bits 95:80 of OTP access key 4 (ECC)"
hexmask.word 0x3A 0.--15. 1. "KEY4_5"
line.word 0x3C "KEY4_6,Bits 111:96 of OTP access key 4 (ECC)"
hexmask.word 0x3C 0.--15. 1. "KEY4_6"
line.word 0x3E "KEY4_7,Bits 127:112 of OTP access key 4 (ECC)"
hexmask.word 0x3E 0.--15. 1. "KEY4_7"
line.word 0x40 "KEY5_0,Bits 15:0 of OTP access key 5 (ECC)"
hexmask.word 0x40 0.--15. 1. "KEY5_0"
line.word 0x42 "KEY5_1,Bits 31:16 of OTP access key 5 (ECC)"
hexmask.word 0x42 0.--15. 1. "KEY5_1"
line.word 0x44 "KEY5_2,Bits 47:32 of OTP access key 5 (ECC)"
hexmask.word 0x44 0.--15. 1. "KEY5_2"
line.word 0x46 "KEY5_3,Bits 63:48 of OTP access key 5 (ECC)"
hexmask.word 0x46 0.--15. 1. "KEY5_3"
line.word 0x48 "KEY5_4,Bits 79:64 of OTP access key 5 (ECC)"
hexmask.word 0x48 0.--15. 1. "KEY5_4"
line.word 0x4A "KEY5_5,Bits 95:80 of OTP access key 5 (ECC)"
hexmask.word 0x4A 0.--15. 1. "KEY5_5"
line.word 0x4C "KEY5_6,Bits 111:96 of OTP access key 5 (ECC)"
hexmask.word 0x4C 0.--15. 1. "KEY5_6"
line.word 0x4E "KEY5_7,Bits 127:112 of OTP access key 5 (ECC)"
hexmask.word 0x4E 0.--15. 1. "KEY5_7"
line.word 0x50 "KEY6_0,Bits 15:0 of OTP access key 6 (ECC)"
hexmask.word 0x50 0.--15. 1. "KEY6_0"
line.word 0x52 "KEY6_1,Bits 31:16 of OTP access key 6 (ECC)"
hexmask.word 0x52 0.--15. 1. "KEY6_1"
line.word 0x54 "KEY6_2,Bits 47:32 of OTP access key 6 (ECC)"
hexmask.word 0x54 0.--15. 1. "KEY6_2"
line.word 0x56 "KEY6_3,Bits 63:48 of OTP access key 6 (ECC)"
hexmask.word 0x56 0.--15. 1. "KEY6_3"
line.word 0x58 "KEY6_4,Bits 79:64 of OTP access key 6 (ECC)"
hexmask.word 0x58 0.--15. 1. "KEY6_4"
line.word 0x5A "KEY6_5,Bits 95:80 of OTP access key 6 (ECC)"
hexmask.word 0x5A 0.--15. 1. "KEY6_5"
line.word 0x5C "KEY6_6,Bits 111:96 of OTP access key 6 (ECC)"
hexmask.word 0x5C 0.--15. 1. "KEY6_6"
line.word 0x5E "KEY6_7,Bits 127:112 of OTP access key 6 (ECC)"
hexmask.word 0x5E 0.--15. 1. "KEY6_7"
tree.end
tree "OTP_DATA_RAW"
base ad:0x40134000
rgroup.long 0x0++0x2F
line.long 0x0 "CHIPID0,Bits 15:0 of public device ID. (ECC)"
hexmask.long.word 0x0 0.--15. 1. "CHIPID0"
line.long 0x4 "CHIPID1,Bits 31:16 of public device ID (ECC)"
hexmask.long.word 0x4 0.--15. 1. "CHIPID1"
line.long 0x8 "CHIPID2,Bits 47:32 of public device ID (ECC)"
hexmask.long.word 0x8 0.--15. 1. "CHIPID2"
line.long 0xC "CHIPID3,Bits 63:48 of public device ID (ECC)"
hexmask.long.word 0xC 0.--15. 1. "CHIPID3"
line.long 0x10 "RANDID0,Bits 15:0 of private per-device random number (ECC)"
hexmask.long.word 0x10 0.--15. 1. "RANDID0"
line.long 0x14 "RANDID1,Bits 31:16 of private per-device random number (ECC)"
hexmask.long.word 0x14 0.--15. 1. "RANDID1"
line.long 0x18 "RANDID2,Bits 47:32 of private per-device random number (ECC)"
hexmask.long.word 0x18 0.--15. 1. "RANDID2"
line.long 0x1C "RANDID3,Bits 63:48 of private per-device random number (ECC)"
hexmask.long.word 0x1C 0.--15. 1. "RANDID3"
line.long 0x20 "RANDID4,Bits 79:64 of private per-device random number (ECC)"
hexmask.long.word 0x20 0.--15. 1. "RANDID4"
line.long 0x24 "RANDID5,Bits 95:80 of private per-device random number (ECC)"
hexmask.long.word 0x24 0.--15. 1. "RANDID5"
line.long 0x28 "RANDID6,Bits 111:96 of private per-device random number (ECC)"
hexmask.long.word 0x28 0.--15. 1. "RANDID6"
line.long 0x2C "RANDID7,Bits 127:112 of private per-device random number (ECC)"
hexmask.long.word 0x2C 0.--15. 1. "RANDID7"
rgroup.long 0x40++0x7
line.long 0x0 "ROSC_CALIB,Ring oscillator frequency in kHz. measured during manufacturing (ECC)"
hexmask.long.word 0x0 0.--15. 1. "ROSC_CALIB"
line.long 0x4 "LPOSC_CALIB,Low-power oscillator frequency in Hz. measured during manufacturing (ECC)"
hexmask.long.word 0x4 0.--15. 1. "LPOSC_CALIB"
rgroup.long 0x60++0x3
line.long 0x0 "NUM_GPIOS,The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package. and 30 in the QFN60 package. (ECC)"
hexmask.long.byte 0x0 0.--7. 1. "NUM_GPIOS"
rgroup.long 0xD8++0x9B
line.long 0x0 "INFO_CRC0,Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7. input reflected. output reflected. seed all-ones. final XOR all-ones) (ECC)"
hexmask.long.word 0x0 0.--15. 1. "INFO_CRC0"
line.long 0x4 "INFO_CRC1,Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"
hexmask.long.word 0x4 0.--15. 1. "INFO_CRC1"
line.long 0x8 "CRIT0,Page 0 critical boot flags (RBIT-8)"
bitfld.long 0x8 1. "RISCV_DISABLE,Permanently disable RISC-V processors (Hazard3)" "0,1"
newline
bitfld.long 0x8 0. "ARM_DISABLE,Permanently disable ARM processors (Cortex-M33)" "0,1"
line.long 0xC "CRIT0_R1,Redundant copy of CRIT0"
hexmask.long.tbyte 0xC 0.--23. 1. "CRIT0_R1"
line.long 0x10 "CRIT0_R2,Redundant copy of CRIT0"
hexmask.long.tbyte 0x10 0.--23. 1. "CRIT0_R2"
line.long 0x14 "CRIT0_R3,Redundant copy of CRIT0"
hexmask.long.tbyte 0x14 0.--23. 1. "CRIT0_R3"
line.long 0x18 "CRIT0_R4,Redundant copy of CRIT0"
hexmask.long.tbyte 0x18 0.--23. 1. "CRIT0_R4"
line.long 0x1C "CRIT0_R5,Redundant copy of CRIT0"
hexmask.long.tbyte 0x1C 0.--23. 1. "CRIT0_R5"
line.long 0x20 "CRIT0_R6,Redundant copy of CRIT0"
hexmask.long.tbyte 0x20 0.--23. 1. "CRIT0_R6"
line.long 0x24 "CRIT0_R7,Redundant copy of CRIT0"
hexmask.long.tbyte 0x24 0.--23. 1. "CRIT0_R7"
line.long 0x28 "CRIT1,Page 1 critical boot flags (RBIT-8)"
bitfld.long 0x28 5.--6. "GLITCH_DETECTOR_SENS,Increase the sensitivity of the glitch detectors from their default." "0,1,2,3"
newline
bitfld.long 0x28 4. "GLITCH_DETECTOR_ENABLE,Arm the glitch detectors to reset the system if an abnormal clock/power event is observed." "0,1"
newline
bitfld.long 0x28 3. "BOOT_ARCH,Set the default boot architecture 0=ARM 1=RISC-V. Ignored if ARM_DISABLE RISCV_DISABLE or SECURE_BOOT_ENABLE is set." "0: ARM,1: RISC-V"
newline
bitfld.long 0x28 2. "DEBUG_DISABLE,Disable all debug access" "0,1"
newline
bitfld.long 0x28 1. "SECURE_DEBUG_DISABLE,Disable Secure debug access" "0,1"
newline
bitfld.long 0x28 0. "SECURE_BOOT_ENABLE,Enable boot signature enforcement and permanently disable the RISC-V cores." "0,1"
line.long 0x2C "CRIT1_R1,Redundant copy of CRIT1"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRIT1_R1"
line.long 0x30 "CRIT1_R2,Redundant copy of CRIT1"
hexmask.long.tbyte 0x30 0.--23. 1. "CRIT1_R2"
line.long 0x34 "CRIT1_R3,Redundant copy of CRIT1"
hexmask.long.tbyte 0x34 0.--23. 1. "CRIT1_R3"
line.long 0x38 "CRIT1_R4,Redundant copy of CRIT1"
hexmask.long.tbyte 0x38 0.--23. 1. "CRIT1_R4"
line.long 0x3C "CRIT1_R5,Redundant copy of CRIT1"
hexmask.long.tbyte 0x3C 0.--23. 1. "CRIT1_R5"
line.long 0x40 "CRIT1_R6,Redundant copy of CRIT1"
hexmask.long.tbyte 0x40 0.--23. 1. "CRIT1_R6"
line.long 0x44 "CRIT1_R7,Redundant copy of CRIT1"
hexmask.long.tbyte 0x44 0.--23. 1. "CRIT1_R7"
line.long 0x48 "BOOT_FLAGS0,Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"
bitfld.long 0x48 21. "DISABLE_SRAM_WINDOW_BOOT" "0,1"
newline
bitfld.long 0x48 20. "DISABLE_XIP_ACCESS_ON_SRAM_ENTRY,Disable all access to XIP after entering an SRAM binary." "0,1"
newline
bitfld.long 0x48 19. "DISABLE_BOOTSEL_UART_BOOT" "0,1"
newline
bitfld.long 0x48 18. "DISABLE_BOOTSEL_USB_PICOBOOT_IFC" "0,1"
newline
bitfld.long 0x48 17. "DISABLE_BOOTSEL_USB_MSD_IFC" "0,1"
newline
bitfld.long 0x48 16. "DISABLE_WATCHDOG_SCRATCH" "0,1"
newline
bitfld.long 0x48 15. "DISABLE_POWER_SCRATCH" "0,1"
newline
bitfld.long 0x48 14. "ENABLE_OTP_BOOT,Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded starting from OTPBOOT_SRC into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0." "0,1"
newline
bitfld.long 0x48 13. "DISABLE_OTP_BOOT,Takes precedence over ENABLE_OTP_BOOT." "0,1"
newline
bitfld.long 0x48 12. "DISABLE_FLASH_BOOT" "0,1"
newline
bitfld.long 0x48 11. "ROLLBACK_REQUIRED,Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted." "0,1"
newline
bitfld.long 0x48 10. "HASHED_PARTITION_TABLE,Require a partition table to be hashed (if not signed)" "0,1"
newline
bitfld.long 0x48 9. "SECURE_PARTITION_TABLE,Require a partition table to be signed" "0,1"
newline
bitfld.long 0x48 8. "DISABLE_AUTO_SWITCH_ARCH,Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled" "0,1"
newline
bitfld.long 0x48 7. "SINGLE_FLASH_BINARY,Restrict flash boot path to use of a single binary at the start of flash" "0,1"
newline
bitfld.long 0x48 6. "OVERRIDE_FLASH_PARTITION_SLOT_SIZE,Override the limit for default flash metadata scanning." "0,1"
newline
bitfld.long 0x48 5. "FLASH_DEVINFO_ENABLE,Mark FLASH_DEVINFO as containing valid ECC'd data which describes external flash devices." "0,1"
newline
bitfld.long 0x48 4. "FAST_SIGCHECK_ROSC_DIV,Enable quartering of ROSC divisor during signature check to reduce secure boot time" "0,1"
newline
bitfld.long 0x48 3. "FLASH_IO_VOLTAGE_1V8,If 1 configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low.." "0,1"
newline
bitfld.long 0x48 2. "ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG,Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode." "0,1"
newline
bitfld.long 0x48 1. "ENABLE_BOOTSEL_LED,Enable bootloader activity LED. If set bootsel_led_cfg is assumed to be valid" "0,1"
newline
bitfld.long 0x48 0. "DISABLE_BOOTSEL_EXEC2" "0,1"
line.long 0x4C "BOOT_FLAGS0_R1,Redundant copy of BOOT_FLAGS0"
hexmask.long.tbyte 0x4C 0.--23. 1. "BOOT_FLAGS0_R1"
line.long 0x50 "BOOT_FLAGS0_R2,Redundant copy of BOOT_FLAGS0"
hexmask.long.tbyte 0x50 0.--23. 1. "BOOT_FLAGS0_R2"
line.long 0x54 "BOOT_FLAGS1,Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"
bitfld.long 0x54 19. "DOUBLE_TAP,Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time as configured by DOUBLE_TAP_DELAY." "0,1"
newline
bitfld.long 0x54 16.--18. "DOUBLE_TAP_DELAY,Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds and each unit of this field adds an additional 50 milliseconds." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x54 8.--11. 1. "KEY_INVALID,Mark a boot key as invalid or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks."
newline
hexmask.long.byte 0x54 0.--3. 1. "KEY_VALID,Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys and ignore invalid boot keys."
line.long 0x58 "BOOT_FLAGS1_R1,Redundant copy of BOOT_FLAGS1"
hexmask.long.tbyte 0x58 0.--23. 1. "BOOT_FLAGS1_R1"
line.long 0x5C "BOOT_FLAGS1_R2,Redundant copy of BOOT_FLAGS1"
hexmask.long.tbyte 0x5C 0.--23. 1. "BOOT_FLAGS1_R2"
line.long 0x60 "DEFAULT_BOOT_VERSION0,Default boot version thermometer counter. bits 23:0 (RBIT-3)"
hexmask.long.tbyte 0x60 0.--23. 1. "DEFAULT_BOOT_VERSION0"
line.long 0x64 "DEFAULT_BOOT_VERSION0_R1,Redundant copy of DEFAULT_BOOT_VERSION0"
hexmask.long.tbyte 0x64 0.--23. 1. "DEFAULT_BOOT_VERSION0_R1"
line.long 0x68 "DEFAULT_BOOT_VERSION0_R2,Redundant copy of DEFAULT_BOOT_VERSION0"
hexmask.long.tbyte 0x68 0.--23. 1. "DEFAULT_BOOT_VERSION0_R2"
line.long 0x6C "DEFAULT_BOOT_VERSION1,Default boot version thermometer counter. bits 47:24 (RBIT-3)"
hexmask.long.tbyte 0x6C 0.--23. 1. "DEFAULT_BOOT_VERSION1"
line.long 0x70 "DEFAULT_BOOT_VERSION1_R1,Redundant copy of DEFAULT_BOOT_VERSION1"
hexmask.long.tbyte 0x70 0.--23. 1. "DEFAULT_BOOT_VERSION1_R1"
line.long 0x74 "DEFAULT_BOOT_VERSION1_R2,Redundant copy of DEFAULT_BOOT_VERSION1"
hexmask.long.tbyte 0x74 0.--23. 1. "DEFAULT_BOOT_VERSION1_R2"
line.long 0x78 "FLASH_DEVINFO,Stores information about external flash device(s). (ECC)"
hexmask.long.byte 0x78 12.--15. 1. "CS1_SIZE,The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff)."
newline
hexmask.long.byte 0x78 8.--11. 1. "CS0_SIZE,The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff)."
newline
bitfld.long 0x78 7. "D8H_ERASE_SUPPORTED,If true all attached devices are assumed to support (or ignore in the case of PSRAM) a block erase command with a command prefix of D8h an erase size of 64 kiB and a 24-bit address. Almost all 25-series flash devices support this.." "0,1"
newline
hexmask.long.byte 0x78 0.--5. 1. "CS1_GPIO,Indicate a GPIO number to be used for the secondary flash chip select (CS1) which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0 as the primary chip select has.."
line.long 0x7C "FLASH_PARTITION_SLOT_SIZE,Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS. the size is 4096 * (value + 1)"
hexmask.long.word 0x7C 0.--15. 1. "FLASH_PARTITION_SLOT_SIZE"
line.long 0x80 "BOOTSEL_LED_CFG,Pin configuration for LED status. used by USB bootloader. (ECC)"
bitfld.long 0x80 8. "ACTIVELOW,LED is active-low. (Default: active-high.)" "0,1"
newline
hexmask.long.byte 0x80 0.--5. 1. "PIN,GPIO index to use for bootloader activity LED."
line.long 0x84 "BOOTSEL_PLL_CFG,Optional PLL configuration for BOOTSEL mode. (ECC)"
bitfld.long 0x84 15. "REFDIV,PLL reference divisor minus one." "0,1"
newline
bitfld.long 0x84 12.--14. "POSTDIV2,PLL post-divide 2 divisor in the range 1..7 inclusive." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x84 9.--11. "POSTDIV1,PLL post-divide 1 divisor in the range 1..7 inclusive." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x84 0.--8. 1. "FBDIV,PLL feedback divisor in the range 16..320 inclusive."
line.long 0x88 "BOOTSEL_XOSC_CFG,Non-default crystal oscillator configuration for the USB bootloader. (ECC)"
bitfld.long 0x88 14.--15. "RANGE,Value of the XOSC_CTRL_FREQ_RANGE register." "0,1,2,3"
newline
hexmask.long.word 0x88 0.--13. 1. "STARTUP,Value of the XOSC_STARTUP register"
line.long 0x8C "USB_BOOT_FLAGS,USB boot specific feature flags (RBIT-3)"
bitfld.long 0x8C 23. "DP_DM_SWAP,Swap DM/DP during USB boot to support board layouts with mirrored USB routing (deliberate or accidental)." "0,1"
newline
bitfld.long 0x8C 22. "WHITE_LABEL_ADDR_VALID,valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15)" "0,1"
newline
bitfld.long 0x8C 15. "WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID,valid flag for the USB_WHITE_LABEL_ADDR field" "0,1"
newline
bitfld.long 0x8C 14. "WL_INFO_UF2_TXT_MODEL_STRDEF_VALID,valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14)" "0,1"
newline
bitfld.long 0x8C 13. "WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID,valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13)" "0,1"
newline
bitfld.long 0x8C 12. "WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID,valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12)" "0,1"
newline
bitfld.long 0x8C 11. "WL_SCSI_INQUIRY_VERSION_STRDEF_VALID,valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11)" "0,1"
newline
bitfld.long 0x8C 10. "WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID,valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10)" "0,1"
newline
bitfld.long 0x8C 9. "WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID,valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9)" "0,1"
newline
bitfld.long 0x8C 8. "WL_VOLUME_LABEL_STRDEF_VALID,valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8)" "0,1"
newline
bitfld.long 0x8C 7. "WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID,valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7)" "0,1"
newline
bitfld.long 0x8C 6. "WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID,valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6)" "0,1"
newline
bitfld.long 0x8C 5. "WL_USB_DEVICE_PRODUCT_STRDEF_VALID,valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5)" "0,1"
newline
bitfld.long 0x8C 4. "WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID,valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4)" "0,1"
newline
bitfld.long 0x8C 3. "WL_USB_DEVICE_LANG_ID_VALUE_VALID,valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3)" "0,1"
newline
bitfld.long 0x8C 2. "WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID,valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2)" "0,1"
newline
bitfld.long 0x8C 1. "WL_USB_DEVICE_PID_VALUE_VALID,valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1)" "0,1"
newline
bitfld.long 0x8C 0. "WL_USB_DEVICE_VID_VALUE_VALID,valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0)" "0,1"
line.long 0x90 "USB_BOOT_FLAGS_R1,Redundant copy of USB_BOOT_FLAGS"
hexmask.long.tbyte 0x90 0.--23. 1. "USB_BOOT_FLAGS_R1"
line.long 0x94 "USB_BOOT_FLAGS_R2,Redundant copy of USB_BOOT_FLAGS"
hexmask.long.tbyte 0x94 0.--23. 1. "USB_BOOT_FLAGS_R2"
line.long 0x98 "USB_WHITE_LABEL_ADDR,Row index of the USB_WHITE_LABEL structure within OTP (ECC)"
hexmask.long.word 0x98 0.--15. 1. "USB_WHITE_LABEL_ADDR"
rgroup.long 0x178++0xF
line.long 0x0 "OTPBOOT_SRC,OTP start row for the OTP boot image. (ECC)"
hexmask.long.word 0x0 0.--15. 1. "OTPBOOT_SRC"
line.long 0x4 "OTPBOOT_LEN,Length in rows of the OTP boot image. (ECC)"
hexmask.long.word 0x4 0.--15. 1. "OTPBOOT_LEN"
line.long 0x8 "OTPBOOT_DST0,Bits 15:0 of the OTP boot image load destination (and entry point). (ECC)"
hexmask.long.word 0x8 0.--15. 1. "OTPBOOT_DST0"
line.long 0xC "OTPBOOT_DST1,Bits 31:16 of the OTP boot image load destination (and entry point). (ECC)"
hexmask.long.word 0xC 0.--15. 1. "OTPBOOT_DST1"
rgroup.long 0x200++0xFF
line.long 0x0 "BOOTKEY0_0,Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x0 0.--15. 1. "BOOTKEY0_0"
line.long 0x4 "BOOTKEY0_1,Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x4 0.--15. 1. "BOOTKEY0_1"
line.long 0x8 "BOOTKEY0_2,Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x8 0.--15. 1. "BOOTKEY0_2"
line.long 0xC "BOOTKEY0_3,Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0xC 0.--15. 1. "BOOTKEY0_3"
line.long 0x10 "BOOTKEY0_4,Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x10 0.--15. 1. "BOOTKEY0_4"
line.long 0x14 "BOOTKEY0_5,Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x14 0.--15. 1. "BOOTKEY0_5"
line.long 0x18 "BOOTKEY0_6,Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x18 0.--15. 1. "BOOTKEY0_6"
line.long 0x1C "BOOTKEY0_7,Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x1C 0.--15. 1. "BOOTKEY0_7"
line.long 0x20 "BOOTKEY0_8,Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x20 0.--15. 1. "BOOTKEY0_8"
line.long 0x24 "BOOTKEY0_9,Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x24 0.--15. 1. "BOOTKEY0_9"
line.long 0x28 "BOOTKEY0_10,Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x28 0.--15. 1. "BOOTKEY0_10"
line.long 0x2C "BOOTKEY0_11,Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x2C 0.--15. 1. "BOOTKEY0_11"
line.long 0x30 "BOOTKEY0_12,Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x30 0.--15. 1. "BOOTKEY0_12"
line.long 0x34 "BOOTKEY0_13,Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x34 0.--15. 1. "BOOTKEY0_13"
line.long 0x38 "BOOTKEY0_14,Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x38 0.--15. 1. "BOOTKEY0_14"
line.long 0x3C "BOOTKEY0_15,Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"
hexmask.long.word 0x3C 0.--15. 1. "BOOTKEY0_15"
line.long 0x40 "BOOTKEY1_0,Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x40 0.--15. 1. "BOOTKEY1_0"
line.long 0x44 "BOOTKEY1_1,Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x44 0.--15. 1. "BOOTKEY1_1"
line.long 0x48 "BOOTKEY1_2,Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x48 0.--15. 1. "BOOTKEY1_2"
line.long 0x4C "BOOTKEY1_3,Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x4C 0.--15. 1. "BOOTKEY1_3"
line.long 0x50 "BOOTKEY1_4,Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x50 0.--15. 1. "BOOTKEY1_4"
line.long 0x54 "BOOTKEY1_5,Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x54 0.--15. 1. "BOOTKEY1_5"
line.long 0x58 "BOOTKEY1_6,Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x58 0.--15. 1. "BOOTKEY1_6"
line.long 0x5C "BOOTKEY1_7,Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x5C 0.--15. 1. "BOOTKEY1_7"
line.long 0x60 "BOOTKEY1_8,Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x60 0.--15. 1. "BOOTKEY1_8"
line.long 0x64 "BOOTKEY1_9,Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x64 0.--15. 1. "BOOTKEY1_9"
line.long 0x68 "BOOTKEY1_10,Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x68 0.--15. 1. "BOOTKEY1_10"
line.long 0x6C "BOOTKEY1_11,Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x6C 0.--15. 1. "BOOTKEY1_11"
line.long 0x70 "BOOTKEY1_12,Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x70 0.--15. 1. "BOOTKEY1_12"
line.long 0x74 "BOOTKEY1_13,Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x74 0.--15. 1. "BOOTKEY1_13"
line.long 0x78 "BOOTKEY1_14,Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x78 0.--15. 1. "BOOTKEY1_14"
line.long 0x7C "BOOTKEY1_15,Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"
hexmask.long.word 0x7C 0.--15. 1. "BOOTKEY1_15"
line.long 0x80 "BOOTKEY2_0,Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0x80 0.--15. 1. "BOOTKEY2_0"
line.long 0x84 "BOOTKEY2_1,Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0x84 0.--15. 1. "BOOTKEY2_1"
line.long 0x88 "BOOTKEY2_2,Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0x88 0.--15. 1. "BOOTKEY2_2"
line.long 0x8C "BOOTKEY2_3,Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0x8C 0.--15. 1. "BOOTKEY2_3"
line.long 0x90 "BOOTKEY2_4,Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0x90 0.--15. 1. "BOOTKEY2_4"
line.long 0x94 "BOOTKEY2_5,Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0x94 0.--15. 1. "BOOTKEY2_5"
line.long 0x98 "BOOTKEY2_6,Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0x98 0.--15. 1. "BOOTKEY2_6"
line.long 0x9C "BOOTKEY2_7,Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0x9C 0.--15. 1. "BOOTKEY2_7"
line.long 0xA0 "BOOTKEY2_8,Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0xA0 0.--15. 1. "BOOTKEY2_8"
line.long 0xA4 "BOOTKEY2_9,Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0xA4 0.--15. 1. "BOOTKEY2_9"
line.long 0xA8 "BOOTKEY2_10,Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0xA8 0.--15. 1. "BOOTKEY2_10"
line.long 0xAC "BOOTKEY2_11,Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0xAC 0.--15. 1. "BOOTKEY2_11"
line.long 0xB0 "BOOTKEY2_12,Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0xB0 0.--15. 1. "BOOTKEY2_12"
line.long 0xB4 "BOOTKEY2_13,Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0xB4 0.--15. 1. "BOOTKEY2_13"
line.long 0xB8 "BOOTKEY2_14,Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0xB8 0.--15. 1. "BOOTKEY2_14"
line.long 0xBC "BOOTKEY2_15,Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"
hexmask.long.word 0xBC 0.--15. 1. "BOOTKEY2_15"
line.long 0xC0 "BOOTKEY3_0,Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xC0 0.--15. 1. "BOOTKEY3_0"
line.long 0xC4 "BOOTKEY3_1,Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xC4 0.--15. 1. "BOOTKEY3_1"
line.long 0xC8 "BOOTKEY3_2,Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xC8 0.--15. 1. "BOOTKEY3_2"
line.long 0xCC "BOOTKEY3_3,Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xCC 0.--15. 1. "BOOTKEY3_3"
line.long 0xD0 "BOOTKEY3_4,Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xD0 0.--15. 1. "BOOTKEY3_4"
line.long 0xD4 "BOOTKEY3_5,Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xD4 0.--15. 1. "BOOTKEY3_5"
line.long 0xD8 "BOOTKEY3_6,Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xD8 0.--15. 1. "BOOTKEY3_6"
line.long 0xDC "BOOTKEY3_7,Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xDC 0.--15. 1. "BOOTKEY3_7"
line.long 0xE0 "BOOTKEY3_8,Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xE0 0.--15. 1. "BOOTKEY3_8"
line.long 0xE4 "BOOTKEY3_9,Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xE4 0.--15. 1. "BOOTKEY3_9"
line.long 0xE8 "BOOTKEY3_10,Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xE8 0.--15. 1. "BOOTKEY3_10"
line.long 0xEC "BOOTKEY3_11,Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xEC 0.--15. 1. "BOOTKEY3_11"
line.long 0xF0 "BOOTKEY3_12,Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xF0 0.--15. 1. "BOOTKEY3_12"
line.long 0xF4 "BOOTKEY3_13,Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xF4 0.--15. 1. "BOOTKEY3_13"
line.long 0xF8 "BOOTKEY3_14,Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xF8 0.--15. 1. "BOOTKEY3_14"
line.long 0xFC "BOOTKEY3_15,Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"
hexmask.long.word 0xFC 0.--15. 1. "BOOTKEY3_15"
rgroup.long 0x3D20++0xBF
line.long 0x0 "KEY1_0,Bits 15:0 of OTP access key 1 (ECC)"
hexmask.long.word 0x0 0.--15. 1. "KEY1_0"
line.long 0x4 "KEY1_1,Bits 31:16 of OTP access key 1 (ECC)"
hexmask.long.word 0x4 0.--15. 1. "KEY1_1"
line.long 0x8 "KEY1_2,Bits 47:32 of OTP access key 1 (ECC)"
hexmask.long.word 0x8 0.--15. 1. "KEY1_2"
line.long 0xC "KEY1_3,Bits 63:48 of OTP access key 1 (ECC)"
hexmask.long.word 0xC 0.--15. 1. "KEY1_3"
line.long 0x10 "KEY1_4,Bits 79:64 of OTP access key 1 (ECC)"
hexmask.long.word 0x10 0.--15. 1. "KEY1_4"
line.long 0x14 "KEY1_5,Bits 95:80 of OTP access key 1 (ECC)"
hexmask.long.word 0x14 0.--15. 1. "KEY1_5"
line.long 0x18 "KEY1_6,Bits 111:96 of OTP access key 1 (ECC)"
hexmask.long.word 0x18 0.--15. 1. "KEY1_6"
line.long 0x1C "KEY1_7,Bits 127:112 of OTP access key 1 (ECC)"
hexmask.long.word 0x1C 0.--15. 1. "KEY1_7"
line.long 0x20 "KEY2_0,Bits 15:0 of OTP access key 2 (ECC)"
hexmask.long.word 0x20 0.--15. 1. "KEY2_0"
line.long 0x24 "KEY2_1,Bits 31:16 of OTP access key 2 (ECC)"
hexmask.long.word 0x24 0.--15. 1. "KEY2_1"
line.long 0x28 "KEY2_2,Bits 47:32 of OTP access key 2 (ECC)"
hexmask.long.word 0x28 0.--15. 1. "KEY2_2"
line.long 0x2C "KEY2_3,Bits 63:48 of OTP access key 2 (ECC)"
hexmask.long.word 0x2C 0.--15. 1. "KEY2_3"
line.long 0x30 "KEY2_4,Bits 79:64 of OTP access key 2 (ECC)"
hexmask.long.word 0x30 0.--15. 1. "KEY2_4"
line.long 0x34 "KEY2_5,Bits 95:80 of OTP access key 2 (ECC)"
hexmask.long.word 0x34 0.--15. 1. "KEY2_5"
line.long 0x38 "KEY2_6,Bits 111:96 of OTP access key 2 (ECC)"
hexmask.long.word 0x38 0.--15. 1. "KEY2_6"
line.long 0x3C "KEY2_7,Bits 127:112 of OTP access key 2 (ECC)"
hexmask.long.word 0x3C 0.--15. 1. "KEY2_7"
line.long 0x40 "KEY3_0,Bits 15:0 of OTP access key 3 (ECC)"
hexmask.long.word 0x40 0.--15. 1. "KEY3_0"
line.long 0x44 "KEY3_1,Bits 31:16 of OTP access key 3 (ECC)"
hexmask.long.word 0x44 0.--15. 1. "KEY3_1"
line.long 0x48 "KEY3_2,Bits 47:32 of OTP access key 3 (ECC)"
hexmask.long.word 0x48 0.--15. 1. "KEY3_2"
line.long 0x4C "KEY3_3,Bits 63:48 of OTP access key 3 (ECC)"
hexmask.long.word 0x4C 0.--15. 1. "KEY3_3"
line.long 0x50 "KEY3_4,Bits 79:64 of OTP access key 3 (ECC)"
hexmask.long.word 0x50 0.--15. 1. "KEY3_4"
line.long 0x54 "KEY3_5,Bits 95:80 of OTP access key 3 (ECC)"
hexmask.long.word 0x54 0.--15. 1. "KEY3_5"
line.long 0x58 "KEY3_6,Bits 111:96 of OTP access key 3 (ECC)"
hexmask.long.word 0x58 0.--15. 1. "KEY3_6"
line.long 0x5C "KEY3_7,Bits 127:112 of OTP access key 3 (ECC)"
hexmask.long.word 0x5C 0.--15. 1. "KEY3_7"
line.long 0x60 "KEY4_0,Bits 15:0 of OTP access key 4 (ECC)"
hexmask.long.word 0x60 0.--15. 1. "KEY4_0"
line.long 0x64 "KEY4_1,Bits 31:16 of OTP access key 4 (ECC)"
hexmask.long.word 0x64 0.--15. 1. "KEY4_1"
line.long 0x68 "KEY4_2,Bits 47:32 of OTP access key 4 (ECC)"
hexmask.long.word 0x68 0.--15. 1. "KEY4_2"
line.long 0x6C "KEY4_3,Bits 63:48 of OTP access key 4 (ECC)"
hexmask.long.word 0x6C 0.--15. 1. "KEY4_3"
line.long 0x70 "KEY4_4,Bits 79:64 of OTP access key 4 (ECC)"
hexmask.long.word 0x70 0.--15. 1. "KEY4_4"
line.long 0x74 "KEY4_5,Bits 95:80 of OTP access key 4 (ECC)"
hexmask.long.word 0x74 0.--15. 1. "KEY4_5"
line.long 0x78 "KEY4_6,Bits 111:96 of OTP access key 4 (ECC)"
hexmask.long.word 0x78 0.--15. 1. "KEY4_6"
line.long 0x7C "KEY4_7,Bits 127:112 of OTP access key 4 (ECC)"
hexmask.long.word 0x7C 0.--15. 1. "KEY4_7"
line.long 0x80 "KEY5_0,Bits 15:0 of OTP access key 5 (ECC)"
hexmask.long.word 0x80 0.--15. 1. "KEY5_0"
line.long 0x84 "KEY5_1,Bits 31:16 of OTP access key 5 (ECC)"
hexmask.long.word 0x84 0.--15. 1. "KEY5_1"
line.long 0x88 "KEY5_2,Bits 47:32 of OTP access key 5 (ECC)"
hexmask.long.word 0x88 0.--15. 1. "KEY5_2"
line.long 0x8C "KEY5_3,Bits 63:48 of OTP access key 5 (ECC)"
hexmask.long.word 0x8C 0.--15. 1. "KEY5_3"
line.long 0x90 "KEY5_4,Bits 79:64 of OTP access key 5 (ECC)"
hexmask.long.word 0x90 0.--15. 1. "KEY5_4"
line.long 0x94 "KEY5_5,Bits 95:80 of OTP access key 5 (ECC)"
hexmask.long.word 0x94 0.--15. 1. "KEY5_5"
line.long 0x98 "KEY5_6,Bits 111:96 of OTP access key 5 (ECC)"
hexmask.long.word 0x98 0.--15. 1. "KEY5_6"
line.long 0x9C "KEY5_7,Bits 127:112 of OTP access key 5 (ECC)"
hexmask.long.word 0x9C 0.--15. 1. "KEY5_7"
line.long 0xA0 "KEY6_0,Bits 15:0 of OTP access key 6 (ECC)"
hexmask.long.word 0xA0 0.--15. 1. "KEY6_0"
line.long 0xA4 "KEY6_1,Bits 31:16 of OTP access key 6 (ECC)"
hexmask.long.word 0xA4 0.--15. 1. "KEY6_1"
line.long 0xA8 "KEY6_2,Bits 47:32 of OTP access key 6 (ECC)"
hexmask.long.word 0xA8 0.--15. 1. "KEY6_2"
line.long 0xAC "KEY6_3,Bits 63:48 of OTP access key 6 (ECC)"
hexmask.long.word 0xAC 0.--15. 1. "KEY6_3"
line.long 0xB0 "KEY6_4,Bits 79:64 of OTP access key 6 (ECC)"
hexmask.long.word 0xB0 0.--15. 1. "KEY6_4"
line.long 0xB4 "KEY6_5,Bits 95:80 of OTP access key 6 (ECC)"
hexmask.long.word 0xB4 0.--15. 1. "KEY6_5"
line.long 0xB8 "KEY6_6,Bits 111:96 of OTP access key 6 (ECC)"
hexmask.long.word 0xB8 0.--15. 1. "KEY6_6"
line.long 0xBC "KEY6_7,Bits 127:112 of OTP access key 6 (ECC)"
hexmask.long.word 0xBC 0.--15. 1. "KEY6_7"
rgroup.long 0x3DE4++0x17
line.long 0x0 "KEY1_VALID,Valid flag for key 1. Once the valid flag is set. the key can no longer be read or written. and becomes a valid fixed key for protecting OTP pages."
bitfld.long 0x0 16. "VALID_R2,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0x0 8. "VALID_R1,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0x0 0. "VALID" "0,1"
line.long 0x4 "KEY2_VALID,Valid flag for key 2. Once the valid flag is set. the key can no longer be read or written. and becomes a valid fixed key for protecting OTP pages."
bitfld.long 0x4 16. "VALID_R2,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0x4 8. "VALID_R1,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0x4 0. "VALID" "0,1"
line.long 0x8 "KEY3_VALID,Valid flag for key 3. Once the valid flag is set. the key can no longer be read or written. and becomes a valid fixed key for protecting OTP pages."
bitfld.long 0x8 16. "VALID_R2,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0x8 8. "VALID_R1,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0x8 0. "VALID" "0,1"
line.long 0xC "KEY4_VALID,Valid flag for key 4. Once the valid flag is set. the key can no longer be read or written. and becomes a valid fixed key for protecting OTP pages."
bitfld.long 0xC 16. "VALID_R2,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0xC 8. "VALID_R1,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0xC 0. "VALID" "0,1"
line.long 0x10 "KEY5_VALID,Valid flag for key 5. Once the valid flag is set. the key can no longer be read or written. and becomes a valid fixed key for protecting OTP pages."
bitfld.long 0x10 16. "VALID_R2,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0x10 8. "VALID_R1,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0x10 0. "VALID" "0,1"
line.long 0x14 "KEY6_VALID,Valid flag for key 6. Once the valid flag is set. the key can no longer be read or written. and becomes a valid fixed key for protecting OTP pages."
bitfld.long 0x14 16. "VALID_R2,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0x14 8. "VALID_R1,Redundant copy of VALID with 3-way majority vote" "0,1"
newline
bitfld.long 0x14 0. "VALID" "0,1"
rgroup.long 0x3E00++0x1FF
line.long 0x0 "PAGE0_LOCK0,Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x4 "PAGE0_LOCK1,Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x8 "PAGE1_LOCK0,Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xC "PAGE1_LOCK1,Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x10 "PAGE2_LOCK0,Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x10 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x10 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x10 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x10 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x14 "PAGE2_LOCK1,Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x14 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x14 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x14 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x14 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x14 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x18 "PAGE3_LOCK0,Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x18 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x18 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x18 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x18 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1C "PAGE3_LOCK1,Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x1C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x1C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x20 "PAGE4_LOCK0,Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x20 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x20 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x20 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x20 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x24 "PAGE4_LOCK1,Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x24 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x24 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x24 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x24 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x24 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x28 "PAGE5_LOCK0,Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x28 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x28 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x28 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x28 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x2C "PAGE5_LOCK1,Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x2C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x2C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x2C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x2C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x2C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x30 "PAGE6_LOCK0,Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x30 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x30 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x30 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x30 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x34 "PAGE6_LOCK1,Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x34 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x34 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x34 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x34 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x34 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x38 "PAGE7_LOCK0,Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x38 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x38 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x38 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x38 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x3C "PAGE7_LOCK1,Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x3C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x3C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x3C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x3C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x3C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x40 "PAGE8_LOCK0,Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x40 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x40 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x40 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x40 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x44 "PAGE8_LOCK1,Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x44 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x44 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x44 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x44 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x44 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x48 "PAGE9_LOCK0,Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x48 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x48 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x48 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x48 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x4C "PAGE9_LOCK1,Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x4C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x4C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x4C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x4C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x4C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x50 "PAGE10_LOCK0,Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x50 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x50 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x50 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x50 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x54 "PAGE10_LOCK1,Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x54 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x54 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x54 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x54 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x54 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x58 "PAGE11_LOCK0,Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x58 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x58 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x58 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x58 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x58 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x5C "PAGE11_LOCK1,Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x5C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x5C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x5C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x5C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x5C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x60 "PAGE12_LOCK0,Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x60 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x60 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x60 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x60 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x60 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x64 "PAGE12_LOCK1,Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x64 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x64 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x64 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x64 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x64 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x68 "PAGE13_LOCK0,Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x68 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x68 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x68 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x68 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x68 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x6C "PAGE13_LOCK1,Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x6C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x6C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x6C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x6C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x6C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x70 "PAGE14_LOCK0,Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x70 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x70 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x70 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x70 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x70 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x74 "PAGE14_LOCK1,Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x74 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x74 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x74 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x74 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x74 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x78 "PAGE15_LOCK0,Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x78 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x78 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x78 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x78 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x78 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x7C "PAGE15_LOCK1,Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x7C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x7C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x7C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x7C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x7C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x80 "PAGE16_LOCK0,Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x80 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x80 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x80 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x80 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x80 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x84 "PAGE16_LOCK1,Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x84 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x84 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x84 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x84 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x84 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x88 "PAGE17_LOCK0,Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x88 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x88 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x88 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x88 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x88 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x8C "PAGE17_LOCK1,Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x8C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x8C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x8C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x8C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x8C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x90 "PAGE18_LOCK0,Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x90 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x90 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x90 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x90 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x90 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x94 "PAGE18_LOCK1,Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x94 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x94 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x94 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x94 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x94 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x98 "PAGE19_LOCK0,Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x98 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x98 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x98 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x98 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x98 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x9C "PAGE19_LOCK1,Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x9C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x9C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x9C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x9C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x9C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xA0 "PAGE20_LOCK0,Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xA0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xA0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xA0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xA0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xA0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xA4 "PAGE20_LOCK1,Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xA4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xA4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xA4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xA4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xA4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xA8 "PAGE21_LOCK0,Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xA8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xA8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xA8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xA8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xA8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xAC "PAGE21_LOCK1,Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xAC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xAC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xAC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xAC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xAC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xB0 "PAGE22_LOCK0,Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xB0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xB0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xB0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xB0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xB0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xB4 "PAGE22_LOCK1,Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xB4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xB4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xB4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xB4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xB4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xB8 "PAGE23_LOCK0,Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xB8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xB8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xB8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xB8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xB8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xBC "PAGE23_LOCK1,Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xBC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xBC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xBC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xBC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xBC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xC0 "PAGE24_LOCK0,Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xC0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xC0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xC0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xC0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xC4 "PAGE24_LOCK1,Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xC4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xC4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xC4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xC4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xC4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xC8 "PAGE25_LOCK0,Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xC8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xC8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xC8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xC8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xCC "PAGE25_LOCK1,Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xCC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xCC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xCC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xCC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xCC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xD0 "PAGE26_LOCK0,Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xD0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xD0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xD0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xD0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xD4 "PAGE26_LOCK1,Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xD4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xD4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xD4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xD4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xD4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xD8 "PAGE27_LOCK0,Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xD8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xD8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xD8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xD8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xDC "PAGE27_LOCK1,Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xDC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xDC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xDC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xDC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xDC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xE0 "PAGE28_LOCK0,Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xE0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xE0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xE0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xE0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xE4 "PAGE28_LOCK1,Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xE4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xE4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xE4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xE4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xE4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xE8 "PAGE29_LOCK0,Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xE8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xE8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xE8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xE8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xEC "PAGE29_LOCK1,Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xEC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xEC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xEC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xEC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xEC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xF0 "PAGE30_LOCK0,Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xF0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xF0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xF0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xF0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xF4 "PAGE30_LOCK1,Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xF4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xF4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xF4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xF4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xF4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0xF8 "PAGE31_LOCK0,Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xF8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xF8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xF8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0xF8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0xFC "PAGE31_LOCK1,Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0xFC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0xFC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0xFC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0xFC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0xFC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x100 "PAGE32_LOCK0,Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x100 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x100 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x100 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x100 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x104 "PAGE32_LOCK1,Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x104 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x104 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x104 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x104 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x104 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x108 "PAGE33_LOCK0,Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x108 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x108 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x108 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x108 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x108 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x10C "PAGE33_LOCK1,Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x10C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x10C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x10C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x10C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x10C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x110 "PAGE34_LOCK0,Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x110 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x110 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x110 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x110 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x110 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x114 "PAGE34_LOCK1,Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x114 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x114 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x114 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x114 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x114 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x118 "PAGE35_LOCK0,Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x118 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x118 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x118 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x118 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x118 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x11C "PAGE35_LOCK1,Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x11C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x11C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x11C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x11C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x11C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x120 "PAGE36_LOCK0,Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x120 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x120 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x120 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x120 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x120 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x124 "PAGE36_LOCK1,Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x124 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x124 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x124 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x124 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x124 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x128 "PAGE37_LOCK0,Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x128 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x128 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x128 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x128 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x128 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x12C "PAGE37_LOCK1,Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x12C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x12C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x12C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x12C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x12C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x130 "PAGE38_LOCK0,Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x130 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x130 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x130 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x130 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x130 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x134 "PAGE38_LOCK1,Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x134 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x134 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x134 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x134 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x134 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x138 "PAGE39_LOCK0,Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x138 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x138 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x138 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x138 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x138 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x13C "PAGE39_LOCK1,Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x13C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x13C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x13C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x13C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x13C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x140 "PAGE40_LOCK0,Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x140 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x140 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x140 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x140 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x144 "PAGE40_LOCK1,Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x144 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x144 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x144 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x144 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x144 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x148 "PAGE41_LOCK0,Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x148 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x148 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x148 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x148 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x148 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x14C "PAGE41_LOCK1,Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x14C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x14C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x14C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x14C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x14C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x150 "PAGE42_LOCK0,Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x150 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x150 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x150 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x150 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x150 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x154 "PAGE42_LOCK1,Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x154 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x154 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x154 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x154 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x154 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x158 "PAGE43_LOCK0,Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x158 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x158 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x158 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x158 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x158 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x15C "PAGE43_LOCK1,Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x15C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x15C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x15C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x15C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x15C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x160 "PAGE44_LOCK0,Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x160 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x160 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x160 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x160 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x160 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x164 "PAGE44_LOCK1,Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x164 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x164 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x164 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x164 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x164 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x168 "PAGE45_LOCK0,Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x168 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x168 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x168 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x168 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x168 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x16C "PAGE45_LOCK1,Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x16C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x16C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x16C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x16C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x16C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x170 "PAGE46_LOCK0,Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x170 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x170 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x170 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x170 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x170 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x174 "PAGE46_LOCK1,Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x174 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x174 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x174 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x174 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x174 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x178 "PAGE47_LOCK0,Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x178 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x178 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x178 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x178 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x178 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x17C "PAGE47_LOCK1,Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x17C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x17C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x17C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x17C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x17C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x180 "PAGE48_LOCK0,Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x180 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x180 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x180 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x180 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x180 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x184 "PAGE48_LOCK1,Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x184 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x184 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x184 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x184 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x184 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x188 "PAGE49_LOCK0,Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x188 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x188 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x188 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x188 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x188 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x18C "PAGE49_LOCK1,Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x18C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x18C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x18C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x18C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x18C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x190 "PAGE50_LOCK0,Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x190 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x190 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x190 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x190 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x190 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x194 "PAGE50_LOCK1,Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x194 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x194 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x194 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x194 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x194 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x198 "PAGE51_LOCK0,Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x198 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x198 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x198 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x198 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x198 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x19C "PAGE51_LOCK1,Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x19C 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x19C 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x19C 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x19C 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x19C 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1A0 "PAGE52_LOCK0,Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1A0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1A0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1A0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x1A0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1A0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1A4 "PAGE52_LOCK1,Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1A4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1A4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1A4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x1A4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x1A4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1A8 "PAGE53_LOCK0,Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1A8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1A8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1A8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x1A8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1A8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1AC "PAGE53_LOCK1,Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1AC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1AC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1AC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x1AC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x1AC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1B0 "PAGE54_LOCK0,Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1B0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1B0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1B0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x1B0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1B0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1B4 "PAGE54_LOCK1,Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1B4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1B4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1B4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x1B4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x1B4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1B8 "PAGE55_LOCK0,Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1B8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1B8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1B8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x1B8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1B8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1BC "PAGE55_LOCK1,Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1BC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1BC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1BC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x1BC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x1BC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1C0 "PAGE56_LOCK0,Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1C0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1C0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1C0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x1C0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1C0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1C4 "PAGE56_LOCK1,Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1C4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1C4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1C4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x1C4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x1C4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1C8 "PAGE57_LOCK0,Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1C8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1C8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1C8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x1C8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1C8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1CC "PAGE57_LOCK1,Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1CC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1CC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1CC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x1CC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x1CC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1D0 "PAGE58_LOCK0,Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1D0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1D0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1D0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x1D0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1D0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1D4 "PAGE58_LOCK1,Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1D4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1D4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1D4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x1D4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x1D4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1D8 "PAGE59_LOCK0,Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1D8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1D8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1D8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x1D8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1D8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1DC "PAGE59_LOCK1,Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1DC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1DC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1DC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x1DC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x1DC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1E0 "PAGE60_LOCK0,Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1E0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1E0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1E0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x1E0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1E0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1E4 "PAGE60_LOCK1,Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1E4 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1E4 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1E4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x1E4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x1E4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1E8 "PAGE61_LOCK0,Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1E8 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1E8 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1E8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x1E8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1E8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1EC "PAGE61_LOCK1,Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1EC 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1EC 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1EC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
newline
bitfld.long 0x1EC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
newline
bitfld.long 0x1EC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1F0 "PAGE62_LOCK0,Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1F0 16.--23. 1. "R2,Redundant copy of bits 7:0"
newline
hexmask.long.byte 0x1F0 8.--15. 1. "R1,Redundant copy of bits 7:0"
newline
bitfld.long 0x1F0 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
newline
bitfld.long 0x1F0 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1F0 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1F4 "PAGE62_LOCK1,Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1F4 16.--23. 1. "R2,Redundant copy of bits 7:0"
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hexmask.long.byte 0x1F4 8.--15. 1. "R1,Redundant copy of bits 7:0"
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bitfld.long 0x1F4 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
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bitfld.long 0x1F4 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
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bitfld.long 0x1F4 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
line.long 0x1F8 "PAGE63_LOCK0,Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1F8 16.--23. 1. "R2,Redundant copy of bits 7:0"
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hexmask.long.byte 0x1F8 8.--15. 1. "R1,Redundant copy of bits 7:0"
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bitfld.long 0x1F8 7. "RMA,Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface and makes pages 3 through 61 of the OTP permanently inaccessible." "0,1"
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bitfld.long 0x1F8 6. "NO_KEY_STATE,State when at least one key is registered for this page and no matching key has been entered." "0,1"
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bitfld.long 0x1F8 3.--5. "KEY_R,Index 1-6 of a hardware key which must be entered to grant read access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F8 0.--2. "KEY_W,Index 1-6 of a hardware key which must be entered to grant write access or 0 if no such key is required." "0,1,2,3,4,5,6,7"
line.long 0x1FC "PAGE63_LOCK1,Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding. so that bits can be set independently."
hexmask.long.byte 0x1FC 16.--23. 1. "R2,Redundant copy of bits 7:0"
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hexmask.long.byte 0x1FC 8.--15. 1. "R1,Redundant copy of bits 7:0"
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bitfld.long 0x1FC 4.--5. "LOCK_BL,Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect and no corresponding SW_LOCKx registers." "0: Bootloader permits user reads and writes to this..,1: Bootloader permits user reads of this page,2: Do not use. Behaves the same as INACCESSIBLE,3: Bootloader does not permit user access to this.."
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bitfld.long 0x1FC 2.--3. "LOCK_NS,Lock state for Non-secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP.." "0: Page can be read by Non-secure software and..,1: Page can be read by Non-secure software,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Non-secure software."
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bitfld.long 0x1FC 0.--1. "LOCK_S,Lock state for Secure accesses to this page. Thermometer-coded so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset).." "0: Page is fully accessible by Secure software.,1: Page can be read by Secure software but can not..,2: Do not use. Behaves the same as INACCESSIBLE.,3: Page can not be accessed by Secure software."
tree.end
tree.end
tree "PIO (Programmable Input/Output Block)"
base ad:0x0
tree "PIO0"
base ad:0x50200000
group.long 0x0++0x3
line.long 0x0 "CTRL,PIO control register"
bitfld.long 0x0 26. "NEXTPREV_CLKDIV_RESTART,Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write." "0,1"
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bitfld.long 0x0 25. "NEXTPREV_SM_DISABLE,Write 1 to disable state machines in neighbouring PIO blocks as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write." "0,1"
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bitfld.long 0x0 24. "NEXTPREV_SM_ENABLE,Write 1 to enable state machines in neighbouring PIO blocks as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write." "0,1"
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hexmask.long.byte 0x0 20.--23. 1. "NEXT_PIO_MASK,A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART NEXTPREV_SM_ENABLE and.."
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hexmask.long.byte 0x0 16.--19. 1. "PREV_PIO_MASK,A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART OP_ENABLE OP_DISABLE in the.."
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hexmask.long.byte 0x0 8.--11. 1. "CLKDIV_RESTART,Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running so once started their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in.."
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hexmask.long.byte 0x0 4.--7. 1. "SM_RESTART,Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution."
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hexmask.long.byte 0x0 0.--3. 1. "SM_ENABLE,Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled a state machine will cease executing instructions except those written directly to SMx_INSTR by the system. Multiple bits can be.."
rgroup.long 0x4++0x3
line.long 0x0 "FSTAT,FIFO status register"
hexmask.long.byte 0x0 24.--27. 1. "TXEMPTY,State machine TX FIFO is empty"
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hexmask.long.byte 0x0 16.--19. 1. "TXFULL,State machine TX FIFO is full"
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hexmask.long.byte 0x0 8.--11. 1. "RXEMPTY,State machine RX FIFO is empty"
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hexmask.long.byte 0x0 0.--3. 1. "RXFULL,State machine RX FIFO is full"
group.long 0x8++0x3
line.long 0x0 "FDEBUG,FIFO debug register"
hexmask.long.byte 0x0 24.--27. 1. "TXSTALL,State machine has stalled on empty TX FIFO during a blocking PULL or an OUT with autopull enabled. Write 1 to clear."
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hexmask.long.byte 0x0 16.--19. 1. "TXOVER,TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way but the data that the system attempted to write is dropped so if this flag is.."
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hexmask.long.byte 0x0 8.--11. 1. "RXUNDER,RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way but the data returned by reading from an empty FIFO is undefined so this flag.."
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hexmask.long.byte 0x0 0.--3. 1. "RXSTALL,State machine has stalled on full RX FIFO during a blocking PUSH or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place in which case the state machine has dropped data. Write 1 to clear."
rgroup.long 0xC++0x3
line.long 0x0 "FLEVEL,FIFO levels"
hexmask.long.byte 0x0 28.--31. 1. "RX3"
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hexmask.long.byte 0x0 24.--27. 1. "TX3"
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hexmask.long.byte 0x0 20.--23. 1. "RX2"
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hexmask.long.byte 0x0 16.--19. 1. "TX2"
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hexmask.long.byte 0x0 12.--15. 1. "RX1"
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hexmask.long.byte 0x0 8.--11. 1. "TX1"
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hexmask.long.byte 0x0 4.--7. 1. "RX0"
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hexmask.long.byte 0x0 0.--3. 1. "TX0"
wgroup.long 0x10++0xF
line.long 0x0 "TXF0,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0x0 0.--31. 1. "TXF0"
line.long 0x4 "TXF1,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0x4 0.--31. 1. "TXF1"
line.long 0x8 "TXF2,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0x8 0.--31. 1. "TXF2"
line.long 0xC "TXF3,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0xC 0.--31. 1. "TXF3"
rgroup.long 0x20++0xF
line.long 0x0 "RXF0,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0x0 0.--31. 1. "RXF0"
line.long 0x4 "RXF1,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0x4 0.--31. 1. "RXF1"
line.long 0x8 "RXF2,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0x8 0.--31. 1. "RXF2"
line.long 0xC "RXF3,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0xC 0.--31. 1. "RXF3"
group.long 0x30++0x3
line.long 0x0 "IRQ,State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags. which can be set. cleared. and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use.."
hexmask.long.byte 0x0 0.--7. 1. "IRQ"
wgroup.long 0x34++0x3
line.long 0x0 "IRQ_FORCE,Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs. and is not.."
hexmask.long.byte 0x0 0.--7. 1. "IRQ_FORCE"
group.long 0x38++0x3
line.long 0x0 "INPUT_SYNC_BYPASS,There is a 2-flipflop synchronizer on each GPIO input. which protects PIO logic from metastabilities. This increases input delay. and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this.."
hexmask.long 0x0 0.--31. 1. "INPUT_SYNC_BYPASS"
rgroup.long 0x3C++0xB
line.long 0x0 "DBG_PADOUT,Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs. so the two most significant bits are hardwired to 0."
hexmask.long 0x0 0.--31. 1. "DBG_PADOUT"
line.long 0x4 "DBG_PADOE,Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs. so the two most significant bits are hardwired to 0."
hexmask.long 0x4 0.--31. 1. "DBG_PADOE"
line.long 0x8 "DBG_CFGINFO,The PIO hardware has some free parameters that may vary between chip products."
hexmask.long.byte 0x8 28.--31. 1. "VERSION,Version of the core PIO hardware."
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hexmask.long.byte 0x8 16.--21. 1. "IMEM_SIZE,The size of the instruction memory measured in units of one instruction"
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hexmask.long.byte 0x8 8.--11. 1. "SM_COUNT,The number of state machines this PIO instance is equipped with."
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hexmask.long.byte 0x8 0.--5. 1. "FIFO_DEPTH,The depth of the state machine TX/RX FIFOs measured in words."
wgroup.long 0x48++0x7F
line.long 0x0 "INSTR_MEM0,Write-only access to instruction memory location 0"
hexmask.long.word 0x0 0.--15. 1. "INSTR_MEM0"
line.long 0x4 "INSTR_MEM1,Write-only access to instruction memory location 1"
hexmask.long.word 0x4 0.--15. 1. "INSTR_MEM1"
line.long 0x8 "INSTR_MEM2,Write-only access to instruction memory location 2"
hexmask.long.word 0x8 0.--15. 1. "INSTR_MEM2"
line.long 0xC "INSTR_MEM3,Write-only access to instruction memory location 3"
hexmask.long.word 0xC 0.--15. 1. "INSTR_MEM3"
line.long 0x10 "INSTR_MEM4,Write-only access to instruction memory location 4"
hexmask.long.word 0x10 0.--15. 1. "INSTR_MEM4"
line.long 0x14 "INSTR_MEM5,Write-only access to instruction memory location 5"
hexmask.long.word 0x14 0.--15. 1. "INSTR_MEM5"
line.long 0x18 "INSTR_MEM6,Write-only access to instruction memory location 6"
hexmask.long.word 0x18 0.--15. 1. "INSTR_MEM6"
line.long 0x1C "INSTR_MEM7,Write-only access to instruction memory location 7"
hexmask.long.word 0x1C 0.--15. 1. "INSTR_MEM7"
line.long 0x20 "INSTR_MEM8,Write-only access to instruction memory location 8"
hexmask.long.word 0x20 0.--15. 1. "INSTR_MEM8"
line.long 0x24 "INSTR_MEM9,Write-only access to instruction memory location 9"
hexmask.long.word 0x24 0.--15. 1. "INSTR_MEM9"
line.long 0x28 "INSTR_MEM10,Write-only access to instruction memory location 10"
hexmask.long.word 0x28 0.--15. 1. "INSTR_MEM10"
line.long 0x2C "INSTR_MEM11,Write-only access to instruction memory location 11"
hexmask.long.word 0x2C 0.--15. 1. "INSTR_MEM11"
line.long 0x30 "INSTR_MEM12,Write-only access to instruction memory location 12"
hexmask.long.word 0x30 0.--15. 1. "INSTR_MEM12"
line.long 0x34 "INSTR_MEM13,Write-only access to instruction memory location 13"
hexmask.long.word 0x34 0.--15. 1. "INSTR_MEM13"
line.long 0x38 "INSTR_MEM14,Write-only access to instruction memory location 14"
hexmask.long.word 0x38 0.--15. 1. "INSTR_MEM14"
line.long 0x3C "INSTR_MEM15,Write-only access to instruction memory location 15"
hexmask.long.word 0x3C 0.--15. 1. "INSTR_MEM15"
line.long 0x40 "INSTR_MEM16,Write-only access to instruction memory location 16"
hexmask.long.word 0x40 0.--15. 1. "INSTR_MEM16"
line.long 0x44 "INSTR_MEM17,Write-only access to instruction memory location 17"
hexmask.long.word 0x44 0.--15. 1. "INSTR_MEM17"
line.long 0x48 "INSTR_MEM18,Write-only access to instruction memory location 18"
hexmask.long.word 0x48 0.--15. 1. "INSTR_MEM18"
line.long 0x4C "INSTR_MEM19,Write-only access to instruction memory location 19"
hexmask.long.word 0x4C 0.--15. 1. "INSTR_MEM19"
line.long 0x50 "INSTR_MEM20,Write-only access to instruction memory location 20"
hexmask.long.word 0x50 0.--15. 1. "INSTR_MEM20"
line.long 0x54 "INSTR_MEM21,Write-only access to instruction memory location 21"
hexmask.long.word 0x54 0.--15. 1. "INSTR_MEM21"
line.long 0x58 "INSTR_MEM22,Write-only access to instruction memory location 22"
hexmask.long.word 0x58 0.--15. 1. "INSTR_MEM22"
line.long 0x5C "INSTR_MEM23,Write-only access to instruction memory location 23"
hexmask.long.word 0x5C 0.--15. 1. "INSTR_MEM23"
line.long 0x60 "INSTR_MEM24,Write-only access to instruction memory location 24"
hexmask.long.word 0x60 0.--15. 1. "INSTR_MEM24"
line.long 0x64 "INSTR_MEM25,Write-only access to instruction memory location 25"
hexmask.long.word 0x64 0.--15. 1. "INSTR_MEM25"
line.long 0x68 "INSTR_MEM26,Write-only access to instruction memory location 26"
hexmask.long.word 0x68 0.--15. 1. "INSTR_MEM26"
line.long 0x6C "INSTR_MEM27,Write-only access to instruction memory location 27"
hexmask.long.word 0x6C 0.--15. 1. "INSTR_MEM27"
line.long 0x70 "INSTR_MEM28,Write-only access to instruction memory location 28"
hexmask.long.word 0x70 0.--15. 1. "INSTR_MEM28"
line.long 0x74 "INSTR_MEM29,Write-only access to instruction memory location 29"
hexmask.long.word 0x74 0.--15. 1. "INSTR_MEM29"
line.long 0x78 "INSTR_MEM30,Write-only access to instruction memory location 30"
hexmask.long.word 0x78 0.--15. 1. "INSTR_MEM30"
line.long 0x7C "INSTR_MEM31,Write-only access to instruction memory location 31"
hexmask.long.word 0x7C 0.--15. 1. "INSTR_MEM31"
group.long 0xC8++0xB
line.long 0x0 "SM0_CLKDIV,Clock divisor register for state machine 0"
hexmask.long.word 0x0 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
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hexmask.long.byte 0x0 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0x4 "SM0_EXECCTRL,Execution/behavioural settings for state machine 0"
rbitfld.long 0x4 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
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bitfld.long 0x4 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
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bitfld.long 0x4 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
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hexmask.long.byte 0x4 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
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hexmask.long.byte 0x4 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
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bitfld.long 0x4 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
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bitfld.long 0x4 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
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hexmask.long.byte 0x4 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
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hexmask.long.byte 0x4 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
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bitfld.long 0x4 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
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hexmask.long.byte 0x4 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x8 "SM0_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 0"
bitfld.long 0x8 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
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bitfld.long 0x8 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
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hexmask.long.byte 0x8 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
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hexmask.long.byte 0x8 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
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bitfld.long 0x8 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
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bitfld.long 0x8 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
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bitfld.long 0x8 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
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bitfld.long 0x8 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
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bitfld.long 0x8 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
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bitfld.long 0x8 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
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hexmask.long.byte 0x8 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0xD4++0x3
line.long 0x0 "SM0_ADDR,Current instruction address of state machine 0"
hexmask.long.byte 0x0 0.--4. 1. "SM0_ADDR"
group.long 0xD8++0x13
line.long 0x0 "SM0_INSTR,Read to see the instruction currently addressed by state machine 0's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM0_INSTR"
line.long 0x4 "SM0_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "SM1_CLKDIV,Clock divisor register for state machine 1"
hexmask.long.word 0x8 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
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hexmask.long.byte 0x8 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0xC "SM1_EXECCTRL,Execution/behavioural settings for state machine 1"
rbitfld.long 0xC 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
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bitfld.long 0xC 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
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bitfld.long 0xC 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
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hexmask.long.byte 0xC 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
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hexmask.long.byte 0xC 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
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bitfld.long 0xC 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
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bitfld.long 0xC 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
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hexmask.long.byte 0xC 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
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hexmask.long.byte 0xC 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
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bitfld.long 0xC 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
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hexmask.long.byte 0xC 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x10 "SM1_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 1"
bitfld.long 0x10 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
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bitfld.long 0x10 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
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hexmask.long.byte 0x10 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
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hexmask.long.byte 0x10 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
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bitfld.long 0x10 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
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bitfld.long 0x10 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
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bitfld.long 0x10 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
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bitfld.long 0x10 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
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bitfld.long 0x10 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
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bitfld.long 0x10 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0xEC++0x3
line.long 0x0 "SM1_ADDR,Current instruction address of state machine 1"
hexmask.long.byte 0x0 0.--4. 1. "SM1_ADDR"
group.long 0xF0++0x13
line.long 0x0 "SM1_INSTR,Read to see the instruction currently addressed by state machine 1's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM1_INSTR"
line.long 0x4 "SM1_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "SM2_CLKDIV,Clock divisor register for state machine 2"
hexmask.long.word 0x8 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
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hexmask.long.byte 0x8 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0xC "SM2_EXECCTRL,Execution/behavioural settings for state machine 2"
rbitfld.long 0xC 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
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bitfld.long 0xC 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
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bitfld.long 0xC 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
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hexmask.long.byte 0xC 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
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hexmask.long.byte 0xC 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
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bitfld.long 0xC 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
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bitfld.long 0xC 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
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hexmask.long.byte 0xC 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
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hexmask.long.byte 0xC 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
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bitfld.long 0xC 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
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hexmask.long.byte 0xC 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x10 "SM2_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 2"
bitfld.long 0x10 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
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bitfld.long 0x10 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
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hexmask.long.byte 0x10 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
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hexmask.long.byte 0x10 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
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bitfld.long 0x10 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
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bitfld.long 0x10 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
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bitfld.long 0x10 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
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bitfld.long 0x10 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
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bitfld.long 0x10 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
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bitfld.long 0x10 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0x104++0x3
line.long 0x0 "SM2_ADDR,Current instruction address of state machine 2"
hexmask.long.byte 0x0 0.--4. 1. "SM2_ADDR"
group.long 0x108++0x13
line.long 0x0 "SM2_INSTR,Read to see the instruction currently addressed by state machine 2's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM2_INSTR"
line.long 0x4 "SM2_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "SM3_CLKDIV,Clock divisor register for state machine 3"
hexmask.long.word 0x8 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
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hexmask.long.byte 0x8 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0xC "SM3_EXECCTRL,Execution/behavioural settings for state machine 3"
rbitfld.long 0xC 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
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bitfld.long 0xC 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
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bitfld.long 0xC 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
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hexmask.long.byte 0xC 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
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hexmask.long.byte 0xC 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
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bitfld.long 0xC 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
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bitfld.long 0xC 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
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hexmask.long.byte 0xC 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
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hexmask.long.byte 0xC 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
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bitfld.long 0xC 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
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hexmask.long.byte 0xC 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x10 "SM3_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 3"
bitfld.long 0x10 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
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bitfld.long 0x10 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
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hexmask.long.byte 0x10 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
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hexmask.long.byte 0x10 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
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bitfld.long 0x10 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
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bitfld.long 0x10 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
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bitfld.long 0x10 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
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bitfld.long 0x10 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
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bitfld.long 0x10 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
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bitfld.long 0x10 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0x11C++0x3
line.long 0x0 "SM3_ADDR,Current instruction address of state machine 3"
hexmask.long.byte 0x0 0.--4. 1. "SM3_ADDR"
group.long 0x120++0x4B
line.long 0x0 "SM3_INSTR,Read to see the instruction currently addressed by state machine 3's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM3_INSTR"
line.long 0x4 "SM3_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "RXF0_PUTGET0,Direct read/write access to entry 0 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x8 0.--31. 1. "RXF0_PUTGET0"
line.long 0xC "RXF0_PUTGET1,Direct read/write access to entry 1 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0xC 0.--31. 1. "RXF0_PUTGET1"
line.long 0x10 "RXF0_PUTGET2,Direct read/write access to entry 2 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x10 0.--31. 1. "RXF0_PUTGET2"
line.long 0x14 "RXF0_PUTGET3,Direct read/write access to entry 3 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x14 0.--31. 1. "RXF0_PUTGET3"
line.long 0x18 "RXF1_PUTGET0,Direct read/write access to entry 0 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x18 0.--31. 1. "RXF1_PUTGET0"
line.long 0x1C "RXF1_PUTGET1,Direct read/write access to entry 1 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x1C 0.--31. 1. "RXF1_PUTGET1"
line.long 0x20 "RXF1_PUTGET2,Direct read/write access to entry 2 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x20 0.--31. 1. "RXF1_PUTGET2"
line.long 0x24 "RXF1_PUTGET3,Direct read/write access to entry 3 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x24 0.--31. 1. "RXF1_PUTGET3"
line.long 0x28 "RXF2_PUTGET0,Direct read/write access to entry 0 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x28 0.--31. 1. "RXF2_PUTGET0"
line.long 0x2C "RXF2_PUTGET1,Direct read/write access to entry 1 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x2C 0.--31. 1. "RXF2_PUTGET1"
line.long 0x30 "RXF2_PUTGET2,Direct read/write access to entry 2 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x30 0.--31. 1. "RXF2_PUTGET2"
line.long 0x34 "RXF2_PUTGET3,Direct read/write access to entry 3 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x34 0.--31. 1. "RXF2_PUTGET3"
line.long 0x38 "RXF3_PUTGET0,Direct read/write access to entry 0 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x38 0.--31. 1. "RXF3_PUTGET0"
line.long 0x3C "RXF3_PUTGET1,Direct read/write access to entry 1 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x3C 0.--31. 1. "RXF3_PUTGET1"
line.long 0x40 "RXF3_PUTGET2,Direct read/write access to entry 2 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x40 0.--31. 1. "RXF3_PUTGET2"
line.long 0x44 "RXF3_PUTGET3,Direct read/write access to entry 3 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x44 0.--31. 1. "RXF3_PUTGET3"
line.long 0x48 "GPIOBASE,Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering. to access more than 32 GPIOs from PIO."
bitfld.long 0x48 4. "GPIOBASE" "0,1"
rgroup.long 0x16C++0x3
line.long 0x0 "INTR,Raw Interrupts"
bitfld.long 0x0 15. "SM7" "0,1"
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bitfld.long 0x0 14. "SM6" "0,1"
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bitfld.long 0x0 13. "SM5" "0,1"
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bitfld.long 0x0 12. "SM4" "0,1"
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bitfld.long 0x0 11. "SM3" "0,1"
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bitfld.long 0x0 10. "SM2" "0,1"
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bitfld.long 0x0 9. "SM1" "0,1"
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bitfld.long 0x0 8. "SM0" "0,1"
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bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
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bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
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bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
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bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
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bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
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bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
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bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
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bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
group.long 0x170++0x7
line.long 0x0 "IRQ0_INTE,Interrupt Enable for irq0"
bitfld.long 0x0 15. "SM7" "0,1"
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bitfld.long 0x0 14. "SM6" "0,1"
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bitfld.long 0x0 13. "SM5" "0,1"
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bitfld.long 0x0 12. "SM4" "0,1"
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bitfld.long 0x0 11. "SM3" "0,1"
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bitfld.long 0x0 10. "SM2" "0,1"
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bitfld.long 0x0 9. "SM1" "0,1"
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bitfld.long 0x0 8. "SM0" "0,1"
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bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
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bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
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bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
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bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
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bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
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bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
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bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
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bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
line.long 0x4 "IRQ0_INTF,Interrupt Force for irq0"
bitfld.long 0x4 15. "SM7" "0,1"
newline
bitfld.long 0x4 14. "SM6" "0,1"
newline
bitfld.long 0x4 13. "SM5" "0,1"
newline
bitfld.long 0x4 12. "SM4" "0,1"
newline
bitfld.long 0x4 11. "SM3" "0,1"
newline
bitfld.long 0x4 10. "SM2" "0,1"
newline
bitfld.long 0x4 9. "SM1" "0,1"
newline
bitfld.long 0x4 8. "SM0" "0,1"
newline
bitfld.long 0x4 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x4 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x4 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x4 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x4 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 0. "SM0_RXNEMPTY" "0,1"
rgroup.long 0x178++0x3
line.long 0x0 "IRQ0_INTS,Interrupt status after masking & forcing for irq0"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
group.long 0x17C++0x7
line.long 0x0 "IRQ1_INTE,Interrupt Enable for irq1"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
line.long 0x4 "IRQ1_INTF,Interrupt Force for irq1"
bitfld.long 0x4 15. "SM7" "0,1"
newline
bitfld.long 0x4 14. "SM6" "0,1"
newline
bitfld.long 0x4 13. "SM5" "0,1"
newline
bitfld.long 0x4 12. "SM4" "0,1"
newline
bitfld.long 0x4 11. "SM3" "0,1"
newline
bitfld.long 0x4 10. "SM2" "0,1"
newline
bitfld.long 0x4 9. "SM1" "0,1"
newline
bitfld.long 0x4 8. "SM0" "0,1"
newline
bitfld.long 0x4 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x4 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x4 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x4 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x4 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 0. "SM0_RXNEMPTY" "0,1"
rgroup.long 0x184++0x3
line.long 0x0 "IRQ1_INTS,Interrupt status after masking & forcing for irq1"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
tree.end
tree "PIO1"
base ad:0x50300000
group.long 0x0++0x3
line.long 0x0 "CTRL,PIO control register"
bitfld.long 0x0 26. "NEXTPREV_CLKDIV_RESTART,Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write." "0,1"
newline
bitfld.long 0x0 25. "NEXTPREV_SM_DISABLE,Write 1 to disable state machines in neighbouring PIO blocks as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write." "0,1"
newline
bitfld.long 0x0 24. "NEXTPREV_SM_ENABLE,Write 1 to enable state machines in neighbouring PIO blocks as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write." "0,1"
newline
hexmask.long.byte 0x0 20.--23. 1. "NEXT_PIO_MASK,A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART NEXTPREV_SM_ENABLE and.."
newline
hexmask.long.byte 0x0 16.--19. 1. "PREV_PIO_MASK,A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART OP_ENABLE OP_DISABLE in the.."
newline
hexmask.long.byte 0x0 8.--11. 1. "CLKDIV_RESTART,Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running so once started their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in.."
newline
hexmask.long.byte 0x0 4.--7. 1. "SM_RESTART,Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution."
newline
hexmask.long.byte 0x0 0.--3. 1. "SM_ENABLE,Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled a state machine will cease executing instructions except those written directly to SMx_INSTR by the system. Multiple bits can be.."
rgroup.long 0x4++0x3
line.long 0x0 "FSTAT,FIFO status register"
hexmask.long.byte 0x0 24.--27. 1. "TXEMPTY,State machine TX FIFO is empty"
newline
hexmask.long.byte 0x0 16.--19. 1. "TXFULL,State machine TX FIFO is full"
newline
hexmask.long.byte 0x0 8.--11. 1. "RXEMPTY,State machine RX FIFO is empty"
newline
hexmask.long.byte 0x0 0.--3. 1. "RXFULL,State machine RX FIFO is full"
group.long 0x8++0x3
line.long 0x0 "FDEBUG,FIFO debug register"
hexmask.long.byte 0x0 24.--27. 1. "TXSTALL,State machine has stalled on empty TX FIFO during a blocking PULL or an OUT with autopull enabled. Write 1 to clear."
newline
hexmask.long.byte 0x0 16.--19. 1. "TXOVER,TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way but the data that the system attempted to write is dropped so if this flag is.."
newline
hexmask.long.byte 0x0 8.--11. 1. "RXUNDER,RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way but the data returned by reading from an empty FIFO is undefined so this flag.."
newline
hexmask.long.byte 0x0 0.--3. 1. "RXSTALL,State machine has stalled on full RX FIFO during a blocking PUSH or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place in which case the state machine has dropped data. Write 1 to clear."
rgroup.long 0xC++0x3
line.long 0x0 "FLEVEL,FIFO levels"
hexmask.long.byte 0x0 28.--31. 1. "RX3"
newline
hexmask.long.byte 0x0 24.--27. 1. "TX3"
newline
hexmask.long.byte 0x0 20.--23. 1. "RX2"
newline
hexmask.long.byte 0x0 16.--19. 1. "TX2"
newline
hexmask.long.byte 0x0 12.--15. 1. "RX1"
newline
hexmask.long.byte 0x0 8.--11. 1. "TX1"
newline
hexmask.long.byte 0x0 4.--7. 1. "RX0"
newline
hexmask.long.byte 0x0 0.--3. 1. "TX0"
wgroup.long 0x10++0xF
line.long 0x0 "TXF0,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0x0 0.--31. 1. "TXF0"
line.long 0x4 "TXF1,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0x4 0.--31. 1. "TXF1"
line.long 0x8 "TXF2,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0x8 0.--31. 1. "TXF2"
line.long 0xC "TXF3,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0xC 0.--31. 1. "TXF3"
rgroup.long 0x20++0xF
line.long 0x0 "RXF0,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0x0 0.--31. 1. "RXF0"
line.long 0x4 "RXF1,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0x4 0.--31. 1. "RXF1"
line.long 0x8 "RXF2,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0x8 0.--31. 1. "RXF2"
line.long 0xC "RXF3,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0xC 0.--31. 1. "RXF3"
group.long 0x30++0x3
line.long 0x0 "IRQ,State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags. which can be set. cleared. and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use.."
hexmask.long.byte 0x0 0.--7. 1. "IRQ"
wgroup.long 0x34++0x3
line.long 0x0 "IRQ_FORCE,Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs. and is not.."
hexmask.long.byte 0x0 0.--7. 1. "IRQ_FORCE"
group.long 0x38++0x3
line.long 0x0 "INPUT_SYNC_BYPASS,There is a 2-flipflop synchronizer on each GPIO input. which protects PIO logic from metastabilities. This increases input delay. and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this.."
hexmask.long 0x0 0.--31. 1. "INPUT_SYNC_BYPASS"
rgroup.long 0x3C++0xB
line.long 0x0 "DBG_PADOUT,Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs. so the two most significant bits are hardwired to 0."
hexmask.long 0x0 0.--31. 1. "DBG_PADOUT"
line.long 0x4 "DBG_PADOE,Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs. so the two most significant bits are hardwired to 0."
hexmask.long 0x4 0.--31. 1. "DBG_PADOE"
line.long 0x8 "DBG_CFGINFO,The PIO hardware has some free parameters that may vary between chip products."
hexmask.long.byte 0x8 28.--31. 1. "VERSION,Version of the core PIO hardware."
newline
hexmask.long.byte 0x8 16.--21. 1. "IMEM_SIZE,The size of the instruction memory measured in units of one instruction"
newline
hexmask.long.byte 0x8 8.--11. 1. "SM_COUNT,The number of state machines this PIO instance is equipped with."
newline
hexmask.long.byte 0x8 0.--5. 1. "FIFO_DEPTH,The depth of the state machine TX/RX FIFOs measured in words."
wgroup.long 0x48++0x7F
line.long 0x0 "INSTR_MEM0,Write-only access to instruction memory location 0"
hexmask.long.word 0x0 0.--15. 1. "INSTR_MEM0"
line.long 0x4 "INSTR_MEM1,Write-only access to instruction memory location 1"
hexmask.long.word 0x4 0.--15. 1. "INSTR_MEM1"
line.long 0x8 "INSTR_MEM2,Write-only access to instruction memory location 2"
hexmask.long.word 0x8 0.--15. 1. "INSTR_MEM2"
line.long 0xC "INSTR_MEM3,Write-only access to instruction memory location 3"
hexmask.long.word 0xC 0.--15. 1. "INSTR_MEM3"
line.long 0x10 "INSTR_MEM4,Write-only access to instruction memory location 4"
hexmask.long.word 0x10 0.--15. 1. "INSTR_MEM4"
line.long 0x14 "INSTR_MEM5,Write-only access to instruction memory location 5"
hexmask.long.word 0x14 0.--15. 1. "INSTR_MEM5"
line.long 0x18 "INSTR_MEM6,Write-only access to instruction memory location 6"
hexmask.long.word 0x18 0.--15. 1. "INSTR_MEM6"
line.long 0x1C "INSTR_MEM7,Write-only access to instruction memory location 7"
hexmask.long.word 0x1C 0.--15. 1. "INSTR_MEM7"
line.long 0x20 "INSTR_MEM8,Write-only access to instruction memory location 8"
hexmask.long.word 0x20 0.--15. 1. "INSTR_MEM8"
line.long 0x24 "INSTR_MEM9,Write-only access to instruction memory location 9"
hexmask.long.word 0x24 0.--15. 1. "INSTR_MEM9"
line.long 0x28 "INSTR_MEM10,Write-only access to instruction memory location 10"
hexmask.long.word 0x28 0.--15. 1. "INSTR_MEM10"
line.long 0x2C "INSTR_MEM11,Write-only access to instruction memory location 11"
hexmask.long.word 0x2C 0.--15. 1. "INSTR_MEM11"
line.long 0x30 "INSTR_MEM12,Write-only access to instruction memory location 12"
hexmask.long.word 0x30 0.--15. 1. "INSTR_MEM12"
line.long 0x34 "INSTR_MEM13,Write-only access to instruction memory location 13"
hexmask.long.word 0x34 0.--15. 1. "INSTR_MEM13"
line.long 0x38 "INSTR_MEM14,Write-only access to instruction memory location 14"
hexmask.long.word 0x38 0.--15. 1. "INSTR_MEM14"
line.long 0x3C "INSTR_MEM15,Write-only access to instruction memory location 15"
hexmask.long.word 0x3C 0.--15. 1. "INSTR_MEM15"
line.long 0x40 "INSTR_MEM16,Write-only access to instruction memory location 16"
hexmask.long.word 0x40 0.--15. 1. "INSTR_MEM16"
line.long 0x44 "INSTR_MEM17,Write-only access to instruction memory location 17"
hexmask.long.word 0x44 0.--15. 1. "INSTR_MEM17"
line.long 0x48 "INSTR_MEM18,Write-only access to instruction memory location 18"
hexmask.long.word 0x48 0.--15. 1. "INSTR_MEM18"
line.long 0x4C "INSTR_MEM19,Write-only access to instruction memory location 19"
hexmask.long.word 0x4C 0.--15. 1. "INSTR_MEM19"
line.long 0x50 "INSTR_MEM20,Write-only access to instruction memory location 20"
hexmask.long.word 0x50 0.--15. 1. "INSTR_MEM20"
line.long 0x54 "INSTR_MEM21,Write-only access to instruction memory location 21"
hexmask.long.word 0x54 0.--15. 1. "INSTR_MEM21"
line.long 0x58 "INSTR_MEM22,Write-only access to instruction memory location 22"
hexmask.long.word 0x58 0.--15. 1. "INSTR_MEM22"
line.long 0x5C "INSTR_MEM23,Write-only access to instruction memory location 23"
hexmask.long.word 0x5C 0.--15. 1. "INSTR_MEM23"
line.long 0x60 "INSTR_MEM24,Write-only access to instruction memory location 24"
hexmask.long.word 0x60 0.--15. 1. "INSTR_MEM24"
line.long 0x64 "INSTR_MEM25,Write-only access to instruction memory location 25"
hexmask.long.word 0x64 0.--15. 1. "INSTR_MEM25"
line.long 0x68 "INSTR_MEM26,Write-only access to instruction memory location 26"
hexmask.long.word 0x68 0.--15. 1. "INSTR_MEM26"
line.long 0x6C "INSTR_MEM27,Write-only access to instruction memory location 27"
hexmask.long.word 0x6C 0.--15. 1. "INSTR_MEM27"
line.long 0x70 "INSTR_MEM28,Write-only access to instruction memory location 28"
hexmask.long.word 0x70 0.--15. 1. "INSTR_MEM28"
line.long 0x74 "INSTR_MEM29,Write-only access to instruction memory location 29"
hexmask.long.word 0x74 0.--15. 1. "INSTR_MEM29"
line.long 0x78 "INSTR_MEM30,Write-only access to instruction memory location 30"
hexmask.long.word 0x78 0.--15. 1. "INSTR_MEM30"
line.long 0x7C "INSTR_MEM31,Write-only access to instruction memory location 31"
hexmask.long.word 0x7C 0.--15. 1. "INSTR_MEM31"
group.long 0xC8++0xB
line.long 0x0 "SM0_CLKDIV,Clock divisor register for state machine 0"
hexmask.long.word 0x0 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
newline
hexmask.long.byte 0x0 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0x4 "SM0_EXECCTRL,Execution/behavioural settings for state machine 0"
rbitfld.long 0x4 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
newline
bitfld.long 0x4 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
newline
bitfld.long 0x4 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
newline
hexmask.long.byte 0x4 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
newline
hexmask.long.byte 0x4 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
newline
bitfld.long 0x4 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
newline
bitfld.long 0x4 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
newline
hexmask.long.byte 0x4 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
newline
hexmask.long.byte 0x4 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
newline
bitfld.long 0x4 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
newline
hexmask.long.byte 0x4 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x8 "SM0_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 0"
bitfld.long 0x8 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
newline
bitfld.long 0x8 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
newline
hexmask.long.byte 0x8 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
newline
hexmask.long.byte 0x8 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
newline
bitfld.long 0x8 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
newline
bitfld.long 0x8 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
newline
bitfld.long 0x8 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
newline
bitfld.long 0x8 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
newline
bitfld.long 0x8 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
newline
bitfld.long 0x8 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
newline
hexmask.long.byte 0x8 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0xD4++0x3
line.long 0x0 "SM0_ADDR,Current instruction address of state machine 0"
hexmask.long.byte 0x0 0.--4. 1. "SM0_ADDR"
group.long 0xD8++0x13
line.long 0x0 "SM0_INSTR,Read to see the instruction currently addressed by state machine 0's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM0_INSTR"
line.long 0x4 "SM0_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "SM1_CLKDIV,Clock divisor register for state machine 1"
hexmask.long.word 0x8 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
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hexmask.long.byte 0x8 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0xC "SM1_EXECCTRL,Execution/behavioural settings for state machine 1"
rbitfld.long 0xC 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
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bitfld.long 0xC 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
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bitfld.long 0xC 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
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hexmask.long.byte 0xC 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
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hexmask.long.byte 0xC 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
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bitfld.long 0xC 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
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bitfld.long 0xC 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
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hexmask.long.byte 0xC 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
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hexmask.long.byte 0xC 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
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bitfld.long 0xC 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
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hexmask.long.byte 0xC 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x10 "SM1_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 1"
bitfld.long 0x10 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
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bitfld.long 0x10 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
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hexmask.long.byte 0x10 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
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hexmask.long.byte 0x10 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
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bitfld.long 0x10 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
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bitfld.long 0x10 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
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bitfld.long 0x10 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
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bitfld.long 0x10 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
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bitfld.long 0x10 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
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bitfld.long 0x10 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0xEC++0x3
line.long 0x0 "SM1_ADDR,Current instruction address of state machine 1"
hexmask.long.byte 0x0 0.--4. 1. "SM1_ADDR"
group.long 0xF0++0x13
line.long 0x0 "SM1_INSTR,Read to see the instruction currently addressed by state machine 1's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM1_INSTR"
line.long 0x4 "SM1_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "SM2_CLKDIV,Clock divisor register for state machine 2"
hexmask.long.word 0x8 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
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hexmask.long.byte 0x8 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0xC "SM2_EXECCTRL,Execution/behavioural settings for state machine 2"
rbitfld.long 0xC 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
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bitfld.long 0xC 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
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bitfld.long 0xC 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
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hexmask.long.byte 0xC 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
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hexmask.long.byte 0xC 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
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bitfld.long 0xC 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
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bitfld.long 0xC 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
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hexmask.long.byte 0xC 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
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hexmask.long.byte 0xC 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
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bitfld.long 0xC 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
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hexmask.long.byte 0xC 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x10 "SM2_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 2"
bitfld.long 0x10 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
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bitfld.long 0x10 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
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hexmask.long.byte 0x10 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
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hexmask.long.byte 0x10 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
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bitfld.long 0x10 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
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bitfld.long 0x10 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
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bitfld.long 0x10 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
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bitfld.long 0x10 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
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bitfld.long 0x10 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
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bitfld.long 0x10 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0x104++0x3
line.long 0x0 "SM2_ADDR,Current instruction address of state machine 2"
hexmask.long.byte 0x0 0.--4. 1. "SM2_ADDR"
group.long 0x108++0x13
line.long 0x0 "SM2_INSTR,Read to see the instruction currently addressed by state machine 2's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM2_INSTR"
line.long 0x4 "SM2_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "SM3_CLKDIV,Clock divisor register for state machine 3"
hexmask.long.word 0x8 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
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hexmask.long.byte 0x8 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0xC "SM3_EXECCTRL,Execution/behavioural settings for state machine 3"
rbitfld.long 0xC 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
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bitfld.long 0xC 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
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bitfld.long 0xC 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
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hexmask.long.byte 0xC 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
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hexmask.long.byte 0xC 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
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bitfld.long 0xC 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
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bitfld.long 0xC 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
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hexmask.long.byte 0xC 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
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hexmask.long.byte 0xC 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
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bitfld.long 0xC 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
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hexmask.long.byte 0xC 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x10 "SM3_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 3"
bitfld.long 0x10 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
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bitfld.long 0x10 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
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hexmask.long.byte 0x10 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
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hexmask.long.byte 0x10 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
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bitfld.long 0x10 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
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bitfld.long 0x10 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
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bitfld.long 0x10 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
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bitfld.long 0x10 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
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bitfld.long 0x10 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
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bitfld.long 0x10 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0x11C++0x3
line.long 0x0 "SM3_ADDR,Current instruction address of state machine 3"
hexmask.long.byte 0x0 0.--4. 1. "SM3_ADDR"
group.long 0x120++0x4B
line.long 0x0 "SM3_INSTR,Read to see the instruction currently addressed by state machine 3's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM3_INSTR"
line.long 0x4 "SM3_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "RXF0_PUTGET0,Direct read/write access to entry 0 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x8 0.--31. 1. "RXF0_PUTGET0"
line.long 0xC "RXF0_PUTGET1,Direct read/write access to entry 1 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0xC 0.--31. 1. "RXF0_PUTGET1"
line.long 0x10 "RXF0_PUTGET2,Direct read/write access to entry 2 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x10 0.--31. 1. "RXF0_PUTGET2"
line.long 0x14 "RXF0_PUTGET3,Direct read/write access to entry 3 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x14 0.--31. 1. "RXF0_PUTGET3"
line.long 0x18 "RXF1_PUTGET0,Direct read/write access to entry 0 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x18 0.--31. 1. "RXF1_PUTGET0"
line.long 0x1C "RXF1_PUTGET1,Direct read/write access to entry 1 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x1C 0.--31. 1. "RXF1_PUTGET1"
line.long 0x20 "RXF1_PUTGET2,Direct read/write access to entry 2 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x20 0.--31. 1. "RXF1_PUTGET2"
line.long 0x24 "RXF1_PUTGET3,Direct read/write access to entry 3 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x24 0.--31. 1. "RXF1_PUTGET3"
line.long 0x28 "RXF2_PUTGET0,Direct read/write access to entry 0 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x28 0.--31. 1. "RXF2_PUTGET0"
line.long 0x2C "RXF2_PUTGET1,Direct read/write access to entry 1 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x2C 0.--31. 1. "RXF2_PUTGET1"
line.long 0x30 "RXF2_PUTGET2,Direct read/write access to entry 2 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x30 0.--31. 1. "RXF2_PUTGET2"
line.long 0x34 "RXF2_PUTGET3,Direct read/write access to entry 3 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x34 0.--31. 1. "RXF2_PUTGET3"
line.long 0x38 "RXF3_PUTGET0,Direct read/write access to entry 0 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x38 0.--31. 1. "RXF3_PUTGET0"
line.long 0x3C "RXF3_PUTGET1,Direct read/write access to entry 1 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x3C 0.--31. 1. "RXF3_PUTGET1"
line.long 0x40 "RXF3_PUTGET2,Direct read/write access to entry 2 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x40 0.--31. 1. "RXF3_PUTGET2"
line.long 0x44 "RXF3_PUTGET3,Direct read/write access to entry 3 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x44 0.--31. 1. "RXF3_PUTGET3"
line.long 0x48 "GPIOBASE,Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering. to access more than 32 GPIOs from PIO."
bitfld.long 0x48 4. "GPIOBASE" "0,1"
rgroup.long 0x16C++0x3
line.long 0x0 "INTR,Raw Interrupts"
bitfld.long 0x0 15. "SM7" "0,1"
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bitfld.long 0x0 14. "SM6" "0,1"
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bitfld.long 0x0 13. "SM5" "0,1"
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bitfld.long 0x0 12. "SM4" "0,1"
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bitfld.long 0x0 11. "SM3" "0,1"
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bitfld.long 0x0 10. "SM2" "0,1"
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bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
group.long 0x170++0x7
line.long 0x0 "IRQ0_INTE,Interrupt Enable for irq0"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
line.long 0x4 "IRQ0_INTF,Interrupt Force for irq0"
bitfld.long 0x4 15. "SM7" "0,1"
newline
bitfld.long 0x4 14. "SM6" "0,1"
newline
bitfld.long 0x4 13. "SM5" "0,1"
newline
bitfld.long 0x4 12. "SM4" "0,1"
newline
bitfld.long 0x4 11. "SM3" "0,1"
newline
bitfld.long 0x4 10. "SM2" "0,1"
newline
bitfld.long 0x4 9. "SM1" "0,1"
newline
bitfld.long 0x4 8. "SM0" "0,1"
newline
bitfld.long 0x4 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x4 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x4 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x4 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x4 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 0. "SM0_RXNEMPTY" "0,1"
rgroup.long 0x178++0x3
line.long 0x0 "IRQ0_INTS,Interrupt status after masking & forcing for irq0"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
group.long 0x17C++0x7
line.long 0x0 "IRQ1_INTE,Interrupt Enable for irq1"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
line.long 0x4 "IRQ1_INTF,Interrupt Force for irq1"
bitfld.long 0x4 15. "SM7" "0,1"
newline
bitfld.long 0x4 14. "SM6" "0,1"
newline
bitfld.long 0x4 13. "SM5" "0,1"
newline
bitfld.long 0x4 12. "SM4" "0,1"
newline
bitfld.long 0x4 11. "SM3" "0,1"
newline
bitfld.long 0x4 10. "SM2" "0,1"
newline
bitfld.long 0x4 9. "SM1" "0,1"
newline
bitfld.long 0x4 8. "SM0" "0,1"
newline
bitfld.long 0x4 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x4 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x4 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x4 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x4 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 0. "SM0_RXNEMPTY" "0,1"
rgroup.long 0x184++0x3
line.long 0x0 "IRQ1_INTS,Interrupt status after masking & forcing for irq1"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
tree.end
tree "PIO2"
base ad:0x50400000
group.long 0x0++0x3
line.long 0x0 "CTRL,PIO control register"
bitfld.long 0x0 26. "NEXTPREV_CLKDIV_RESTART,Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write." "0,1"
newline
bitfld.long 0x0 25. "NEXTPREV_SM_DISABLE,Write 1 to disable state machines in neighbouring PIO blocks as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write." "0,1"
newline
bitfld.long 0x0 24. "NEXTPREV_SM_ENABLE,Write 1 to enable state machines in neighbouring PIO blocks as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write." "0,1"
newline
hexmask.long.byte 0x0 20.--23. 1. "NEXT_PIO_MASK,A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART NEXTPREV_SM_ENABLE and.."
newline
hexmask.long.byte 0x0 16.--19. 1. "PREV_PIO_MASK,A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART OP_ENABLE OP_DISABLE in the.."
newline
hexmask.long.byte 0x0 8.--11. 1. "CLKDIV_RESTART,Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running so once started their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in.."
newline
hexmask.long.byte 0x0 4.--7. 1. "SM_RESTART,Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution."
newline
hexmask.long.byte 0x0 0.--3. 1. "SM_ENABLE,Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled a state machine will cease executing instructions except those written directly to SMx_INSTR by the system. Multiple bits can be.."
rgroup.long 0x4++0x3
line.long 0x0 "FSTAT,FIFO status register"
hexmask.long.byte 0x0 24.--27. 1. "TXEMPTY,State machine TX FIFO is empty"
newline
hexmask.long.byte 0x0 16.--19. 1. "TXFULL,State machine TX FIFO is full"
newline
hexmask.long.byte 0x0 8.--11. 1. "RXEMPTY,State machine RX FIFO is empty"
newline
hexmask.long.byte 0x0 0.--3. 1. "RXFULL,State machine RX FIFO is full"
group.long 0x8++0x3
line.long 0x0 "FDEBUG,FIFO debug register"
hexmask.long.byte 0x0 24.--27. 1. "TXSTALL,State machine has stalled on empty TX FIFO during a blocking PULL or an OUT with autopull enabled. Write 1 to clear."
newline
hexmask.long.byte 0x0 16.--19. 1. "TXOVER,TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way but the data that the system attempted to write is dropped so if this flag is.."
newline
hexmask.long.byte 0x0 8.--11. 1. "RXUNDER,RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way but the data returned by reading from an empty FIFO is undefined so this flag.."
newline
hexmask.long.byte 0x0 0.--3. 1. "RXSTALL,State machine has stalled on full RX FIFO during a blocking PUSH or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place in which case the state machine has dropped data. Write 1 to clear."
rgroup.long 0xC++0x3
line.long 0x0 "FLEVEL,FIFO levels"
hexmask.long.byte 0x0 28.--31. 1. "RX3"
newline
hexmask.long.byte 0x0 24.--27. 1. "TX3"
newline
hexmask.long.byte 0x0 20.--23. 1. "RX2"
newline
hexmask.long.byte 0x0 16.--19. 1. "TX2"
newline
hexmask.long.byte 0x0 12.--15. 1. "RX1"
newline
hexmask.long.byte 0x0 8.--11. 1. "TX1"
newline
hexmask.long.byte 0x0 4.--7. 1. "RX0"
newline
hexmask.long.byte 0x0 0.--3. 1. "TX0"
wgroup.long 0x10++0xF
line.long 0x0 "TXF0,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0x0 0.--31. 1. "TXF0"
line.long 0x4 "TXF1,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0x4 0.--31. 1. "TXF1"
line.long 0x8 "TXF2,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0x8 0.--31. 1. "TXF2"
line.long 0xC "TXF3,Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents. and sets the sticky FDEBUG_TXOVER error flag for this FIFO."
hexmask.long 0xC 0.--31. 1. "TXF3"
rgroup.long 0x20++0xF
line.long 0x0 "RXF0,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0x0 0.--31. 1. "RXF0"
line.long 0x4 "RXF1,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0x4 0.--31. 1. "RXF1"
line.long 0x8 "RXF2,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0x8 0.--31. 1. "RXF2"
line.long 0xC "RXF3,Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state. and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to.."
hexmask.long 0xC 0.--31. 1. "RXF3"
group.long 0x30++0x3
line.long 0x0 "IRQ,State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags. which can be set. cleared. and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use.."
hexmask.long.byte 0x0 0.--7. 1. "IRQ"
wgroup.long 0x34++0x3
line.long 0x0 "IRQ_FORCE,Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs. and is not.."
hexmask.long.byte 0x0 0.--7. 1. "IRQ_FORCE"
group.long 0x38++0x3
line.long 0x0 "INPUT_SYNC_BYPASS,There is a 2-flipflop synchronizer on each GPIO input. which protects PIO logic from metastabilities. This increases input delay. and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this.."
hexmask.long 0x0 0.--31. 1. "INPUT_SYNC_BYPASS"
rgroup.long 0x3C++0xB
line.long 0x0 "DBG_PADOUT,Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs. so the two most significant bits are hardwired to 0."
hexmask.long 0x0 0.--31. 1. "DBG_PADOUT"
line.long 0x4 "DBG_PADOE,Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs. so the two most significant bits are hardwired to 0."
hexmask.long 0x4 0.--31. 1. "DBG_PADOE"
line.long 0x8 "DBG_CFGINFO,The PIO hardware has some free parameters that may vary between chip products."
hexmask.long.byte 0x8 28.--31. 1. "VERSION,Version of the core PIO hardware."
newline
hexmask.long.byte 0x8 16.--21. 1. "IMEM_SIZE,The size of the instruction memory measured in units of one instruction"
newline
hexmask.long.byte 0x8 8.--11. 1. "SM_COUNT,The number of state machines this PIO instance is equipped with."
newline
hexmask.long.byte 0x8 0.--5. 1. "FIFO_DEPTH,The depth of the state machine TX/RX FIFOs measured in words."
wgroup.long 0x48++0x7F
line.long 0x0 "INSTR_MEM0,Write-only access to instruction memory location 0"
hexmask.long.word 0x0 0.--15. 1. "INSTR_MEM0"
line.long 0x4 "INSTR_MEM1,Write-only access to instruction memory location 1"
hexmask.long.word 0x4 0.--15. 1. "INSTR_MEM1"
line.long 0x8 "INSTR_MEM2,Write-only access to instruction memory location 2"
hexmask.long.word 0x8 0.--15. 1. "INSTR_MEM2"
line.long 0xC "INSTR_MEM3,Write-only access to instruction memory location 3"
hexmask.long.word 0xC 0.--15. 1. "INSTR_MEM3"
line.long 0x10 "INSTR_MEM4,Write-only access to instruction memory location 4"
hexmask.long.word 0x10 0.--15. 1. "INSTR_MEM4"
line.long 0x14 "INSTR_MEM5,Write-only access to instruction memory location 5"
hexmask.long.word 0x14 0.--15. 1. "INSTR_MEM5"
line.long 0x18 "INSTR_MEM6,Write-only access to instruction memory location 6"
hexmask.long.word 0x18 0.--15. 1. "INSTR_MEM6"
line.long 0x1C "INSTR_MEM7,Write-only access to instruction memory location 7"
hexmask.long.word 0x1C 0.--15. 1. "INSTR_MEM7"
line.long 0x20 "INSTR_MEM8,Write-only access to instruction memory location 8"
hexmask.long.word 0x20 0.--15. 1. "INSTR_MEM8"
line.long 0x24 "INSTR_MEM9,Write-only access to instruction memory location 9"
hexmask.long.word 0x24 0.--15. 1. "INSTR_MEM9"
line.long 0x28 "INSTR_MEM10,Write-only access to instruction memory location 10"
hexmask.long.word 0x28 0.--15. 1. "INSTR_MEM10"
line.long 0x2C "INSTR_MEM11,Write-only access to instruction memory location 11"
hexmask.long.word 0x2C 0.--15. 1. "INSTR_MEM11"
line.long 0x30 "INSTR_MEM12,Write-only access to instruction memory location 12"
hexmask.long.word 0x30 0.--15. 1. "INSTR_MEM12"
line.long 0x34 "INSTR_MEM13,Write-only access to instruction memory location 13"
hexmask.long.word 0x34 0.--15. 1. "INSTR_MEM13"
line.long 0x38 "INSTR_MEM14,Write-only access to instruction memory location 14"
hexmask.long.word 0x38 0.--15. 1. "INSTR_MEM14"
line.long 0x3C "INSTR_MEM15,Write-only access to instruction memory location 15"
hexmask.long.word 0x3C 0.--15. 1. "INSTR_MEM15"
line.long 0x40 "INSTR_MEM16,Write-only access to instruction memory location 16"
hexmask.long.word 0x40 0.--15. 1. "INSTR_MEM16"
line.long 0x44 "INSTR_MEM17,Write-only access to instruction memory location 17"
hexmask.long.word 0x44 0.--15. 1. "INSTR_MEM17"
line.long 0x48 "INSTR_MEM18,Write-only access to instruction memory location 18"
hexmask.long.word 0x48 0.--15. 1. "INSTR_MEM18"
line.long 0x4C "INSTR_MEM19,Write-only access to instruction memory location 19"
hexmask.long.word 0x4C 0.--15. 1. "INSTR_MEM19"
line.long 0x50 "INSTR_MEM20,Write-only access to instruction memory location 20"
hexmask.long.word 0x50 0.--15. 1. "INSTR_MEM20"
line.long 0x54 "INSTR_MEM21,Write-only access to instruction memory location 21"
hexmask.long.word 0x54 0.--15. 1. "INSTR_MEM21"
line.long 0x58 "INSTR_MEM22,Write-only access to instruction memory location 22"
hexmask.long.word 0x58 0.--15. 1. "INSTR_MEM22"
line.long 0x5C "INSTR_MEM23,Write-only access to instruction memory location 23"
hexmask.long.word 0x5C 0.--15. 1. "INSTR_MEM23"
line.long 0x60 "INSTR_MEM24,Write-only access to instruction memory location 24"
hexmask.long.word 0x60 0.--15. 1. "INSTR_MEM24"
line.long 0x64 "INSTR_MEM25,Write-only access to instruction memory location 25"
hexmask.long.word 0x64 0.--15. 1. "INSTR_MEM25"
line.long 0x68 "INSTR_MEM26,Write-only access to instruction memory location 26"
hexmask.long.word 0x68 0.--15. 1. "INSTR_MEM26"
line.long 0x6C "INSTR_MEM27,Write-only access to instruction memory location 27"
hexmask.long.word 0x6C 0.--15. 1. "INSTR_MEM27"
line.long 0x70 "INSTR_MEM28,Write-only access to instruction memory location 28"
hexmask.long.word 0x70 0.--15. 1. "INSTR_MEM28"
line.long 0x74 "INSTR_MEM29,Write-only access to instruction memory location 29"
hexmask.long.word 0x74 0.--15. 1. "INSTR_MEM29"
line.long 0x78 "INSTR_MEM30,Write-only access to instruction memory location 30"
hexmask.long.word 0x78 0.--15. 1. "INSTR_MEM30"
line.long 0x7C "INSTR_MEM31,Write-only access to instruction memory location 31"
hexmask.long.word 0x7C 0.--15. 1. "INSTR_MEM31"
group.long 0xC8++0xB
line.long 0x0 "SM0_CLKDIV,Clock divisor register for state machine 0"
hexmask.long.word 0x0 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
newline
hexmask.long.byte 0x0 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0x4 "SM0_EXECCTRL,Execution/behavioural settings for state machine 0"
rbitfld.long 0x4 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
newline
bitfld.long 0x4 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
newline
bitfld.long 0x4 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
newline
hexmask.long.byte 0x4 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
newline
hexmask.long.byte 0x4 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
newline
bitfld.long 0x4 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
newline
bitfld.long 0x4 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
newline
hexmask.long.byte 0x4 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
newline
hexmask.long.byte 0x4 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
newline
bitfld.long 0x4 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
newline
hexmask.long.byte 0x4 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x8 "SM0_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 0"
bitfld.long 0x8 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
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bitfld.long 0x8 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
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hexmask.long.byte 0x8 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
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hexmask.long.byte 0x8 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
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bitfld.long 0x8 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
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bitfld.long 0x8 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
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bitfld.long 0x8 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
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bitfld.long 0x8 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
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bitfld.long 0x8 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
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bitfld.long 0x8 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
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hexmask.long.byte 0x8 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0xD4++0x3
line.long 0x0 "SM0_ADDR,Current instruction address of state machine 0"
hexmask.long.byte 0x0 0.--4. 1. "SM0_ADDR"
group.long 0xD8++0x13
line.long 0x0 "SM0_INSTR,Read to see the instruction currently addressed by state machine 0's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM0_INSTR"
line.long 0x4 "SM0_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "SM1_CLKDIV,Clock divisor register for state machine 1"
hexmask.long.word 0x8 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
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hexmask.long.byte 0x8 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0xC "SM1_EXECCTRL,Execution/behavioural settings for state machine 1"
rbitfld.long 0xC 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
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bitfld.long 0xC 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
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bitfld.long 0xC 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
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hexmask.long.byte 0xC 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
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hexmask.long.byte 0xC 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
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bitfld.long 0xC 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
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bitfld.long 0xC 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
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hexmask.long.byte 0xC 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
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hexmask.long.byte 0xC 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
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bitfld.long 0xC 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
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hexmask.long.byte 0xC 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x10 "SM1_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 1"
bitfld.long 0x10 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
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bitfld.long 0x10 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
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hexmask.long.byte 0x10 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
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hexmask.long.byte 0x10 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
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bitfld.long 0x10 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
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bitfld.long 0x10 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
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bitfld.long 0x10 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
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bitfld.long 0x10 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
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bitfld.long 0x10 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
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bitfld.long 0x10 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0xEC++0x3
line.long 0x0 "SM1_ADDR,Current instruction address of state machine 1"
hexmask.long.byte 0x0 0.--4. 1. "SM1_ADDR"
group.long 0xF0++0x13
line.long 0x0 "SM1_INSTR,Read to see the instruction currently addressed by state machine 1's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM1_INSTR"
line.long 0x4 "SM1_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "SM2_CLKDIV,Clock divisor register for state machine 2"
hexmask.long.word 0x8 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
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hexmask.long.byte 0x8 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0xC "SM2_EXECCTRL,Execution/behavioural settings for state machine 2"
rbitfld.long 0xC 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
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bitfld.long 0xC 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
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bitfld.long 0xC 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
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hexmask.long.byte 0xC 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
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hexmask.long.byte 0xC 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
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bitfld.long 0xC 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
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bitfld.long 0xC 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
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hexmask.long.byte 0xC 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
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hexmask.long.byte 0xC 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
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bitfld.long 0xC 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
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hexmask.long.byte 0xC 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x10 "SM2_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 2"
bitfld.long 0x10 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
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bitfld.long 0x10 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
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hexmask.long.byte 0x10 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
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hexmask.long.byte 0x10 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
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bitfld.long 0x10 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
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bitfld.long 0x10 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
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bitfld.long 0x10 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
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bitfld.long 0x10 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
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bitfld.long 0x10 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
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bitfld.long 0x10 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0x104++0x3
line.long 0x0 "SM2_ADDR,Current instruction address of state machine 2"
hexmask.long.byte 0x0 0.--4. 1. "SM2_ADDR"
group.long 0x108++0x13
line.long 0x0 "SM2_INSTR,Read to see the instruction currently addressed by state machine 2's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM2_INSTR"
line.long 0x4 "SM2_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "SM3_CLKDIV,Clock divisor register for state machine 3"
hexmask.long.word 0x8 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256)."
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hexmask.long.byte 0x8 8.--15. 1. "FRAC,Fractional part of clock divisor"
line.long 0xC "SM3_EXECCTRL,Execution/behavioural settings for state machine 3"
rbitfld.long 0xC 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine. Will clear to 0 once this instruction completes." "0,1"
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bitfld.long 0xC 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit. This allows instructions to perform side-set optionally rather than on every instruction but the maximum possible side-set width.." "0,1"
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bitfld.long 0xC 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1"
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hexmask.long.byte 0xC 24.--28. 1. "JMP_PIN,The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."
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hexmask.long.byte 0xC 19.--23. 1. "OUT_EN_SEL,Which data bit to use for inline OUT enable"
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bitfld.long 0xC 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable" "0,1"
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bitfld.long 0xC 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1"
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hexmask.long.byte 0xC 12.--16. 1. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom."
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hexmask.long.byte 0xC 7.--11. 1. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address."
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bitfld.long 0xC 5.--6. "STATUS_SEL,Comparison used for the MOV x STATUS instruction." "0: All-ones if TX FIFO level < N otherwise all-zeroes,1: All-ones if RX FIFO level < N otherwise all-zeroes,2: All-ones if the indexed IRQ flag is raised..,?"
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hexmask.long.byte 0xC 0.--4. 1. "STATUS_N,Comparison level or IRQ index for the MOV x STATUS instruction."
line.long 0x10 "SM3_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 3"
bitfld.long 0x10 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep." "0,1"
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bitfld.long 0x10 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep." "0,1"
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hexmask.long.byte 0x10 25.--29. 1. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place."
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hexmask.long.byte 0x10 20.--24. 1. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place."
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bitfld.long 0x10 19. "OUT_SHIFTDIR,1 = shift out of output shift register to right. 0 = to left." "0: to left,1: shift out of output shift register to right"
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bitfld.long 0x10 18. "IN_SHIFTDIR,1 = shift input shift register to right (data enters from left). 0 = to left." "0: to left,1: shift input shift register to right"
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bitfld.long 0x10 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH." "0,1"
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bitfld.long 0x10 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH." "0,1"
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bitfld.long 0x10 15. "FJOIN_RX_PUT,If 1 disable this state machine's RX FIFO make its storage available for random write access by the state machine (using the `put` instruction) and unless FJOIN_RX_GET is also set random read access by the processor (through the.." "0,1"
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bitfld.long 0x10 14. "FJOIN_RX_GET,If 1 disable this state machine's RX FIFO make its storage available for random read access by the state machine (using the `get` instruction) and unless FJOIN_RX_PUT is also set random write access by the processor (through the.." "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "IN_COUNT,Set the number of pins which are not masked to 0 when read by an IN PINS WAIT PIN or MOV x PINS instruction."
rgroup.long 0x11C++0x3
line.long 0x0 "SM3_ADDR,Current instruction address of state machine 3"
hexmask.long.byte 0x0 0.--4. 1. "SM3_ADDR"
group.long 0x120++0x4B
line.long 0x0 "SM3_INSTR,Read to see the instruction currently addressed by state machine 3's program counter"
hexmask.long.word 0x0 0.--15. 1. "SM3_INSTR"
line.long 0x4 "SM3_PINCTRL,State machine pin control"
bitfld.long 0x4 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit if present. Minimum of 0 (all delay bits no side-set) and maximum of 5 (all side-set no delay)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 26.--28. "SET_COUNT,The number of pins asserted by a SET. In the range 0 to 5 inclusive." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 20.--25. 1. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."
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hexmask.long.byte 0x4 15.--19. 1. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits with a modulo of 32 applied to pin number."
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hexmask.long.byte 0x4 10.--14. 1. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5 determined by SIDESET_COUNT) are used for side-set data with the remaining LSBs used for delay. The.."
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hexmask.long.byte 0x4 5.--9. 1. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."
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hexmask.long.byte 0x4 0.--4. 1. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."
line.long 0x8 "RXF0_PUTGET0,Direct read/write access to entry 0 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x8 0.--31. 1. "RXF0_PUTGET0"
line.long 0xC "RXF0_PUTGET1,Direct read/write access to entry 1 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0xC 0.--31. 1. "RXF0_PUTGET1"
line.long 0x10 "RXF0_PUTGET2,Direct read/write access to entry 2 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x10 0.--31. 1. "RXF0_PUTGET2"
line.long 0x14 "RXF0_PUTGET3,Direct read/write access to entry 3 of SM0's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x14 0.--31. 1. "RXF0_PUTGET3"
line.long 0x18 "RXF1_PUTGET0,Direct read/write access to entry 0 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x18 0.--31. 1. "RXF1_PUTGET0"
line.long 0x1C "RXF1_PUTGET1,Direct read/write access to entry 1 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x1C 0.--31. 1. "RXF1_PUTGET1"
line.long 0x20 "RXF1_PUTGET2,Direct read/write access to entry 2 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x20 0.--31. 1. "RXF1_PUTGET2"
line.long 0x24 "RXF1_PUTGET3,Direct read/write access to entry 3 of SM1's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x24 0.--31. 1. "RXF1_PUTGET3"
line.long 0x28 "RXF2_PUTGET0,Direct read/write access to entry 0 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x28 0.--31. 1. "RXF2_PUTGET0"
line.long 0x2C "RXF2_PUTGET1,Direct read/write access to entry 1 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x2C 0.--31. 1. "RXF2_PUTGET1"
line.long 0x30 "RXF2_PUTGET2,Direct read/write access to entry 2 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x30 0.--31. 1. "RXF2_PUTGET2"
line.long 0x34 "RXF2_PUTGET3,Direct read/write access to entry 3 of SM2's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x34 0.--31. 1. "RXF2_PUTGET3"
line.long 0x38 "RXF3_PUTGET0,Direct read/write access to entry 0 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x38 0.--31. 1. "RXF3_PUTGET0"
line.long 0x3C "RXF3_PUTGET1,Direct read/write access to entry 1 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x3C 0.--31. 1. "RXF3_PUTGET1"
line.long 0x40 "RXF3_PUTGET2,Direct read/write access to entry 2 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x40 0.--31. 1. "RXF3_PUTGET2"
line.long 0x44 "RXF3_PUTGET3,Direct read/write access to entry 3 of SM3's RX FIFO. if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."
hexmask.long 0x44 0.--31. 1. "RXF3_PUTGET3"
line.long 0x48 "GPIOBASE,Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering. to access more than 32 GPIOs from PIO."
bitfld.long 0x48 4. "GPIOBASE" "0,1"
rgroup.long 0x16C++0x3
line.long 0x0 "INTR,Raw Interrupts"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
group.long 0x170++0x7
line.long 0x0 "IRQ0_INTE,Interrupt Enable for irq0"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
line.long 0x4 "IRQ0_INTF,Interrupt Force for irq0"
bitfld.long 0x4 15. "SM7" "0,1"
newline
bitfld.long 0x4 14. "SM6" "0,1"
newline
bitfld.long 0x4 13. "SM5" "0,1"
newline
bitfld.long 0x4 12. "SM4" "0,1"
newline
bitfld.long 0x4 11. "SM3" "0,1"
newline
bitfld.long 0x4 10. "SM2" "0,1"
newline
bitfld.long 0x4 9. "SM1" "0,1"
newline
bitfld.long 0x4 8. "SM0" "0,1"
newline
bitfld.long 0x4 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x4 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x4 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x4 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x4 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 0. "SM0_RXNEMPTY" "0,1"
rgroup.long 0x178++0x3
line.long 0x0 "IRQ0_INTS,Interrupt status after masking & forcing for irq0"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
group.long 0x17C++0x7
line.long 0x0 "IRQ1_INTE,Interrupt Enable for irq1"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
line.long 0x4 "IRQ1_INTF,Interrupt Force for irq1"
bitfld.long 0x4 15. "SM7" "0,1"
newline
bitfld.long 0x4 14. "SM6" "0,1"
newline
bitfld.long 0x4 13. "SM5" "0,1"
newline
bitfld.long 0x4 12. "SM4" "0,1"
newline
bitfld.long 0x4 11. "SM3" "0,1"
newline
bitfld.long 0x4 10. "SM2" "0,1"
newline
bitfld.long 0x4 9. "SM1" "0,1"
newline
bitfld.long 0x4 8. "SM0" "0,1"
newline
bitfld.long 0x4 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x4 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x4 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x4 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x4 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x4 0. "SM0_RXNEMPTY" "0,1"
rgroup.long 0x184++0x3
line.long 0x0 "IRQ1_INTS,Interrupt status after masking & forcing for irq1"
bitfld.long 0x0 15. "SM7" "0,1"
newline
bitfld.long 0x0 14. "SM6" "0,1"
newline
bitfld.long 0x0 13. "SM5" "0,1"
newline
bitfld.long 0x0 12. "SM4" "0,1"
newline
bitfld.long 0x0 11. "SM3" "0,1"
newline
bitfld.long 0x0 10. "SM2" "0,1"
newline
bitfld.long 0x0 9. "SM1" "0,1"
newline
bitfld.long 0x0 8. "SM0" "0,1"
newline
bitfld.long 0x0 7. "SM3_TXNFULL" "0,1"
newline
bitfld.long 0x0 6. "SM2_TXNFULL" "0,1"
newline
bitfld.long 0x0 5. "SM1_TXNFULL" "0,1"
newline
bitfld.long 0x0 4. "SM0_TXNFULL" "0,1"
newline
bitfld.long 0x0 3. "SM3_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 2. "SM2_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 1. "SM1_RXNEMPTY" "0,1"
newline
bitfld.long 0x0 0. "SM0_RXNEMPTY" "0,1"
tree.end
tree.end
tree "PLL"
base ad:0x0
tree "PLL_SYS"
base ad:0x40050000
group.long 0x0++0x1B
line.long 0x0 "CS,Control and Status"
rbitfld.long 0x0 31. "LOCK,PLL is locked" "0,1"
eventfld.long 0x0 30. "LOCK_N,PLL is not locked" "0,1"
bitfld.long 0x0 8. "BYPASS,Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so." "0,1"
hexmask.long.byte 0x0 0.--5. 1. "REFDIV,Divides the PLL input reference clock."
line.long 0x4 "PWR,Controls the PLL power modes."
bitfld.long 0x4 5. "VCOPD,PLL VCO powerdown" "0,1"
bitfld.long 0x4 3. "POSTDIVPD,PLL post divider powerdown" "0,1"
bitfld.long 0x4 2. "DSMPD,PLL DSM powerdown" "0,1"
bitfld.long 0x4 0. "PD,PLL powerdown" "0,1"
line.long 0x8 "FBDIV_INT,Feedback divisor"
hexmask.long.word 0x8 0.--11. 1. "FBDIV_INT,see ctrl reg description for constraints"
line.long 0xC "PRIM,Controls the PLL post dividers for the primary output"
bitfld.long 0xC 16.--18. "POSTDIV1,divide by 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 12.--14. "POSTDIV2,divide by 1-7" "0,1,2,3,4,5,6,7"
line.long 0x10 "INTR,Raw Interrupts"
eventfld.long 0x10 0. "LOCK_N_STICKY" "0,1"
line.long 0x14 "INTE,Interrupt Enable"
bitfld.long 0x14 0. "LOCK_N_STICKY" "0,1"
line.long 0x18 "INTF,Interrupt Force"
bitfld.long 0x18 0. "LOCK_N_STICKY" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "INTS,Interrupt status after masking & forcing"
bitfld.long 0x0 0. "LOCK_N_STICKY" "0,1"
tree.end
tree "PLL_USB"
base ad:0x40058000
group.long 0x0++0x1B
line.long 0x0 "CS,Control and Status"
rbitfld.long 0x0 31. "LOCK,PLL is locked" "0,1"
eventfld.long 0x0 30. "LOCK_N,PLL is not locked" "0,1"
bitfld.long 0x0 8. "BYPASS,Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so." "0,1"
hexmask.long.byte 0x0 0.--5. 1. "REFDIV,Divides the PLL input reference clock."
line.long 0x4 "PWR,Controls the PLL power modes."
bitfld.long 0x4 5. "VCOPD,PLL VCO powerdown" "0,1"
bitfld.long 0x4 3. "POSTDIVPD,PLL post divider powerdown" "0,1"
bitfld.long 0x4 2. "DSMPD,PLL DSM powerdown" "0,1"
bitfld.long 0x4 0. "PD,PLL powerdown" "0,1"
line.long 0x8 "FBDIV_INT,Feedback divisor"
hexmask.long.word 0x8 0.--11. 1. "FBDIV_INT,see ctrl reg description for constraints"
line.long 0xC "PRIM,Controls the PLL post dividers for the primary output"
bitfld.long 0xC 16.--18. "POSTDIV1,divide by 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 12.--14. "POSTDIV2,divide by 1-7" "0,1,2,3,4,5,6,7"
line.long 0x10 "INTR,Raw Interrupts"
eventfld.long 0x10 0. "LOCK_N_STICKY" "0,1"
line.long 0x14 "INTE,Interrupt Enable"
bitfld.long 0x14 0. "LOCK_N_STICKY" "0,1"
line.long 0x18 "INTF,Interrupt Force"
bitfld.long 0x18 0. "LOCK_N_STICKY" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "INTS,Interrupt status after masking & forcing"
bitfld.long 0x0 0. "LOCK_N_STICKY" "0,1"
tree.end
tree.end
tree "POWMAN (Power Management)"
base ad:0x40100000
group.long 0x0++0x7
line.long 0x0 "BADPASSWD,Indicates a bad password has been used"
eventfld.long 0x0 0. "BADPASSWD" "0,1"
line.long 0x4 "VREG_CTRL,Voltage Regulator Control"
bitfld.long 0x4 15. "RST_N,returns the regulator to its startup settings" "0,1"
bitfld.long 0x4 13. "UNLOCK,unlocks the VREG control interface after power up" "0,1"
newline
bitfld.long 0x4 12. "ISOLATE,isolates the VREG control interface" "0,1"
bitfld.long 0x4 8. "DISABLE_VOLTAGE_LIMIT,0=not disabled 1=enabled" "0: not disabled,1: enabled"
newline
bitfld.long 0x4 4.--6. "HT_TH,high temperature protection threshold" "0,1,2,3,4,5,6,7"
rgroup.long 0x8++0x3
line.long 0x0 "VREG_STS,Voltage Regulator Status"
bitfld.long 0x0 4. "VOUT_OK,output regulation status" "0: not in regulation,1: in regulation"
bitfld.long 0x0 0. "STARTUP,startup status" "0: startup complete,1: starting up"
group.long 0xC++0x63
line.long 0x0 "VREG,Voltage Regulator Settings"
rbitfld.long 0x0 15. "UPDATE_IN_PROGRESS,regulator state is being updated" "0,1"
hexmask.long.byte 0x0 4.--8. 1. "VSEL,output voltage select"
newline
bitfld.long 0x0 1. "HIZ,high impedance mode select" "0: not in high impedance mode,1: in high impedance mode"
line.long 0x4 "VREG_LP_ENTRY,Voltage Regulator Low Power Entry Settings"
hexmask.long.byte 0x4 4.--8. 1. "VSEL,output voltage select"
bitfld.long 0x4 2. "MODE,selects either normal (switching) mode or low power (linear) mode" "0: normal mode,1: low power mode"
newline
bitfld.long 0x4 1. "HIZ,high impedance mode select" "0: not in high impedance mode,1: in high impedance mode"
line.long 0x8 "VREG_LP_EXIT,Voltage Regulator Low Power Exit Settings"
hexmask.long.byte 0x8 4.--8. 1. "VSEL,output voltage select"
bitfld.long 0x8 2. "MODE,selects either normal (switching) mode or low power (linear) mode" "0: normal mode,1: low power mode"
newline
bitfld.long 0x8 1. "HIZ,high impedance mode select" "0: not in high impedance mode,1: in high impedance mode"
line.long 0xC "BOD_CTRL,Brown-out Detection Control"
bitfld.long 0xC 12. "ISOLATE,isolates the brown-out detection control interface" "0,1"
line.long 0x10 "BOD,Brown-out Detection Settings"
hexmask.long.byte 0x10 4.--8. 1. "VSEL,threshold select"
bitfld.long 0x10 0. "EN,enable brown-out detection" "0: not enabled,1: enabled"
line.long 0x14 "BOD_LP_ENTRY,Brown-out Detection Low Power Entry Settings"
hexmask.long.byte 0x14 4.--8. 1. "VSEL,threshold select"
bitfld.long 0x14 0. "EN,enable brown-out detection" "0: not enabled,1: enabled"
line.long 0x18 "BOD_LP_EXIT,Brown-out Detection Low Power Exit Settings"
hexmask.long.byte 0x18 4.--8. 1. "VSEL,threshold select"
bitfld.long 0x18 0. "EN,enable brown-out detection" "0: not enabled,1: enabled"
line.long 0x1C "LPOSC,Low power oscillator control register."
hexmask.long.byte 0x1C 4.--9. 1. "TRIM,Frequency trim - the trim step is typically 1% of the reset frequency but can be up to 3%"
bitfld.long 0x1C 0.--1. "MODE,This feature has been removed" "0,1,2,3"
line.long 0x20 "CHIP_RESET,Chip reset control and status"
rbitfld.long 0x20 28. "HAD_WATCHDOG_RESET_RSM,Last reset was a watchdog timeout which was configured to reset the power-on state machine" "0,1"
rbitfld.long 0x20 27. "HAD_HZD_SYS_RESET_REQ,Last reset was a system reset from the hazard debugger" "0,1"
newline
rbitfld.long 0x20 26. "HAD_GLITCH_DETECT,Last reset was due to a power supply glitch" "0,1"
rbitfld.long 0x20 25. "HAD_SWCORE_PD,Last reset was a switched core powerdown" "0,1"
newline
rbitfld.long 0x20 24. "HAD_WATCHDOG_RESET_SWCORE,Last reset was a watchdog timeout which was configured to reset the switched-core" "0,1"
rbitfld.long 0x20 23. "HAD_WATCHDOG_RESET_POWMAN,Last reset was a watchdog timeout which was configured to reset the power manager" "0,1"
newline
rbitfld.long 0x20 22. "HAD_WATCHDOG_RESET_POWMAN_ASYNC,Last reset was a watchdog timeout which was configured to reset the power manager asynchronously" "0,1"
rbitfld.long 0x20 21. "HAD_RESCUE,Last reset was a rescue reset from the debugger" "0,1"
newline
rbitfld.long 0x20 19. "HAD_DP_RESET_REQ,Last reset was an reset request from the arm debugger" "0,1"
rbitfld.long 0x20 18. "HAD_RUN_LOW,Last reset was from the RUN pin" "0,1"
newline
rbitfld.long 0x20 17. "HAD_BOR,Last reset was from the brown-out detection block" "0,1"
rbitfld.long 0x20 16. "HAD_POR,Last reset was from the power-on reset" "0,1"
newline
eventfld.long 0x20 4. "RESCUE_FLAG,This is set by a rescue reset from the RP-AP." "0,1"
bitfld.long 0x20 0. "DOUBLE_TAP,This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader." "0,1"
line.long 0x24 "WDSEL,Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM)."
bitfld.long 0x24 12. "RESET_RSM,If set to 1 a watchdog reset will run the full power-on state machine (PSM) sequence" "0,1"
bitfld.long 0x24 8. "RESET_SWCORE,If set to 1 a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence" "0,1"
newline
bitfld.long 0x24 4. "RESET_POWMAN,If set to 1 a watchdog reset will restore powman defaults reset the timer reset the switched core power domain" "0,1"
bitfld.long 0x24 0. "RESET_POWMAN_ASYNC,If set to 1 a watchdog reset will restore powman defaults reset the timer " "0,1"
line.long 0x28 "SEQ_CFG,For configuration of the power sequencer"
rbitfld.long 0x28 20. "USING_FAST_POWCK,0 indicates the POWMAN clock is running from the low power oscillator (32kHz)" "0,1"
newline
rbitfld.long 0x28 17. "USING_BOD_LP,Indicates the brown-out detector (BOD) mode" "0: BOD high power mode which is the default,1: BOD low power mode"
newline
rbitfld.long 0x28 16. "USING_VREG_LP,Indicates the voltage regulator (VREG) mode" "0: VREG high power mode which is the default,1: VREG low power mode"
bitfld.long 0x28 12. "USE_FAST_POWCK,selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running." "0,1"
newline
bitfld.long 0x28 8. "RUN_LPOSC_IN_LP,Set to 0 to stop the low power osc when the switched-core is powered down which is unwise if using it to clock the timer" "0,1"
bitfld.long 0x28 7. "USE_BOD_HP,Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up" "0,1"
newline
bitfld.long 0x28 6. "USE_BOD_LP,Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down" "0,1"
bitfld.long 0x28 5. "USE_VREG_HP,Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up" "0,1"
newline
bitfld.long 0x28 4. "USE_VREG_LP,Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down" "0,1"
bitfld.long 0x28 1. "HW_PWRUP_SRAM0,Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx)." "0: power-up,1: no change"
newline
bitfld.long 0x28 0. "HW_PWRUP_SRAM1,Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx)." "0: power-up,1: no change"
line.long 0x2C "STATE,This register controls the power state of the 4 power domains."
rbitfld.long 0x2C 13. "CHANGING" "0,1"
rbitfld.long 0x2C 12. "WAITING" "0,1"
newline
rbitfld.long 0x2C 11. "BAD_HW_REQ,Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up)" "0,1"
rbitfld.long 0x2C 10. "BAD_SW_REQ,Bad software initiated state request. No action taken." "0,1"
newline
eventfld.long 0x2C 9. "PWRUP_WHILE_WAITING,Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down." "0,1"
eventfld.long 0x2C 8. "REQ_IGNORED" "0,1"
newline
hexmask.long.byte 0x2C 4.--7. 1. "REQ"
hexmask.long.byte 0x2C 0.--3. 1. "CURRENT"
line.long 0x30 "POW_FASTDIV"
hexmask.long.word 0x30 0.--10. 1. "POW_FASTDIV,divides the POWMAN clock to provide a tick for the delay module and state machines"
line.long 0x34 "POW_DELAY,power state machine delays"
hexmask.long.byte 0x34 8.--15. 1. "SRAM_STEP,timing between the sram0 and sram1 power state machine steps"
hexmask.long.byte 0x34 4.--7. 1. "XIP_STEP,timing between the xip power state machine steps"
newline
hexmask.long.byte 0x34 0.--3. 1. "SWCORE_STEP,timing between the swcore power state machine steps"
line.long 0x38 "EXT_CTRL0,Configures a gpio as a power mode aware control output"
bitfld.long 0x38 14. "LP_EXIT_STATE,output level when exiting the low power state" "0,1"
bitfld.long 0x38 13. "LP_ENTRY_STATE,output level when entering the low power state" "0,1"
newline
bitfld.long 0x38 12. "INIT_STATE" "0,1"
bitfld.long 0x38 8. "INIT" "0,1"
newline
hexmask.long.byte 0x38 0.--5. 1. "GPIO_SELECT,selects from gpio 0->30"
line.long 0x3C "EXT_CTRL1,Configures a gpio as a power mode aware control output"
bitfld.long 0x3C 14. "LP_EXIT_STATE,output level when exiting the low power state" "0,1"
bitfld.long 0x3C 13. "LP_ENTRY_STATE,output level when entering the low power state" "0,1"
newline
bitfld.long 0x3C 12. "INIT_STATE" "0,1"
bitfld.long 0x3C 8. "INIT" "0,1"
newline
hexmask.long.byte 0x3C 0.--5. 1. "GPIO_SELECT,selects from gpio 0->30"
line.long 0x40 "EXT_TIME_REF,Select a GPIO to use as a time reference. the source can be used to drive the low power clock at 32kHz. or to provide a 1ms tick to the timer. or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register."
bitfld.long 0x40 4. "DRIVE_LPCK,Use the selected GPIO to drive the 32kHz low power clock in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0" "0,1"
bitfld.long 0x40 0.--1. "SOURCE_SEL,0 -> gpio12" "0: gpio12,1: gpio20,2: gpio14,3: gpio22"
line.long 0x44 "LPOSC_FREQ_KHZ_INT,Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC."
hexmask.long.byte 0x44 0.--5. 1. "LPOSC_FREQ_KHZ_INT,Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"
line.long 0x48 "LPOSC_FREQ_KHZ_FRAC,Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC."
hexmask.long.word 0x48 0.--15. 1. "LPOSC_FREQ_KHZ_FRAC,Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"
line.long 0x4C "XOSC_FREQ_KHZ_INT,Informs the AON Timer of the integer component of the clock frequency when running off the XOSC."
hexmask.long.word 0x4C 0.--15. 1. "XOSC_FREQ_KHZ_INT,Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"
line.long 0x50 "XOSC_FREQ_KHZ_FRAC,Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC."
hexmask.long.word 0x50 0.--15. 1. "XOSC_FREQ_KHZ_FRAC,Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"
line.long 0x54 "SET_TIME_63TO48"
hexmask.long.word 0x54 0.--15. 1. "SET_TIME_63TO48,For setting the time do not use for reading the time use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"
line.long 0x58 "SET_TIME_47TO32"
hexmask.long.word 0x58 0.--15. 1. "SET_TIME_47TO32,For setting the time do not use for reading the time use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"
line.long 0x5C "SET_TIME_31TO16"
hexmask.long.word 0x5C 0.--15. 1. "SET_TIME_31TO16,For setting the time do not use for reading the time use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"
line.long 0x60 "SET_TIME_15TO0"
hexmask.long.word 0x60 0.--15. 1. "SET_TIME_15TO0,For setting the time do not use for reading the time use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"
rgroup.long 0x70++0x7
line.long 0x0 "READ_TIME_UPPER"
hexmask.long 0x0 0.--31. 1. "READ_TIME_UPPER,For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER then LOWER then re-read UPPER and if it has changed re-read LOWER."
line.long 0x4 "READ_TIME_LOWER"
hexmask.long 0x4 0.--31. 1. "READ_TIME_LOWER,For reading bits 31:0 of the timer."
group.long 0x78++0x23
line.long 0x0 "ALARM_TIME_63TO48"
hexmask.long.word 0x0 0.--15. 1. "ALARM_TIME_63TO48,This field must only be written when POWMAN_ALARM_ENAB=0"
line.long 0x4 "ALARM_TIME_47TO32"
hexmask.long.word 0x4 0.--15. 1. "ALARM_TIME_47TO32,This field must only be written when POWMAN_ALARM_ENAB=0"
line.long 0x8 "ALARM_TIME_31TO16"
hexmask.long.word 0x8 0.--15. 1. "ALARM_TIME_31TO16,This field must only be written when POWMAN_ALARM_ENAB=0"
line.long 0xC "ALARM_TIME_15TO0"
hexmask.long.word 0xC 0.--15. 1. "ALARM_TIME_15TO0,This field must only be written when POWMAN_ALARM_ENAB=0"
line.long 0x10 "TIMER"
rbitfld.long 0x10 19. "USING_GPIO_1HZ,Timer is synchronised to a 1hz gpio source" "0,1"
rbitfld.long 0x10 18. "USING_GPIO_1KHZ,Timer is running from a 1khz gpio source" "0,1"
newline
rbitfld.long 0x10 17. "USING_LPOSC,Timer is running from lposc" "0,1"
rbitfld.long 0x10 16. "USING_XOSC,Timer is running from xosc" "0,1"
newline
bitfld.long 0x10 13. "USE_GPIO_1HZ,Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference." "0,1"
bitfld.long 0x10 10. "USE_GPIO_1KHZ,switch to gpio as the source of the 1kHz timer tick" "0,1"
newline
bitfld.long 0x10 9. "USE_XOSC,switch to xosc as the source of the 1kHz timer tick" "0,1"
bitfld.long 0x10 8. "USE_LPOSC,Switch to lposc as the source of the 1kHz timer tick" "0,1"
newline
eventfld.long 0x10 6. "ALARM,Alarm has fired. Write to 1 to clear the alarm." "0,1"
bitfld.long 0x10 5. "PWRUP_ON_ALARM,Alarm wakes the chip from low power mode" "0,1"
newline
bitfld.long 0x10 4. "ALARM_ENAB,Enables the alarm. The alarm must be disabled while writing the alarm time." "0,1"
bitfld.long 0x10 2. "CLEAR,Clears the timer does not disable the timer and does not affect the alarm. This control can be written at any time." "0,1"
newline
bitfld.long 0x10 1. "RUN,Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting." "0,1"
bitfld.long 0x10 0. "NONSEC_WRITE,Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure." "0,1"
line.long 0x14 "PWRUP0,4 GPIO powerup events can be configured to wake the chip up from a low power state."
rbitfld.long 0x14 10. "RAW_STATUS,Value of selected gpio pin (only if enable == 1)" "0,1"
eventfld.long 0x14 9. "STATUS,Status of gpio wakeup. Write to 1 to clear a latched edge detect." "0,1"
newline
bitfld.long 0x14 8. "MODE,Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register." "0,1"
bitfld.long 0x14 7. "DIRECTION" "0,1"
newline
bitfld.long 0x14 6. "ENABLE,Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event." "0,1"
hexmask.long.byte 0x14 0.--5. 1. "SOURCE"
line.long 0x18 "PWRUP1,4 GPIO powerup events can be configured to wake the chip up from a low power state."
rbitfld.long 0x18 10. "RAW_STATUS,Value of selected gpio pin (only if enable == 1)" "0,1"
eventfld.long 0x18 9. "STATUS,Status of gpio wakeup. Write to 1 to clear a latched edge detect." "0,1"
newline
bitfld.long 0x18 8. "MODE,Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register." "0,1"
bitfld.long 0x18 7. "DIRECTION" "0,1"
newline
bitfld.long 0x18 6. "ENABLE,Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event." "0,1"
hexmask.long.byte 0x18 0.--5. 1. "SOURCE"
line.long 0x1C "PWRUP2,4 GPIO powerup events can be configured to wake the chip up from a low power state."
rbitfld.long 0x1C 10. "RAW_STATUS,Value of selected gpio pin (only if enable == 1)" "0,1"
eventfld.long 0x1C 9. "STATUS,Status of gpio wakeup. Write to 1 to clear a latched edge detect." "0,1"
newline
bitfld.long 0x1C 8. "MODE,Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register." "0,1"
bitfld.long 0x1C 7. "DIRECTION" "0,1"
newline
bitfld.long 0x1C 6. "ENABLE,Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event." "0,1"
hexmask.long.byte 0x1C 0.--5. 1. "SOURCE"
line.long 0x20 "PWRUP3,4 GPIO powerup events can be configured to wake the chip up from a low power state."
rbitfld.long 0x20 10. "RAW_STATUS,Value of selected gpio pin (only if enable == 1)" "0,1"
eventfld.long 0x20 9. "STATUS,Status of gpio wakeup. Write to 1 to clear a latched edge detect." "0,1"
newline
bitfld.long 0x20 8. "MODE,Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register." "0,1"
bitfld.long 0x20 7. "DIRECTION" "0,1"
newline
bitfld.long 0x20 6. "ENABLE,Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event." "0,1"
hexmask.long.byte 0x20 0.--5. 1. "SOURCE"
rgroup.long 0x9C++0x7
line.long 0x0 "CURRENT_PWRUP_REQ,Indicates current powerup request state"
hexmask.long.byte 0x0 0.--6. 1. "CURRENT_PWRUP_REQ"
line.long 0x4 "LAST_SWCORE_PWRUP,Indicates which pwrup source triggered the last switched-core power up"
hexmask.long.byte 0x4 0.--6. 1. "LAST_SWCORE_PWRUP"
group.long 0xA4++0x47
line.long 0x0 "DBG_PWRCFG"
bitfld.long 0x0 0. "IGNORE,Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req" "0,1"
line.long 0x4 "BOOTDIS,Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up)."
bitfld.long 0x4 1. "NEXT,This flag always ORs writes into its current contents. It can be set but not cleared by software." "0,1"
eventfld.long 0x4 0. "NOW,When powman resets the RSM the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW and BOOTDIS_NEXT is cleared." "0,1"
line.long 0x8 "DBGCONFIG"
hexmask.long.byte 0x8 0.--3. 1. "DP_INSTID,Configure DP instance ID for SWD multidrop selection."
line.long 0xC "SCRATCH0,Scratch register. Information persists in low power mode"
hexmask.long 0xC 0.--31. 1. "SCRATCH0"
line.long 0x10 "SCRATCH1,Scratch register. Information persists in low power mode"
hexmask.long 0x10 0.--31. 1. "SCRATCH1"
line.long 0x14 "SCRATCH2,Scratch register. Information persists in low power mode"
hexmask.long 0x14 0.--31. 1. "SCRATCH2"
line.long 0x18 "SCRATCH3,Scratch register. Information persists in low power mode"
hexmask.long 0x18 0.--31. 1. "SCRATCH3"
line.long 0x1C "SCRATCH4,Scratch register. Information persists in low power mode"
hexmask.long 0x1C 0.--31. 1. "SCRATCH4"
line.long 0x20 "SCRATCH5,Scratch register. Information persists in low power mode"
hexmask.long 0x20 0.--31. 1. "SCRATCH5"
line.long 0x24 "SCRATCH6,Scratch register. Information persists in low power mode"
hexmask.long 0x24 0.--31. 1. "SCRATCH6"
line.long 0x28 "SCRATCH7,Scratch register. Information persists in low power mode"
hexmask.long 0x28 0.--31. 1. "SCRATCH7"
line.long 0x2C "BOOT0,Scratch register. Information persists in low power mode"
hexmask.long 0x2C 0.--31. 1. "BOOT0"
line.long 0x30 "BOOT1,Scratch register. Information persists in low power mode"
hexmask.long 0x30 0.--31. 1. "BOOT1"
line.long 0x34 "BOOT2,Scratch register. Information persists in low power mode"
hexmask.long 0x34 0.--31. 1. "BOOT2"
line.long 0x38 "BOOT3,Scratch register. Information persists in low power mode"
hexmask.long 0x38 0.--31. 1. "BOOT3"
line.long 0x3C "INTR,Raw Interrupts"
rbitfld.long 0x3C 3. "PWRUP_WHILE_WAITING,Source is state.pwrup_while_waiting" "0,1"
rbitfld.long 0x3C 2. "STATE_REQ_IGNORED,Source is state.req_ignored" "0,1"
newline
rbitfld.long 0x3C 1. "TIMER" "0,1"
eventfld.long 0x3C 0. "VREG_OUTPUT_LOW" "0,1"
line.long 0x40 "INTE,Interrupt Enable"
bitfld.long 0x40 3. "PWRUP_WHILE_WAITING,Source is state.pwrup_while_waiting" "0,1"
bitfld.long 0x40 2. "STATE_REQ_IGNORED,Source is state.req_ignored" "0,1"
newline
bitfld.long 0x40 1. "TIMER" "0,1"
bitfld.long 0x40 0. "VREG_OUTPUT_LOW" "0,1"
line.long 0x44 "INTF,Interrupt Force"
bitfld.long 0x44 3. "PWRUP_WHILE_WAITING,Source is state.pwrup_while_waiting" "0,1"
bitfld.long 0x44 2. "STATE_REQ_IGNORED,Source is state.req_ignored" "0,1"
newline
bitfld.long 0x44 1. "TIMER" "0,1"
bitfld.long 0x44 0. "VREG_OUTPUT_LOW" "0,1"
rgroup.long 0xEC++0x3
line.long 0x0 "INTS,Interrupt status after masking & forcing"
bitfld.long 0x0 3. "PWRUP_WHILE_WAITING,Source is state.pwrup_while_waiting" "0,1"
bitfld.long 0x0 2. "STATE_REQ_IGNORED,Source is state.req_ignored" "0,1"
newline
bitfld.long 0x0 1. "TIMER" "0,1"
bitfld.long 0x0 0. "VREG_OUTPUT_LOW" "0,1"
tree.end
tree "PSM (Power-on State Machine)"
base ad:0x40018000
group.long 0x0++0xB
line.long 0x0 "FRCE_ON,Force block out of reset (i.e. power it on)"
bitfld.long 0x0 24. "PROC1" "0,1"
bitfld.long 0x0 23. "PROC0" "0,1"
bitfld.long 0x0 22. "ACCESSCTRL" "0,1"
bitfld.long 0x0 21. "SIO" "0,1"
bitfld.long 0x0 20. "XIP" "0,1"
bitfld.long 0x0 19. "SRAM9" "0,1"
bitfld.long 0x0 18. "SRAM8" "0,1"
bitfld.long 0x0 17. "SRAM7" "0,1"
bitfld.long 0x0 16. "SRAM6" "0,1"
bitfld.long 0x0 15. "SRAM5" "0,1"
newline
bitfld.long 0x0 14. "SRAM4" "0,1"
bitfld.long 0x0 13. "SRAM3" "0,1"
bitfld.long 0x0 12. "SRAM2" "0,1"
bitfld.long 0x0 11. "SRAM1" "0,1"
bitfld.long 0x0 10. "SRAM0" "0,1"
bitfld.long 0x0 9. "BOOTRAM" "0,1"
bitfld.long 0x0 8. "ROM" "0,1"
bitfld.long 0x0 7. "BUSFABRIC" "0,1"
bitfld.long 0x0 6. "PSM_READY" "0,1"
bitfld.long 0x0 5. "CLOCKS" "0,1"
newline
bitfld.long 0x0 4. "RESETS" "0,1"
bitfld.long 0x0 3. "XOSC" "0,1"
bitfld.long 0x0 2. "ROSC" "0,1"
bitfld.long 0x0 1. "OTP" "0,1"
bitfld.long 0x0 0. "PROC_COLD" "0,1"
line.long 0x4 "FRCE_OFF,Force into reset (i.e. power it off)"
bitfld.long 0x4 24. "PROC1" "0,1"
bitfld.long 0x4 23. "PROC0" "0,1"
bitfld.long 0x4 22. "ACCESSCTRL" "0,1"
bitfld.long 0x4 21. "SIO" "0,1"
bitfld.long 0x4 20. "XIP" "0,1"
bitfld.long 0x4 19. "SRAM9" "0,1"
bitfld.long 0x4 18. "SRAM8" "0,1"
bitfld.long 0x4 17. "SRAM7" "0,1"
bitfld.long 0x4 16. "SRAM6" "0,1"
bitfld.long 0x4 15. "SRAM5" "0,1"
newline
bitfld.long 0x4 14. "SRAM4" "0,1"
bitfld.long 0x4 13. "SRAM3" "0,1"
bitfld.long 0x4 12. "SRAM2" "0,1"
bitfld.long 0x4 11. "SRAM1" "0,1"
bitfld.long 0x4 10. "SRAM0" "0,1"
bitfld.long 0x4 9. "BOOTRAM" "0,1"
bitfld.long 0x4 8. "ROM" "0,1"
bitfld.long 0x4 7. "BUSFABRIC" "0,1"
bitfld.long 0x4 6. "PSM_READY" "0,1"
bitfld.long 0x4 5. "CLOCKS" "0,1"
newline
bitfld.long 0x4 4. "RESETS" "0,1"
bitfld.long 0x4 3. "XOSC" "0,1"
bitfld.long 0x4 2. "ROSC" "0,1"
bitfld.long 0x4 1. "OTP" "0,1"
bitfld.long 0x4 0. "PROC_COLD" "0,1"
line.long 0x8 "WDSEL,Set to 1 if the watchdog should reset this"
bitfld.long 0x8 24. "PROC1" "0,1"
bitfld.long 0x8 23. "PROC0" "0,1"
bitfld.long 0x8 22. "ACCESSCTRL" "0,1"
bitfld.long 0x8 21. "SIO" "0,1"
bitfld.long 0x8 20. "XIP" "0,1"
bitfld.long 0x8 19. "SRAM9" "0,1"
bitfld.long 0x8 18. "SRAM8" "0,1"
bitfld.long 0x8 17. "SRAM7" "0,1"
bitfld.long 0x8 16. "SRAM6" "0,1"
bitfld.long 0x8 15. "SRAM5" "0,1"
newline
bitfld.long 0x8 14. "SRAM4" "0,1"
bitfld.long 0x8 13. "SRAM3" "0,1"
bitfld.long 0x8 12. "SRAM2" "0,1"
bitfld.long 0x8 11. "SRAM1" "0,1"
bitfld.long 0x8 10. "SRAM0" "0,1"
bitfld.long 0x8 9. "BOOTRAM" "0,1"
bitfld.long 0x8 8. "ROM" "0,1"
bitfld.long 0x8 7. "BUSFABRIC" "0,1"
bitfld.long 0x8 6. "PSM_READY" "0,1"
bitfld.long 0x8 5. "CLOCKS" "0,1"
newline
bitfld.long 0x8 4. "RESETS" "0,1"
bitfld.long 0x8 3. "XOSC" "0,1"
bitfld.long 0x8 2. "ROSC" "0,1"
bitfld.long 0x8 1. "OTP" "0,1"
bitfld.long 0x8 0. "PROC_COLD" "0,1"
rgroup.long 0xC++0x3
line.long 0x0 "DONE,Is the subsystem ready?"
bitfld.long 0x0 24. "PROC1" "0,1"
bitfld.long 0x0 23. "PROC0" "0,1"
bitfld.long 0x0 22. "ACCESSCTRL" "0,1"
bitfld.long 0x0 21. "SIO" "0,1"
bitfld.long 0x0 20. "XIP" "0,1"
bitfld.long 0x0 19. "SRAM9" "0,1"
bitfld.long 0x0 18. "SRAM8" "0,1"
bitfld.long 0x0 17. "SRAM7" "0,1"
bitfld.long 0x0 16. "SRAM6" "0,1"
bitfld.long 0x0 15. "SRAM5" "0,1"
newline
bitfld.long 0x0 14. "SRAM4" "0,1"
bitfld.long 0x0 13. "SRAM3" "0,1"
bitfld.long 0x0 12. "SRAM2" "0,1"
bitfld.long 0x0 11. "SRAM1" "0,1"
bitfld.long 0x0 10. "SRAM0" "0,1"
bitfld.long 0x0 9. "BOOTRAM" "0,1"
bitfld.long 0x0 8. "ROM" "0,1"
bitfld.long 0x0 7. "BUSFABRIC" "0,1"
bitfld.long 0x0 6. "PSM_READY" "0,1"
bitfld.long 0x0 5. "CLOCKS" "0,1"
newline
bitfld.long 0x0 4. "RESETS" "0,1"
bitfld.long 0x0 3. "XOSC" "0,1"
bitfld.long 0x0 2. "ROSC" "0,1"
bitfld.long 0x0 1. "OTP" "0,1"
bitfld.long 0x0 0. "PROC_COLD" "0,1"
tree.end
tree "PWM (Pulse-Width Modulator)"
base ad:0x400A8000
group.long 0x0++0xFF
line.long 0x0 "CH0_CSR,Control and status register"
bitfld.long 0x0 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x0 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x0 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0x0 3. "B_INV,Invert output B" "0,1"
bitfld.long 0x0 2. "A_INV,Invert output A" "0,1"
bitfld.long 0x0 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0x0 0. "EN,Enable the PWM channel." "0,1"
line.long 0x4 "CH0_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0x4 4.--11. 1. "INT"
hexmask.long.byte 0x4 0.--3. 1. "FRAC"
line.long 0x8 "CH0_CTR,Direct access to the PWM counter"
hexmask.long.word 0x8 0.--15. 1. "CH0_CTR"
line.long 0xC "CH0_CC,Counter compare values"
hexmask.long.word 0xC 16.--31. 1. "B"
hexmask.long.word 0xC 0.--15. 1. "A"
line.long 0x10 "CH0_TOP,Counter wrap value"
hexmask.long.word 0x10 0.--15. 1. "CH0_TOP"
line.long 0x14 "CH1_CSR,Control and status register"
bitfld.long 0x14 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x14 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x14 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0x14 3. "B_INV,Invert output B" "0,1"
bitfld.long 0x14 2. "A_INV,Invert output A" "0,1"
bitfld.long 0x14 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0x14 0. "EN,Enable the PWM channel." "0,1"
line.long 0x18 "CH1_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0x18 4.--11. 1. "INT"
hexmask.long.byte 0x18 0.--3. 1. "FRAC"
line.long 0x1C "CH1_CTR,Direct access to the PWM counter"
hexmask.long.word 0x1C 0.--15. 1. "CH1_CTR"
line.long 0x20 "CH1_CC,Counter compare values"
hexmask.long.word 0x20 16.--31. 1. "B"
hexmask.long.word 0x20 0.--15. 1. "A"
line.long 0x24 "CH1_TOP,Counter wrap value"
hexmask.long.word 0x24 0.--15. 1. "CH1_TOP"
line.long 0x28 "CH2_CSR,Control and status register"
bitfld.long 0x28 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x28 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x28 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0x28 3. "B_INV,Invert output B" "0,1"
bitfld.long 0x28 2. "A_INV,Invert output A" "0,1"
bitfld.long 0x28 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0x28 0. "EN,Enable the PWM channel." "0,1"
line.long 0x2C "CH2_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0x2C 4.--11. 1. "INT"
hexmask.long.byte 0x2C 0.--3. 1. "FRAC"
line.long 0x30 "CH2_CTR,Direct access to the PWM counter"
hexmask.long.word 0x30 0.--15. 1. "CH2_CTR"
line.long 0x34 "CH2_CC,Counter compare values"
hexmask.long.word 0x34 16.--31. 1. "B"
hexmask.long.word 0x34 0.--15. 1. "A"
line.long 0x38 "CH2_TOP,Counter wrap value"
hexmask.long.word 0x38 0.--15. 1. "CH2_TOP"
line.long 0x3C "CH3_CSR,Control and status register"
bitfld.long 0x3C 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x3C 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x3C 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0x3C 3. "B_INV,Invert output B" "0,1"
bitfld.long 0x3C 2. "A_INV,Invert output A" "0,1"
bitfld.long 0x3C 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0x3C 0. "EN,Enable the PWM channel." "0,1"
line.long 0x40 "CH3_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0x40 4.--11. 1. "INT"
hexmask.long.byte 0x40 0.--3. 1. "FRAC"
line.long 0x44 "CH3_CTR,Direct access to the PWM counter"
hexmask.long.word 0x44 0.--15. 1. "CH3_CTR"
line.long 0x48 "CH3_CC,Counter compare values"
hexmask.long.word 0x48 16.--31. 1. "B"
hexmask.long.word 0x48 0.--15. 1. "A"
line.long 0x4C "CH3_TOP,Counter wrap value"
hexmask.long.word 0x4C 0.--15. 1. "CH3_TOP"
line.long 0x50 "CH4_CSR,Control and status register"
bitfld.long 0x50 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x50 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x50 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0x50 3. "B_INV,Invert output B" "0,1"
bitfld.long 0x50 2. "A_INV,Invert output A" "0,1"
bitfld.long 0x50 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0x50 0. "EN,Enable the PWM channel." "0,1"
line.long 0x54 "CH4_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0x54 4.--11. 1. "INT"
hexmask.long.byte 0x54 0.--3. 1. "FRAC"
line.long 0x58 "CH4_CTR,Direct access to the PWM counter"
hexmask.long.word 0x58 0.--15. 1. "CH4_CTR"
line.long 0x5C "CH4_CC,Counter compare values"
hexmask.long.word 0x5C 16.--31. 1. "B"
hexmask.long.word 0x5C 0.--15. 1. "A"
line.long 0x60 "CH4_TOP,Counter wrap value"
hexmask.long.word 0x60 0.--15. 1. "CH4_TOP"
line.long 0x64 "CH5_CSR,Control and status register"
bitfld.long 0x64 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x64 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x64 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0x64 3. "B_INV,Invert output B" "0,1"
bitfld.long 0x64 2. "A_INV,Invert output A" "0,1"
bitfld.long 0x64 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0x64 0. "EN,Enable the PWM channel." "0,1"
line.long 0x68 "CH5_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0x68 4.--11. 1. "INT"
hexmask.long.byte 0x68 0.--3. 1. "FRAC"
line.long 0x6C "CH5_CTR,Direct access to the PWM counter"
hexmask.long.word 0x6C 0.--15. 1. "CH5_CTR"
line.long 0x70 "CH5_CC,Counter compare values"
hexmask.long.word 0x70 16.--31. 1. "B"
hexmask.long.word 0x70 0.--15. 1. "A"
line.long 0x74 "CH5_TOP,Counter wrap value"
hexmask.long.word 0x74 0.--15. 1. "CH5_TOP"
line.long 0x78 "CH6_CSR,Control and status register"
bitfld.long 0x78 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x78 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x78 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0x78 3. "B_INV,Invert output B" "0,1"
bitfld.long 0x78 2. "A_INV,Invert output A" "0,1"
bitfld.long 0x78 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0x78 0. "EN,Enable the PWM channel." "0,1"
line.long 0x7C "CH6_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0x7C 4.--11. 1. "INT"
hexmask.long.byte 0x7C 0.--3. 1. "FRAC"
line.long 0x80 "CH6_CTR,Direct access to the PWM counter"
hexmask.long.word 0x80 0.--15. 1. "CH6_CTR"
line.long 0x84 "CH6_CC,Counter compare values"
hexmask.long.word 0x84 16.--31. 1. "B"
hexmask.long.word 0x84 0.--15. 1. "A"
line.long 0x88 "CH6_TOP,Counter wrap value"
hexmask.long.word 0x88 0.--15. 1. "CH6_TOP"
line.long 0x8C "CH7_CSR,Control and status register"
bitfld.long 0x8C 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x8C 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0x8C 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0x8C 3. "B_INV,Invert output B" "0,1"
bitfld.long 0x8C 2. "A_INV,Invert output A" "0,1"
bitfld.long 0x8C 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0x8C 0. "EN,Enable the PWM channel." "0,1"
line.long 0x90 "CH7_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0x90 4.--11. 1. "INT"
hexmask.long.byte 0x90 0.--3. 1. "FRAC"
line.long 0x94 "CH7_CTR,Direct access to the PWM counter"
hexmask.long.word 0x94 0.--15. 1. "CH7_CTR"
line.long 0x98 "CH7_CC,Counter compare values"
hexmask.long.word 0x98 16.--31. 1. "B"
hexmask.long.word 0x98 0.--15. 1. "A"
line.long 0x9C "CH7_TOP,Counter wrap value"
hexmask.long.word 0x9C 0.--15. 1. "CH7_TOP"
line.long 0xA0 "CH8_CSR,Control and status register"
bitfld.long 0xA0 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0xA0 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0xA0 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0xA0 3. "B_INV,Invert output B" "0,1"
bitfld.long 0xA0 2. "A_INV,Invert output A" "0,1"
bitfld.long 0xA0 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0xA0 0. "EN,Enable the PWM channel." "0,1"
line.long 0xA4 "CH8_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0xA4 4.--11. 1. "INT"
hexmask.long.byte 0xA4 0.--3. 1. "FRAC"
line.long 0xA8 "CH8_CTR,Direct access to the PWM counter"
hexmask.long.word 0xA8 0.--15. 1. "CH8_CTR"
line.long 0xAC "CH8_CC,Counter compare values"
hexmask.long.word 0xAC 16.--31. 1. "B"
hexmask.long.word 0xAC 0.--15. 1. "A"
line.long 0xB0 "CH8_TOP,Counter wrap value"
hexmask.long.word 0xB0 0.--15. 1. "CH8_TOP"
line.long 0xB4 "CH9_CSR,Control and status register"
bitfld.long 0xB4 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0xB4 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0xB4 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0xB4 3. "B_INV,Invert output B" "0,1"
bitfld.long 0xB4 2. "A_INV,Invert output A" "0,1"
bitfld.long 0xB4 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0xB4 0. "EN,Enable the PWM channel." "0,1"
line.long 0xB8 "CH9_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0xB8 4.--11. 1. "INT"
hexmask.long.byte 0xB8 0.--3. 1. "FRAC"
line.long 0xBC "CH9_CTR,Direct access to the PWM counter"
hexmask.long.word 0xBC 0.--15. 1. "CH9_CTR"
line.long 0xC0 "CH9_CC,Counter compare values"
hexmask.long.word 0xC0 16.--31. 1. "B"
hexmask.long.word 0xC0 0.--15. 1. "A"
line.long 0xC4 "CH9_TOP,Counter wrap value"
hexmask.long.word 0xC4 0.--15. 1. "CH9_TOP"
line.long 0xC8 "CH10_CSR,Control and status register"
bitfld.long 0xC8 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0xC8 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0xC8 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0xC8 3. "B_INV,Invert output B" "0,1"
bitfld.long 0xC8 2. "A_INV,Invert output A" "0,1"
bitfld.long 0xC8 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0xC8 0. "EN,Enable the PWM channel." "0,1"
line.long 0xCC "CH10_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0xCC 4.--11. 1. "INT"
hexmask.long.byte 0xCC 0.--3. 1. "FRAC"
line.long 0xD0 "CH10_CTR,Direct access to the PWM counter"
hexmask.long.word 0xD0 0.--15. 1. "CH10_CTR"
line.long 0xD4 "CH10_CC,Counter compare values"
hexmask.long.word 0xD4 16.--31. 1. "B"
hexmask.long.word 0xD4 0.--15. 1. "A"
line.long 0xD8 "CH10_TOP,Counter wrap value"
hexmask.long.word 0xD8 0.--15. 1. "CH10_TOP"
line.long 0xDC "CH11_CSR,Control and status register"
bitfld.long 0xDC 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0xDC 6. "PH_RET,Retard the phase of the counter by 1 count while it is running." "0,1"
bitfld.long 0xDC 4.--5. "DIVMODE" "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the PWM..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of the.."
newline
bitfld.long 0xDC 3. "B_INV,Invert output B" "0,1"
bitfld.long 0xDC 2. "A_INV,Invert output A" "0,1"
bitfld.long 0xDC 1. "PH_CORRECT,1: Enable phase-correct modulation. 0: Trailing-edge" "0: Trailing-edge,1: Enable phase-correct modulation"
newline
bitfld.long 0xDC 0. "EN,Enable the PWM channel." "0,1"
line.long 0xE0 "CH11_DIV,INT and FRAC form a fixed-point fractional number."
hexmask.long.byte 0xE0 4.--11. 1. "INT"
hexmask.long.byte 0xE0 0.--3. 1. "FRAC"
line.long 0xE4 "CH11_CTR,Direct access to the PWM counter"
hexmask.long.word 0xE4 0.--15. 1. "CH11_CTR"
line.long 0xE8 "CH11_CC,Counter compare values"
hexmask.long.word 0xE8 16.--31. 1. "B"
hexmask.long.word 0xE8 0.--15. 1. "A"
line.long 0xEC "CH11_TOP,Counter wrap value"
hexmask.long.word 0xEC 0.--15. 1. "CH11_TOP"
line.long 0xF0 "EN,This register aliases the CSR_EN bits for all channels."
bitfld.long 0xF0 11. "CH11" "0,1"
bitfld.long 0xF0 10. "CH10" "0,1"
bitfld.long 0xF0 9. "CH9" "0,1"
newline
bitfld.long 0xF0 8. "CH8" "0,1"
bitfld.long 0xF0 7. "CH7" "0,1"
bitfld.long 0xF0 6. "CH6" "0,1"
newline
bitfld.long 0xF0 5. "CH5" "0,1"
bitfld.long 0xF0 4. "CH4" "0,1"
bitfld.long 0xF0 3. "CH3" "0,1"
newline
bitfld.long 0xF0 2. "CH2" "0,1"
bitfld.long 0xF0 1. "CH1" "0,1"
bitfld.long 0xF0 0. "CH0" "0,1"
line.long 0xF4 "INTR,Raw Interrupts"
eventfld.long 0xF4 11. "CH11" "0,1"
eventfld.long 0xF4 10. "CH10" "0,1"
eventfld.long 0xF4 9. "CH9" "0,1"
newline
eventfld.long 0xF4 8. "CH8" "0,1"
eventfld.long 0xF4 7. "CH7" "0,1"
eventfld.long 0xF4 6. "CH6" "0,1"
newline
eventfld.long 0xF4 5. "CH5" "0,1"
eventfld.long 0xF4 4. "CH4" "0,1"
eventfld.long 0xF4 3. "CH3" "0,1"
newline
eventfld.long 0xF4 2. "CH2" "0,1"
eventfld.long 0xF4 1. "CH1" "0,1"
eventfld.long 0xF4 0. "CH0" "0,1"
line.long 0xF8 "IRQ0_INTE,Interrupt Enable for irq0"
bitfld.long 0xF8 11. "CH11" "0,1"
bitfld.long 0xF8 10. "CH10" "0,1"
bitfld.long 0xF8 9. "CH9" "0,1"
newline
bitfld.long 0xF8 8. "CH8" "0,1"
bitfld.long 0xF8 7. "CH7" "0,1"
bitfld.long 0xF8 6. "CH6" "0,1"
newline
bitfld.long 0xF8 5. "CH5" "0,1"
bitfld.long 0xF8 4. "CH4" "0,1"
bitfld.long 0xF8 3. "CH3" "0,1"
newline
bitfld.long 0xF8 2. "CH2" "0,1"
bitfld.long 0xF8 1. "CH1" "0,1"
bitfld.long 0xF8 0. "CH0" "0,1"
line.long 0xFC "IRQ0_INTF,Interrupt Force for irq0"
bitfld.long 0xFC 11. "CH11" "0,1"
bitfld.long 0xFC 10. "CH10" "0,1"
bitfld.long 0xFC 9. "CH9" "0,1"
newline
bitfld.long 0xFC 8. "CH8" "0,1"
bitfld.long 0xFC 7. "CH7" "0,1"
bitfld.long 0xFC 6. "CH6" "0,1"
newline
bitfld.long 0xFC 5. "CH5" "0,1"
bitfld.long 0xFC 4. "CH4" "0,1"
bitfld.long 0xFC 3. "CH3" "0,1"
newline
bitfld.long 0xFC 2. "CH2" "0,1"
bitfld.long 0xFC 1. "CH1" "0,1"
bitfld.long 0xFC 0. "CH0" "0,1"
rgroup.long 0x100++0x3
line.long 0x0 "IRQ0_INTS,Interrupt status after masking & forcing for irq0"
bitfld.long 0x0 11. "CH11" "0,1"
bitfld.long 0x0 10. "CH10" "0,1"
bitfld.long 0x0 9. "CH9" "0,1"
newline
bitfld.long 0x0 8. "CH8" "0,1"
bitfld.long 0x0 7. "CH7" "0,1"
bitfld.long 0x0 6. "CH6" "0,1"
newline
bitfld.long 0x0 5. "CH5" "0,1"
bitfld.long 0x0 4. "CH4" "0,1"
bitfld.long 0x0 3. "CH3" "0,1"
newline
bitfld.long 0x0 2. "CH2" "0,1"
bitfld.long 0x0 1. "CH1" "0,1"
bitfld.long 0x0 0. "CH0" "0,1"
group.long 0x104++0x7
line.long 0x0 "IRQ1_INTE,Interrupt Enable for irq1"
bitfld.long 0x0 11. "CH11" "0,1"
bitfld.long 0x0 10. "CH10" "0,1"
bitfld.long 0x0 9. "CH9" "0,1"
newline
bitfld.long 0x0 8. "CH8" "0,1"
bitfld.long 0x0 7. "CH7" "0,1"
bitfld.long 0x0 6. "CH6" "0,1"
newline
bitfld.long 0x0 5. "CH5" "0,1"
bitfld.long 0x0 4. "CH4" "0,1"
bitfld.long 0x0 3. "CH3" "0,1"
newline
bitfld.long 0x0 2. "CH2" "0,1"
bitfld.long 0x0 1. "CH1" "0,1"
bitfld.long 0x0 0. "CH0" "0,1"
line.long 0x4 "IRQ1_INTF,Interrupt Force for irq1"
bitfld.long 0x4 11. "CH11" "0,1"
bitfld.long 0x4 10. "CH10" "0,1"
bitfld.long 0x4 9. "CH9" "0,1"
newline
bitfld.long 0x4 8. "CH8" "0,1"
bitfld.long 0x4 7. "CH7" "0,1"
bitfld.long 0x4 6. "CH6" "0,1"
newline
bitfld.long 0x4 5. "CH5" "0,1"
bitfld.long 0x4 4. "CH4" "0,1"
bitfld.long 0x4 3. "CH3" "0,1"
newline
bitfld.long 0x4 2. "CH2" "0,1"
bitfld.long 0x4 1. "CH1" "0,1"
bitfld.long 0x4 0. "CH0" "0,1"
rgroup.long 0x10C++0x3
line.long 0x0 "IRQ1_INTS,Interrupt status after masking & forcing for irq1"
bitfld.long 0x0 11. "CH11" "0,1"
bitfld.long 0x0 10. "CH10" "0,1"
bitfld.long 0x0 9. "CH9" "0,1"
newline
bitfld.long 0x0 8. "CH8" "0,1"
bitfld.long 0x0 7. "CH7" "0,1"
bitfld.long 0x0 6. "CH6" "0,1"
newline
bitfld.long 0x0 5. "CH5" "0,1"
bitfld.long 0x0 4. "CH4" "0,1"
bitfld.long 0x0 3. "CH3" "0,1"
newline
bitfld.long 0x0 2. "CH2" "0,1"
bitfld.long 0x0 1. "CH1" "0,1"
bitfld.long 0x0 0. "CH0" "0,1"
tree.end
tree "QMI (QSPI Memory Interface)"
base ad:0x400D0000
group.long 0x0++0x3
line.long 0x0 "DIRECT_CSR,Control and status for direct serial mode"
bitfld.long 0x0 30.--31. "RXDELAY,Delay the read data sample timing in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)" "0,1,2,3"
hexmask.long.byte 0x0 22.--29. 1. "CLKDIV,Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly and the maximum divisor of 256 is encoded by a value of CLKDIV=0."
rbitfld.long 0x0 18.--20. "RXLEVEL,Current level of DIRECT_RX FIFO" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "RXFULL,When 1 the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full." "0,1"
rbitfld.long 0x0 16. "RXEMPTY,When 1 the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data the FIFO state is not affected but the value returned to the processor is undefined." "0,1"
rbitfld.long 0x0 12.--14. "TXLEVEL,Current level of DIRECT_TX FIFO" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 11. "TXEMPTY,When 1 the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data transmission will stop and BUSY will go low once the current 8-bit serial frame completes." "0,1"
rbitfld.long 0x0 10. "TXFULL,When 1 the DIRECT_TX FIFO is currently full. If the processor tries to write more data that data will be ignored." "0,1"
bitfld.long 0x0 7. "AUTO_CS1N,When 1 automatically assert the CS1n chip select line whenever the BUSY flag is set." "0,1"
newline
bitfld.long 0x0 6. "AUTO_CS0N,When 1 automatically assert the CS0n chip select line whenever the BUSY flag is set." "0,1"
bitfld.long 0x0 3. "ASSERT_CS1N,When 1 assert (i.e. drive low) the CS1n chip select line." "0,1"
bitfld.long 0x0 2. "ASSERT_CS0N,When 1 assert (i.e. drive low) the CS0n chip select line." "0,1"
newline
rbitfld.long 0x0 1. "BUSY,Direct mode busy flag. If 1 data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO) and the chip select must not yet be deasserted." "0,1"
bitfld.long 0x0 0. "EN,Enable direct mode." "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "DIRECT_TX,Transmit FIFO for direct mode"
bitfld.long 0x0 20. "NOPUSH,Inhibit the RX FIFO push that would correspond to this TX FIFO entry." "0,1"
bitfld.long 0x0 19. "OE,Output enable (active-high). For single width (SPI) this field is ignored and SD0 is always set to output with SD1 always set to input." "0,1"
bitfld.long 0x0 18. "DWIDTH,Data width. If 0 hardware will transmit the 8 LSBs of the DIRECT_TX DATA field and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1 the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely." "0,1"
newline
bitfld.long 0x0 16.--17. "IWIDTH,Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely." "0: Single width,1: Dual width,2: Quad width,?"
hexmask.long.word 0x0 0.--15. 1. "DATA,Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK if this is the first pulse). For each byte clocked out the interface will simultaneously sample one byte on rising edges of SCK and push this.."
rgroup.long 0x8++0x3
line.long 0x0 "DIRECT_RX,Receive FIFO for direct mode"
hexmask.long.word 0x0 0.--15. 1. "DIRECT_RX,With each byte clocked out on the serial interface one byte will simultaneously be clocked in and will appear in this FIFO. The serial interface will stall when this FIFO is full to avoid dropping data."
group.long 0xC++0x47
line.long 0x0 "M0_TIMING,Timing configuration register for memory address window 0."
bitfld.long 0x0 30.--31. "COOLDOWN,Chip select cooldown period. When a memory transfer finishes the chip select remains asserted for 64 x COOLDOWN system clock cycles plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires the chip select.." "0,1,2,3"
bitfld.long 0x0 28.--29. "PAGEBREAK,When page break is enabled chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst even if the address of the next access follows in.." "0: No page boundary is enforced,1: Break bursts crossing a 256-byte page boundary,2: Break bursts crossing a 1024-byte quad-page..,3: Break bursts crossing a 4096-byte sector boundary"
bitfld.long 0x0 25. "SELECT_SETUP,Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK." "0,1"
newline
bitfld.long 0x0 23.--24. "SELECT_HOLD,Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select." "0,1,2,3"
hexmask.long.byte 0x0 17.--22. 1. "MAX_SELECT,Enforce a maximum assertion duration for this window's chip select in units of 64 system clock cycles. If 0 the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN)."
hexmask.long.byte 0x0 12.--16. 1. "MIN_DESELECT,After this window's chip select is deasserted it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles) plus MIN_DESELECT additional system clock cycles before the QMI reasserts either chip.."
newline
bitfld.long 0x0 8.--10. "RXDELAY,Delay the read data sample timing in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched.." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--7. 1. "CLKDIV,Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly and a divisor of 256 is encoded with a value of CLKDIV=0."
line.long 0x4 "M0_RFMT,Read transfer format configuration for memory address window 0."
bitfld.long 0x4 28. "DTR,Enable double transfer rate (DTR) for read commands: address suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge and SDI data is captured on the SCK edge that follows its launch." "0,1"
bitfld.long 0x4 16.--18. "DUMMY_LEN,Length of dummy phase between command suffix and data phase in units of 4 bits. (i.e. 1 cycle for quad width 2 for dual 4 for single)" "0: No dummy phase,1: 4 dummy bits,2: 8 dummy bits,3: 12 dummy bits,4: 16 dummy bits,5: 20 dummy bits,6: 24 dummy bits,7: 28 dummy bits"
bitfld.long 0x4 14.--15. "SUFFIX_LEN,Length of post-address command suffix in units of 4 bits. (i.e. 1 cycle for quad width 2 for dual 4 for single)" "0: No suffix,?,2: 8-bit suffix,?"
newline
bitfld.long 0x4 12. "PREFIX_LEN,Length of command prefix in units of 8 bits. (i.e. 2 cycles for quad width 4 for dual 8 for single)" "0: No prefix,1: 8-bit prefix"
bitfld.long 0x4 8.--9. "DATA_WIDTH,The width used for the data transfer" "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0x4 6.--7. "DUMMY_WIDTH,The width used for the dummy phase if any." "0: Single width,1: Dual width,2: Quad width,?"
newline
bitfld.long 0x4 4.--5. "SUFFIX_WIDTH,The width used for the post-address command suffix if any" "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0x4 2.--3. "ADDR_WIDTH,The transfer width used for the address. The address phase always transfers 24 bits in total." "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0x4 0.--1. "PREFIX_WIDTH,The transfer width used for the command prefix if any" "0: Single width,1: Dual width,2: Quad width,?"
line.long 0x8 "M0_RCMD,Command constants used for reads from memory address window 0."
hexmask.long.byte 0x8 8.--15. 1. "SUFFIX,The command suffix bits following the address if Mx_RFMT_SUFFIX_LEN is nonzero."
hexmask.long.byte 0x8 0.--7. 1. "PREFIX,The command prefix bits to prepend on each new transfer if Mx_RFMT_PREFIX_LEN is nonzero."
line.long 0xC "M0_WFMT,Write transfer format configuration for memory address window 0."
bitfld.long 0xC 28. "DTR,Enable double transfer rate (DTR) for write commands: address suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge and SDI data is captured on the SCK edge that follows its launch." "0,1"
bitfld.long 0xC 16.--18. "DUMMY_LEN,Length of dummy phase between command suffix and data phase in units of 4 bits. (i.e. 1 cycle for quad width 2 for dual 4 for single)" "0: No dummy phase,1: 4 dummy bits,2: 8 dummy bits,3: 12 dummy bits,4: 16 dummy bits,5: 20 dummy bits,6: 24 dummy bits,7: 28 dummy bits"
bitfld.long 0xC 14.--15. "SUFFIX_LEN,Length of post-address command suffix in units of 4 bits. (i.e. 1 cycle for quad width 2 for dual 4 for single)" "0: No suffix,?,2: 8-bit suffix,?"
newline
bitfld.long 0xC 12. "PREFIX_LEN,Length of command prefix in units of 8 bits. (i.e. 2 cycles for quad width 4 for dual 8 for single)" "0: No prefix,1: 8-bit prefix"
bitfld.long 0xC 8.--9. "DATA_WIDTH,The width used for the data transfer" "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0xC 6.--7. "DUMMY_WIDTH,The width used for the dummy phase if any." "0: Single width,1: Dual width,2: Quad width,?"
newline
bitfld.long 0xC 4.--5. "SUFFIX_WIDTH,The width used for the post-address command suffix if any" "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0xC 2.--3. "ADDR_WIDTH,The transfer width used for the address. The address phase always transfers 24 bits in total." "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0xC 0.--1. "PREFIX_WIDTH,The transfer width used for the command prefix if any" "0: Single width,1: Dual width,2: Quad width,?"
line.long 0x10 "M0_WCMD,Command constants used for writes to memory address window 0."
hexmask.long.byte 0x10 8.--15. 1. "SUFFIX,The command suffix bits following the address if Mx_WFMT_SUFFIX_LEN is nonzero."
hexmask.long.byte 0x10 0.--7. 1. "PREFIX,The command prefix bits to prepend on each new transfer if Mx_WFMT_PREFIX_LEN is nonzero."
line.long 0x14 "M1_TIMING,Timing configuration register for memory address window 1."
bitfld.long 0x14 30.--31. "COOLDOWN,Chip select cooldown period. When a memory transfer finishes the chip select remains asserted for 64 x COOLDOWN system clock cycles plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires the chip select.." "0,1,2,3"
bitfld.long 0x14 28.--29. "PAGEBREAK,When page break is enabled chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst even if the address of the next access follows in.." "0: No page boundary is enforced,1: Break bursts crossing a 256-byte page boundary,2: Break bursts crossing a 1024-byte quad-page..,3: Break bursts crossing a 4096-byte sector boundary"
bitfld.long 0x14 25. "SELECT_SETUP,Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK." "0,1"
newline
bitfld.long 0x14 23.--24. "SELECT_HOLD,Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select." "0,1,2,3"
hexmask.long.byte 0x14 17.--22. 1. "MAX_SELECT,Enforce a maximum assertion duration for this window's chip select in units of 64 system clock cycles. If 0 the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN)."
hexmask.long.byte 0x14 12.--16. 1. "MIN_DESELECT,After this window's chip select is deasserted it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles) plus MIN_DESELECT additional system clock cycles before the QMI reasserts either chip.."
newline
bitfld.long 0x14 8.--10. "RXDELAY,Delay the read data sample timing in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched.." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 0.--7. 1. "CLKDIV,Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly and a divisor of 256 is encoded with a value of CLKDIV=0."
line.long 0x18 "M1_RFMT,Read transfer format configuration for memory address window 1."
bitfld.long 0x18 28. "DTR,Enable double transfer rate (DTR) for read commands: address suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge and SDI data is captured on the SCK edge that follows its launch." "0,1"
bitfld.long 0x18 16.--18. "DUMMY_LEN,Length of dummy phase between command suffix and data phase in units of 4 bits. (i.e. 1 cycle for quad width 2 for dual 4 for single)" "0: No dummy phase,1: 4 dummy bits,2: 8 dummy bits,3: 12 dummy bits,4: 16 dummy bits,5: 20 dummy bits,6: 24 dummy bits,7: 28 dummy bits"
bitfld.long 0x18 14.--15. "SUFFIX_LEN,Length of post-address command suffix in units of 4 bits. (i.e. 1 cycle for quad width 2 for dual 4 for single)" "0: No suffix,?,2: 8-bit suffix,?"
newline
bitfld.long 0x18 12. "PREFIX_LEN,Length of command prefix in units of 8 bits. (i.e. 2 cycles for quad width 4 for dual 8 for single)" "0: No prefix,1: 8-bit prefix"
bitfld.long 0x18 8.--9. "DATA_WIDTH,The width used for the data transfer" "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0x18 6.--7. "DUMMY_WIDTH,The width used for the dummy phase if any." "0: Single width,1: Dual width,2: Quad width,?"
newline
bitfld.long 0x18 4.--5. "SUFFIX_WIDTH,The width used for the post-address command suffix if any" "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0x18 2.--3. "ADDR_WIDTH,The transfer width used for the address. The address phase always transfers 24 bits in total." "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0x18 0.--1. "PREFIX_WIDTH,The transfer width used for the command prefix if any" "0: Single width,1: Dual width,2: Quad width,?"
line.long 0x1C "M1_RCMD,Command constants used for reads from memory address window 1."
hexmask.long.byte 0x1C 8.--15. 1. "SUFFIX,The command suffix bits following the address if Mx_RFMT_SUFFIX_LEN is nonzero."
hexmask.long.byte 0x1C 0.--7. 1. "PREFIX,The command prefix bits to prepend on each new transfer if Mx_RFMT_PREFIX_LEN is nonzero."
line.long 0x20 "M1_WFMT,Write transfer format configuration for memory address window 1."
bitfld.long 0x20 28. "DTR,Enable double transfer rate (DTR) for write commands: address suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge and SDI data is captured on the SCK edge that follows its launch." "0,1"
bitfld.long 0x20 16.--18. "DUMMY_LEN,Length of dummy phase between command suffix and data phase in units of 4 bits. (i.e. 1 cycle for quad width 2 for dual 4 for single)" "0: No dummy phase,1: 4 dummy bits,2: 8 dummy bits,3: 12 dummy bits,4: 16 dummy bits,5: 20 dummy bits,6: 24 dummy bits,7: 28 dummy bits"
bitfld.long 0x20 14.--15. "SUFFIX_LEN,Length of post-address command suffix in units of 4 bits. (i.e. 1 cycle for quad width 2 for dual 4 for single)" "0: No suffix,?,2: 8-bit suffix,?"
newline
bitfld.long 0x20 12. "PREFIX_LEN,Length of command prefix in units of 8 bits. (i.e. 2 cycles for quad width 4 for dual 8 for single)" "0: No prefix,1: 8-bit prefix"
bitfld.long 0x20 8.--9. "DATA_WIDTH,The width used for the data transfer" "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0x20 6.--7. "DUMMY_WIDTH,The width used for the dummy phase if any." "0: Single width,1: Dual width,2: Quad width,?"
newline
bitfld.long 0x20 4.--5. "SUFFIX_WIDTH,The width used for the post-address command suffix if any" "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0x20 2.--3. "ADDR_WIDTH,The transfer width used for the address. The address phase always transfers 24 bits in total." "0: Single width,1: Dual width,2: Quad width,?"
bitfld.long 0x20 0.--1. "PREFIX_WIDTH,The transfer width used for the command prefix if any" "0: Single width,1: Dual width,2: Quad width,?"
line.long 0x24 "M1_WCMD,Command constants used for writes to memory address window 1."
hexmask.long.byte 0x24 8.--15. 1. "SUFFIX,The command suffix bits following the address if Mx_WFMT_SUFFIX_LEN is nonzero."
hexmask.long.byte 0x24 0.--7. 1. "PREFIX,The command prefix bits to prepend on each new transfer if Mx_WFMT_PREFIX_LEN is nonzero."
line.long 0x28 "ATRANS0,Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB)."
hexmask.long.word 0x28 16.--26. 1. "SIZE,Translation aperture size for this virtual address range in units of 4 kiB (one flash sector)."
hexmask.long.word 0x28 0.--11. 1. "BASE,Physical address base for this virtual address range in units of 4 kiB (one flash sector)."
line.long 0x2C "ATRANS1,Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB)."
hexmask.long.word 0x2C 16.--26. 1. "SIZE,Translation aperture size for this virtual address range in units of 4 kiB (one flash sector)."
hexmask.long.word 0x2C 0.--11. 1. "BASE,Physical address base for this virtual address range in units of 4 kiB (one flash sector)."
line.long 0x30 "ATRANS2,Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB)."
hexmask.long.word 0x30 16.--26. 1. "SIZE,Translation aperture size for this virtual address range in units of 4 kiB (one flash sector)."
hexmask.long.word 0x30 0.--11. 1. "BASE,Physical address base for this virtual address range in units of 4 kiB (one flash sector)."
line.long 0x34 "ATRANS3,Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB)."
hexmask.long.word 0x34 16.--26. 1. "SIZE,Translation aperture size for this virtual address range in units of 4 kiB (one flash sector)."
hexmask.long.word 0x34 0.--11. 1. "BASE,Physical address base for this virtual address range in units of 4 kiB (one flash sector)."
line.long 0x38 "ATRANS4,Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB)."
hexmask.long.word 0x38 16.--26. 1. "SIZE,Translation aperture size for this virtual address range in units of 4 kiB (one flash sector)."
hexmask.long.word 0x38 0.--11. 1. "BASE,Physical address base for this virtual address range in units of 4 kiB (one flash sector)."
line.long 0x3C "ATRANS5,Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB)."
hexmask.long.word 0x3C 16.--26. 1. "SIZE,Translation aperture size for this virtual address range in units of 4 kiB (one flash sector)."
hexmask.long.word 0x3C 0.--11. 1. "BASE,Physical address base for this virtual address range in units of 4 kiB (one flash sector)."
line.long 0x40 "ATRANS6,Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB)."
hexmask.long.word 0x40 16.--26. 1. "SIZE,Translation aperture size for this virtual address range in units of 4 kiB (one flash sector)."
hexmask.long.word 0x40 0.--11. 1. "BASE,Physical address base for this virtual address range in units of 4 kiB (one flash sector)."
line.long 0x44 "ATRANS7,Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB)."
hexmask.long.word 0x44 16.--26. 1. "SIZE,Translation aperture size for this virtual address range in units of 4 kiB (one flash sector)."
hexmask.long.word 0x44 0.--11. 1. "BASE,Physical address base for this virtual address range in units of 4 kiB (one flash sector)."
tree.end
tree "RESETS"
base ad:0x40020000
group.long 0x0++0x7
line.long 0x0 "RESET"
bitfld.long 0x0 28. "USBCTRL" "0,1"
bitfld.long 0x0 27. "UART1" "0,1"
bitfld.long 0x0 26. "UART0" "0,1"
bitfld.long 0x0 25. "TRNG" "0,1"
bitfld.long 0x0 24. "TIMER1" "0,1"
bitfld.long 0x0 23. "TIMER0" "0,1"
bitfld.long 0x0 22. "TBMAN" "0,1"
bitfld.long 0x0 21. "SYSINFO" "0,1"
bitfld.long 0x0 20. "SYSCFG" "0,1"
newline
bitfld.long 0x0 19. "SPI1" "0,1"
bitfld.long 0x0 18. "SPI0" "0,1"
bitfld.long 0x0 17. "SHA256" "0,1"
bitfld.long 0x0 16. "PWM" "0,1"
bitfld.long 0x0 15. "PLL_USB" "0,1"
bitfld.long 0x0 14. "PLL_SYS" "0,1"
bitfld.long 0x0 13. "PIO2" "0,1"
bitfld.long 0x0 12. "PIO1" "0,1"
bitfld.long 0x0 11. "PIO0" "0,1"
newline
bitfld.long 0x0 10. "PADS_QSPI" "0,1"
bitfld.long 0x0 9. "PADS_BANK0" "0,1"
bitfld.long 0x0 8. "JTAG" "0,1"
bitfld.long 0x0 7. "IO_QSPI" "0,1"
bitfld.long 0x0 6. "IO_BANK0" "0,1"
bitfld.long 0x0 5. "I2C1" "0,1"
bitfld.long 0x0 4. "I2C0" "0,1"
bitfld.long 0x0 3. "HSTX" "0,1"
bitfld.long 0x0 2. "DMA" "0,1"
newline
bitfld.long 0x0 1. "BUSCTRL" "0,1"
bitfld.long 0x0 0. "ADC" "0,1"
line.long 0x4 "WDSEL"
bitfld.long 0x4 28. "USBCTRL" "0,1"
bitfld.long 0x4 27. "UART1" "0,1"
bitfld.long 0x4 26. "UART0" "0,1"
bitfld.long 0x4 25. "TRNG" "0,1"
bitfld.long 0x4 24. "TIMER1" "0,1"
bitfld.long 0x4 23. "TIMER0" "0,1"
bitfld.long 0x4 22. "TBMAN" "0,1"
bitfld.long 0x4 21. "SYSINFO" "0,1"
bitfld.long 0x4 20. "SYSCFG" "0,1"
newline
bitfld.long 0x4 19. "SPI1" "0,1"
bitfld.long 0x4 18. "SPI0" "0,1"
bitfld.long 0x4 17. "SHA256" "0,1"
bitfld.long 0x4 16. "PWM" "0,1"
bitfld.long 0x4 15. "PLL_USB" "0,1"
bitfld.long 0x4 14. "PLL_SYS" "0,1"
bitfld.long 0x4 13. "PIO2" "0,1"
bitfld.long 0x4 12. "PIO1" "0,1"
bitfld.long 0x4 11. "PIO0" "0,1"
newline
bitfld.long 0x4 10. "PADS_QSPI" "0,1"
bitfld.long 0x4 9. "PADS_BANK0" "0,1"
bitfld.long 0x4 8. "JTAG" "0,1"
bitfld.long 0x4 7. "IO_QSPI" "0,1"
bitfld.long 0x4 6. "IO_BANK0" "0,1"
bitfld.long 0x4 5. "I2C1" "0,1"
bitfld.long 0x4 4. "I2C0" "0,1"
bitfld.long 0x4 3. "HSTX" "0,1"
bitfld.long 0x4 2. "DMA" "0,1"
newline
bitfld.long 0x4 1. "BUSCTRL" "0,1"
bitfld.long 0x4 0. "ADC" "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "RESET_DONE"
bitfld.long 0x0 28. "USBCTRL" "0,1"
bitfld.long 0x0 27. "UART1" "0,1"
bitfld.long 0x0 26. "UART0" "0,1"
bitfld.long 0x0 25. "TRNG" "0,1"
bitfld.long 0x0 24. "TIMER1" "0,1"
bitfld.long 0x0 23. "TIMER0" "0,1"
bitfld.long 0x0 22. "TBMAN" "0,1"
bitfld.long 0x0 21. "SYSINFO" "0,1"
bitfld.long 0x0 20. "SYSCFG" "0,1"
newline
bitfld.long 0x0 19. "SPI1" "0,1"
bitfld.long 0x0 18. "SPI0" "0,1"
bitfld.long 0x0 17. "SHA256" "0,1"
bitfld.long 0x0 16. "PWM" "0,1"
bitfld.long 0x0 15. "PLL_USB" "0,1"
bitfld.long 0x0 14. "PLL_SYS" "0,1"
bitfld.long 0x0 13. "PIO2" "0,1"
bitfld.long 0x0 12. "PIO1" "0,1"
bitfld.long 0x0 11. "PIO0" "0,1"
newline
bitfld.long 0x0 10. "PADS_QSPI" "0,1"
bitfld.long 0x0 9. "PADS_BANK0" "0,1"
bitfld.long 0x0 8. "JTAG" "0,1"
bitfld.long 0x0 7. "IO_QSPI" "0,1"
bitfld.long 0x0 6. "IO_BANK0" "0,1"
bitfld.long 0x0 5. "I2C1" "0,1"
bitfld.long 0x0 4. "I2C0" "0,1"
bitfld.long 0x0 3. "HSTX" "0,1"
bitfld.long 0x0 2. "DMA" "0,1"
newline
bitfld.long 0x0 1. "BUSCTRL" "0,1"
bitfld.long 0x0 0. "ADC" "0,1"
tree.end
tree "ROSC (Ring Oscillator)"
base ad:0x400E8000
group.long 0x0++0x1F
line.long 0x0 "CTRL,Ring Oscillator control"
hexmask.long.word 0x0 12.--23. 1. "ENABLE,On power-up this field is initialised to ENABLE"
hexmask.long.word 0x0 0.--11. 1. "FREQ_RANGE,Controls the number of delay stages in the ROSC ring"
line.long 0x4 "FREQA,The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage"
hexmask.long.word 0x4 16.--31. 1. "PASSWD,Set to 0x9696 to apply the settings"
bitfld.long 0x4 12.--14. "DS3,Stage 3 drive strength" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 8.--10. "DS2,Stage 2 drive strength" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 7. "DS1_RANDOM,Randomises the stage 1 drive strength" "0,1"
bitfld.long 0x4 4.--6. "DS1,Stage 1 drive strength" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "DS0_RANDOM,Randomises the stage 0 drive strength" "0,1"
bitfld.long 0x4 0.--2. "DS0,Stage 0 drive strength" "0,1,2,3,4,5,6,7"
line.long 0x8 "FREQB,For a detailed description see freqa register"
hexmask.long.word 0x8 16.--31. 1. "PASSWD,Set to 0x9696 to apply the settings"
bitfld.long 0x8 12.--14. "DS7,Stage 7 drive strength" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 8.--10. "DS6,Stage 6 drive strength" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 4.--6. "DS5,Stage 5 drive strength" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 0.--2. "DS4,Stage 4 drive strength" "0,1,2,3,4,5,6,7"
line.long 0xC "RANDOM,Loads a value to the LFSR randomiser"
hexmask.long 0xC 0.--31. 1. "SEED"
line.long 0x10 "DORMANT,Ring Oscillator pause control"
hexmask.long 0x10 0.--31. 1. "DORMANT,This is used to save power by pausing the ROSC"
line.long 0x14 "DIV,Controls the output divider"
hexmask.long.word 0x14 0.--15. 1. "DIV,set to 0xaa00 + div where"
line.long 0x18 "PHASE,Controls the phase shifted output"
hexmask.long.byte 0x18 4.--11. 1. "PASSWD,set to 0xaa"
bitfld.long 0x18 3. "ENABLE,enable the phase-shifted output" "0,1"
bitfld.long 0x18 2. "FLIP,invert the phase-shifted output" "0,1"
bitfld.long 0x18 0.--1. "SHIFT,phase shift the phase-shifted output by SHIFT input clocks" "0,1,2,3"
line.long 0x1C "STATUS,Ring Oscillator Status"
rbitfld.long 0x1C 31. "STABLE,Oscillator is running and stable" "0,1"
eventfld.long 0x1C 24. "BADWRITE,An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT" "0,1"
rbitfld.long 0x1C 16. "DIV_RUNNING,post-divider is running" "0,1"
rbitfld.long 0x1C 12. "ENABLED,Oscillator is enabled but not necessarily running and stable" "0,1"
rgroup.long 0x20++0x3
line.long 0x0 "RANDOMBIT,This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency"
bitfld.long 0x0 0. "RANDOMBIT" "0,1"
group.long 0x24++0x3
line.long 0x0 "COUNT,A down counter running at the ROSC frequency which counts to zero and stops."
hexmask.long.word 0x0 0.--15. 1. "COUNT"
tree.end
tree "SHA256 (SHA-256 hash function implementation)"
base ad:0x400F8000
group.long 0x0++0x3
line.long 0x0 "CSR,Control and status register"
bitfld.long 0x0 12. "BSWAP,Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler." "0,1"
bitfld.long 0x0 8.--9. "DMA_SIZE,Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered." "0,1,2,3"
eventfld.long 0x0 4. "ERR_WDATA_NOT_RDY,Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear." "0,1"
rbitfld.long 0x0 2. "SUM_VLD,If 1 the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid." "0,1"
rbitfld.long 0x0 1. "WDATA_RDY,If 1 the SHA-256 core is ready to accept more data through the WDATA register." "0,1"
bitfld.long 0x0 0. "START,Write 1 to prepare the SHA-256 core for a new checksum." "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "WDATA,Write data register"
hexmask.long 0x0 0.--31. 1. "WDATA,After pulsing START and writing 16 words of data to this register WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block."
rgroup.long 0x8++0x1F
line.long 0x0 "SUM0,256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."
hexmask.long 0x0 0.--31. 1. "SUM0"
line.long 0x4 "SUM1,256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."
hexmask.long 0x4 0.--31. 1. "SUM1"
line.long 0x8 "SUM2,256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."
hexmask.long 0x8 0.--31. 1. "SUM2"
line.long 0xC "SUM3,256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."
hexmask.long 0xC 0.--31. 1. "SUM3"
line.long 0x10 "SUM4,256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."
hexmask.long 0x10 0.--31. 1. "SUM4"
line.long 0x14 "SUM5,256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."
hexmask.long 0x14 0.--31. 1. "SUM5"
line.long 0x18 "SUM6,256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."
hexmask.long 0x18 0.--31. 1. "SUM6"
line.long 0x1C "SUM7,256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."
hexmask.long 0x1C 0.--31. 1. "SUM7"
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
tree "SPI0"
base ad:0x40080000
group.long 0x0++0xB
line.long 0x0 "SSPCR0,Control register 0. SSPCR0 on page 3-4"
hexmask.long.byte 0x0 8.--15. 1. "SCR,Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254 programmed through the SSPCPSR register and SCR is a.."
bitfld.long 0x0 7. "SPH,SSPCLKOUT phase applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10." "0,1"
bitfld.long 0x0 6. "SPO,SSPCLKOUT polarity applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10." "0,1"
bitfld.long 0x0 4.--5. "FRF,Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved undefined operation." "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "DSS,Data Size Select: 0000 Reserved undefined operation. 0001 Reserved undefined operation. 0010 Reserved undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010.."
line.long 0x4 "SSPCR1,Control register 1. SSPCR1 on page 3-5"
bitfld.long 0x4 3. "SOD,Slave-mode output disable. This bit is relevant only in the slave mode MS=1. In multiple-slave systems it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto.." "0,1"
bitfld.long 0x4 2. "MS,Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled SSE=0: 0 Device configured as master default. 1 Device configured as slave." "0: 0 Device configured as master,?"
bitfld.long 0x4 1. "SSE,Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled." "0,1"
bitfld.long 0x4 0. "LBM,Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally." "0,1"
line.long 0x8 "SSPDR,Data register. SSPDR on page 3-6"
hexmask.long.word 0x8 0.--15. 1. "DATA,Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic.."
rgroup.long 0xC++0x3
line.long 0x0 "SSPSR,Status register. SSPSR on page 3-7"
bitfld.long 0x0 4. "BSY,PrimeCell SSP busy flag RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty." "0,1"
bitfld.long 0x0 3. "RFF,Receive FIFO full RO: 0 Receive FIFO is not full. 1 Receive FIFO is full." "0,1"
bitfld.long 0x0 2. "RNE,Receive FIFO not empty RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty." "0,1"
bitfld.long 0x0 1. "TNF,Transmit FIFO not full RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full." "0,1"
bitfld.long 0x0 0. "TFE,Transmit FIFO empty RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty." "0,1"
group.long 0x10++0x7
line.long 0x0 "SSPCPSR,Clock prescale register. SSPCPSR on page 3-8"
hexmask.long.byte 0x0 0.--7. 1. "CPSDVSR,Clock prescale divisor. Must be an even number from 2-254 depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."
line.long 0x4 "SSPIMSC,Interrupt mask set or clear register. SSPIMSC on page 3-9"
bitfld.long 0x4 3. "TXIM,Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked." "0,1"
bitfld.long 0x4 2. "RXIM,Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked." "0,1"
bitfld.long 0x4 1. "RTIM,Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked." "0,1"
bitfld.long 0x4 0. "RORIM,Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked." "0,1"
rgroup.long 0x18++0x7
line.long 0x0 "SSPRIS,Raw interrupt status register. SSPRIS on page 3-10"
bitfld.long 0x0 3. "TXRIS,Gives the raw interrupt state prior to masking of the SSPTXINTR interrupt" "0,1"
bitfld.long 0x0 2. "RXRIS,Gives the raw interrupt state prior to masking of the SSPRXINTR interrupt" "0,1"
bitfld.long 0x0 1. "RTRIS,Gives the raw interrupt state prior to masking of the SSPRTINTR interrupt" "0,1"
bitfld.long 0x0 0. "RORRIS,Gives the raw interrupt state prior to masking of the SSPRORINTR interrupt" "0,1"
line.long 0x4 "SSPMIS,Masked interrupt status register. SSPMIS on page 3-11"
bitfld.long 0x4 3. "TXMIS,Gives the transmit FIFO masked interrupt state after masking of the SSPTXINTR interrupt" "0,1"
bitfld.long 0x4 2. "RXMIS,Gives the receive FIFO masked interrupt state after masking of the SSPRXINTR interrupt" "0,1"
bitfld.long 0x4 1. "RTMIS,Gives the receive timeout masked interrupt state after masking of the SSPRTINTR interrupt" "0,1"
bitfld.long 0x4 0. "RORMIS,Gives the receive over run masked interrupt status after masking of the SSPRORINTR interrupt" "0,1"
group.long 0x20++0x7
line.long 0x0 "SSPICR,Interrupt clear register. SSPICR on page 3-11"
eventfld.long 0x0 1. "RTIC,Clears the SSPRTINTR interrupt" "0,1"
eventfld.long 0x0 0. "RORIC,Clears the SSPRORINTR interrupt" "0,1"
line.long 0x4 "SSPDMACR,DMA control register. SSPDMACR on page 3-12"
bitfld.long 0x4 1. "TXDMAE,Transmit DMA Enable. If this bit is set to 1 DMA for the transmit FIFO is enabled." "0,1"
bitfld.long 0x4 0. "RXDMAE,Receive DMA Enable. If this bit is set to 1 DMA for the receive FIFO is enabled." "0,1"
rgroup.long 0xFE0++0x1F
line.long 0x0 "SSPPERIPHID0,Peripheral identification registers. SSPPeriphID0-3 on page 3-13"
hexmask.long.byte 0x0 0.--7. 1. "PARTNUMBER0,These bits read back as 0x22"
line.long 0x4 "SSPPERIPHID1,Peripheral identification registers. SSPPeriphID0-3 on page 3-13"
hexmask.long.byte 0x4 4.--7. 1. "DESIGNER0,These bits read back as 0x1"
hexmask.long.byte 0x4 0.--3. 1. "PARTNUMBER1,These bits read back as 0x0"
line.long 0x8 "SSPPERIPHID2,Peripheral identification registers. SSPPeriphID0-3 on page 3-13"
hexmask.long.byte 0x8 4.--7. 1. "REVISION,These bits return the peripheral revision"
hexmask.long.byte 0x8 0.--3. 1. "DESIGNER1,These bits read back as 0x4"
line.long 0xC "SSPPERIPHID3,Peripheral identification registers. SSPPeriphID0-3 on page 3-13"
hexmask.long.byte 0xC 0.--7. 1. "CONFIGURATION,These bits read back as 0x00"
line.long 0x10 "SSPPCELLID0,PrimeCell identification registers. SSPPCellID0-3 on page 3-16"
hexmask.long.byte 0x10 0.--7. 1. "SSPPCELLID0,These bits read back as 0x0D"
line.long 0x14 "SSPPCELLID1,PrimeCell identification registers. SSPPCellID0-3 on page 3-16"
hexmask.long.byte 0x14 0.--7. 1. "SSPPCELLID1,These bits read back as 0xF0"
line.long 0x18 "SSPPCELLID2,PrimeCell identification registers. SSPPCellID0-3 on page 3-16"
hexmask.long.byte 0x18 0.--7. 1. "SSPPCELLID2,These bits read back as 0x05"
line.long 0x1C "SSPPCELLID3,PrimeCell identification registers. SSPPCellID0-3 on page 3-16"
hexmask.long.byte 0x1C 0.--7. 1. "SSPPCELLID3,These bits read back as 0xB1"
tree.end
tree "SPI1"
base ad:0x40088000
group.long 0x0++0xB
line.long 0x0 "SSPCR0,Control register 0. SSPCR0 on page 3-4"
hexmask.long.byte 0x0 8.--15. 1. "SCR,Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254 programmed through the SSPCPSR register and SCR is a.."
bitfld.long 0x0 7. "SPH,SSPCLKOUT phase applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10." "0,1"
bitfld.long 0x0 6. "SPO,SSPCLKOUT polarity applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10." "0,1"
bitfld.long 0x0 4.--5. "FRF,Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved undefined operation." "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "DSS,Data Size Select: 0000 Reserved undefined operation. 0001 Reserved undefined operation. 0010 Reserved undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010.."
line.long 0x4 "SSPCR1,Control register 1. SSPCR1 on page 3-5"
bitfld.long 0x4 3. "SOD,Slave-mode output disable. This bit is relevant only in the slave mode MS=1. In multiple-slave systems it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto.." "0,1"
bitfld.long 0x4 2. "MS,Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled SSE=0: 0 Device configured as master default. 1 Device configured as slave." "0: 0 Device configured as master,?"
bitfld.long 0x4 1. "SSE,Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled." "0,1"
bitfld.long 0x4 0. "LBM,Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally." "0,1"
line.long 0x8 "SSPDR,Data register. SSPDR on page 3-6"
hexmask.long.word 0x8 0.--15. 1. "DATA,Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic.."
rgroup.long 0xC++0x3
line.long 0x0 "SSPSR,Status register. SSPSR on page 3-7"
bitfld.long 0x0 4. "BSY,PrimeCell SSP busy flag RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty." "0,1"
bitfld.long 0x0 3. "RFF,Receive FIFO full RO: 0 Receive FIFO is not full. 1 Receive FIFO is full." "0,1"
bitfld.long 0x0 2. "RNE,Receive FIFO not empty RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty." "0,1"
bitfld.long 0x0 1. "TNF,Transmit FIFO not full RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full." "0,1"
bitfld.long 0x0 0. "TFE,Transmit FIFO empty RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty." "0,1"
group.long 0x10++0x7
line.long 0x0 "SSPCPSR,Clock prescale register. SSPCPSR on page 3-8"
hexmask.long.byte 0x0 0.--7. 1. "CPSDVSR,Clock prescale divisor. Must be an even number from 2-254 depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."
line.long 0x4 "SSPIMSC,Interrupt mask set or clear register. SSPIMSC on page 3-9"
bitfld.long 0x4 3. "TXIM,Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked." "0,1"
bitfld.long 0x4 2. "RXIM,Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked." "0,1"
bitfld.long 0x4 1. "RTIM,Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked." "0,1"
bitfld.long 0x4 0. "RORIM,Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked." "0,1"
rgroup.long 0x18++0x7
line.long 0x0 "SSPRIS,Raw interrupt status register. SSPRIS on page 3-10"
bitfld.long 0x0 3. "TXRIS,Gives the raw interrupt state prior to masking of the SSPTXINTR interrupt" "0,1"
bitfld.long 0x0 2. "RXRIS,Gives the raw interrupt state prior to masking of the SSPRXINTR interrupt" "0,1"
bitfld.long 0x0 1. "RTRIS,Gives the raw interrupt state prior to masking of the SSPRTINTR interrupt" "0,1"
bitfld.long 0x0 0. "RORRIS,Gives the raw interrupt state prior to masking of the SSPRORINTR interrupt" "0,1"
line.long 0x4 "SSPMIS,Masked interrupt status register. SSPMIS on page 3-11"
bitfld.long 0x4 3. "TXMIS,Gives the transmit FIFO masked interrupt state after masking of the SSPTXINTR interrupt" "0,1"
bitfld.long 0x4 2. "RXMIS,Gives the receive FIFO masked interrupt state after masking of the SSPRXINTR interrupt" "0,1"
bitfld.long 0x4 1. "RTMIS,Gives the receive timeout masked interrupt state after masking of the SSPRTINTR interrupt" "0,1"
bitfld.long 0x4 0. "RORMIS,Gives the receive over run masked interrupt status after masking of the SSPRORINTR interrupt" "0,1"
group.long 0x20++0x7
line.long 0x0 "SSPICR,Interrupt clear register. SSPICR on page 3-11"
eventfld.long 0x0 1. "RTIC,Clears the SSPRTINTR interrupt" "0,1"
eventfld.long 0x0 0. "RORIC,Clears the SSPRORINTR interrupt" "0,1"
line.long 0x4 "SSPDMACR,DMA control register. SSPDMACR on page 3-12"
bitfld.long 0x4 1. "TXDMAE,Transmit DMA Enable. If this bit is set to 1 DMA for the transmit FIFO is enabled." "0,1"
bitfld.long 0x4 0. "RXDMAE,Receive DMA Enable. If this bit is set to 1 DMA for the receive FIFO is enabled." "0,1"
rgroup.long 0xFE0++0x1F
line.long 0x0 "SSPPERIPHID0,Peripheral identification registers. SSPPeriphID0-3 on page 3-13"
hexmask.long.byte 0x0 0.--7. 1. "PARTNUMBER0,These bits read back as 0x22"
line.long 0x4 "SSPPERIPHID1,Peripheral identification registers. SSPPeriphID0-3 on page 3-13"
hexmask.long.byte 0x4 4.--7. 1. "DESIGNER0,These bits read back as 0x1"
hexmask.long.byte 0x4 0.--3. 1. "PARTNUMBER1,These bits read back as 0x0"
line.long 0x8 "SSPPERIPHID2,Peripheral identification registers. SSPPeriphID0-3 on page 3-13"
hexmask.long.byte 0x8 4.--7. 1. "REVISION,These bits return the peripheral revision"
hexmask.long.byte 0x8 0.--3. 1. "DESIGNER1,These bits read back as 0x4"
line.long 0xC "SSPPERIPHID3,Peripheral identification registers. SSPPeriphID0-3 on page 3-13"
hexmask.long.byte 0xC 0.--7. 1. "CONFIGURATION,These bits read back as 0x00"
line.long 0x10 "SSPPCELLID0,PrimeCell identification registers. SSPPCellID0-3 on page 3-16"
hexmask.long.byte 0x10 0.--7. 1. "SSPPCELLID0,These bits read back as 0x0D"
line.long 0x14 "SSPPCELLID1,PrimeCell identification registers. SSPPCellID0-3 on page 3-16"
hexmask.long.byte 0x14 0.--7. 1. "SSPPCELLID1,These bits read back as 0xF0"
line.long 0x18 "SSPPCELLID2,PrimeCell identification registers. SSPPCellID0-3 on page 3-16"
hexmask.long.byte 0x18 0.--7. 1. "SSPPCELLID2,These bits read back as 0x05"
line.long 0x1C "SSPPCELLID3,PrimeCell identification registers. SSPPCellID0-3 on page 3-16"
hexmask.long.byte 0x1C 0.--7. 1. "SSPPCELLID3,These bits read back as 0xB1"
tree.end
tree.end
tree "SYSCFG (System Configuration)"
base ad:0x40008000
rgroup.long 0x0++0x3
line.long 0x0 "PROC_CONFIG,Configuration for processors"
bitfld.long 0x0 1. "PROC1_HALTED,Indication that proc1 has halted" "0,1"
bitfld.long 0x0 0. "PROC0_HALTED,Indication that proc0 has halted" "0,1"
group.long 0x4++0x13
line.long 0x0 "PROC_IN_SYNC_BYPASS,For each bit. if 1. bypass the input synchronizer between that GPIO"
hexmask.long 0x0 0.--31. 1. "GPIO"
line.long 0x4 "PROC_IN_SYNC_BYPASS_HI,For each bit. if 1. bypass the input synchronizer between that GPIO"
hexmask.long.byte 0x4 28.--31. 1. "QSPI_SD"
bitfld.long 0x4 27. "QSPI_CSN" "0,1"
bitfld.long 0x4 26. "QSPI_SCK" "0,1"
bitfld.long 0x4 25. "USB_DM" "0,1"
bitfld.long 0x4 24. "USB_DP" "0,1"
hexmask.long.word 0x4 0.--15. 1. "GPIO"
line.long 0x8 "DBGFORCE,Directly control the chip SWD debug port"
bitfld.long 0x8 3. "ATTACH,Attach chip debug port to syscfg controls and disconnect it from external SWD pads." "0,1"
bitfld.long 0x8 2. "SWCLK,Directly drive SWCLK if ATTACH is set" "0,1"
bitfld.long 0x8 1. "SWDI,Directly drive SWDIO input if ATTACH is set" "0,1"
rbitfld.long 0x8 0. "SWDO,Observe the value of SWDIO output." "0,1"
line.long 0xC "MEMPOWERDOWN,Control PD pins to memories."
bitfld.long 0xC 12. "BOOTRAM" "0,1"
bitfld.long 0xC 11. "ROM" "0,1"
bitfld.long 0xC 10. "USB" "0,1"
bitfld.long 0xC 9. "SRAM9" "0,1"
bitfld.long 0xC 8. "SRAM8" "0,1"
bitfld.long 0xC 7. "SRAM7" "0,1"
newline
bitfld.long 0xC 6. "SRAM6" "0,1"
bitfld.long 0xC 5. "SRAM5" "0,1"
bitfld.long 0xC 4. "SRAM4" "0,1"
bitfld.long 0xC 3. "SRAM3" "0,1"
bitfld.long 0xC 2. "SRAM2" "0,1"
bitfld.long 0xC 1. "SRAM1" "0,1"
newline
bitfld.long 0xC 0. "SRAM0" "0,1"
line.long 0x10 "AUXCTRL,Auxiliary system control register"
hexmask.long.byte 0x10 0.--7. 1. "AUXCTRL,* Bits 7:2: Reserved"
tree.end
tree "SYSINFO (System Information)"
base ad:0x40000000
rgroup.long 0x0++0xB
line.long 0x0 "CHIP_ID,JEDEC JEP-106 compliant chip identifier."
hexmask.long.byte 0x0 28.--31. 1. "REVISION"
hexmask.long.word 0x0 12.--27. 1. "PART"
hexmask.long.word 0x0 1.--11. 1. "MANUFACTURER"
bitfld.long 0x0 0. "STOP_BIT" "0,1"
line.long 0x4 "PACKAGE_SEL"
bitfld.long 0x4 0. "PACKAGE_SEL" "0,1"
line.long 0x8 "PLATFORM,Platform register. Allows software to know what environment it is running in during pre-production development. Post-production. the PLATFORM is always ASIC. non-SIM."
bitfld.long 0x8 4. "GATESIM" "0,1"
bitfld.long 0x8 3. "BATCHSIM" "0,1"
bitfld.long 0x8 2. "HDLSIM" "0,1"
bitfld.long 0x8 1. "ASIC" "0,1"
bitfld.long 0x8 0. "FPGA" "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "GITREF_RP2350,Git hash of the chip source. Used to identify chip version."
hexmask.long 0x0 0.--31. 1. "GITREF_RP2350"
tree.end
tree "TBMAN (Testbench Manager)"
base ad:0x40160000
rgroup.long 0x0++0x3
line.long 0x0 "PLATFORM,Indicates the type of platform in use"
bitfld.long 0x0 2. "HDLSIM,Indicates the platform is a simulation" "0,1"
bitfld.long 0x0 1. "FPGA,Indicates the platform is an FPGA" "0,1"
bitfld.long 0x0 0. "ASIC,Indicates the platform is an ASIC" "0,1"
tree.end
tree "TICKS"
base ad:0x40108000
group.long 0x0++0x7
line.long 0x0 "PROC0_CTRL,Controls the tick generator"
rbitfld.long 0x0 1. "RUNNING,Is the tick generator running?" "0,1"
bitfld.long 0x0 0. "ENABLE,start / stop tick generation" "0,1"
line.long 0x4 "PROC0_CYCLES"
hexmask.long.word 0x4 0.--8. 1. "PROC0_CYCLES,Total number of clk_tick cycles before the next tick."
rgroup.long 0x8++0x3
line.long 0x0 "PROC0_COUNT"
hexmask.long.word 0x0 0.--8. 1. "PROC0_COUNT,Count down timer: the remaining number clk_tick cycles before the next tick is generated."
group.long 0xC++0x7
line.long 0x0 "PROC1_CTRL,Controls the tick generator"
rbitfld.long 0x0 1. "RUNNING,Is the tick generator running?" "0,1"
bitfld.long 0x0 0. "ENABLE,start / stop tick generation" "0,1"
line.long 0x4 "PROC1_CYCLES"
hexmask.long.word 0x4 0.--8. 1. "PROC1_CYCLES,Total number of clk_tick cycles before the next tick."
rgroup.long 0x14++0x3
line.long 0x0 "PROC1_COUNT"
hexmask.long.word 0x0 0.--8. 1. "PROC1_COUNT,Count down timer: the remaining number clk_tick cycles before the next tick is generated."
group.long 0x18++0x7
line.long 0x0 "TIMER0_CTRL,Controls the tick generator"
rbitfld.long 0x0 1. "RUNNING,Is the tick generator running?" "0,1"
bitfld.long 0x0 0. "ENABLE,start / stop tick generation" "0,1"
line.long 0x4 "TIMER0_CYCLES"
hexmask.long.word 0x4 0.--8. 1. "TIMER0_CYCLES,Total number of clk_tick cycles before the next tick."
rgroup.long 0x20++0x3
line.long 0x0 "TIMER0_COUNT"
hexmask.long.word 0x0 0.--8. 1. "TIMER0_COUNT,Count down timer: the remaining number clk_tick cycles before the next tick is generated."
group.long 0x24++0x7
line.long 0x0 "TIMER1_CTRL,Controls the tick generator"
rbitfld.long 0x0 1. "RUNNING,Is the tick generator running?" "0,1"
bitfld.long 0x0 0. "ENABLE,start / stop tick generation" "0,1"
line.long 0x4 "TIMER1_CYCLES"
hexmask.long.word 0x4 0.--8. 1. "TIMER1_CYCLES,Total number of clk_tick cycles before the next tick."
rgroup.long 0x2C++0x3
line.long 0x0 "TIMER1_COUNT"
hexmask.long.word 0x0 0.--8. 1. "TIMER1_COUNT,Count down timer: the remaining number clk_tick cycles before the next tick is generated."
group.long 0x30++0x7
line.long 0x0 "WATCHDOG_CTRL,Controls the tick generator"
rbitfld.long 0x0 1. "RUNNING,Is the tick generator running?" "0,1"
bitfld.long 0x0 0. "ENABLE,start / stop tick generation" "0,1"
line.long 0x4 "WATCHDOG_CYCLES"
hexmask.long.word 0x4 0.--8. 1. "WATCHDOG_CYCLES,Total number of clk_tick cycles before the next tick."
rgroup.long 0x38++0x3
line.long 0x0 "WATCHDOG_COUNT"
hexmask.long.word 0x0 0.--8. 1. "WATCHDOG_COUNT,Count down timer: the remaining number clk_tick cycles before the next tick is generated."
group.long 0x3C++0x7
line.long 0x0 "RISCV_CTRL,Controls the tick generator"
rbitfld.long 0x0 1. "RUNNING,Is the tick generator running?" "0,1"
bitfld.long 0x0 0. "ENABLE,start / stop tick generation" "0,1"
line.long 0x4 "RISCV_CYCLES"
hexmask.long.word 0x4 0.--8. 1. "RISCV_CYCLES,Total number of clk_tick cycles before the next tick."
rgroup.long 0x44++0x3
line.long 0x0 "RISCV_COUNT"
hexmask.long.word 0x0 0.--8. 1. "RISCV_COUNT,Count down timer: the remaining number clk_tick cycles before the next tick is generated."
tree.end
tree "TIMER"
base ad:0x0
tree "TIMER0"
base ad:0x400B0000
wgroup.long 0x0++0x7
line.long 0x0 "TIMEHW,Write to bits 63:32 of time always write timelw before timehw"
hexmask.long 0x0 0.--31. 1. "TIMEHW"
line.long 0x4 "TIMELW,Write to bits 31:0 of time writes do not get copied to time until timehw is written"
hexmask.long 0x4 0.--31. 1. "TIMELW"
rgroup.long 0x8++0x7
line.long 0x0 "TIMEHR,Read from bits 63:32 of time always read timelr before timehr"
hexmask.long 0x0 0.--31. 1. "TIMEHR"
line.long 0x4 "TIMELR,Read from bits 31:0 of time"
hexmask.long 0x4 0.--31. 1. "TIMELR"
group.long 0x10++0x13
line.long 0x0 "ALARM0,Arm alarm 0. and configure the time it will fire. Once armed. the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires. and can be disarmed early using the ARMED status register."
hexmask.long 0x0 0.--31. 1. "ALARM0"
line.long 0x4 "ALARM1,Arm alarm 1. and configure the time it will fire. Once armed. the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires. and can be disarmed early using the ARMED status register."
hexmask.long 0x4 0.--31. 1. "ALARM1"
line.long 0x8 "ALARM2,Arm alarm 2. and configure the time it will fire. Once armed. the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires. and can be disarmed early using the ARMED status register."
hexmask.long 0x8 0.--31. 1. "ALARM2"
line.long 0xC "ALARM3,Arm alarm 3. and configure the time it will fire. Once armed. the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires. and can be disarmed early using the ARMED status register."
hexmask.long 0xC 0.--31. 1. "ALARM3"
line.long 0x10 "ARMED,Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing. but writing ones here will disarm immediately without waiting to fire."
hexmask.long.byte 0x10 0.--3. 1. "ARMED"
rgroup.long 0x24++0x7
line.long 0x0 "TIMERAWH,Raw read from bits 63:32 of time (no side effects)"
hexmask.long 0x0 0.--31. 1. "TIMERAWH"
line.long 0x4 "TIMERAWL,Raw read from bits 31:0 of time (no side effects)"
hexmask.long 0x4 0.--31. 1. "TIMERAWL"
group.long 0x2C++0x1B
line.long 0x0 "DBGPAUSE,Set bits high to enable pause when the corresponding debug ports are active"
bitfld.long 0x0 2. "DBG1,Pause when processor 1 is in debug mode" "0,1"
bitfld.long 0x0 1. "DBG0,Pause when processor 0 is in debug mode" "0,1"
line.long 0x4 "PAUSE,Set high to pause the timer"
bitfld.long 0x4 0. "PAUSE" "0,1"
line.long 0x8 "LOCKED,Set locked bit to disable write access to timer Once set. cannot be cleared (without a reset)"
bitfld.long 0x8 0. "LOCKED" "0,1"
line.long 0xC "SOURCE,Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead."
bitfld.long 0xC 0. "CLK_SYS" "0,1"
line.long 0x10 "INTR,Raw Interrupts"
eventfld.long 0x10 3. "ALARM_3" "0,1"
eventfld.long 0x10 2. "ALARM_2" "0,1"
eventfld.long 0x10 1. "ALARM_1" "0,1"
eventfld.long 0x10 0. "ALARM_0" "0,1"
line.long 0x14 "INTE,Interrupt Enable"
bitfld.long 0x14 3. "ALARM_3" "0,1"
bitfld.long 0x14 2. "ALARM_2" "0,1"
bitfld.long 0x14 1. "ALARM_1" "0,1"
bitfld.long 0x14 0. "ALARM_0" "0,1"
line.long 0x18 "INTF,Interrupt Force"
bitfld.long 0x18 3. "ALARM_3" "0,1"
bitfld.long 0x18 2. "ALARM_2" "0,1"
bitfld.long 0x18 1. "ALARM_1" "0,1"
bitfld.long 0x18 0. "ALARM_0" "0,1"
rgroup.long 0x48++0x3
line.long 0x0 "INTS,Interrupt status after masking & forcing"
bitfld.long 0x0 3. "ALARM_3" "0,1"
bitfld.long 0x0 2. "ALARM_2" "0,1"
bitfld.long 0x0 1. "ALARM_1" "0,1"
bitfld.long 0x0 0. "ALARM_0" "0,1"
tree.end
tree "TIMER1"
base ad:0x400B8000
wgroup.long 0x0++0x7
line.long 0x0 "TIMEHW,Write to bits 63:32 of time always write timelw before timehw"
hexmask.long 0x0 0.--31. 1. "TIMEHW"
line.long 0x4 "TIMELW,Write to bits 31:0 of time writes do not get copied to time until timehw is written"
hexmask.long 0x4 0.--31. 1. "TIMELW"
rgroup.long 0x8++0x7
line.long 0x0 "TIMEHR,Read from bits 63:32 of time always read timelr before timehr"
hexmask.long 0x0 0.--31. 1. "TIMEHR"
line.long 0x4 "TIMELR,Read from bits 31:0 of time"
hexmask.long 0x4 0.--31. 1. "TIMELR"
group.long 0x10++0x13
line.long 0x0 "ALARM0,Arm alarm 0. and configure the time it will fire. Once armed. the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires. and can be disarmed early using the ARMED status register."
hexmask.long 0x0 0.--31. 1. "ALARM0"
line.long 0x4 "ALARM1,Arm alarm 1. and configure the time it will fire. Once armed. the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires. and can be disarmed early using the ARMED status register."
hexmask.long 0x4 0.--31. 1. "ALARM1"
line.long 0x8 "ALARM2,Arm alarm 2. and configure the time it will fire. Once armed. the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires. and can be disarmed early using the ARMED status register."
hexmask.long 0x8 0.--31. 1. "ALARM2"
line.long 0xC "ALARM3,Arm alarm 3. and configure the time it will fire. Once armed. the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires. and can be disarmed early using the ARMED status register."
hexmask.long 0xC 0.--31. 1. "ALARM3"
line.long 0x10 "ARMED,Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing. but writing ones here will disarm immediately without waiting to fire."
hexmask.long.byte 0x10 0.--3. 1. "ARMED"
rgroup.long 0x24++0x7
line.long 0x0 "TIMERAWH,Raw read from bits 63:32 of time (no side effects)"
hexmask.long 0x0 0.--31. 1. "TIMERAWH"
line.long 0x4 "TIMERAWL,Raw read from bits 31:0 of time (no side effects)"
hexmask.long 0x4 0.--31. 1. "TIMERAWL"
group.long 0x2C++0x1B
line.long 0x0 "DBGPAUSE,Set bits high to enable pause when the corresponding debug ports are active"
bitfld.long 0x0 2. "DBG1,Pause when processor 1 is in debug mode" "0,1"
bitfld.long 0x0 1. "DBG0,Pause when processor 0 is in debug mode" "0,1"
line.long 0x4 "PAUSE,Set high to pause the timer"
bitfld.long 0x4 0. "PAUSE" "0,1"
line.long 0x8 "LOCKED,Set locked bit to disable write access to timer Once set. cannot be cleared (without a reset)"
bitfld.long 0x8 0. "LOCKED" "0,1"
line.long 0xC "SOURCE,Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead."
bitfld.long 0xC 0. "CLK_SYS" "0,1"
line.long 0x10 "INTR,Raw Interrupts"
eventfld.long 0x10 3. "ALARM_3" "0,1"
eventfld.long 0x10 2. "ALARM_2" "0,1"
eventfld.long 0x10 1. "ALARM_1" "0,1"
eventfld.long 0x10 0. "ALARM_0" "0,1"
line.long 0x14 "INTE,Interrupt Enable"
bitfld.long 0x14 3. "ALARM_3" "0,1"
bitfld.long 0x14 2. "ALARM_2" "0,1"
bitfld.long 0x14 1. "ALARM_1" "0,1"
bitfld.long 0x14 0. "ALARM_0" "0,1"
line.long 0x18 "INTF,Interrupt Force"
bitfld.long 0x18 3. "ALARM_3" "0,1"
bitfld.long 0x18 2. "ALARM_2" "0,1"
bitfld.long 0x18 1. "ALARM_1" "0,1"
bitfld.long 0x18 0. "ALARM_0" "0,1"
rgroup.long 0x48++0x3
line.long 0x0 "INTS,Interrupt status after masking & forcing"
bitfld.long 0x0 3. "ALARM_3" "0,1"
bitfld.long 0x0 2. "ALARM_2" "0,1"
bitfld.long 0x0 1. "ALARM_1" "0,1"
bitfld.long 0x0 0. "ALARM_0" "0,1"
tree.end
tree.end
tree "TRNG (True Random Number Generator)"
base ad:0x400F0000
group.long 0x100++0x3
line.long 0x0 "RNG_IMR,Interrupt masking."
hexmask.long 0x0 4.--31. 1. "RESERVED,RESERVED"
bitfld.long 0x0 3. "VN_ERR_INT_MASK,1'b1-mask interrupt no interrupt will be generated. See RNG_ISR for an explanation on this interrupt." "0,1"
bitfld.long 0x0 2. "CRNGT_ERR_INT_MASK,1'b1-mask interrupt no interrupt will be generated. See RNG_ISR for an explanation on this interrupt." "0,1"
bitfld.long 0x0 1. "AUTOCORR_ERR_INT_MASK,1'b1-mask interrupt no interrupt will be generated. See RNG_ISR for an explanation on this interrupt." "0,1"
newline
bitfld.long 0x0 0. "EHR_VALID_INT_MASK,1'b1-mask interrupt no interrupt will be generated. See RNG_ISR for an explanation on this interrupt." "0,1"
rgroup.long 0x104++0x3
line.long 0x0 "RNG_ISR,RNG status register. If corresponding RNG_IMR bit is unmasked. an interrupt will be generated."
hexmask.long 0x0 4.--31. 1. "RESERVED,RESERVED"
bitfld.long 0x0 3. "VN_ERR,1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical ZERO or ONE." "0,1"
bitfld.long 0x0 2. "CRNGT_ERR,1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal." "0,1"
bitfld.long 0x0 1. "AUTOCORR_ERR,1'b1 indicates Autocorrelation test failed four times in a row. When set RNG cease from functioning until next reset." "0,1"
newline
bitfld.long 0x0 0. "EHR_VALID,1'b1 indicates that 192 bits have been collected in the RNG and are ready to be read." "0,1"
group.long 0x108++0x7
line.long 0x0 "RNG_ICR,Interrupt/status bit clear Register."
hexmask.long 0x0 4.--31. 1. "RESERVED,RESERVED"
bitfld.long 0x0 3. "VN_ERR,Write 1'b1 - clear corresponding bit in RNG_ISR." "0,1"
bitfld.long 0x0 2. "CRNGT_ERR,Write 1'b1 - clear corresponding bit in RNG_ISR." "0,1"
bitfld.long 0x0 1. "AUTOCORR_ERR,Cannot be cleared by SW! Only RNG reset clears this bit." "0,1"
newline
bitfld.long 0x0 0. "EHR_VALID,Write 1'b1 - clear corresponding bit in RNG_ISR." "0,1"
line.long 0x4 "TRNG_CONFIG,Selecting the inverter-chain length."
hexmask.long 0x4 2.--31. 1. "RESERVED,RESERVED"
bitfld.long 0x4 0.--1. "RND_SRC_SEL,Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source)." "0,1,2,3"
rgroup.long 0x110++0x1B
line.long 0x0 "TRNG_VALID,192 bit collection indication."
hexmask.long 0x0 1.--31. 1. "RESERVED,RESERVED"
bitfld.long 0x0 0. "EHR_VALID,1'b1 indicates that collection of bits in the RNG is completed and data can be read from EHR_DATA register." "0,1"
line.long 0x4 "EHR_DATA0,RNG collected bits."
hexmask.long 0x4 0.--31. 1. "EHR_DATA0,Bits [31:0] of Entropy Holding Register (EHR) - RNG output register"
line.long 0x8 "EHR_DATA1,RNG collected bits."
hexmask.long 0x8 0.--31. 1. "EHR_DATA1,Bits [63:32] of Entropy Holding Register (EHR) - RNG output register"
line.long 0xC "EHR_DATA2,RNG collected bits."
hexmask.long 0xC 0.--31. 1. "EHR_DATA2,Bits [95:64] of Entropy Holding Register (EHR) - RNG output register"
line.long 0x10 "EHR_DATA3,RNG collected bits."
hexmask.long 0x10 0.--31. 1. "EHR_DATA3,Bits [127:96] of Entropy Holding Register (EHR) - RNG output register"
line.long 0x14 "EHR_DATA4,RNG collected bits."
hexmask.long 0x14 0.--31. 1. "EHR_DATA4,Bits [159:128] of Entropy Holding Register (EHR) - RNG output register"
line.long 0x18 "EHR_DATA5,RNG collected bits."
hexmask.long 0x18 0.--31. 1. "EHR_DATA5,Bits [191:160] of Entropy Holding Register (EHR) - RNG output register"
group.long 0x12C++0xF
line.long 0x0 "RND_SOURCE_ENABLE,Enable signal for the random source."
hexmask.long 0x0 1.--31. 1. "RESERVED,RESERVED"
bitfld.long 0x0 0. "RND_SRC_EN,* 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled" "0,1"
line.long 0x4 "SAMPLE_CNT1,Counts clocks between sampling of random bit."
hexmask.long 0x4 0.--31. 1. "SAMPLE_CNTR1,Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed the minimum value for sample counter must not be less then decimal seventeen"
line.long 0x8 "AUTOCORR_STATISTIC,Statistic about Autocorrelation test activations."
hexmask.long.word 0x8 22.--31. 1. "RESERVED,RESERVED"
hexmask.long.byte 0x8 14.--21. 1. "AUTOCORR_FAILS,Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."
hexmask.long.word 0x8 0.--13. 1. "AUTOCORR_TRYS,Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."
line.long 0xC "TRNG_DEBUG_CONTROL,Debug register."
bitfld.long 0xC 3. "AUTO_CORRELATE_BYPASS,When set the autocorrelation test in the TRNG module is bypassed." "0,1"
bitfld.long 0xC 2. "TRNG_CRNGT_BYPASS,When set the CRNGT test in the RNG is bypassed." "0,1"
bitfld.long 0xC 1. "VNC_BYPASS,When set the Von-Neuman balancer is bypassed (including the 32 consecutive bits test)." "0,1"
rbitfld.long 0xC 0. "RESERVED,N/A" "0,1"
group.long 0x140++0x3
line.long 0x0 "TRNG_SW_RESET,Generate internal SW reset within the RNG block."
hexmask.long 0x0 1.--31. 1. "RESERVED,RESERVED"
bitfld.long 0x0 0. "TRNG_SW_RESET,Writing 1'b1 to this register causes an internal RNG reset." "0,1"
group.long 0x1B4++0x3
line.long 0x0 "RNG_DEBUG_EN_INPUT,Enable the RNG debug mode"
hexmask.long 0x0 1.--31. 1. "RESERVED,RESERVED"
bitfld.long 0x0 0. "RNG_DEBUG_EN,* 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled" "0,1"
rgroup.long 0x1B8++0x3
line.long 0x0 "TRNG_BUSY,RNG Busy indication."
hexmask.long 0x0 1.--31. 1. "RESERVED,RESERVED"
bitfld.long 0x0 0. "TRNG_BUSY,Reflects rng_busy status." "0,1"
group.long 0x1BC++0x3
line.long 0x0 "RST_BITS_COUNTER,Reset the counter of collected bits in the RNG."
hexmask.long 0x0 1.--31. 1. "RESERVED,RESERVED"
bitfld.long 0x0 0. "RST_BITS_COUNTER,Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place." "0,1"
rgroup.long 0x1C0++0x3
line.long 0x0 "RNG_VERSION,Displays the version settings of the TRNG."
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,RESERVED"
bitfld.long 0x0 7. "RNG_USE_5_SBOXES,* 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES" "0,1"
bitfld.long 0x0 6. "RESEEDING_EXISTS,* 1'b1 - Exists. *1'b0 - Does not exist" "0,1"
bitfld.long 0x0 5. "KAT_EXISTS,* 1'b1 - Exists. *1'b0 - Does not exist" "0,1"
newline
bitfld.long 0x0 4. "PRNG_EXISTS,* 1'b1 - Exists. *1'b0 - Does not exist" "0,1"
bitfld.long 0x0 3. "TRNG_TESTS_BYPASS_EN,* 1'b1 - Exists. *1'b0 - Does not exist" "0,1"
bitfld.long 0x0 2. "AUTOCORR_EXISTS,* 1'b1 - Exists. *1'b0 - Does not exist" "0,1"
bitfld.long 0x0 1. "CRNGT_EXISTS,* 1'b1 - Exists. *1'b0 - Does not exist" "0,1"
newline
bitfld.long 0x0 0. "EHR_WIDTH_192,* 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR" "0,1"
rgroup.long 0x1E0++0xB
line.long 0x0 "RNG_BIST_CNTR_0,Collected BIST results."
hexmask.long.word 0x0 22.--31. 1. "RESERVED,RESERVED"
hexmask.long.tbyte 0x0 0.--21. 1. "ROSC_CNTR_VAL,Reflects the results of RNG BIST counter."
line.long 0x4 "RNG_BIST_CNTR_1,Collected BIST results."
hexmask.long.word 0x4 22.--31. 1. "RESERVED,RESERVED"
hexmask.long.tbyte 0x4 0.--21. 1. "ROSC_CNTR_VAL,Reflects the results of RNG BIST counter."
line.long 0x8 "RNG_BIST_CNTR_2,Collected BIST results."
hexmask.long.word 0x8 22.--31. 1. "RESERVED,RESERVED"
hexmask.long.tbyte 0x8 0.--21. 1. "ROSC_CNTR_VAL,Reflects the results of RNG BIST counter."
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "UART0"
base ad:0x40070000
group.long 0x0++0x7
line.long 0x0 "UARTDR,Data Register. UARTDR"
rbitfld.long 0x0 11. "OE,Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it." "0,1"
rbitfld.long 0x0 10. "BE,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). In FIFO mode this error is.." "0,1"
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rbitfld.long 0x0 9. "PE,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCR_H. In FIFO mode this error is associated with the character at the top.." "0,1"
rbitfld.long 0x0 8. "FE,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode this error is associated with the character at the top of the FIFO." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive (read) data character. Transmit (write) data character."
line.long 0x4 "UARTRSR,Receive Status Register/Error Clear Register. UARTRSR/UARTECR"
eventfld.long 0x4 3. "OE,Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the shift.." "0,1"
eventfld.long 0x4 2. "BE,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). This bit is cleared to 0 after a.." "0,1"
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eventfld.long 0x4 1. "PE,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode this.." "0,1"
eventfld.long 0x4 0. "FE,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode this error is associated with the character at the top of the.." "0,1"
rgroup.long 0x18++0x3
line.long 0x0 "UARTFR,Flag Register. UARTFR"
bitfld.long 0x0 8. "RI,Ring indicator. This bit is the complement of the UART ring indicator nUARTRI modem status input. That is the bit is 1 when nUARTRI is LOW." "0,1"
bitfld.long 0x0 7. "TXFE,Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register UARTLCR_H. If the FIFO is disabled this bit is set when the transmit holding register is empty. If the FIFO is enabled the TXFE bit is.." "0,1"
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bitfld.long 0x0 6. "RXFF,Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled this bit is set when the receive holding register is full. If the FIFO is enabled the RXFF bit is set when the.." "0,1"
bitfld.long 0x0 5. "TXFF,Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled this bit is set when the transmit holding register is full. If the FIFO is enabled the TXFF bit is set when the.." "0,1"
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bitfld.long 0x0 4. "RXFE,Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled this bit is set when the receive holding register is empty. If the FIFO is enabled the RXFE bit is set when the.." "0,1"
bitfld.long 0x0 3. "BUSY,UART busy. If this bit is set to 1 the UART is busy transmitting data. This bit remains set until the complete byte including all the stop bits has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty .." "0,1"
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bitfld.long 0x0 2. "DCD,Data carrier detect. This bit is the complement of the UART data carrier detect nUARTDCD modem status input. That is the bit is 1 when nUARTDCD is LOW." "0,1"
bitfld.long 0x0 1. "DSR,Data set ready. This bit is the complement of the UART data set ready nUARTDSR modem status input. That is the bit is 1 when nUARTDSR is LOW." "0,1"
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bitfld.long 0x0 0. "CTS,Clear to send. This bit is the complement of the UART clear to send nUARTCTS modem status input. That is the bit is 1 when nUARTCTS is LOW." "0,1"
group.long 0x20++0x1B
line.long 0x0 "UARTILPR,IrDA Low-Power Counter Register. UARTILPR"
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,8-bit low-power divisor value. These bits are cleared to 0 at reset."
line.long 0x4 "UARTIBRD,Integer Baud Rate Register. UARTIBRD"
hexmask.long.word 0x4 0.--15. 1. "BAUD_DIVINT,The integer baud rate divisor. These bits are cleared to 0 on reset."
line.long 0x8 "UARTFBRD,Fractional Baud Rate Register. UARTFBRD"
hexmask.long.byte 0x8 0.--5. 1. "BAUD_DIVFRAC,The fractional baud rate divisor. These bits are cleared to 0 on reset."
line.long 0xC "UARTLCR_H,Line Control Register. UARTLCR_H"
bitfld.long 0xC 7. "SPS,Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN.." "0: stick parity is disabled,1: either: * if the EPS bit is 0 then the parity.."
bitfld.long 0xC 5.--6. "WLEN,Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits." "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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bitfld.long 0xC 4. "FEN,Enable FIFOs: 0 = FIFOs are disabled (character mode) that is the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)." "0: FIFOs are disabled,1: transmit and receive FIFO buffers are enabled"
bitfld.long 0xC 3. "STP2,Two stop bits select. If this bit is set to 1 two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received." "0,1"
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bitfld.long 0xC 2. "EPS,Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an.." "0: odd parity,1: even parity"
bitfld.long 0xC 1. "PEN,Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled." "0: parity is disabled and no parity bit added to..,1: parity checking and generation is enabled"
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bitfld.long 0xC 0. "BRK,Send break. If this bit is set to 1 a low-level is continually output on the UARTTXD output after completing transmission of the current character. For the proper execution of the break command the software must set this bit for at least two.." "0,1"
line.long 0x10 "UARTCR,Control Register. UARTCR"
bitfld.long 0x10 15. "CTSEN,CTS hardware flow control enable. If this bit is set to 1 CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted." "0,1"
bitfld.long 0x10 14. "RTSEN,RTS hardware flow control enable. If this bit is set to 1 RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received." "0,1"
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bitfld.long 0x10 13. "OUT2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Ring Indicator (RI)." "0,1"
bitfld.long 0x10 12. "OUT1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)." "0,1"
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bitfld.long 0x10 11. "RTS,Request to send. This bit is the complement of the UART request to send nUARTRTS modem status output. That is when the bit is programmed to a 1 then nUARTRTS is LOW." "0,1"
bitfld.long 0x10 10. "DTR,Data transmit ready. This bit is the complement of the UART data transmit ready nUARTDTR modem status output. That is when the bit is programmed to a 1 then nUARTDTR is LOW." "0,1"
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bitfld.long 0x10 9. "RXE,Receive enable. If this bit is set to 1 the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception it.." "0,1"
bitfld.long 0x10 8. "TXE,Transmit enable. If this bit is set to 1 the transmit section of the UART is enabled. Data transmission occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of.." "0,1"
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bitfld.long 0x10 7. "LBE,Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register UARTTCR is set to 1 then the nSIROUT path is inverted and fed through to the SIRIN path. The SIRTEST bit in the test register.." "0,1"
bitfld.long 0x10 2. "SIRLP,SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0 low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1 low-level bits are.." "0,1"
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bitfld.long 0x10 1. "SIREN,SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated) and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH .." "0: IrDA SIR ENDEC is disabled,1: IrDA SIR ENDEC is enabled"
bitfld.long 0x10 0. "UARTEN,UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or.." "0: UART is disabled,1: the UART is enabled"
line.long 0x14 "UARTIFLS,Interrupt FIFO Level Select Register. UARTIFLS"
bitfld.long 0x14 3.--5. "RXIFLSEL,Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO.." "0: Receive FIFO becomes >= 1 / 8 full,1: Receive FIFO becomes >= 1 / 4 full,2: Receive FIFO becomes >= 1 / 2 full,3: Receive FIFO becomes >= 3 / 4 full,4: Receive FIFO becomes >= 7 / 8 full b101-b111 =..,?,?,?"
bitfld.long 0x14 0.--2. "TXIFLSEL,Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit.." "0: Transmit FIFO becomes <= 1 / 8 full,1: Transmit FIFO becomes <= 1 / 4 full,2: Transmit FIFO becomes <= 1 / 2 full,3: Transmit FIFO becomes <= 3 / 4 full,4: Transmit FIFO becomes <= 7 / 8 full b101-b111 =..,?,?,?"
line.long 0x18 "UARTIMSC,Interrupt Mask Set/Clear Register. UARTIMSC"
bitfld.long 0x18 10. "OEIM,Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1 the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask." "0,1"
bitfld.long 0x18 9. "BEIM,Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1 the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask." "0,1"
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bitfld.long 0x18 8. "PEIM,Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1 the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask." "0,1"
bitfld.long 0x18 7. "FEIM,Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1 the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask." "0,1"
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bitfld.long 0x18 6. "RTIM,Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1 the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask." "0,1"
bitfld.long 0x18 5. "TXIM,Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1 the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask." "0,1"
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bitfld.long 0x18 4. "RXIM,Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1 the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask." "0,1"
bitfld.long 0x18 3. "DSRMIM,nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1 the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask." "0,1"
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bitfld.long 0x18 2. "DCDMIM,nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1 the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask." "0,1"
bitfld.long 0x18 1. "CTSMIM,nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1 the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask." "0,1"
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bitfld.long 0x18 0. "RIMIM,nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1 the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask." "0,1"
rgroup.long 0x3C++0x7
line.long 0x0 "UARTRIS,Raw Interrupt Status Register. UARTRIS"
bitfld.long 0x0 10. "OERIS,Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt." "0,1"
bitfld.long 0x0 9. "BERIS,Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt." "0,1"
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bitfld.long 0x0 8. "PERIS,Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt." "0,1"
bitfld.long 0x0 7. "FERIS,Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt." "0,1"
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bitfld.long 0x0 6. "RTRIS,Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a" "0,1"
bitfld.long 0x0 5. "TXRIS,Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt." "0,1"
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bitfld.long 0x0 4. "RXRIS,Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt." "0,1"
bitfld.long 0x0 3. "DSRRMIS,nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt." "0,1"
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bitfld.long 0x0 2. "DCDRMIS,nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt." "0,1"
bitfld.long 0x0 1. "CTSRMIS,nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt." "0,1"
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bitfld.long 0x0 0. "RIRMIS,nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt." "0,1"
line.long 0x4 "UARTMIS,Masked Interrupt Status Register. UARTMIS"
bitfld.long 0x4 10. "OEMIS,Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt." "0,1"
bitfld.long 0x4 9. "BEMIS,Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt." "0,1"
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bitfld.long 0x4 8. "PEMIS,Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt." "0,1"
bitfld.long 0x4 7. "FEMIS,Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt." "0,1"
newline
bitfld.long 0x4 6. "RTMIS,Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt." "0,1"
bitfld.long 0x4 5. "TXMIS,Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt." "0,1"
newline
bitfld.long 0x4 4. "RXMIS,Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt." "0,1"
bitfld.long 0x4 3. "DSRMMIS,nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt." "0,1"
newline
bitfld.long 0x4 2. "DCDMMIS,nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt." "0,1"
bitfld.long 0x4 1. "CTSMMIS,nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt." "0,1"
newline
bitfld.long 0x4 0. "RIMMIS,nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt." "0,1"
group.long 0x44++0x7
line.long 0x0 "UARTICR,Interrupt Clear Register. UARTICR"
eventfld.long 0x0 10. "OEIC,Overrun error interrupt clear. Clears the UARTOEINTR interrupt." "0,1"
eventfld.long 0x0 9. "BEIC,Break error interrupt clear. Clears the UARTBEINTR interrupt." "0,1"
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eventfld.long 0x0 8. "PEIC,Parity error interrupt clear. Clears the UARTPEINTR interrupt." "0,1"
eventfld.long 0x0 7. "FEIC,Framing error interrupt clear. Clears the UARTFEINTR interrupt." "0,1"
newline
eventfld.long 0x0 6. "RTIC,Receive timeout interrupt clear. Clears the UARTRTINTR interrupt." "0,1"
eventfld.long 0x0 5. "TXIC,Transmit interrupt clear. Clears the UARTTXINTR interrupt." "0,1"
newline
eventfld.long 0x0 4. "RXIC,Receive interrupt clear. Clears the UARTRXINTR interrupt." "0,1"
eventfld.long 0x0 3. "DSRMIC,nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt." "0,1"
newline
eventfld.long 0x0 2. "DCDMIC,nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt." "0,1"
eventfld.long 0x0 1. "CTSMIC,nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt." "0,1"
newline
eventfld.long 0x0 0. "RIMIC,nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt." "0,1"
line.long 0x4 "UARTDMACR,DMA Control Register. UARTDMACR"
bitfld.long 0x4 2. "DMAONERR,DMA on error. If this bit is set to 1 the DMA receive request outputs UARTRXDMASREQ or UARTRXDMABREQ are disabled when the UART error interrupt is asserted." "0,1"
bitfld.long 0x4 1. "TXDMAE,Transmit DMA enable. If this bit is set to 1 DMA for the transmit FIFO is enabled." "0,1"
newline
bitfld.long 0x4 0. "RXDMAE,Receive DMA enable. If this bit is set to 1 DMA for the receive FIFO is enabled." "0,1"
rgroup.long 0xFE0++0x1F
line.long 0x0 "UARTPERIPHID0,UARTPeriphID0 Register"
hexmask.long.byte 0x0 0.--7. 1. "PARTNUMBER0,These bits read back as 0x11"
line.long 0x4 "UARTPERIPHID1,UARTPeriphID1 Register"
hexmask.long.byte 0x4 4.--7. 1. "DESIGNER0,These bits read back as 0x1"
hexmask.long.byte 0x4 0.--3. 1. "PARTNUMBER1,These bits read back as 0x0"
line.long 0x8 "UARTPERIPHID2,UARTPeriphID2 Register"
hexmask.long.byte 0x8 4.--7. 1. "REVISION,This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3"
hexmask.long.byte 0x8 0.--3. 1. "DESIGNER1,These bits read back as 0x4"
line.long 0xC "UARTPERIPHID3,UARTPeriphID3 Register"
hexmask.long.byte 0xC 0.--7. 1. "CONFIGURATION,These bits read back as 0x00"
line.long 0x10 "UARTPCELLID0,UARTPCellID0 Register"
hexmask.long.byte 0x10 0.--7. 1. "UARTPCELLID0,These bits read back as 0x0D"
line.long 0x14 "UARTPCELLID1,UARTPCellID1 Register"
hexmask.long.byte 0x14 0.--7. 1. "UARTPCELLID1,These bits read back as 0xF0"
line.long 0x18 "UARTPCELLID2,UARTPCellID2 Register"
hexmask.long.byte 0x18 0.--7. 1. "UARTPCELLID2,These bits read back as 0x05"
line.long 0x1C "UARTPCELLID3,UARTPCellID3 Register"
hexmask.long.byte 0x1C 0.--7. 1. "UARTPCELLID3,These bits read back as 0xB1"
tree.end
tree "UART1"
base ad:0x40078000
group.long 0x0++0x7
line.long 0x0 "UARTDR,Data Register. UARTDR"
rbitfld.long 0x0 11. "OE,Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it." "0,1"
rbitfld.long 0x0 10. "BE,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). In FIFO mode this error is.." "0,1"
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rbitfld.long 0x0 9. "PE,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCR_H. In FIFO mode this error is associated with the character at the top.." "0,1"
rbitfld.long 0x0 8. "FE,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode this error is associated with the character at the top of the FIFO." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive (read) data character. Transmit (write) data character."
line.long 0x4 "UARTRSR,Receive Status Register/Error Clear Register. UARTRSR/UARTECR"
eventfld.long 0x4 3. "OE,Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full only the contents of the shift.." "0,1"
eventfld.long 0x4 2. "BE,Break error. This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits). This bit is cleared to 0 after a.." "0,1"
newline
eventfld.long 0x4 1. "PE,Parity error. When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode this.." "0,1"
eventfld.long 0x4 0. "FE,Framing error. When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode this error is associated with the character at the top of the.." "0,1"
rgroup.long 0x18++0x3
line.long 0x0 "UARTFR,Flag Register. UARTFR"
bitfld.long 0x0 8. "RI,Ring indicator. This bit is the complement of the UART ring indicator nUARTRI modem status input. That is the bit is 1 when nUARTRI is LOW." "0,1"
bitfld.long 0x0 7. "TXFE,Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register UARTLCR_H. If the FIFO is disabled this bit is set when the transmit holding register is empty. If the FIFO is enabled the TXFE bit is.." "0,1"
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bitfld.long 0x0 6. "RXFF,Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled this bit is set when the receive holding register is full. If the FIFO is enabled the RXFF bit is set when the.." "0,1"
bitfld.long 0x0 5. "TXFF,Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled this bit is set when the transmit holding register is full. If the FIFO is enabled the TXFF bit is set when the.." "0,1"
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bitfld.long 0x0 4. "RXFE,Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled this bit is set when the receive holding register is empty. If the FIFO is enabled the RXFE bit is set when the.." "0,1"
bitfld.long 0x0 3. "BUSY,UART busy. If this bit is set to 1 the UART is busy transmitting data. This bit remains set until the complete byte including all the stop bits has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty .." "0,1"
newline
bitfld.long 0x0 2. "DCD,Data carrier detect. This bit is the complement of the UART data carrier detect nUARTDCD modem status input. That is the bit is 1 when nUARTDCD is LOW." "0,1"
bitfld.long 0x0 1. "DSR,Data set ready. This bit is the complement of the UART data set ready nUARTDSR modem status input. That is the bit is 1 when nUARTDSR is LOW." "0,1"
newline
bitfld.long 0x0 0. "CTS,Clear to send. This bit is the complement of the UART clear to send nUARTCTS modem status input. That is the bit is 1 when nUARTCTS is LOW." "0,1"
group.long 0x20++0x1B
line.long 0x0 "UARTILPR,IrDA Low-Power Counter Register. UARTILPR"
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,8-bit low-power divisor value. These bits are cleared to 0 at reset."
line.long 0x4 "UARTIBRD,Integer Baud Rate Register. UARTIBRD"
hexmask.long.word 0x4 0.--15. 1. "BAUD_DIVINT,The integer baud rate divisor. These bits are cleared to 0 on reset."
line.long 0x8 "UARTFBRD,Fractional Baud Rate Register. UARTFBRD"
hexmask.long.byte 0x8 0.--5. 1. "BAUD_DIVFRAC,The fractional baud rate divisor. These bits are cleared to 0 on reset."
line.long 0xC "UARTLCR_H,Line Control Register. UARTLCR_H"
bitfld.long 0xC 7. "SPS,Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN.." "0: stick parity is disabled,1: either: * if the EPS bit is 0 then the parity.."
bitfld.long 0xC 5.--6. "WLEN,Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits." "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
newline
bitfld.long 0xC 4. "FEN,Enable FIFOs: 0 = FIFOs are disabled (character mode) that is the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)." "0: FIFOs are disabled,1: transmit and receive FIFO buffers are enabled"
bitfld.long 0xC 3. "STP2,Two stop bits select. If this bit is set to 1 two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received." "0,1"
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bitfld.long 0xC 2. "EPS,Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an.." "0: odd parity,1: even parity"
bitfld.long 0xC 1. "PEN,Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled." "0: parity is disabled and no parity bit added to..,1: parity checking and generation is enabled"
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bitfld.long 0xC 0. "BRK,Send break. If this bit is set to 1 a low-level is continually output on the UARTTXD output after completing transmission of the current character. For the proper execution of the break command the software must set this bit for at least two.." "0,1"
line.long 0x10 "UARTCR,Control Register. UARTCR"
bitfld.long 0x10 15. "CTSEN,CTS hardware flow control enable. If this bit is set to 1 CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted." "0,1"
bitfld.long 0x10 14. "RTSEN,RTS hardware flow control enable. If this bit is set to 1 RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received." "0,1"
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bitfld.long 0x10 13. "OUT2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Ring Indicator (RI)." "0,1"
bitfld.long 0x10 12. "OUT1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)." "0,1"
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bitfld.long 0x10 11. "RTS,Request to send. This bit is the complement of the UART request to send nUARTRTS modem status output. That is when the bit is programmed to a 1 then nUARTRTS is LOW." "0,1"
bitfld.long 0x10 10. "DTR,Data transmit ready. This bit is the complement of the UART data transmit ready nUARTDTR modem status output. That is when the bit is programmed to a 1 then nUARTDTR is LOW." "0,1"
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bitfld.long 0x10 9. "RXE,Receive enable. If this bit is set to 1 the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception it.." "0,1"
bitfld.long 0x10 8. "TXE,Transmit enable. If this bit is set to 1 the transmit section of the UART is enabled. Data transmission occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of.." "0,1"
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bitfld.long 0x10 7. "LBE,Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register UARTTCR is set to 1 then the nSIROUT path is inverted and fed through to the SIRIN path. The SIRTEST bit in the test register.." "0,1"
bitfld.long 0x10 2. "SIRLP,SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0 low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1 low-level bits are.." "0,1"
newline
bitfld.long 0x10 1. "SIREN,SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated) and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH .." "0: IrDA SIR ENDEC is disabled,1: IrDA SIR ENDEC is enabled"
bitfld.long 0x10 0. "UARTEN,UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or.." "0: UART is disabled,1: the UART is enabled"
line.long 0x14 "UARTIFLS,Interrupt FIFO Level Select Register. UARTIFLS"
bitfld.long 0x14 3.--5. "RXIFLSEL,Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO.." "0: Receive FIFO becomes >= 1 / 8 full,1: Receive FIFO becomes >= 1 / 4 full,2: Receive FIFO becomes >= 1 / 2 full,3: Receive FIFO becomes >= 3 / 4 full,4: Receive FIFO becomes >= 7 / 8 full b101-b111 =..,?,?,?"
bitfld.long 0x14 0.--2. "TXIFLSEL,Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit.." "0: Transmit FIFO becomes <= 1 / 8 full,1: Transmit FIFO becomes <= 1 / 4 full,2: Transmit FIFO becomes <= 1 / 2 full,3: Transmit FIFO becomes <= 3 / 4 full,4: Transmit FIFO becomes <= 7 / 8 full b101-b111 =..,?,?,?"
line.long 0x18 "UARTIMSC,Interrupt Mask Set/Clear Register. UARTIMSC"
bitfld.long 0x18 10. "OEIM,Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1 the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask." "0,1"
bitfld.long 0x18 9. "BEIM,Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1 the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask." "0,1"
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bitfld.long 0x18 8. "PEIM,Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1 the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask." "0,1"
bitfld.long 0x18 7. "FEIM,Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1 the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask." "0,1"
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bitfld.long 0x18 6. "RTIM,Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1 the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask." "0,1"
bitfld.long 0x18 5. "TXIM,Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1 the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask." "0,1"
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bitfld.long 0x18 4. "RXIM,Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1 the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask." "0,1"
bitfld.long 0x18 3. "DSRMIM,nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1 the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask." "0,1"
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bitfld.long 0x18 2. "DCDMIM,nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1 the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask." "0,1"
bitfld.long 0x18 1. "CTSMIM,nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1 the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask." "0,1"
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bitfld.long 0x18 0. "RIMIM,nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1 the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask." "0,1"
rgroup.long 0x3C++0x7
line.long 0x0 "UARTRIS,Raw Interrupt Status Register. UARTRIS"
bitfld.long 0x0 10. "OERIS,Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt." "0,1"
bitfld.long 0x0 9. "BERIS,Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt." "0,1"
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bitfld.long 0x0 8. "PERIS,Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt." "0,1"
bitfld.long 0x0 7. "FERIS,Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt." "0,1"
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bitfld.long 0x0 6. "RTRIS,Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a" "0,1"
bitfld.long 0x0 5. "TXRIS,Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt." "0,1"
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bitfld.long 0x0 4. "RXRIS,Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt." "0,1"
bitfld.long 0x0 3. "DSRRMIS,nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt." "0,1"
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bitfld.long 0x0 2. "DCDRMIS,nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt." "0,1"
bitfld.long 0x0 1. "CTSRMIS,nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt." "0,1"
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bitfld.long 0x0 0. "RIRMIS,nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt." "0,1"
line.long 0x4 "UARTMIS,Masked Interrupt Status Register. UARTMIS"
bitfld.long 0x4 10. "OEMIS,Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt." "0,1"
bitfld.long 0x4 9. "BEMIS,Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt." "0,1"
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bitfld.long 0x4 8. "PEMIS,Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt." "0,1"
bitfld.long 0x4 7. "FEMIS,Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt." "0,1"
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bitfld.long 0x4 6. "RTMIS,Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt." "0,1"
bitfld.long 0x4 5. "TXMIS,Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt." "0,1"
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bitfld.long 0x4 4. "RXMIS,Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt." "0,1"
bitfld.long 0x4 3. "DSRMMIS,nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt." "0,1"
newline
bitfld.long 0x4 2. "DCDMMIS,nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt." "0,1"
bitfld.long 0x4 1. "CTSMMIS,nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt." "0,1"
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bitfld.long 0x4 0. "RIMMIS,nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt." "0,1"
group.long 0x44++0x7
line.long 0x0 "UARTICR,Interrupt Clear Register. UARTICR"
eventfld.long 0x0 10. "OEIC,Overrun error interrupt clear. Clears the UARTOEINTR interrupt." "0,1"
eventfld.long 0x0 9. "BEIC,Break error interrupt clear. Clears the UARTBEINTR interrupt." "0,1"
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eventfld.long 0x0 8. "PEIC,Parity error interrupt clear. Clears the UARTPEINTR interrupt." "0,1"
eventfld.long 0x0 7. "FEIC,Framing error interrupt clear. Clears the UARTFEINTR interrupt." "0,1"
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eventfld.long 0x0 6. "RTIC,Receive timeout interrupt clear. Clears the UARTRTINTR interrupt." "0,1"
eventfld.long 0x0 5. "TXIC,Transmit interrupt clear. Clears the UARTTXINTR interrupt." "0,1"
newline
eventfld.long 0x0 4. "RXIC,Receive interrupt clear. Clears the UARTRXINTR interrupt." "0,1"
eventfld.long 0x0 3. "DSRMIC,nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt." "0,1"
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eventfld.long 0x0 2. "DCDMIC,nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt." "0,1"
eventfld.long 0x0 1. "CTSMIC,nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt." "0,1"
newline
eventfld.long 0x0 0. "RIMIC,nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt." "0,1"
line.long 0x4 "UARTDMACR,DMA Control Register. UARTDMACR"
bitfld.long 0x4 2. "DMAONERR,DMA on error. If this bit is set to 1 the DMA receive request outputs UARTRXDMASREQ or UARTRXDMABREQ are disabled when the UART error interrupt is asserted." "0,1"
bitfld.long 0x4 1. "TXDMAE,Transmit DMA enable. If this bit is set to 1 DMA for the transmit FIFO is enabled." "0,1"
newline
bitfld.long 0x4 0. "RXDMAE,Receive DMA enable. If this bit is set to 1 DMA for the receive FIFO is enabled." "0,1"
rgroup.long 0xFE0++0x1F
line.long 0x0 "UARTPERIPHID0,UARTPeriphID0 Register"
hexmask.long.byte 0x0 0.--7. 1. "PARTNUMBER0,These bits read back as 0x11"
line.long 0x4 "UARTPERIPHID1,UARTPeriphID1 Register"
hexmask.long.byte 0x4 4.--7. 1. "DESIGNER0,These bits read back as 0x1"
hexmask.long.byte 0x4 0.--3. 1. "PARTNUMBER1,These bits read back as 0x0"
line.long 0x8 "UARTPERIPHID2,UARTPeriphID2 Register"
hexmask.long.byte 0x8 4.--7. 1. "REVISION,This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3"
hexmask.long.byte 0x8 0.--3. 1. "DESIGNER1,These bits read back as 0x4"
line.long 0xC "UARTPERIPHID3,UARTPeriphID3 Register"
hexmask.long.byte 0xC 0.--7. 1. "CONFIGURATION,These bits read back as 0x00"
line.long 0x10 "UARTPCELLID0,UARTPCellID0 Register"
hexmask.long.byte 0x10 0.--7. 1. "UARTPCELLID0,These bits read back as 0x0D"
line.long 0x14 "UARTPCELLID1,UARTPCellID1 Register"
hexmask.long.byte 0x14 0.--7. 1. "UARTPCELLID1,These bits read back as 0xF0"
line.long 0x18 "UARTPCELLID2,UARTPCellID2 Register"
hexmask.long.byte 0x18 0.--7. 1. "UARTPCELLID2,These bits read back as 0x05"
line.long 0x1C "UARTPCELLID3,UARTPCellID3 Register"
hexmask.long.byte 0x1C 0.--7. 1. "UARTPCELLID3,These bits read back as 0xB1"
tree.end
tree.end
tree "USB (Universal Serial Bus)"
base ad:0x0
tree "USB"
base ad:0x50110000
group.long 0x0++0x43
line.long 0x0 "ADDR_ENDP,Device address and endpoint control"
hexmask.long.byte 0x0 16.--19. 1. "ENDPOINT,Device endpoint to send data to. Only valid for HOST mode."
hexmask.long.byte 0x0 0.--6. 1. "ADDRESS,In device mode the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."
line.long 0x4 "ADDR_ENDP1,Interrupt endpoint 1. Only valid for HOST mode."
bitfld.long 0x4 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x4 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x4 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x4 0.--6. 1. "ADDRESS,Device address"
line.long 0x8 "ADDR_ENDP2,Interrupt endpoint 2. Only valid for HOST mode."
bitfld.long 0x8 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x8 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x8 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x8 0.--6. 1. "ADDRESS,Device address"
line.long 0xC "ADDR_ENDP3,Interrupt endpoint 3. Only valid for HOST mode."
bitfld.long 0xC 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0xC 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0xC 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0xC 0.--6. 1. "ADDRESS,Device address"
line.long 0x10 "ADDR_ENDP4,Interrupt endpoint 4. Only valid for HOST mode."
bitfld.long 0x10 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x10 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x10 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x10 0.--6. 1. "ADDRESS,Device address"
line.long 0x14 "ADDR_ENDP5,Interrupt endpoint 5. Only valid for HOST mode."
bitfld.long 0x14 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x14 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x14 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x14 0.--6. 1. "ADDRESS,Device address"
line.long 0x18 "ADDR_ENDP6,Interrupt endpoint 6. Only valid for HOST mode."
bitfld.long 0x18 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x18 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x18 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x18 0.--6. 1. "ADDRESS,Device address"
line.long 0x1C "ADDR_ENDP7,Interrupt endpoint 7. Only valid for HOST mode."
bitfld.long 0x1C 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x1C 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x1C 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x1C 0.--6. 1. "ADDRESS,Device address"
line.long 0x20 "ADDR_ENDP8,Interrupt endpoint 8. Only valid for HOST mode."
bitfld.long 0x20 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x20 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x20 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x20 0.--6. 1. "ADDRESS,Device address"
line.long 0x24 "ADDR_ENDP9,Interrupt endpoint 9. Only valid for HOST mode."
bitfld.long 0x24 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x24 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x24 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x24 0.--6. 1. "ADDRESS,Device address"
line.long 0x28 "ADDR_ENDP10,Interrupt endpoint 10. Only valid for HOST mode."
bitfld.long 0x28 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x28 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x28 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x28 0.--6. 1. "ADDRESS,Device address"
line.long 0x2C "ADDR_ENDP11,Interrupt endpoint 11. Only valid for HOST mode."
bitfld.long 0x2C 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x2C 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x2C 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x2C 0.--6. 1. "ADDRESS,Device address"
line.long 0x30 "ADDR_ENDP12,Interrupt endpoint 12. Only valid for HOST mode."
bitfld.long 0x30 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x30 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x30 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x30 0.--6. 1. "ADDRESS,Device address"
line.long 0x34 "ADDR_ENDP13,Interrupt endpoint 13. Only valid for HOST mode."
bitfld.long 0x34 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x34 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x34 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x34 0.--6. 1. "ADDRESS,Device address"
line.long 0x38 "ADDR_ENDP14,Interrupt endpoint 14. Only valid for HOST mode."
bitfld.long 0x38 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x38 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x38 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x38 0.--6. 1. "ADDRESS,Device address"
line.long 0x3C "ADDR_ENDP15,Interrupt endpoint 15. Only valid for HOST mode."
bitfld.long 0x3C 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1"
bitfld.long 0x3C 25. "INTEP_DIR,Direction of the interrupt endpoint. In=0 Out=1" "0,1"
newline
hexmask.long.byte 0x3C 16.--19. 1. "ENDPOINT,Endpoint number of the interrupt endpoint"
hexmask.long.byte 0x3C 0.--6. 1. "ADDRESS,Device address"
line.long 0x40 "MAIN_CTRL,Main control register"
bitfld.long 0x40 31. "SIM_TIMING,Reduced timings for simulation" "0,1"
bitfld.long 0x40 2. "PHY_ISO,Isolates USB phy after controller power-up" "0,1"
newline
bitfld.long 0x40 1. "HOST_NDEVICE,Device mode = 0 Host mode = 1" "0,1"
bitfld.long 0x40 0. "CONTROLLER_EN,Enable controller" "0,1"
wgroup.long 0x44++0x3
line.long 0x0 "SOF_WR,Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time."
hexmask.long.word 0x0 0.--10. 1. "COUNT"
rgroup.long 0x48++0x3
line.long 0x0 "SOF_RD,Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host."
hexmask.long.word 0x0 0.--10. 1. "COUNT"
group.long 0x4C++0xF
line.long 0x0 "SIE_CTRL,SIE control register"
bitfld.long 0x0 31. "EP0_INT_STALL,Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL" "0,1"
bitfld.long 0x0 30. "EP0_DOUBLE_BUF,Device: EP0 single buffered = 0 double buffered = 1" "0,1"
newline
bitfld.long 0x0 29. "EP0_INT_1BUF,Device: Set bit in BUFF_STATUS for every buffer completed on EP0" "0,1"
bitfld.long 0x0 28. "EP0_INT_2BUF,Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0" "0,1"
newline
bitfld.long 0x0 27. "EP0_INT_NAK,Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK" "0,1"
bitfld.long 0x0 26. "DIRECT_EN,Direct bus drive enable" "0,1"
newline
bitfld.long 0x0 25. "DIRECT_DP,Direct control of DP" "0,1"
bitfld.long 0x0 24. "DIRECT_DM,Direct control of DM" "0,1"
newline
bitfld.long 0x0 19. "EP0_STOP_ON_SHORT_PACKET,Device: Stop EP0 on a short packet." "0,1"
bitfld.long 0x0 18. "TRANSCEIVER_PD,Power down bus transceiver" "0,1"
newline
bitfld.long 0x0 17. "RPU_OPT,Device: Pull-up strength (0=1K2 1=2k3)" "0: 1K2,1: 2k3"
bitfld.long 0x0 16. "PULLUP_EN,Device: Enable pull up resistor" "0,1"
newline
bitfld.long 0x0 15. "PULLDOWN_EN,Host: Enable pull down resistors" "0,1"
bitfld.long 0x0 13. "RESET_BUS,Host: Reset bus" "0,1"
newline
bitfld.long 0x0 12. "RESUME,Device: Remote wakeup. Device can initiate its own resume after suspend." "0,1"
bitfld.long 0x0 11. "VBUS_EN,Host: Enable VBUS" "0,1"
newline
bitfld.long 0x0 10. "KEEP_ALIVE_EN,Host: Enable keep alive packet (for low speed bus)" "0,1"
bitfld.long 0x0 9. "SOF_EN,Host: Enable SOF generation (for full speed bus)" "0,1"
newline
bitfld.long 0x0 8. "SOF_SYNC,Host: Delay packet(s) until after SOF" "0,1"
bitfld.long 0x0 6. "PREAMBLE_EN,Host: Preable enable for LS device on FS hub" "0,1"
newline
bitfld.long 0x0 4. "STOP_TRANS,Host: Stop transaction" "0,1"
bitfld.long 0x0 3. "RECEIVE_DATA,Host: Receive transaction (IN to host)" "0,1"
newline
bitfld.long 0x0 2. "SEND_DATA,Host: Send transaction (OUT from host)" "0,1"
bitfld.long 0x0 1. "SEND_SETUP,Host: Send Setup packet" "0,1"
newline
bitfld.long 0x0 0. "START_TRANS,Host: Start transaction" "0,1"
line.long 0x4 "SIE_STATUS,SIE status register"
eventfld.long 0x4 31. "DATA_SEQ_ERROR,Data Sequence Error." "0,1"
eventfld.long 0x4 30. "ACK_REC,ACK received. Raised by both host and device." "0,1"
newline
eventfld.long 0x4 29. "STALL_REC,Host: STALL received" "0,1"
eventfld.long 0x4 28. "NAK_REC,Host: NAK received" "0,1"
newline
eventfld.long 0x4 27. "RX_TIMEOUT,RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec." "0,1"
eventfld.long 0x4 26. "RX_OVERFLOW,RX overflow is raised by the Serial RX engine if the incoming data is too fast." "0,1"
newline
eventfld.long 0x4 25. "BIT_STUFF_ERROR,Bit Stuff Error. Raised by the Serial RX engine." "0,1"
eventfld.long 0x4 24. "CRC_ERROR,CRC Error. Raised by the Serial RX engine." "0,1"
newline
eventfld.long 0x4 23. "ENDPOINT_ERROR,An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error." "0,1"
eventfld.long 0x4 19. "BUS_RESET,Device: bus reset received" "0,1"
newline
eventfld.long 0x4 18. "TRANS_COMPLETE,Transaction complete." "0,1"
eventfld.long 0x4 17. "SETUP_REC,Device: Setup packet received" "0,1"
newline
rbitfld.long 0x4 16. "CONNECTED,Device: connected" "0,1"
eventfld.long 0x4 12. "RX_SHORT_PACKET,Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status.." "0,1"
newline
eventfld.long 0x4 11. "RESUME,Host: Device has initiated a remote resume. Device: host has initiated a resume." "0,1"
rbitfld.long 0x4 10. "VBUS_OVER_CURR,VBUS over current detected" "0,1"
newline
rbitfld.long 0x4 8.--9. "SPEED,Host: device speed. Disconnected = 00 LS = 01 FS = 10" "0,1,2,3"
eventfld.long 0x4 4. "SUSPENDED,Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled." "0,1"
newline
rbitfld.long 0x4 2.--3. "LINE_STATE,USB bus line state" "0,1,2,3"
rbitfld.long 0x4 0. "VBUS_DETECTED,Device: VBUS Detected" "0,1"
line.long 0x8 "INT_EP_CTRL,interrupt endpoint control register"
hexmask.long.word 0x8 1.--15. 1. "INT_EP_ACTIVE,Host: Enable interrupt endpoint 1 -> 15"
line.long 0xC "BUFF_STATUS,Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed. so clearing the buffer status bit may instantly re set it on the.."
eventfld.long 0xC 31. "EP15_OUT" "0,1"
eventfld.long 0xC 30. "EP15_IN" "0,1"
newline
eventfld.long 0xC 29. "EP14_OUT" "0,1"
eventfld.long 0xC 28. "EP14_IN" "0,1"
newline
eventfld.long 0xC 27. "EP13_OUT" "0,1"
eventfld.long 0xC 26. "EP13_IN" "0,1"
newline
eventfld.long 0xC 25. "EP12_OUT" "0,1"
eventfld.long 0xC 24. "EP12_IN" "0,1"
newline
eventfld.long 0xC 23. "EP11_OUT" "0,1"
eventfld.long 0xC 22. "EP11_IN" "0,1"
newline
eventfld.long 0xC 21. "EP10_OUT" "0,1"
eventfld.long 0xC 20. "EP10_IN" "0,1"
newline
eventfld.long 0xC 19. "EP9_OUT" "0,1"
eventfld.long 0xC 18. "EP9_IN" "0,1"
newline
eventfld.long 0xC 17. "EP8_OUT" "0,1"
eventfld.long 0xC 16. "EP8_IN" "0,1"
newline
eventfld.long 0xC 15. "EP7_OUT" "0,1"
eventfld.long 0xC 14. "EP7_IN" "0,1"
newline
eventfld.long 0xC 13. "EP6_OUT" "0,1"
eventfld.long 0xC 12. "EP6_IN" "0,1"
newline
eventfld.long 0xC 11. "EP5_OUT" "0,1"
eventfld.long 0xC 10. "EP5_IN" "0,1"
newline
eventfld.long 0xC 9. "EP4_OUT" "0,1"
eventfld.long 0xC 8. "EP4_IN" "0,1"
newline
eventfld.long 0xC 7. "EP3_OUT" "0,1"
eventfld.long 0xC 6. "EP3_IN" "0,1"
newline
eventfld.long 0xC 5. "EP2_OUT" "0,1"
eventfld.long 0xC 4. "EP2_IN" "0,1"
newline
eventfld.long 0xC 3. "EP1_OUT" "0,1"
eventfld.long 0xC 2. "EP1_IN" "0,1"
newline
eventfld.long 0xC 1. "EP0_OUT" "0,1"
eventfld.long 0xC 0. "EP0_IN" "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "BUFF_CPU_SHOULD_HANDLE,Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered."
bitfld.long 0x0 31. "EP15_OUT" "0,1"
bitfld.long 0x0 30. "EP15_IN" "0,1"
newline
bitfld.long 0x0 29. "EP14_OUT" "0,1"
bitfld.long 0x0 28. "EP14_IN" "0,1"
newline
bitfld.long 0x0 27. "EP13_OUT" "0,1"
bitfld.long 0x0 26. "EP13_IN" "0,1"
newline
bitfld.long 0x0 25. "EP12_OUT" "0,1"
bitfld.long 0x0 24. "EP12_IN" "0,1"
newline
bitfld.long 0x0 23. "EP11_OUT" "0,1"
bitfld.long 0x0 22. "EP11_IN" "0,1"
newline
bitfld.long 0x0 21. "EP10_OUT" "0,1"
bitfld.long 0x0 20. "EP10_IN" "0,1"
newline
bitfld.long 0x0 19. "EP9_OUT" "0,1"
bitfld.long 0x0 18. "EP9_IN" "0,1"
newline
bitfld.long 0x0 17. "EP8_OUT" "0,1"
bitfld.long 0x0 16. "EP8_IN" "0,1"
newline
bitfld.long 0x0 15. "EP7_OUT" "0,1"
bitfld.long 0x0 14. "EP7_IN" "0,1"
newline
bitfld.long 0x0 13. "EP6_OUT" "0,1"
bitfld.long 0x0 12. "EP6_IN" "0,1"
newline
bitfld.long 0x0 11. "EP5_OUT" "0,1"
bitfld.long 0x0 10. "EP5_IN" "0,1"
newline
bitfld.long 0x0 9. "EP4_OUT" "0,1"
bitfld.long 0x0 8. "EP4_IN" "0,1"
newline
bitfld.long 0x0 7. "EP3_OUT" "0,1"
bitfld.long 0x0 6. "EP3_IN" "0,1"
newline
bitfld.long 0x0 5. "EP2_OUT" "0,1"
bitfld.long 0x0 4. "EP2_IN" "0,1"
newline
bitfld.long 0x0 3. "EP1_OUT" "0,1"
bitfld.long 0x0 2. "EP1_IN" "0,1"
newline
bitfld.long 0x0 1. "EP0_OUT" "0,1"
bitfld.long 0x0 0. "EP0_IN" "0,1"
group.long 0x60++0x2B
line.long 0x0 "EP_ABORT,Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is.."
bitfld.long 0x0 31. "EP15_OUT" "0,1"
bitfld.long 0x0 30. "EP15_IN" "0,1"
newline
bitfld.long 0x0 29. "EP14_OUT" "0,1"
bitfld.long 0x0 28. "EP14_IN" "0,1"
newline
bitfld.long 0x0 27. "EP13_OUT" "0,1"
bitfld.long 0x0 26. "EP13_IN" "0,1"
newline
bitfld.long 0x0 25. "EP12_OUT" "0,1"
bitfld.long 0x0 24. "EP12_IN" "0,1"
newline
bitfld.long 0x0 23. "EP11_OUT" "0,1"
bitfld.long 0x0 22. "EP11_IN" "0,1"
newline
bitfld.long 0x0 21. "EP10_OUT" "0,1"
bitfld.long 0x0 20. "EP10_IN" "0,1"
newline
bitfld.long 0x0 19. "EP9_OUT" "0,1"
bitfld.long 0x0 18. "EP9_IN" "0,1"
newline
bitfld.long 0x0 17. "EP8_OUT" "0,1"
bitfld.long 0x0 16. "EP8_IN" "0,1"
newline
bitfld.long 0x0 15. "EP7_OUT" "0,1"
bitfld.long 0x0 14. "EP7_IN" "0,1"
newline
bitfld.long 0x0 13. "EP6_OUT" "0,1"
bitfld.long 0x0 12. "EP6_IN" "0,1"
newline
bitfld.long 0x0 11. "EP5_OUT" "0,1"
bitfld.long 0x0 10. "EP5_IN" "0,1"
newline
bitfld.long 0x0 9. "EP4_OUT" "0,1"
bitfld.long 0x0 8. "EP4_IN" "0,1"
newline
bitfld.long 0x0 7. "EP3_OUT" "0,1"
bitfld.long 0x0 6. "EP3_IN" "0,1"
newline
bitfld.long 0x0 5. "EP2_OUT" "0,1"
bitfld.long 0x0 4. "EP2_IN" "0,1"
newline
bitfld.long 0x0 3. "EP1_OUT" "0,1"
bitfld.long 0x0 2. "EP1_IN" "0,1"
newline
bitfld.long 0x0 1. "EP0_OUT" "0,1"
bitfld.long 0x0 0. "EP0_IN" "0,1"
line.long 0x4 "EP_ABORT_DONE,Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register."
eventfld.long 0x4 31. "EP15_OUT" "0,1"
eventfld.long 0x4 30. "EP15_IN" "0,1"
newline
eventfld.long 0x4 29. "EP14_OUT" "0,1"
eventfld.long 0x4 28. "EP14_IN" "0,1"
newline
eventfld.long 0x4 27. "EP13_OUT" "0,1"
eventfld.long 0x4 26. "EP13_IN" "0,1"
newline
eventfld.long 0x4 25. "EP12_OUT" "0,1"
eventfld.long 0x4 24. "EP12_IN" "0,1"
newline
eventfld.long 0x4 23. "EP11_OUT" "0,1"
eventfld.long 0x4 22. "EP11_IN" "0,1"
newline
eventfld.long 0x4 21. "EP10_OUT" "0,1"
eventfld.long 0x4 20. "EP10_IN" "0,1"
newline
eventfld.long 0x4 19. "EP9_OUT" "0,1"
eventfld.long 0x4 18. "EP9_IN" "0,1"
newline
eventfld.long 0x4 17. "EP8_OUT" "0,1"
eventfld.long 0x4 16. "EP8_IN" "0,1"
newline
eventfld.long 0x4 15. "EP7_OUT" "0,1"
eventfld.long 0x4 14. "EP7_IN" "0,1"
newline
eventfld.long 0x4 13. "EP6_OUT" "0,1"
eventfld.long 0x4 12. "EP6_IN" "0,1"
newline
eventfld.long 0x4 11. "EP5_OUT" "0,1"
eventfld.long 0x4 10. "EP5_IN" "0,1"
newline
eventfld.long 0x4 9. "EP4_OUT" "0,1"
eventfld.long 0x4 8. "EP4_IN" "0,1"
newline
eventfld.long 0x4 7. "EP3_OUT" "0,1"
eventfld.long 0x4 6. "EP3_IN" "0,1"
newline
eventfld.long 0x4 5. "EP2_OUT" "0,1"
eventfld.long 0x4 4. "EP2_IN" "0,1"
newline
eventfld.long 0x4 3. "EP1_OUT" "0,1"
eventfld.long 0x4 2. "EP1_IN" "0,1"
newline
eventfld.long 0x4 1. "EP0_OUT" "0,1"
eventfld.long 0x4 0. "EP0_IN" "0,1"
line.long 0x8 "EP_STALL_ARM,Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL.."
bitfld.long 0x8 1. "EP0_OUT" "0,1"
bitfld.long 0x8 0. "EP0_IN" "0,1"
line.long 0xC "NAK_POLL,Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK."
hexmask.long.byte 0xC 28.--31. 1. "RETRY_COUNT_HI,Bits 9:6 of nak_retry count"
eventfld.long 0xC 27. "EPX_STOPPED_ON_NAK,EPX polling has stopped because a nak was received" "0,1"
newline
bitfld.long 0xC 26. "STOP_EPX_ON_NAK,Stop polling epx when a nak is received" "0,1"
hexmask.long.word 0xC 16.--25. 1. "DELAY_FS,NAK polling interval for a full speed device"
newline
hexmask.long.byte 0xC 10.--15. 1. "RETRY_COUNT_LO,Bits 5:0 of nak_retry_count"
hexmask.long.word 0xC 0.--9. 1. "DELAY_LS,NAK polling interval for a low speed device"
line.long 0x10 "EP_STATUS_STALL_NAK,Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register."
eventfld.long 0x10 31. "EP15_OUT" "0,1"
eventfld.long 0x10 30. "EP15_IN" "0,1"
newline
eventfld.long 0x10 29. "EP14_OUT" "0,1"
eventfld.long 0x10 28. "EP14_IN" "0,1"
newline
eventfld.long 0x10 27. "EP13_OUT" "0,1"
eventfld.long 0x10 26. "EP13_IN" "0,1"
newline
eventfld.long 0x10 25. "EP12_OUT" "0,1"
eventfld.long 0x10 24. "EP12_IN" "0,1"
newline
eventfld.long 0x10 23. "EP11_OUT" "0,1"
eventfld.long 0x10 22. "EP11_IN" "0,1"
newline
eventfld.long 0x10 21. "EP10_OUT" "0,1"
eventfld.long 0x10 20. "EP10_IN" "0,1"
newline
eventfld.long 0x10 19. "EP9_OUT" "0,1"
eventfld.long 0x10 18. "EP9_IN" "0,1"
newline
eventfld.long 0x10 17. "EP8_OUT" "0,1"
eventfld.long 0x10 16. "EP8_IN" "0,1"
newline
eventfld.long 0x10 15. "EP7_OUT" "0,1"
eventfld.long 0x10 14. "EP7_IN" "0,1"
newline
eventfld.long 0x10 13. "EP6_OUT" "0,1"
eventfld.long 0x10 12. "EP6_IN" "0,1"
newline
eventfld.long 0x10 11. "EP5_OUT" "0,1"
eventfld.long 0x10 10. "EP5_IN" "0,1"
newline
eventfld.long 0x10 9. "EP4_OUT" "0,1"
eventfld.long 0x10 8. "EP4_IN" "0,1"
newline
eventfld.long 0x10 7. "EP3_OUT" "0,1"
eventfld.long 0x10 6. "EP3_IN" "0,1"
newline
eventfld.long 0x10 5. "EP2_OUT" "0,1"
eventfld.long 0x10 4. "EP2_IN" "0,1"
newline
eventfld.long 0x10 3. "EP1_OUT" "0,1"
eventfld.long 0x10 2. "EP1_IN" "0,1"
newline
eventfld.long 0x10 1. "EP0_OUT" "0,1"
eventfld.long 0x10 0. "EP0_IN" "0,1"
line.long 0x14 "USB_MUXING,Where to connect the USB controller. Should be to_phy by default."
bitfld.long 0x14 31. "SWAP_DPDM,Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB." "0,1"
bitfld.long 0x14 4. "USBPHY_AS_GPIO,Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller." "0,1"
newline
bitfld.long 0x14 3. "SOFTCON" "0,1"
bitfld.long 0x14 2. "TO_DIGITAL_PAD" "0,1"
newline
bitfld.long 0x14 1. "TO_EXTPHY" "0,1"
bitfld.long 0x14 0. "TO_PHY" "0,1"
line.long 0x18 "USB_PWR,Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."
bitfld.long 0x18 5. "OVERCURR_DETECT_EN" "0,1"
bitfld.long 0x18 4. "OVERCURR_DETECT" "0,1"
newline
bitfld.long 0x18 3. "VBUS_DETECT_OVERRIDE_EN" "0,1"
bitfld.long 0x18 2. "VBUS_DETECT" "0,1"
newline
bitfld.long 0x18 1. "VBUS_EN_OVERRIDE_EN" "0,1"
bitfld.long 0x18 0. "VBUS_EN" "0,1"
line.long 0x1C "USBPHY_DIRECT,This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."
bitfld.long 0x1C 25. "RX_DM_OVERRIDE,Override rx_dm value into controller" "0,1"
bitfld.long 0x1C 24. "RX_DP_OVERRIDE,Override rx_dp value into controller" "0,1"
newline
bitfld.long 0x1C 23. "RX_DD_OVERRIDE,Override rx_dd value into controller" "0,1"
rbitfld.long 0x1C 22. "DM_OVV,DM over voltage" "0,1"
newline
rbitfld.long 0x1C 21. "DP_OVV,DP over voltage" "0,1"
rbitfld.long 0x1C 20. "DM_OVCN,DM overcurrent" "0,1"
newline
rbitfld.long 0x1C 19. "DP_OVCN,DP overcurrent" "0,1"
rbitfld.long 0x1C 18. "RX_DM,DPM pin state" "0,1"
newline
rbitfld.long 0x1C 17. "RX_DP,DPP pin state" "0,1"
rbitfld.long 0x1C 16. "RX_DD,Differential RX" "0,1"
newline
bitfld.long 0x1C 15. "TX_DIFFMODE,TX_DIFFMODE=0: Single ended mode" "0: Single ended mode,1: Differential drive mode"
bitfld.long 0x1C 14. "TX_FSSLEW,TX_FSSLEW=0: Low speed slew rate" "0: Low speed slew rate,1: Full speed slew rate"
newline
bitfld.long 0x1C 13. "TX_PD,TX power down override (if override enable is set). 1 = powered down." "?,1: powered down"
bitfld.long 0x1C 12. "RX_PD,RX power down override (if override enable is set). 1 = powered down." "?,1: powered down"
newline
bitfld.long 0x1C 11. "TX_DM,Output data. TX_DIFFMODE=1 Ignored" "0,1"
bitfld.long 0x1C 10. "TX_DP,Output data. If TX_DIFFMODE=1 Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP DPM=~TX_DP" "0,1"
newline
bitfld.long 0x1C 9. "TX_DM_OE,Output enable. If TX_DIFFMODE=1 Ignored." "0,1"
bitfld.long 0x1C 8. "TX_DP_OE,Output enable. If TX_DIFFMODE=1 OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving" "0,1"
newline
bitfld.long 0x1C 6. "DM_PULLDN_EN,DM pull down enable" "0,1"
bitfld.long 0x1C 5. "DM_PULLUP_EN,DM pull up enable" "0,1"
newline
bitfld.long 0x1C 4. "DM_PULLUP_HISEL,Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2" "0,1"
bitfld.long 0x1C 2. "DP_PULLDN_EN,DP pull down enable" "0,1"
newline
bitfld.long 0x1C 1. "DP_PULLUP_EN,DP pull up enable" "0,1"
bitfld.long 0x1C 0. "DP_PULLUP_HISEL,Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2" "0,1"
line.long 0x20 "USBPHY_DIRECT_OVERRIDE,Override enable for each control in usbphy_direct"
bitfld.long 0x20 18. "RX_DM_OVERRIDE_EN" "0,1"
bitfld.long 0x20 17. "RX_DP_OVERRIDE_EN" "0,1"
newline
bitfld.long 0x20 16. "RX_DD_OVERRIDE_EN" "0,1"
bitfld.long 0x20 15. "TX_DIFFMODE_OVERRIDE_EN" "0,1"
newline
bitfld.long 0x20 12. "DM_PULLUP_OVERRIDE_EN" "0,1"
bitfld.long 0x20 11. "TX_FSSLEW_OVERRIDE_EN" "0,1"
newline
bitfld.long 0x20 10. "TX_PD_OVERRIDE_EN" "0,1"
bitfld.long 0x20 9. "RX_PD_OVERRIDE_EN" "0,1"
newline
bitfld.long 0x20 8. "TX_DM_OVERRIDE_EN" "0,1"
bitfld.long 0x20 7. "TX_DP_OVERRIDE_EN" "0,1"
newline
bitfld.long 0x20 6. "TX_DM_OE_OVERRIDE_EN" "0,1"
bitfld.long 0x20 5. "TX_DP_OE_OVERRIDE_EN" "0,1"
newline
bitfld.long 0x20 4. "DM_PULLDN_EN_OVERRIDE_EN" "0,1"
bitfld.long 0x20 3. "DP_PULLDN_EN_OVERRIDE_EN" "0,1"
newline
bitfld.long 0x20 2. "DP_PULLUP_EN_OVERRIDE_EN" "0,1"
bitfld.long 0x20 1. "DM_PULLUP_HISEL_OVERRIDE_EN" "0,1"
newline
bitfld.long 0x20 0. "DP_PULLUP_HISEL_OVERRIDE_EN" "0,1"
line.long 0x24 "USBPHY_TRIM,Used to adjust trim values of USB phy pull down resistors."
hexmask.long.byte 0x24 8.--12. 1. "DM_PULLDN_TRIM,Value to drive to USB PHY"
hexmask.long.byte 0x24 0.--4. 1. "DP_PULLDN_TRIM,Value to drive to USB PHY"
line.long 0x28 "LINESTATE_TUNING,Used for debug only."
hexmask.long.byte 0x28 8.--11. 1. "SPARE_FIX"
bitfld.long 0x28 7. "DEV_LS_WAKE_FIX,Device - exit suspend on any non-idle signalling not qualified with a 1ms timer" "0,1"
newline
bitfld.long 0x28 6. "DEV_RX_ERR_QUIESCE,Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet." "0,1"
bitfld.long 0x28 5. "SIE_RX_CHATTER_SE0_FIX,RX - when recovering from line chatter or bitstuff errors treat SE0 as the end of chatter as well as" "0,1"
newline
bitfld.long 0x28 4. "SIE_RX_BITSTUFF_FIX,RX - when a bitstuff error is signalled by rx_dasm unconditionally terminate RX decode to" "0,1"
bitfld.long 0x28 3. "DEV_BUFF_CONTROL_DOUBLE_READ_FIX,Device - the controller FSM performs two reads of the buffer status memory address to" "0,1"
newline
bitfld.long 0x28 2. "MULTI_HUB_FIX,Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays." "0,1"
bitfld.long 0x28 1. "LINESTATE_DELAY,Device/Host - add an extra 1-bit debounce of linestate sampling." "0,1"
newline
bitfld.long 0x28 0. "RCV_DELAY,Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs." "0,1"
rgroup.long 0x8C++0x3
line.long 0x0 "INTR,Raw Interrupts"
bitfld.long 0x0 23. "EPX_STOPPED_ON_NAK,Source: NAK_POLL.EPX_STOPPED_ON_NAK" "0,1"
bitfld.long 0x0 22. "DEV_SM_WATCHDOG_FIRED,Source: DEV_SM_WATCHDOG.FIRED" "0,1"
newline
bitfld.long 0x0 21. "ENDPOINT_ERROR,Source: SIE_STATUS.ENDPOINT_ERROR" "0,1"
bitfld.long 0x0 20. "RX_SHORT_PACKET,Source: SIE_STATUS.RX_SHORT_PACKET" "0,1"
newline
bitfld.long 0x0 19. "EP_STALL_NAK,Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK." "0,1"
bitfld.long 0x0 18. "ABORT_DONE,Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE." "0,1"
newline
bitfld.long 0x0 17. "DEV_SOF,Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD" "0,1"
bitfld.long 0x0 16. "SETUP_REQ,Device. Source: SIE_STATUS.SETUP_REC" "0,1"
newline
bitfld.long 0x0 15. "DEV_RESUME_FROM_HOST,Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME" "0,1"
bitfld.long 0x0 14. "DEV_SUSPEND,Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED" "0,1"
newline
bitfld.long 0x0 13. "DEV_CONN_DIS,Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED" "0,1"
bitfld.long 0x0 12. "BUS_RESET,Source: SIE_STATUS.BUS_RESET" "0,1"
newline
bitfld.long 0x0 11. "VBUS_DETECT,Source: SIE_STATUS.VBUS_DETECTED" "0,1"
bitfld.long 0x0 10. "STALL,Source: SIE_STATUS.STALL_REC" "0,1"
newline
bitfld.long 0x0 9. "ERROR_CRC,Source: SIE_STATUS.CRC_ERROR" "0,1"
bitfld.long 0x0 8. "ERROR_BIT_STUFF,Source: SIE_STATUS.BIT_STUFF_ERROR" "0,1"
newline
bitfld.long 0x0 7. "ERROR_RX_OVERFLOW,Source: SIE_STATUS.RX_OVERFLOW" "0,1"
bitfld.long 0x0 6. "ERROR_RX_TIMEOUT,Source: SIE_STATUS.RX_TIMEOUT" "0,1"
newline
bitfld.long 0x0 5. "ERROR_DATA_SEQ,Source: SIE_STATUS.DATA_SEQ_ERROR" "0,1"
bitfld.long 0x0 4. "BUFF_STATUS,Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS." "0,1"
newline
bitfld.long 0x0 3. "TRANS_COMPLETE,Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit." "0,1"
bitfld.long 0x0 2. "HOST_SOF,Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD" "0,1"
newline
bitfld.long 0x0 1. "HOST_RESUME,Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME" "0,1"
bitfld.long 0x0 0. "HOST_CONN_DIS,Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED" "0,1"
group.long 0x90++0x7
line.long 0x0 "INTE,Interrupt Enable"
bitfld.long 0x0 23. "EPX_STOPPED_ON_NAK,Source: NAK_POLL.EPX_STOPPED_ON_NAK" "0,1"
bitfld.long 0x0 22. "DEV_SM_WATCHDOG_FIRED,Source: DEV_SM_WATCHDOG.FIRED" "0,1"
newline
bitfld.long 0x0 21. "ENDPOINT_ERROR,Source: SIE_STATUS.ENDPOINT_ERROR" "0,1"
bitfld.long 0x0 20. "RX_SHORT_PACKET,Source: SIE_STATUS.RX_SHORT_PACKET" "0,1"
newline
bitfld.long 0x0 19. "EP_STALL_NAK,Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK." "0,1"
bitfld.long 0x0 18. "ABORT_DONE,Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE." "0,1"
newline
bitfld.long 0x0 17. "DEV_SOF,Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD" "0,1"
bitfld.long 0x0 16. "SETUP_REQ,Device. Source: SIE_STATUS.SETUP_REC" "0,1"
newline
bitfld.long 0x0 15. "DEV_RESUME_FROM_HOST,Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME" "0,1"
bitfld.long 0x0 14. "DEV_SUSPEND,Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED" "0,1"
newline
bitfld.long 0x0 13. "DEV_CONN_DIS,Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED" "0,1"
bitfld.long 0x0 12. "BUS_RESET,Source: SIE_STATUS.BUS_RESET" "0,1"
newline
bitfld.long 0x0 11. "VBUS_DETECT,Source: SIE_STATUS.VBUS_DETECTED" "0,1"
bitfld.long 0x0 10. "STALL,Source: SIE_STATUS.STALL_REC" "0,1"
newline
bitfld.long 0x0 9. "ERROR_CRC,Source: SIE_STATUS.CRC_ERROR" "0,1"
bitfld.long 0x0 8. "ERROR_BIT_STUFF,Source: SIE_STATUS.BIT_STUFF_ERROR" "0,1"
newline
bitfld.long 0x0 7. "ERROR_RX_OVERFLOW,Source: SIE_STATUS.RX_OVERFLOW" "0,1"
bitfld.long 0x0 6. "ERROR_RX_TIMEOUT,Source: SIE_STATUS.RX_TIMEOUT" "0,1"
newline
bitfld.long 0x0 5. "ERROR_DATA_SEQ,Source: SIE_STATUS.DATA_SEQ_ERROR" "0,1"
bitfld.long 0x0 4. "BUFF_STATUS,Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS." "0,1"
newline
bitfld.long 0x0 3. "TRANS_COMPLETE,Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit." "0,1"
bitfld.long 0x0 2. "HOST_SOF,Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD" "0,1"
newline
bitfld.long 0x0 1. "HOST_RESUME,Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME" "0,1"
bitfld.long 0x0 0. "HOST_CONN_DIS,Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED" "0,1"
line.long 0x4 "INTF,Interrupt Force"
bitfld.long 0x4 23. "EPX_STOPPED_ON_NAK,Source: NAK_POLL.EPX_STOPPED_ON_NAK" "0,1"
bitfld.long 0x4 22. "DEV_SM_WATCHDOG_FIRED,Source: DEV_SM_WATCHDOG.FIRED" "0,1"
newline
bitfld.long 0x4 21. "ENDPOINT_ERROR,Source: SIE_STATUS.ENDPOINT_ERROR" "0,1"
bitfld.long 0x4 20. "RX_SHORT_PACKET,Source: SIE_STATUS.RX_SHORT_PACKET" "0,1"
newline
bitfld.long 0x4 19. "EP_STALL_NAK,Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK." "0,1"
bitfld.long 0x4 18. "ABORT_DONE,Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE." "0,1"
newline
bitfld.long 0x4 17. "DEV_SOF,Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD" "0,1"
bitfld.long 0x4 16. "SETUP_REQ,Device. Source: SIE_STATUS.SETUP_REC" "0,1"
newline
bitfld.long 0x4 15. "DEV_RESUME_FROM_HOST,Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME" "0,1"
bitfld.long 0x4 14. "DEV_SUSPEND,Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED" "0,1"
newline
bitfld.long 0x4 13. "DEV_CONN_DIS,Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED" "0,1"
bitfld.long 0x4 12. "BUS_RESET,Source: SIE_STATUS.BUS_RESET" "0,1"
newline
bitfld.long 0x4 11. "VBUS_DETECT,Source: SIE_STATUS.VBUS_DETECTED" "0,1"
bitfld.long 0x4 10. "STALL,Source: SIE_STATUS.STALL_REC" "0,1"
newline
bitfld.long 0x4 9. "ERROR_CRC,Source: SIE_STATUS.CRC_ERROR" "0,1"
bitfld.long 0x4 8. "ERROR_BIT_STUFF,Source: SIE_STATUS.BIT_STUFF_ERROR" "0,1"
newline
bitfld.long 0x4 7. "ERROR_RX_OVERFLOW,Source: SIE_STATUS.RX_OVERFLOW" "0,1"
bitfld.long 0x4 6. "ERROR_RX_TIMEOUT,Source: SIE_STATUS.RX_TIMEOUT" "0,1"
newline
bitfld.long 0x4 5. "ERROR_DATA_SEQ,Source: SIE_STATUS.DATA_SEQ_ERROR" "0,1"
bitfld.long 0x4 4. "BUFF_STATUS,Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS." "0,1"
newline
bitfld.long 0x4 3. "TRANS_COMPLETE,Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit." "0,1"
bitfld.long 0x4 2. "HOST_SOF,Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD" "0,1"
newline
bitfld.long 0x4 1. "HOST_RESUME,Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME" "0,1"
bitfld.long 0x4 0. "HOST_CONN_DIS,Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED" "0,1"
rgroup.long 0x98++0x3
line.long 0x0 "INTS,Interrupt status after masking & forcing"
bitfld.long 0x0 23. "EPX_STOPPED_ON_NAK,Source: NAK_POLL.EPX_STOPPED_ON_NAK" "0,1"
bitfld.long 0x0 22. "DEV_SM_WATCHDOG_FIRED,Source: DEV_SM_WATCHDOG.FIRED" "0,1"
newline
bitfld.long 0x0 21. "ENDPOINT_ERROR,Source: SIE_STATUS.ENDPOINT_ERROR" "0,1"
bitfld.long 0x0 20. "RX_SHORT_PACKET,Source: SIE_STATUS.RX_SHORT_PACKET" "0,1"
newline
bitfld.long 0x0 19. "EP_STALL_NAK,Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK." "0,1"
bitfld.long 0x0 18. "ABORT_DONE,Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE." "0,1"
newline
bitfld.long 0x0 17. "DEV_SOF,Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD" "0,1"
bitfld.long 0x0 16. "SETUP_REQ,Device. Source: SIE_STATUS.SETUP_REC" "0,1"
newline
bitfld.long 0x0 15. "DEV_RESUME_FROM_HOST,Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME" "0,1"
bitfld.long 0x0 14. "DEV_SUSPEND,Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED" "0,1"
newline
bitfld.long 0x0 13. "DEV_CONN_DIS,Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED" "0,1"
bitfld.long 0x0 12. "BUS_RESET,Source: SIE_STATUS.BUS_RESET" "0,1"
newline
bitfld.long 0x0 11. "VBUS_DETECT,Source: SIE_STATUS.VBUS_DETECTED" "0,1"
bitfld.long 0x0 10. "STALL,Source: SIE_STATUS.STALL_REC" "0,1"
newline
bitfld.long 0x0 9. "ERROR_CRC,Source: SIE_STATUS.CRC_ERROR" "0,1"
bitfld.long 0x0 8. "ERROR_BIT_STUFF,Source: SIE_STATUS.BIT_STUFF_ERROR" "0,1"
newline
bitfld.long 0x0 7. "ERROR_RX_OVERFLOW,Source: SIE_STATUS.RX_OVERFLOW" "0,1"
bitfld.long 0x0 6. "ERROR_RX_TIMEOUT,Source: SIE_STATUS.RX_TIMEOUT" "0,1"
newline
bitfld.long 0x0 5. "ERROR_DATA_SEQ,Source: SIE_STATUS.DATA_SEQ_ERROR" "0,1"
bitfld.long 0x0 4. "BUFF_STATUS,Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS." "0,1"
newline
bitfld.long 0x0 3. "TRANS_COMPLETE,Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit." "0,1"
bitfld.long 0x0 2. "HOST_SOF,Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD" "0,1"
newline
bitfld.long 0x0 1. "HOST_RESUME,Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME" "0,1"
bitfld.long 0x0 0. "HOST_CONN_DIS,Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED" "0,1"
rgroup.long 0x100++0xB
line.long 0x0 "SOF_TIMESTAMP_RAW,Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events."
hexmask.long.tbyte 0x0 0.--20. 1. "SOF_TIMESTAMP_RAW"
line.long 0x4 "SOF_TIMESTAMP_LAST,Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred."
hexmask.long.tbyte 0x4 0.--20. 1. "SOF_TIMESTAMP_LAST"
line.long 0x8 "SM_STATE"
hexmask.long.byte 0x8 8.--11. 1. "RX_DASM"
bitfld.long 0x8 5.--7. "BC_STATE" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 0.--4. 1. "STATE"
group.long 0x10C++0xB
line.long 0x0 "EP_TX_ERROR,TX error count for each endpoint. Write to each field to reset the counter to 0."
eventfld.long 0x0 30.--31. "EP15" "0,1,2,3"
eventfld.long 0x0 28.--29. "EP14" "0,1,2,3"
newline
eventfld.long 0x0 26.--27. "EP13" "0,1,2,3"
eventfld.long 0x0 24.--25. "EP12" "0,1,2,3"
newline
eventfld.long 0x0 22.--23. "EP11" "0,1,2,3"
eventfld.long 0x0 20.--21. "EP10" "0,1,2,3"
newline
eventfld.long 0x0 18.--19. "EP9" "0,1,2,3"
eventfld.long 0x0 16.--17. "EP8" "0,1,2,3"
newline
eventfld.long 0x0 14.--15. "EP7" "0,1,2,3"
eventfld.long 0x0 12.--13. "EP6" "0,1,2,3"
newline
eventfld.long 0x0 10.--11. "EP5" "0,1,2,3"
eventfld.long 0x0 8.--9. "EP4" "0,1,2,3"
newline
eventfld.long 0x0 6.--7. "EP3" "0,1,2,3"
eventfld.long 0x0 4.--5. "EP2" "0,1,2,3"
newline
eventfld.long 0x0 2.--3. "EP1" "0,1,2,3"
eventfld.long 0x0 0.--1. "EP0" "0,1,2,3"
line.long 0x4 "EP_RX_ERROR,RX error count for each endpoint. Write to each field to reset the counter to 0."
eventfld.long 0x4 31. "EP15_SEQ" "0,1"
eventfld.long 0x4 30. "EP15_TRANSACTION" "0,1"
newline
eventfld.long 0x4 29. "EP14_SEQ" "0,1"
eventfld.long 0x4 28. "EP14_TRANSACTION" "0,1"
newline
eventfld.long 0x4 27. "EP13_SEQ" "0,1"
eventfld.long 0x4 26. "EP13_TRANSACTION" "0,1"
newline
eventfld.long 0x4 25. "EP12_SEQ" "0,1"
eventfld.long 0x4 24. "EP12_TRANSACTION" "0,1"
newline
eventfld.long 0x4 23. "EP11_SEQ" "0,1"
eventfld.long 0x4 22. "EP11_TRANSACTION" "0,1"
newline
eventfld.long 0x4 21. "EP10_SEQ" "0,1"
eventfld.long 0x4 20. "EP10_TRANSACTION" "0,1"
newline
eventfld.long 0x4 19. "EP9_SEQ" "0,1"
eventfld.long 0x4 18. "EP9_TRANSACTION" "0,1"
newline
eventfld.long 0x4 17. "EP8_SEQ" "0,1"
eventfld.long 0x4 16. "EP8_TRANSACTION" "0,1"
newline
eventfld.long 0x4 15. "EP7_SEQ" "0,1"
eventfld.long 0x4 14. "EP7_TRANSACTION" "0,1"
newline
eventfld.long 0x4 13. "EP6_SEQ" "0,1"
eventfld.long 0x4 12. "EP6_TRANSACTION" "0,1"
newline
eventfld.long 0x4 11. "EP5_SEQ" "0,1"
eventfld.long 0x4 10. "EP5_TRANSACTION" "0,1"
newline
eventfld.long 0x4 9. "EP4_SEQ" "0,1"
eventfld.long 0x4 8. "EP4_TRANSACTION" "0,1"
newline
eventfld.long 0x4 7. "EP3_SEQ" "0,1"
eventfld.long 0x4 6. "EP3_TRANSACTION" "0,1"
newline
eventfld.long 0x4 5. "EP2_SEQ" "0,1"
eventfld.long 0x4 4. "EP2_TRANSACTION" "0,1"
newline
eventfld.long 0x4 3. "EP1_SEQ" "0,1"
eventfld.long 0x4 2. "EP1_TRANSACTION" "0,1"
newline
eventfld.long 0x4 1. "EP0_SEQ" "0,1"
eventfld.long 0x4 0. "EP0_TRANSACTION" "0,1"
line.long 0x8 "DEV_SM_WATCHDOG,Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition."
eventfld.long 0x8 20. "FIRED" "0,1"
bitfld.long 0x8 19. "RESET,Set to 1 to forcibly reset the device state machine on watchdog expiry" "0,1"
newline
bitfld.long 0x8 18. "ENABLE" "0,1"
hexmask.long.tbyte 0x8 0.--17. 1. "LIMIT"
tree.end
tree "USB_DPRAM"
base ad:0x50100000
group.long 0x0++0xFF
line.long 0x0 "SETUP_PACKET_LOW,Bytes 0-3 of the SETUP packet from the host."
hexmask.long.word 0x0 16.--31. 1. "WVALUE"
hexmask.long.byte 0x0 8.--15. 1. "BREQUEST"
hexmask.long.byte 0x0 0.--7. 1. "BMREQUESTTYPE"
line.long 0x4 "SETUP_PACKET_HIGH,Bytes 4-7 of the setup packet from the host."
hexmask.long.word 0x4 16.--31. 1. "WLENGTH"
hexmask.long.word 0x4 0.--15. 1. "WINDEX"
line.long 0x8 "EP1_IN_CONTROL"
bitfld.long 0x8 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x8 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x8 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x8 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x8 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x8 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x8 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x8 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0xC "EP1_OUT_CONTROL"
bitfld.long 0xC 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0xC 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0xC 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0xC 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0xC 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0xC 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0xC 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0xC 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x10 "EP2_IN_CONTROL"
bitfld.long 0x10 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x10 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x10 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x10 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x10 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x10 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x10 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x10 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x14 "EP2_OUT_CONTROL"
bitfld.long 0x14 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x14 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x14 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x14 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x14 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x14 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x14 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x14 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x18 "EP3_IN_CONTROL"
bitfld.long 0x18 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x18 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x18 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x18 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x18 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x18 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x18 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x18 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x1C "EP3_OUT_CONTROL"
bitfld.long 0x1C 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x1C 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x1C 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x1C 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x1C 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x1C 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x1C 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x1C 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x20 "EP4_IN_CONTROL"
bitfld.long 0x20 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x20 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x20 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x20 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x20 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x20 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x20 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x20 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x24 "EP4_OUT_CONTROL"
bitfld.long 0x24 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x24 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x24 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x24 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x24 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x24 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x24 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x24 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x28 "EP5_IN_CONTROL"
bitfld.long 0x28 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x28 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x28 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x28 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x28 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x28 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x28 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x28 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x2C "EP5_OUT_CONTROL"
bitfld.long 0x2C 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x2C 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x2C 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x2C 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x2C 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x2C 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x2C 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x2C 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x30 "EP6_IN_CONTROL"
bitfld.long 0x30 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x30 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x30 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x30 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x30 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x30 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x30 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x30 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x34 "EP6_OUT_CONTROL"
bitfld.long 0x34 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x34 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x34 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x34 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x34 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x34 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x34 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x34 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x38 "EP7_IN_CONTROL"
bitfld.long 0x38 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x38 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x38 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x38 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x38 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x38 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x38 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x38 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x3C "EP7_OUT_CONTROL"
bitfld.long 0x3C 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x3C 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x3C 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x3C 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x3C 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x3C 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x3C 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x3C 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x40 "EP8_IN_CONTROL"
bitfld.long 0x40 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x40 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x40 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x40 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x40 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x40 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x40 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x40 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x44 "EP8_OUT_CONTROL"
bitfld.long 0x44 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x44 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x44 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x44 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x44 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x44 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x44 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x44 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x48 "EP9_IN_CONTROL"
bitfld.long 0x48 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x48 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x48 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x48 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x48 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x48 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x48 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x48 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x4C "EP9_OUT_CONTROL"
bitfld.long 0x4C 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x4C 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x4C 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x4C 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x4C 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x4C 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x4C 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x4C 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x50 "EP10_IN_CONTROL"
bitfld.long 0x50 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x50 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x50 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x50 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x50 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x50 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x50 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x50 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x54 "EP10_OUT_CONTROL"
bitfld.long 0x54 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x54 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x54 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x54 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x54 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x54 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x54 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x54 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x58 "EP11_IN_CONTROL"
bitfld.long 0x58 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x58 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x58 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x58 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x58 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x58 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x58 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x58 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x5C "EP11_OUT_CONTROL"
bitfld.long 0x5C 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x5C 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x5C 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x5C 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x5C 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x5C 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x5C 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x5C 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x60 "EP12_IN_CONTROL"
bitfld.long 0x60 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x60 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x60 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x60 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x60 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x60 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x60 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x60 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x64 "EP12_OUT_CONTROL"
bitfld.long 0x64 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x64 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x64 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x64 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x64 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x64 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x64 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x64 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x68 "EP13_IN_CONTROL"
bitfld.long 0x68 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x68 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x68 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x68 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x68 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x68 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x68 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x68 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x6C "EP13_OUT_CONTROL"
bitfld.long 0x6C 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x6C 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x6C 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x6C 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x6C 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x6C 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x6C 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x6C 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x70 "EP14_IN_CONTROL"
bitfld.long 0x70 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x70 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x70 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x70 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x70 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x70 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x70 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x70 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x74 "EP14_OUT_CONTROL"
bitfld.long 0x74 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x74 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x74 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x74 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x74 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x74 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x74 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x74 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x78 "EP15_IN_CONTROL"
bitfld.long 0x78 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x78 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x78 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x78 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x78 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x78 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x78 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x78 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x7C "EP15_OUT_CONTROL"
bitfld.long 0x7C 31. "ENABLE,Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set." "0,1"
bitfld.long 0x7C 30. "DOUBLE_BUFFERED,This endpoint is double buffered." "0,1"
bitfld.long 0x7C 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done." "0,1"
newline
bitfld.long 0x7C 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done. Only valid in double buffered mode." "0,1"
bitfld.long 0x7C 26.--27. "ENDPOINT_TYPE" "0,1,2,3"
bitfld.long 0x7C 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent. Intended for debug only." "0,1"
newline
bitfld.long 0x7C 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent. Intended for debug only." "0,1"
hexmask.long.word 0x7C 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."
line.long 0x80 "EP0_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0x80 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x80 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0x80 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0x80 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0x80 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0x80 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0x80 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x80 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0x80 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0x80 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0x80 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0x80 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0x80 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0x84 "EP0_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0x84 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x84 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0x84 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0x84 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0x84 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0x84 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0x84 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x84 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0x84 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0x84 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0x84 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0x84 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0x84 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0x88 "EP1_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0x88 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x88 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0x88 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0x88 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0x88 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0x88 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0x88 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x88 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0x88 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0x88 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0x88 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0x88 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0x88 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0x8C "EP1_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0x8C 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x8C 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0x8C 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0x8C 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0x8C 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0x8C 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0x8C 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x8C 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0x8C 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0x8C 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0x8C 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0x8C 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0x8C 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0x90 "EP2_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0x90 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x90 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0x90 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0x90 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0x90 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0x90 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0x90 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x90 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0x90 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0x90 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0x90 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0x90 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0x90 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0x94 "EP2_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0x94 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x94 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0x94 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0x94 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0x94 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0x94 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0x94 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x94 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0x94 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0x94 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0x94 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0x94 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0x94 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0x98 "EP3_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0x98 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x98 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0x98 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0x98 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0x98 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0x98 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0x98 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x98 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0x98 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0x98 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0x98 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0x98 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0x98 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0x9C "EP3_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0x9C 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x9C 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0x9C 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0x9C 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0x9C 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0x9C 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0x9C 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0x9C 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0x9C 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0x9C 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0x9C 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0x9C 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0x9C 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xA0 "EP4_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xA0 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xA0 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xA0 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xA0 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xA0 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xA0 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xA0 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xA0 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xA0 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xA0 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xA0 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xA0 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xA0 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xA4 "EP4_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xA4 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xA4 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xA4 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xA4 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xA4 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xA4 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xA4 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xA4 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xA4 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xA4 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xA4 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xA4 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xA4 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xA8 "EP5_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xA8 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xA8 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xA8 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xA8 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xA8 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xA8 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xA8 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xA8 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xA8 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xA8 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xA8 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xA8 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xA8 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xAC "EP5_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xAC 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xAC 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xAC 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xAC 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xAC 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xAC 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xAC 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xAC 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xAC 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xAC 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xAC 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xAC 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xAC 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xB0 "EP6_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xB0 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xB0 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xB0 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xB0 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xB0 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xB0 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xB0 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xB0 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xB0 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xB0 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xB0 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xB0 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xB0 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xB4 "EP6_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xB4 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xB4 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xB4 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xB4 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xB4 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xB4 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xB4 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xB4 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xB4 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xB4 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xB4 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xB4 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xB4 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xB8 "EP7_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xB8 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xB8 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xB8 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xB8 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xB8 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xB8 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xB8 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xB8 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xB8 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xB8 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xB8 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xB8 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xB8 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xBC "EP7_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xBC 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xBC 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xBC 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xBC 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xBC 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xBC 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xBC 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xBC 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xBC 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xBC 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xBC 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xBC 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xBC 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xC0 "EP8_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xC0 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xC0 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xC0 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xC0 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xC0 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xC0 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xC0 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xC0 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xC0 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xC0 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xC0 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xC0 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xC0 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xC4 "EP8_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xC4 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xC4 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xC4 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xC4 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xC4 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xC4 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xC4 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xC4 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xC4 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xC4 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xC4 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xC4 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xC4 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xC8 "EP9_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xC8 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xC8 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xC8 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xC8 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xC8 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xC8 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xC8 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xC8 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xC8 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xC8 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xC8 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xC8 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xC8 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xCC "EP9_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xCC 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xCC 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xCC 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xCC 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xCC 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xCC 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xCC 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xCC 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xCC 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xCC 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xCC 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xCC 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xCC 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xD0 "EP10_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xD0 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xD0 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xD0 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xD0 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xD0 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xD0 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xD0 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xD0 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xD0 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xD0 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xD0 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xD0 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xD0 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xD4 "EP10_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xD4 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xD4 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xD4 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xD4 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xD4 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xD4 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xD4 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xD4 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xD4 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xD4 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xD4 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xD4 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xD4 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xD8 "EP11_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xD8 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xD8 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xD8 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xD8 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xD8 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xD8 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xD8 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xD8 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xD8 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xD8 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xD8 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xD8 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xD8 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xDC "EP11_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xDC 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xDC 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xDC 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xDC 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xDC 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xDC 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xDC 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xDC 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xDC 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xDC 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xDC 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xDC 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xDC 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xE0 "EP12_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xE0 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xE0 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xE0 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xE0 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xE0 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xE0 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xE0 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xE0 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xE0 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xE0 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xE0 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xE0 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xE0 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xE4 "EP12_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xE4 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xE4 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xE4 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xE4 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xE4 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xE4 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xE4 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xE4 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xE4 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xE4 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xE4 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xE4 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xE4 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xE8 "EP13_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xE8 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xE8 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xE8 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xE8 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xE8 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xE8 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xE8 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xE8 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xE8 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xE8 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xE8 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xE8 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xE8 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xEC "EP13_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xEC 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xEC 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xEC 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xEC 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xEC 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xEC 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xEC 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xEC 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xEC 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xEC 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xEC 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xEC 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xEC 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xF0 "EP14_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xF0 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xF0 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xF0 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xF0 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xF0 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xF0 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xF0 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xF0 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xF0 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xF0 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xF0 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xF0 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xF0 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xF4 "EP14_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xF4 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xF4 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xF4 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xF4 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xF4 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xF4 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xF4 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xF4 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xF4 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xF4 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xF4 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xF4 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xF4 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xF8 "EP15_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xF8 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xF8 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xF8 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xF8 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xF8 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xF8 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xF8 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xF8 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xF8 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xF8 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xF8 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xF8 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xF8 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
line.long 0xFC "EP15_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1."
bitfld.long 0xFC 31. "FULL_1,Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xFC 30. "LAST_1,Buffer 1 is the last buffer of the transfer." "0,1"
bitfld.long 0xFC 29. "PID_1,The data pid of buffer 1." "0,1"
newline
bitfld.long 0xFC 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint." "0,1,2,3"
bitfld.long 0xFC 26. "AVAILABLE_1,Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
hexmask.long.word 0xFC 16.--25. 1. "LENGTH_1,The length of the data in buffer 1."
newline
bitfld.long 0xFC 15. "FULL_0,Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data." "0,1"
bitfld.long 0xFC 14. "LAST_0,Buffer 0 is the last buffer of the transfer." "0,1"
bitfld.long 0xFC 13. "PID_0,The data pid of buffer 0." "0,1"
newline
bitfld.long 0xFC 12. "RESET,Reset the buffer selector to buffer 0." "0,1"
bitfld.long 0xFC 11. "STALL,Reply with a stall (valid for both buffers)." "0,1"
bitfld.long 0xFC 10. "AVAILABLE_0,Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back." "0,1"
newline
hexmask.long.word 0xFC 0.--9. 1. "LENGTH_0,The length of the data in buffer 1."
tree.end
tree.end
tree "WATCHDOG (Watchdog Timer)"
base ad:0x400D8000
group.long 0x0++0x3
line.long 0x0 "CTRL,Watchdog control"
bitfld.long 0x0 31. "TRIGGER,Trigger a watchdog reset" "0,1"
bitfld.long 0x0 30. "ENABLE,When not enabled the watchdog timer is paused" "0,1"
bitfld.long 0x0 26. "PAUSE_DBG1,Pause the watchdog timer when processor 1 is in debug mode" "0,1"
bitfld.long 0x0 25. "PAUSE_DBG0,Pause the watchdog timer when processor 0 is in debug mode" "0,1"
bitfld.long 0x0 24. "PAUSE_JTAG,Pause the watchdog timer when JTAG is accessing the bus fabric" "0,1"
hexmask.long.tbyte 0x0 0.--23. 1. "TIME,Indicates the time in usec before a watchdog reset will be triggered"
wgroup.long 0x4++0x3
line.long 0x0 "LOAD,Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds."
hexmask.long.tbyte 0x0 0.--23. 1. "LOAD"
rgroup.long 0x8++0x3
line.long 0x0 "REASON,Logs the reason for the last reset. Both bits are zero for the case of a hardware reset."
bitfld.long 0x0 1. "FORCE" "0,1"
bitfld.long 0x0 0. "TIMER" "0,1"
group.long 0xC++0x1F
line.long 0x0 "SCRATCH0,Scratch register. Information persists through soft reset of the chip."
hexmask.long 0x0 0.--31. 1. "SCRATCH0"
line.long 0x4 "SCRATCH1,Scratch register. Information persists through soft reset of the chip."
hexmask.long 0x4 0.--31. 1. "SCRATCH1"
line.long 0x8 "SCRATCH2,Scratch register. Information persists through soft reset of the chip."
hexmask.long 0x8 0.--31. 1. "SCRATCH2"
line.long 0xC "SCRATCH3,Scratch register. Information persists through soft reset of the chip."
hexmask.long 0xC 0.--31. 1. "SCRATCH3"
line.long 0x10 "SCRATCH4,Scratch register. Information persists through soft reset of the chip."
hexmask.long 0x10 0.--31. 1. "SCRATCH4"
line.long 0x14 "SCRATCH5,Scratch register. Information persists through soft reset of the chip."
hexmask.long 0x14 0.--31. 1. "SCRATCH5"
line.long 0x18 "SCRATCH6,Scratch register. Information persists through soft reset of the chip."
hexmask.long 0x18 0.--31. 1. "SCRATCH6"
line.long 0x1C "SCRATCH7,Scratch register. Information persists through soft reset of the chip."
hexmask.long 0x1C 0.--31. 1. "SCRATCH7"
tree.end
tree "XIP (External Flash and PSRAM)"
base ad:0x0
tree "XIP_AUX"
base ad:0x50500000
rgroup.long 0x0++0x3
line.long 0x0 "STREAM,Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO)"
hexmask.long 0x0 0.--31. 1. "STREAM"
wgroup.long 0x4++0x3
line.long 0x0 "QMI_DIRECT_TX,Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX)"
bitfld.long 0x0 20. "NOPUSH,Inhibit the RX FIFO push that would correspond to this TX FIFO entry." "0,1"
bitfld.long 0x0 19. "OE,Output enable (active-high). For single width (SPI) this field is ignored and SD0 is always set to output with SD1 always set to input." "0,1"
bitfld.long 0x0 18. "DWIDTH,Data width. If 0 hardware will transmit the 8 LSBs of the DIRECT_TX DATA field and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1 the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely." "0,1"
bitfld.long 0x0 16.--17. "IWIDTH,Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely." "0: Single width,1: Dual width,2: Quad width,?"
hexmask.long.word 0x0 0.--15. 1. "DATA,Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK if this is the first pulse). For each byte clocked out the interface will simultaneously sample one byte on rising edges of SCK and push this.."
rgroup.long 0x8++0x3
line.long 0x0 "QMI_DIRECT_RX,Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX)"
hexmask.long.word 0x0 0.--15. 1. "QMI_DIRECT_RX,With each byte clocked out on the serial interface one byte will simultaneously be clocked in and will appear in this FIFO. The serial interface will stall when this FIFO is full to avoid dropping data."
tree.end
tree "XIP_CTRL"
base ad:0x400C8000
group.long 0x0++0x3
line.long 0x0 "CTRL,Cache control register. Read-only from a Non-secure context."
bitfld.long 0x0 11. "WRITABLE_M1,If 1 enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff and their uncached mirrors). If 0 this region is read-only." "0,1"
bitfld.long 0x0 10. "WRITABLE_M0,If 1 enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff and their uncached mirrors). If 0 this region is read-only." "0,1"
bitfld.long 0x0 9. "SPLIT_WAYS,When 1 route all cached+Secure accesses to way 0 of the cache and route all cached+Non-secure accesses to way 1 of the cache." "0,1"
bitfld.long 0x0 8. "MAINT_NONSEC,When 0 Non-secure accesses to the cache maintenance address window (addr[27] == 1 addr[26] == 0) will generate a bus error. When 1 Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address.." "0,1"
bitfld.long 0x0 7. "NO_UNTRANSLATED_NONSEC,When 1 Non-secure accesses to the uncached untranslated window (addr[27:26] == 3) will generate a bus error." "0,1"
newline
bitfld.long 0x0 6. "NO_UNTRANSLATED_SEC,When 1 Secure accesses to the uncached untranslated window (addr[27:26] == 3) will generate a bus error." "0,1"
bitfld.long 0x0 5. "NO_UNCACHED_NONSEC,When 1 Non-secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents." "0,1"
bitfld.long 0x0 4. "NO_UNCACHED_SEC,When 1 Secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents." "0,1"
bitfld.long 0x0 3. "POWER_DOWN,When 1 the cache memories are powered down. They retain state but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0 i.e. the cache cannot be enabled when.." "0,1"
bitfld.long 0x0 1. "EN_NONSECURE,When 1 enable the cache for Non-secure accesses. When enabled Non-secure XIP accesses to the cached (addr[26] == 0) window will query the cache and QSPI accesses are performed only if the requested data is not present. When disabled .." "0,1"
newline
bitfld.long 0x0 0. "EN_SECURE,When 1 enable the cache for Secure accesses. When enabled Secure XIP accesses to the cached (addr[26] == 0) window will query the cache and QSPI accesses are performed only if the requested data is not present. When disabled Secure access.." "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "STAT"
bitfld.long 0x0 2. "FIFO_FULL,When 1 indicates the XIP streaming FIFO is completely full." "0,1"
bitfld.long 0x0 1. "FIFO_EMPTY,When 1 indicates the XIP streaming FIFO is completely empty." "0,1"
group.long 0xC++0xF
line.long 0x0 "CTR_HIT,Cache Hit counter"
hexmask.long 0x0 0.--31. 1. "CTR_HIT,A 32 bit saturating counter that increments upon each cache hit "
line.long 0x4 "CTR_ACC,Cache Access counter"
hexmask.long 0x4 0.--31. 1. "CTR_ACC,A 32 bit saturating counter that increments upon each XIP access "
line.long 0x8 "STREAM_ADDR,FIFO stream address"
hexmask.long 0x8 2.--31. 1. "STREAM_ADDR,The address of the next word to be streamed from flash to the streaming FIFO."
line.long 0xC "STREAM_CTR,FIFO stream control"
hexmask.long.tbyte 0xC 0.--21. 1. "STREAM_CTR,Write a nonzero value to start a streaming read. This will then"
rgroup.long 0x1C++0x3
line.long 0x0 "STREAM_FIFO,FIFO stream data"
hexmask.long 0x0 0.--31. 1. "STREAM_FIFO,Streamed data is buffered here for retrieval by the system DMA."
tree.end
tree.end
tree "XOSC (Crystal Oscillator)"
base ad:0x40048000
group.long 0x0++0x13
line.long 0x0 "CTRL,Crystal Oscillator Control"
hexmask.long.word 0x0 12.--23. 1. "ENABLE,On power-up this field is initialised to DISABLE and the chip runs from the ROSC."
hexmask.long.word 0x0 0.--11. 1. "FREQ_RANGE,The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE"
line.long 0x4 "STATUS,Crystal Oscillator Status"
rbitfld.long 0x4 31. "STABLE,Oscillator is running and stable" "0,1"
eventfld.long 0x4 24. "BADWRITE,An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT" "0,1"
rbitfld.long 0x4 12. "ENABLED,Oscillator is enabled but not necessarily running and stable resets to 0" "0,1"
rbitfld.long 0x4 0.--1. "FREQ_RANGE,The current frequency range setting" "0,1,2,3"
line.long 0x8 "DORMANT,Crystal Oscillator pause control"
hexmask.long 0x8 0.--31. 1. "DORMANT,This is used to save power by pausing the XOSC"
line.long 0xC "STARTUP,Controls the startup delay"
bitfld.long 0xC 20. "X4,Multiplies the startup_delay by 4 just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0." "0,1"
hexmask.long.word 0xC 0.--13. 1. "DELAY,in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."
line.long 0x10 "COUNT,A down counter running at the xosc frequency which counts to zero and stops."
hexmask.long.word 0x10 0.--15. 1. "COUNT"
tree.end
newline
AUTOINDENT.OFF
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