5679 lines
802 KiB
Plaintext
5679 lines
802 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: NUC200 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2025-03-28 NEJ
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: Generated (TRACE32, build: 178434.), based on:
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; NUC400_v1.svd (Ver. 1.0)
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; @Core: Cortex-M0
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; @Chip: NUC200LC2AN, NUC200LD2AN, NUC200LE3AN, NUC200SC2AN
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; NUC200SD2AN, NUC200SE3AN, NUC200VE3AN
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; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pernuc200.per 19321 2025-04-02 08:57:50Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC21=Cortex-M1"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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elif (CORENAME()=="CORTEXM0+")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC60=Cortex-M0+"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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else
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC20=Cortex-M0"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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endif
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ACMP (Analog Comparator Controller)"
|
|
base ad:0x400D0000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CMPCR0,Comparator 0 Control Register"
|
|
bitfld.long 0x0 4. "CMPCN,Comparator Negative Input Selection\n" "0: The source of the negative comparator input is..,1: Internal band-gap reference voltage is selected.."
|
|
bitfld.long 0x0 2. "CMP_HYSEN,Comparator Hysteresis Enable\n" "0: Hysteresis function Disabled (Default),1: Hysteresis function Enabled. The typical range.."
|
|
newline
|
|
bitfld.long 0x0 1. "CMPIE,Comparator Interrupt Enable\n" "0: Interrupt function Disabled,1: Interrupt function Enabled"
|
|
bitfld.long 0x0 0. "CMPEN,Comparator Enable\nComparator output needs to wait 2 us stable time after CMPEN is set." "0: Disabled,1: Enabled"
|
|
line.long 0x4 "CMPCR1,Comparator 1 Control Register"
|
|
bitfld.long 0x4 4. "CMPCN,Comparator Negative Input Selection\n" "0: The source of the negative comparator input is..,1: Internal band-gap reference voltage is selected.."
|
|
bitfld.long 0x4 2. "CMP_HYSEN,Comparator Hysteresis Enable\n" "0: Hysteresis function Disabled (Default),1: Hysteresis function Enabled. The typical range.."
|
|
newline
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bitfld.long 0x4 1. "CMPIE,Comparator Interrupt Enable\n" "0: Interrupt function Disabled,1: Interrupt function Enabled"
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bitfld.long 0x4 0. "CMPEN,Comparator Enable\nComparator output needs to wait 2 us stable time after CMPEN is set." "0: Disabled,1: Enabled"
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line.long 0x8 "CMPSR,Comparator Status Register"
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bitfld.long 0x8 3. "CO1,Comparator 1 Output\n" "0,1"
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bitfld.long 0x8 2. "CO0,Comparator 0 Output\n" "0,1"
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bitfld.long 0x8 1. "CMPF1,Comparator 1 Flag\nThis bit is set by hardware whenever the comparator 1 output changes state. This will cause an interrupt if CMPCR1[1] is set to 1.\nWrite 1 to clear this bit to 0." "0,1"
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bitfld.long 0x8 0. "CMPF0,Comparator 0 Flag\nThis bit is set by hardware whenever the comparator 0 output changes state. This will cause an interrupt if CMPCR0[1] is set to 1.\nWrite 1 to clear this bit to 0." "0,1"
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tree.end
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tree "ADC (Analog-to-Digital Converter)"
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base ad:0x400E0000
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rgroup.long 0x0++0x1F
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line.long 0x0 "ADDR0,ADC Data Register 0"
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bitfld.long 0x0 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit." "0: Data in RSLT[15:0] bits is not valid,1: Data in RSLT[15:0] bits is valid"
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bitfld.long 0x0 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a.." "0: Data in RSLT[15:0] is recent conversion result,1: Data in RSLT[15:0] is overwritten"
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hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF bit (ADCR[31]) set to 0 12-bit ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12].\nWhen DMOF bit (ADCR[31]).."
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line.long 0x4 "ADDR1,ADC Data Register 1"
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bitfld.long 0x4 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit." "0: Data in RSLT[15:0] bits is not valid,1: Data in RSLT[15:0] bits is valid"
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bitfld.long 0x4 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a.." "0: Data in RSLT[15:0] is recent conversion result,1: Data in RSLT[15:0] is overwritten"
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hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF bit (ADCR[31]) set to 0 12-bit ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12].\nWhen DMOF bit (ADCR[31]).."
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line.long 0x8 "ADDR2,ADC Data Register 2"
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bitfld.long 0x8 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit." "0: Data in RSLT[15:0] bits is not valid,1: Data in RSLT[15:0] bits is valid"
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bitfld.long 0x8 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a.." "0: Data in RSLT[15:0] is recent conversion result,1: Data in RSLT[15:0] is overwritten"
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hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF bit (ADCR[31]) set to 0 12-bit ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12].\nWhen DMOF bit (ADCR[31]).."
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line.long 0xC "ADDR3,ADC Data Register 3"
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bitfld.long 0xC 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit." "0: Data in RSLT[15:0] bits is not valid,1: Data in RSLT[15:0] bits is valid"
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bitfld.long 0xC 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a.." "0: Data in RSLT[15:0] is recent conversion result,1: Data in RSLT[15:0] is overwritten"
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hexmask.long.word 0xC 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF bit (ADCR[31]) set to 0 12-bit ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12].\nWhen DMOF bit (ADCR[31]).."
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line.long 0x10 "ADDR4,ADC Data Register 4"
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bitfld.long 0x10 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit." "0: Data in RSLT[15:0] bits is not valid,1: Data in RSLT[15:0] bits is valid"
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bitfld.long 0x10 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a.." "0: Data in RSLT[15:0] is recent conversion result,1: Data in RSLT[15:0] is overwritten"
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hexmask.long.word 0x10 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF bit (ADCR[31]) set to 0 12-bit ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12].\nWhen DMOF bit (ADCR[31]).."
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line.long 0x14 "ADDR5,ADC Data Register 5"
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bitfld.long 0x14 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit." "0: Data in RSLT[15:0] bits is not valid,1: Data in RSLT[15:0] bits is valid"
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bitfld.long 0x14 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a.." "0: Data in RSLT[15:0] is recent conversion result,1: Data in RSLT[15:0] is overwritten"
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hexmask.long.word 0x14 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF bit (ADCR[31]) set to 0 12-bit ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12].\nWhen DMOF bit (ADCR[31]).."
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line.long 0x18 "ADDR6,ADC Data Register 6"
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bitfld.long 0x18 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit." "0: Data in RSLT[15:0] bits is not valid,1: Data in RSLT[15:0] bits is valid"
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bitfld.long 0x18 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a.." "0: Data in RSLT[15:0] is recent conversion result,1: Data in RSLT[15:0] is overwritten"
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hexmask.long.word 0x18 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF bit (ADCR[31]) set to 0 12-bit ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12].\nWhen DMOF bit (ADCR[31]).."
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line.long 0x1C "ADDR7,ADC Data Register 7"
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bitfld.long 0x1C 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit." "0: Data in RSLT[15:0] bits is not valid,1: Data in RSLT[15:0] bits is valid"
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bitfld.long 0x1C 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a.." "0: Data in RSLT[15:0] is recent conversion result,1: Data in RSLT[15:0] is overwritten"
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hexmask.long.word 0x1C 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF bit (ADCR[31]) set to 0 12-bit ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12].\nWhen DMOF bit (ADCR[31]).."
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group.long 0x20++0x13
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line.long 0x0 "ADCR,ADC Control Register"
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bitfld.long 0x0 31. "DMOF,A/D Differential Input Mode Output Format\n" "0: A/D Conversion result will be filled in RSLT at..,1: A/D Conversion result will be filled in RSLT at.."
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bitfld.long 0x0 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from three sources: software PWM Center-aligned trigger and external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous.." "0: Conversion stops and A/D converter enter idle..,1: Conversion starts"
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bitfld.long 0x0 10. "DIFFEN,Differential Input Mode Enable\n" "0: Single-end analog input mode,1: Differential analog input mode"
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bitfld.long 0x0 9. "PTEN,PDMA Transfer Enable\n" "0: PDMA data transfer Disabled,1: PDMA data transfer in ADDR 0~7 Enabled"
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bitfld.long 0x0 8. "TRGEN,Hardware Trigger Enable\nEnable or disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger).\nADC hardware trigger function is only supported in single-cycle scan mode.\nIf hardware trigger mode the ADST.." "0: Disabled,1: Enabled"
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bitfld.long 0x0 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.\n" "0: Low level,1: High level,?,?"
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bitfld.long 0x0 4.--5. "TRGS,Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS." "0: A/D conversion is started by external STADC pin,?,?,?"
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bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode\nWhen changing the operation mode software should disable ADST bit firstly." "0: Single conversion,1: Reserved,?,?"
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bitfld.long 0x0 1. "ADIE,A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
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bitfld.long 0x0 0. "ADEN,A/D Converter Enable\nBefore starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption." "0: Disabled,1: Enabled"
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line.long 0x4 "ADCHER,ADC Channel Enable Register"
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bitfld.long 0x4 8.--9. "PRESEL,Analog Input Channel 7 Select\nNote:\nWhen software select the band-gap voltage as the analog input source of ADC channel 7 ADC clock rate needs to be limited to slower than 300 kHz." "0: External analog input,1: Internal band-gap voltage,?,?"
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hexmask.long.byte 0x4 0.--7. 1. "CHEN,Analog Input Channel Enable\nSet CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. If DIFFEN bit is set to 1 only the even number channels need to be enabled.\n"
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line.long 0x8 "ADCMPR0,ADC Compare Register 0"
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hexmask.long.word 0x8 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit is set to 0 ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen.."
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hexmask.long.byte 0x8 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.."
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bitfld.long 0x8 3.--5. "CMPCH,Compare Channel Selection\n" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,?,?,?,?,?,?"
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bitfld.long 0x8 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x8 1. "CMPIE,Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPF bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x8 0. "CMPEN,Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register." "0: Compare function Disabled,1: Compare function Enabled"
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line.long 0xC "ADCMPR1,ADC Compare Register 1"
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hexmask.long.word 0xC 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit is set to 0 ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen.."
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hexmask.long.byte 0xC 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.."
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bitfld.long 0xC 3.--5. "CMPCH,Compare Channel Selection\n" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,?,?,?,?,?,?"
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bitfld.long 0xC 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0xC 1. "CMPIE,Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPF bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0xC 0. "CMPEN,Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register." "0: Compare function Disabled,1: Compare function Enabled"
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line.long 0x10 "ADSR,ADC Status Register"
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hexmask.long.byte 0x10 16.--23. 1. "OVERRUN,Overrun Flag\nIt is a mirror to OVERRUN bit in ADDRx.\nIt is read only."
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hexmask.long.byte 0x10 8.--15. 1. "VALID,Data Valid Flag\nIt is a mirror of VALID bit in ADDRx.\nIt is read only."
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bitfld.long 0x10 4.--6. "CHANNEL,Current Conversion Channel\nIt is read only." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 3. "BUSY,BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only." "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
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bitfld.long 0x10 2. "CMPF1,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\n" "0: Conversion result in ADDR does not meet ADCMPR1..,1: Conversion result in ADDR meets ADCMPR1 setting"
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bitfld.long 0x10 1. "CMPF0,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\n" "0: Conversion result in ADDR does not meet ADCMPR0..,1: Conversion result in ADDR meets ADCMPR0 setting"
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bitfld.long 0x10 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode.\n2. When A/D conversion ends on all specified channels in Scan mode.\nThis flag.." "0,1"
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rgroup.long 0x40++0x3
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line.long 0x0 "ADPDMA,ADC PDMA Current Transfer Data Register"
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hexmask.long.tbyte 0x0 0.--17. 1. "AD_PDMA,ADC PDMA Current Transfer Data Register\nWhen PDMA transferring read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data is the content of ADDR0 ~ ADDR7.\nThis is a read only register."
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tree.end
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tree "CLK (Clock Controller)"
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base ad:0x50000200
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group.long 0x0++0x27
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line.long 0x0 "PWRCON,System Power-down Control Register"
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bitfld.long 0x0 8. "PD_WAIT_CPU,This Bit Control the Power-down Entry Condition (Write Protected)\n" "0: Chip enters Power-down mode when the PWR_DOWN_EN..,1: Chip enters Power- down mode when the both.."
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bitfld.long 0x0 7. "PWR_DOWN_EN,System Power-down Enable Bit (Write Protected)\nWhen this bit is set to 1 Power-down mode is enabled and chip power-down behavior will depend on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0 then the chip enters Power-down mode.." "0: Chip operating normally or chip in Idle mode..,1: Chip enters Power-down mode instantly or waits.."
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bitfld.long 0x0 6. "PD_WU_STS,Power-down Mode Wake-up Interrupt Status\nSet by 'power-down wake-up event' it indicates that resume from Power-down mode' \nThe flag is set if the GPIO USB UART WDT CAN I2C TIMER ACMP BOD or RTC wake-up occurred.\nWrite 1 to clear the.." "0,1"
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bitfld.long 0x0 5. "PD_WU_INT_EN,Power-down Mode Wake-up Interrupt Enable (Write Protected)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 4. "PD_WU_DLY,Enable the Wake-up Delay Counter (Write Protected)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
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bitfld.long 0x0 3. "OSC10K_EN,Internal 10 KHz Low Speed Oscillator Enable (Write Protected)\n" "0: Internal 10 kHz low speed oscillator Disabled,1: Internal 10 kHz low speed oscillator Enabled"
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bitfld.long 0x0 2. "OSC22M_EN,Internal 22.1184 MHz High Speed Oscillator Enable (Write Protected)\n" "0: Internal 22.1184 MHz high speed oscillator..,1: Internal 22.1184 MHz high speed oscillator Enabled"
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bitfld.long 0x0 1. "XTL32K_EN,External 32.768 KHz Low Speed Crystal Enable (Write Protected)\n" "0: External 32.768 kHz low speed crystal oscillator..,1: External 32.768 kHz low speed crystal oscillator.."
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bitfld.long 0x0 0. "XTL12M_EN,External 4~24 MHz High Speed Crystal Enable (Write Protected)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal this bit is.." "0: External 4~24 MHz high speed crystal oscillator..,1: External 4~24 MHz high speed crystal oscillator.."
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line.long 0x4 "AHBCLK,AHB Devices Clock Enable Control Register"
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bitfld.long 0x4 2. "ISP_EN,Flash ISP Controller Clock Enable Control\n" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
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bitfld.long 0x4 1. "PDMA_EN,PDMA Controller Clock Enable Control\n" "0: PDMA peripheral clock Disabled,1: PDMA peripheral clock Enabled"
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line.long 0x8 "APBCLK,APB Devices Clock Enable Control Register"
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bitfld.long 0x8 31. "PS2_EN,PS/2 Clock Enable\n" "0: PS/2 clock Disabled,1: PS/2 clock Enabled"
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bitfld.long 0x8 30. "ACMP_EN,Analog Comparator Clock Enable\n" "0: Analog Comparator clock Disabled,1: Analog Comparator clock Enabled"
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bitfld.long 0x8 29. "I2S_EN,I2S Clock Enable\n" "0: I2S clock Disabled,1: I2S clock Enabled"
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bitfld.long 0x8 28. "ADC_EN,Analog-digital-converter (ADC) Clock Enable\n" "0: ADC clock Disabled,1: ADC clock Enabled"
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bitfld.long 0x8 27. "USBD_EN,USB 2.0 FS Device Controller Clock Enable\n" "0: USB clock Enabled,1: USB clock Enabled"
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bitfld.long 0x8 23. "PWM67_EN,PWM_67 Clock Enable \n" "0: PWM67 clock Disabled,1: PWM67 clock Enabled"
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bitfld.long 0x8 22. "PWM45_EN,PWM_45 Clock Enable \n" "0: PWM45 clock Disabled,1: PWM45 clock Enabled"
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bitfld.long 0x8 21. "PWM23_EN,PWM_23 Clock Enable\n" "0: PWM23 clock Disabled,1: PWM23 clock Enabled"
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bitfld.long 0x8 20. "PWM01_EN,PWM_01 Clock Enable\n" "0: PWM01 clock Disabled,1: PWM01 clock Enabled"
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bitfld.long 0x8 18. "UART2_EN,UART2 Clock Enable \n" "0: UART2 clock Disabled,1: UART2 clock Enabled"
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bitfld.long 0x8 17. "UART1_EN,UART1 Clock Enable\n" "0: UART1 clock Disabled,1: UART1 clock Enabled"
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bitfld.long 0x8 16. "UART0_EN,UART0 Clock Enable\n" "0: UART0 clock Disabled,1: UART0 clock Enabled"
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bitfld.long 0x8 15. "SPI3_EN,SPI3 Clock Enable \n" "0: SPI3 clock Disabled,1: SPI3 clock Enabled"
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bitfld.long 0x8 14. "SPI2_EN,SPI2 Clock Enable\n" "0: SPI2 clock Disabled,1: SPI2 clock Enabled"
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bitfld.long 0x8 13. "SPI1_EN,SPI1 Clock Enable\n" "0: SPI1 clock Disabled,1: SPI1 clock Enabled"
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bitfld.long 0x8 12. "SPI0_EN,SPI0 Clock Enable\n" "0: SPI0 clock Disabled,1: SPI0 clock Enabled"
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bitfld.long 0x8 9. "I2C1_EN,I2C1 Clock Enable\n" "0: I2C1 clock Disabled,1: I2C1 clock Enabled"
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bitfld.long 0x8 8. "I2C0_EN,I2C0 Clock Enable\n" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
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bitfld.long 0x8 6. "FDIV_EN,Frequency Divider Output Clock Enable\n" "0: FDIV clock Disabled,1: FDIV clock Enabled"
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bitfld.long 0x8 5. "TMR3_EN,Timer3 Clock Enable\n" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
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bitfld.long 0x8 4. "TMR2_EN,Timer2 Clock Enable\n" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
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bitfld.long 0x8 3. "TMR1_EN,Timer1 Clock Enable\n" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
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bitfld.long 0x8 2. "TMR0_EN,Timer0 Clock Enable\n" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
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bitfld.long 0x8 1. "RTC_EN,Real-time-clock APB Interface Clock Enable\nThis bit is used to control the RTC APB clock only The RTC peripheral clock source is from the external 32.768 kHz low speed crystal.\n" "0: RTC clock Disabled,1: RTC clock Enabled"
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bitfld.long 0x8 0. "WDT_EN,Watchdog Timer Clock Enable (Write Protected)\nThis bit is the protected bit. It means programming this needs to write '59h' '16h' '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: Watchdog Timer clock Disabled,1: Watchdog Timer clock Enabled"
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line.long 0xC "CLKSTATUS,Clock Status Monitor Register"
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bitfld.long 0xC 7. "CLK_SW_FAIL,Clock Switching Fail Flag\nThis bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1.\nWrite 1 to clear the bit.." "0: Clock switching success,1: Clock switching failed"
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bitfld.long 0xC 4. "OSC22M_STB,Internal 22.1184 MHz High Speed Oscillator Clock Source Stable Flag\nThis bit is read only." "0: Internal 22.1184 MHz high speed oscillator clock..,1: Internal 22.1184 MHz high speed oscillator clock.."
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bitfld.long 0xC 3. "OSC10K_STB,Internal 10 KHz Low Speed Oscillator Clock Source Stable Flag\nThis bit is read only." "0: Internal 10 kHz low speed oscillator clock is..,1: Internal 10 kHz low speed oscillator clock is.."
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bitfld.long 0xC 2. "PLL_STB,Internal PLL Clock Source Stable Flag\nThis bit is read only." "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable"
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bitfld.long 0xC 1. "XTL32K_STB,External 32.768 KHz Low Speed Crystal Clock Source Stable Flag\nThis bit is read only." "0: External 32.768 kHz low speed crystal clock is..,1: External 32.768 kHz low speed crystal clock is.."
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bitfld.long 0xC 0. "XTL12M_STB,External 4~24 MHz High Speed Crystal Clock Source Stable Flag\nThis bit is read only." "0: External 4~24 MHz high speed crystal clock is..,1: External 4~24 MHz high speed crystal clock is.."
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line.long 0x10 "CLKSEL0,Clock Source Select Control Register 0"
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bitfld.long 0x10 3.--5. "STCLK_S,Cortex-M0 SysTick Clock Source Select (Write-protection Bits)\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from external 32.768 kHz low speed..,?,?,?,?,?,?"
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bitfld.long 0x10 0.--2. "HCLK_S,HCLK Clock Source Select (Write-protection Bits)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turn on\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user.." "0: Clock source from external 4~24 MHz high speed..,1: Clock source from external 32.768 kHz low speed..,?,?,?,?,?,?"
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line.long 0x14 "CLKSEL1,Clock Source Select Control Register 1"
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bitfld.long 0x14 30.--31. "PWM23_S,PWM2 and PWM3 Clock Source Selection\nPWM2 and PWM3 use the same Peripheral clock source; both of them use the same prescaler. The Peripheral clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and.." "0,1,2,3"
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bitfld.long 0x14 28.--29. "PWM01_S,PWM0 and PWM1 Clock Source Selection\nPWM0 and PWM1 use the same Peripheral clock source both of them use the same prescaler. The Peripheral clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and.." "0,1,2,3"
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bitfld.long 0x14 24.--25. "UART_S,UART Clock Source Selection\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from PLL clock,?,?"
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bitfld.long 0x14 20.--22. "TMR3_S,TIMER3 Clock Source Selection\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from external 32.768 kHz low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 16.--18. "TMR2_S,TIMER2 Clock Source Selection\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from external 32.768 kHz low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 12.--14. "TMR1_S,TIMER1 Clock Source Selection\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from external 32.768 kHz low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 8.--10. "TMR0_S,TIMER0 Clock Source Selection\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from external 32.768 kHz low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 7. "SPI3_S,SPI3 Clock Source Selection\n" "0: Clock source from PLL clock,1: Clock source from HCLK"
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bitfld.long 0x14 6. "SPI2_S,SPI2 Clock Source Selection\n" "0: Clock source from PLL clock,1: Clock source from HCLK"
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bitfld.long 0x14 5. "SPI1_S,SPI1 Clock Source Selection\n" "0: Clock source from PLL clock,1: Clock source from HCLK"
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bitfld.long 0x14 4. "SPI0_S,SPI0 Clock Source Selection\n" "0: Clock source from PLL clock,1: Clock source from HCLK"
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bitfld.long 0x14 2.--3. "ADC_S,ADC Clock Source Select\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from PLL clock,?,?"
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bitfld.long 0x14 0.--1. "WDT_S,Watchdog Timer Clock Source Select (Write-protection Bits)\nThese bits are protected bits and programming this needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address.." "0: Reserved,1: Clock source from external 32.768 kHz low speed..,?,?"
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line.long 0x18 "CLKDIV,Clock Divider Number Register"
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hexmask.long.byte 0x18 16.--23. 1. "ADC_N,ADC Clock Divide Number From ADC Clock Source\n"
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hexmask.long.byte 0x18 8.--11. 1. "UART_N,UART Clock Divide Number From UART Clock Source\n"
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hexmask.long.byte 0x18 4.--7. 1. "USB_N,USB Clock Divide Number From PLL Clock\n"
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hexmask.long.byte 0x18 0.--3. 1. "HCLK_N,HCLK Clock Divide Number From HCLK Clock Source\n"
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line.long 0x1C "CLKSEL2,Clock Source Select Control Register 2"
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bitfld.long 0x1C 16.--17. "WWDT_S,Window Watchdog Timer Clock Source Selection\n" "?,?,?,?"
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bitfld.long 0x1C 11. "PWM67_S_E,PWM6 and PWM7 Clock Source Selection\nPWM6 and PWM7 used the same Peripheral clock source; both of them used the same prescaler. The Peripheral clock source of PWM6 and PWM7 is defined by PWM67_S[2:0] and this field is combined by CLKSEL2[11].." "0,1"
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bitfld.long 0x1C 10. "PWM45_S_E,PWM4 and PWM5 Clock Source Selection\nPWM4 and PWM5 used the same Peripheral clock source; both of them used the same prescaler. The Peripheral clock source of PWM4 and PWM5 is defined by PWM45_S[2:0] and this field is combined by CLKSEL2[10].." "0,1"
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bitfld.long 0x1C 9. "PWM23_S_E,PWM2 and PWM3 Clock Source Selection\nPWM2 and PWM3 used the same Peripheral clock source; both of them used the same prescaler. The Peripheral clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9].." "0,1"
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bitfld.long 0x1C 8. "PWM01_S_E,PWM0 and PWM1 Clock Source Selection\nPWM0 and PWM1 used the same Peripheral clock source; both of them used the same prescaler. The Peripheral clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8].." "0,1"
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bitfld.long 0x1C 6.--7. "PWM67_S,PWM6 and PWM7 Clock Source Selection\nPWM6 and PWM7 used the same Peripheral clock source; both of them used the same prescaler. The Peripheral clock source of PWM6 and PWM7 is defined by PWM67_S (CLKSEL2[7:6]) and PWM67_S_E (CLKSEL2[11]). this.." "0,1,2,3"
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bitfld.long 0x1C 4.--5. "PWM45_S,PWM4 and PWM5 Clock Source Selection\nPWM4 and PWM5 used the same Peripheral clock source; both of them used the same prescaler. The Peripheral clock source of PWM4 and PWM5 is defined by PWM45_S[2:0] and this field is combined by CLKSEL2[10] and.." "0,1,2,3"
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bitfld.long 0x1C 2.--3. "FRQDIV_S,Clock Divider Clock Source Selection\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from external 32.768 kHz low speed..,?,?"
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bitfld.long 0x1C 0.--1. "I2S_S,I2S Clock Source Selection\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from PLL clock,?,?"
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line.long 0x20 "PLLCON,PLL Control Register"
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bitfld.long 0x20 19. "PLL_SRC,PLL Source Clock Selection\n" "0: PLL source clock from external 4~24 MHz high..,1: PLL source clock from internal 22.1184 MHz high.."
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bitfld.long 0x20 18. "OE,PLL OE (FOUT Enable) Pin Control\n" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
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bitfld.long 0x20 17. "BP,PLL Bypass Control\n" "0: PLL is in Normal mode (default),1: PLL clock output is same as PLL source clock input"
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bitfld.long 0x20 16. "PD,Power-down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register the PLL will enter Power-down mode too.\n" "0: PLL is in Normal mode,1: PLL is in Power-down mode (default)"
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bitfld.long 0x20 14.--15. "OUT_DV,PLL Output Divider Control Bits\nRefer to the formulas below the table." "0,1,2,3"
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hexmask.long.byte 0x20 9.--13. 1. "IN_DV,PLL Input Divider Control Bits\nRefer to the formulas below the table."
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hexmask.long.word 0x20 0.--8. 1. "FB_DV,PLL Feedback Divider Control Bits\nRefer to the formulas below the table."
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line.long 0x24 "FRQDIV,Frequency Divider Control Register"
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bitfld.long 0x24 4. "DIVIDER_EN,Frequency Divider Enable Bit\n" "0: Frequency Divider Disabled,1: Frequency Divider Enabled"
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hexmask.long.byte 0x24 0.--3. 1. "FSEL,Divider Output Frequency Selection Bits\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]."
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group.long 0x30++0xB
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line.long 0x0 "APBCLK1,APB Devices Clock Enable Control Register 1"
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bitfld.long 0x0 2. "SC2_EN,SC2 Clock Enable\n" "0: SC2 clock Disabled,1: SC2 clock Enabled"
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bitfld.long 0x0 1. "SC1_EN,SC1 Clock Enable\n" "0: SC1 clock Disabled,1: SC1 clock Enabled"
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bitfld.long 0x0 0. "SC0_EN,SC0 Clock Enable\n" "0: SC0 Clock Disabled,1: SC0 Clock Enabled"
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line.long 0x4 "CLKSEL3,Clock Source Select Control Register 3"
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bitfld.long 0x4 4.--5. "SC2_S,SC2 Clock Source Selection\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from PLL clock,?,?"
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bitfld.long 0x4 2.--3. "SC1_S,SC1 Clock Source Selection\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from PLL clock,?,?"
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bitfld.long 0x4 0.--1. "SC0_S,SC0 Clock Source Selection\n" "0: Clock source from external 4~24 MHz high speed..,1: Clock source from PLL clock,?,?"
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line.long 0x8 "CLKDIV1,Clock Divider Number Register 1"
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hexmask.long.byte 0x8 16.--23. 1. "SC2_N,SC2 Clock Divide Number From SC2 Clock Source\n"
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hexmask.long.byte 0x8 8.--15. 1. "SC1_N,SC1 Clock Divide Number From SC1 Clock Source\n"
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hexmask.long.byte 0x8 0.--7. 1. "SC0_N,SC0 Clock Divide Number From SC0 Clock Source\n"
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tree.end
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tree "FMC (Flash Memory Controller)"
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base ad:0x5000C000
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group.long 0x0++0x13
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line.long 0x0 "ISPCON,ISP Control Register"
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protected)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0\n(2) LDROM writes to itself if LDUEN is set to 0\n(3) CONFIG is.." "0,1"
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bitfld.long 0x0 5. "LDUEN,LDROM Update Enable (Write Protected)\nLDROM update enable bit.\n" "0: LDROM cannot be updated,1: LDROM can be updated when chip runs in APROM"
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bitfld.long 0x0 4. "CFGUEN,Enable Config-bits Update by ISP (Write Protected)\n" "0: ISP update config-bits Disabled,1: ISP update config-bits Enabled"
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bitfld.long 0x0 3. "APUEN,APROM Update Enable (Write Protected)\n" "0: APROM cannot be updated when chip runs in APROM,1: APROM can be updated when chip runs in APROM"
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bitfld.long 0x0 1. "BS,Boot Select (Write Protected)\nSet/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Boot from APROM,1: Boot from LDROM"
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bitfld.long 0x0 0. "ISPEN,ISP Enable (Write Protected)\nISP function enable bit. Set this bit to enable ISP function.\n" "0: ISP function Disabled,1: ISP function Enabled"
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line.long 0x4 "ISPADR,ISP Address Register"
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hexmask.long 0x4 0.--31. 1. "ISPADR,ISP Address\nThe NuMicro( NUC200 Series has a maximum 32Kx32 (128 KB) of embedded Flash which supports word program only. ISPADR[1:0] must be kept 00b for ISP operation."
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line.long 0x8 "ISPDAT,ISP Data Register"
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hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation"
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line.long 0xC "ISPCMD,ISP Command Register"
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hexmask.long.byte 0xC 0.--5. 1. "ISPCMD,ISP Command\n"
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line.long 0x10 "ISPTRG,ISP Trigger Control Register"
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bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protected)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the protected bit It means programming this bit needs to write '59h' .." "0: ISP operation finished,1: ISP progressed"
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rgroup.long 0x14++0x3
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line.long 0x0 "DFBADR,Data Flash Base Address"
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hexmask.long 0x0 0.--31. 1. "DFBADR,Data Flash Base Address\nThis register indicates Data Flash start address. It is read only.\nFor 128 KB flash memory device the Data Flash size is defined by user configuration register content is loaded from Config1 when chip is powered on but.."
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group.long 0x18++0x3
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line.long 0x0 "FATCON,Flash Access Time Control Register"
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bitfld.long 0x0 4. "LFOM,Low Frequency Optimization Mode (Write Protected)\nWhen chip operation frequency is lower than 25 MHz chip can work more efficiently by setting this bit to 1\n" "0: Low frequency optimization mode Disabled,1: Low frequency optimization mode Enabled"
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group.long 0x40++0x3
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line.long 0x0 "ISPSTA,ISP Status Register"
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hexmask.long.word 0x0 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}"
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protected)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination.." "0,1"
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rbitfld.long 0x0 1.--2. "CBS,Chip Boot Selection (Read Only)\nThis is a mirror of CBS in Config0." "0,1,2,3"
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rbitfld.long 0x0 0. "ISPGO,ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same as ISPTRG bit0" "0: ISP operation finished,1: ISP operation progressed"
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tree.end
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tree "GCR (Global Control Registers)"
|
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base ad:0x50000000
|
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rgroup.long 0x0++0x3
|
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line.long 0x0 "PDID,Part Device Identification Number Register"
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hexmask.long 0x0 0.--31. 1. "PDID,Part Device Identification Number\nThis register reflects the device part number code. Software can read this register to identify which device is used."
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group.long 0x4++0xF
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line.long 0x0 "RSTSRC,System Reset Source Register"
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bitfld.long 0x0 7. "RSTS_CPU,The RSTS_CPU Flag Is Set by Hardware If Software Writes CPU_RST (IPRSTC1[1]) 1 to Reset Cortex-M0 CPU Kernel and Flash Memory Controller (FMC)\nWrite 1 to clear this bit to 0." "0: No reset from CPU,1: Cortex-M0 CPU kernel and FMC are reset by.."
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bitfld.long 0x0 5. "RSTS_SYS,The RSTS_SYS Flag Is Set by the 'Reset Signal' From the Cortex-M0 Kernel to Indicate the Previous Reset Source\nWrite 1 to clear this bit to 0." "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.."
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bitfld.long 0x0 4. "RSTS_BOD,The RSTS_BOD Flag Is Set by the 'Reset Signal' From the Brown-out Detector to Indicate the Previous Reset Source\nWrite 1 to clear this bit to 0." "0: No reset from BOD,1: BOD had issued the reset signal to reset the.."
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bitfld.long 0x0 3. "RSTS_LVR,The RSTS_LVR Flag Is Set by the 'Reset Signal' From the Low-voltage-reset Controller to Indicate the Previous Reset Source\nWrite 1 to clear this bit to 0." "0: No reset from LVR,1: The LVR controller had issued the reset signal.."
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bitfld.long 0x0 2. "RSTS_WDT,The RSTS_WDT Flag Is Set by the 'Reset Signal' From the Watchdog Timer to Indicate the Previous Reset Source\nWrite 1 to clear this bit to 0." "0: No reset from watchdog timer,1: The watchdog timer had issued the reset signal.."
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bitfld.long 0x0 1. "RSTS_RESET,The RSTS_RESET Flag Is Set by the 'Reset Signal' From the NRESET Pin to Indicate the Previous Reset Source\nWrite 1 to clear this bit to 0." "0: No reset from the nRESET pin,1: The nRESET pin had issued the reset signal to.."
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bitfld.long 0x0 0. "RSTS_POR,The RSTS_POR Flag Is Set by the 'Reset Signal' From the Power-on Reset (POR) Controller or Bit CHIP_RST (IPRSTC1[0]) to Indicate the Previous Reset Source\nWrite 1 to clear this bit to 0." "0: No reset from POR or CHIP_RST,1: Power-On Reset (POR) or CHIP_RST had issued the.."
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line.long 0x4 "IPRSTC1,IP Reset Control Register 1"
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bitfld.long 0x4 2. "PDMA_RST,PDMA Controller Reset (Write Protected)\nSetting this bit to 1 will generate a reset signal to the PDMA. User need to set this bit to 0 to release from reset state.\nThis bit is the protected bit It means programming this bit needs to write.." "0: PDMA controller normal operation,1: PDMA controller reset"
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bitfld.long 0x4 1. "CPU_RST,CPU Kernel One-shot Reset (Write Protected)\nSetting this bit will only reset the CPU kernel and Flash Memory Controller(FMC) and this bit will automatically return 0 after the two clock cycles\nThis bit is the protected bit It means.." "0: CPU normal operation,1: CPU one-shot reset"
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bitfld.long 0x4 0. "CHIP_RST,CHIP One-shot Reset (Write Protected)\nSetting this bit will reset the whole chip including CPU kernel and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset all.." "0: CHIP normal operation,1: CHIP one-shot reset"
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line.long 0x8 "IPRSTC2,IP Reset Control Register 2"
|
|
bitfld.long 0x8 29. "I2S_RST,I2S Controller Reset\n" "0: I2S controller normal operation,1: I2S controller reset"
|
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bitfld.long 0x8 28. "ADC_RST,ADC Controller Reset\n" "0: ADC controller normal operation,1: ADC controller reset"
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bitfld.long 0x8 27. "USBD_RST,USB Device Controller Reset\n" "0: USB device controller normal operation,1: USB device controller reset"
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bitfld.long 0x8 23. "PS2_RST,PS/2 Controller Reset\n" "0: PS/2 controller normal operation,1: PS/2 controller reset"
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bitfld.long 0x8 22. "ACMP_RST,Analog Comparator Controller Reset\n" "0: Analog Comparator controller normal operation,1: Analog Comparator controller reset"
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|
bitfld.long 0x8 21. "PWM47_RST,PWM47 Controller Reset\n" "0: PWM47 controller normal operation,1: PWM47 controller reset"
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bitfld.long 0x8 20. "PWM03_RST,PWM03 Controller Reset\n" "0: PWM03 controller normal operation,1: PWM03 controller reset"
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bitfld.long 0x8 18. "UART2_RST,UART2 Controller Reset \n" "0: UART2 controller normal operation,1: UART2 controller reset"
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bitfld.long 0x8 17. "UART1_RST,UART1 Controller Reset\n" "0: UART1 controller normal operation,1: UART1 controller reset"
|
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bitfld.long 0x8 16. "UART0_RST,UART0 Controller Reset\n" "0: UART0 controller normal operation,1: UART0 controller reset"
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bitfld.long 0x8 15. "SPI3_RST,SPI3 Controller Reset \n" "0: SPI3 controller normal operation,1: SPI3 controller reset"
|
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bitfld.long 0x8 14. "SPI2_RST,SPI2 Controller Reset \n" "0: SPI2 controller normal operation,1: SPI2 controller reset"
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bitfld.long 0x8 13. "SPI1_RST,SPI1 Controller Reset\n" "0: SPI1 controller normal operation,1: SPI1 controller reset"
|
|
bitfld.long 0x8 12. "SPI0_RST,SPI0 Controller Reset\n" "0: SPI0 controller normal operation,1: SPI0 controller reset"
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bitfld.long 0x8 9. "I2C1_RST,I2C1 Controller Reset\n" "0: I2C1 controller normal operation,1: I2C1 controller reset"
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bitfld.long 0x8 8. "I2C0_RST,I2C0 Controller Reset\n" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x8 5. "TMR3_RST,Timer3 Controller Reset\n" "0: Timer3 controller normal operation,1: Timer3 controller reset"
|
|
bitfld.long 0x8 4. "TMR2_RST,Timer2 Controller Reset\n" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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|
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bitfld.long 0x8 3. "TMR1_RST,Timer1 Controller Reset\n" "0: Timer1 controller normal operation,1: Timer1 controller reset"
|
|
bitfld.long 0x8 2. "TMR0_RST,Timer0 Controller Reset\n" "0: Timer0 controller normal operation,1: Timer0 controller reset"
|
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|
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bitfld.long 0x8 1. "GPIO_RST,GPIO Controller Reset\n" "0: GPIO controller normal operation,1: GPIO controller reset"
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line.long 0xC "IPRSTC3,IP Reset Control Register 3"
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bitfld.long 0xC 2. "SC2_RST,SC2 Controller Reset\n" "0: SC2 controller normal operation,1: SC2 controller reset"
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bitfld.long 0xC 1. "SC1_RST,SC1 Controller Reset\n" "0: SC1 controller normal operation,1: SC1 controller reset"
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newline
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bitfld.long 0xC 0. "SC0_RST,SC0 Controller Reset\n" "0: SC0 controller normal operation,1: SC0 controller reset"
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group.long 0x18++0x7
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line.long 0x0 "BODCR,Brown-out Detector Control Register"
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bitfld.long 0x0 7. "LVR_EN,Low Voltage Reset Enable (Write Protected)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nThis bit is the protected bit. It means programming it needs to write.." "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled - After.."
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bitfld.long 0x0 6. "BOD_OUT,Brown-out Detector Output Status\n" "0: Brown-out Detector output status is 0. It means..,1: Brown-out Detector output status is 1. It means.."
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bitfld.long 0x0 5. "BOD_LPM,Brown-out Detector Low Power Mode (Write Protected)\nThe BOD consumes about 100 uA in Normal mode and the low power mode can reduce the current to about 1/10 but slow the BOD response.\nThis bit is the protected bit which means programming it.." "0: BOD operated in Normal mode (default),1: BOD Low Power mode Enabled"
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bitfld.long 0x0 4. "BOD_INTF,Brown-out Detector Interrupt Flag\nWrite 1 to clear this bit to 0." "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the VDD is.."
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bitfld.long 0x0 3. "BOD_RSTEN,Brown-out Reset Enable (Write Protected)\nWhile the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high) BOD will assert a signal to reset chip when the detected voltage is lower than the.." "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled"
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bitfld.long 0x0 1.--2. "BOD_VL,Brown-out Detector Threshold Voltage Selection (Write Protected)\n" "0,1,2,3"
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bitfld.long 0x0 0. "BOD_EN,Brown-out Detector Enable (Write Protected)\nThe default value is set by flash controller user configuration register config0 bit[23]\nThis bit is the protected bit which means programming it needs to write '59h' '16h' and '88h' to address.." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
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line.long 0x4 "TEMPCR,Temperature Sensor Control Register"
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bitfld.long 0x4 0. "VTEMP_EN,Temperature Sensor Enable\nThis bit is used to enable/disable temperature sensor function.\nAfter this bit is set to 1 the value of temperature can be obtained from ADC conversion result by ADC channel selecting channel 7 and alternative.." "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
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group.long 0x24++0x3
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line.long 0x0 "PORCR,Power-on Reset Controller Register"
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hexmask.long.word 0x0 0.--15. 1. "POR_DIS_CODE,Power-on-reset Enable Control (Write Protected)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to.."
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group.long 0x30++0x17
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line.long 0x0 "GPA_MFP,GPIOA Multiple Function and Input Type Control Register"
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hexmask.long.word 0x0 16.--31. 1. "GPA_TYPEn"
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bitfld.long 0x0 15. "GPA_MFP15,PA.15 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 14. "GPA_MFP14,PA.14 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 13. "GPA_MFP13,PA.13 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 12. "GPA_MFP12,PA.12 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 11. "GPA_MFP11,PA.11 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 10. "GPA_MFP10,PA.10 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 9. "GPA_MFP9,PA.9 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 8. "GPA_MFP8,PA.8 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 7. "GPA_MFP7,PA.7 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 6. "GPA_MFP6,PA.6 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 5. "GPA_MFP5,PA.5 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 4. "GPA_MFP4,PA.4 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 3. "GPA_MFP3,PA.3 Pin Function Selection\n" "0,1"
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newline
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bitfld.long 0x0 2. "GPA_MFP2,PA.2 Pin Function Selection\n" "0,1"
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bitfld.long 0x0 1. "GPA_MFP1,PA.1 Pin Function Selection\n" "0,1"
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newline
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bitfld.long 0x0 0. "GPA_MFP0,PA.0 Pin Function Selection\n" "0,1"
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line.long 0x4 "GPB_MFP,GPIOB Multiple Function and Input Type Control Register"
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hexmask.long.word 0x4 16.--31. 1. "GPB_TYPEn"
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bitfld.long 0x4 15. "GPB_MFP15,PB.15 Pin Function Selection\n" "0,1"
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bitfld.long 0x4 14. "GPB_MFP14,PB.14 Pin Function Selection\n" "0,1"
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bitfld.long 0x4 13. "GPB_MFP13,PB.13 Pin Function Selection\n" "0,1"
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newline
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bitfld.long 0x4 12. "GPB_MFP12,Reserved." "0,1"
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bitfld.long 0x4 11. "GPB_MFP11,PB.11 Pin Function Selection\n" "0,1"
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bitfld.long 0x4 10. "GPB_MFP10,PB.10 Pin Function Selection\n" "0,1"
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bitfld.long 0x4 9. "GPB_MFP9,PB.9 Pin Function Selection\n" "0,1"
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bitfld.long 0x4 8. "GPB_MFP8,PB.8 Pin Function Selection\n" "0,1"
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bitfld.long 0x4 7. "GPB_MFP7,PB.7 Pin Function Selection\n" "0: The GPIOB[7] is selected to the pin PB.7,1: The UART1_nCST function is selected to the pin.."
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bitfld.long 0x4 6. "GPB_MFP6,PB.6 Pin Function Selection\n" "0: The GPIOB[6] is selected to the pin PB.6,1: The UART1_nRST function is selected to the pin.."
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bitfld.long 0x4 5. "GPB_MFP5,PB 5 Pin Function Selection\n" "0: The GPIOB[5] is selected to the pin PB.5,1: The UART1_TXD function is selected to the pin PB.5"
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bitfld.long 0x4 4. "GPB_MFP4,PB.4 Pin Function Selection\n" "0: The GPIOB[4] is selected to the pin PB.4,1: The UART1_RXD function is selected to the pin PB.4"
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bitfld.long 0x4 3. "GPB_MFP3,PB.3 Pin Function Selection\n" "0,1"
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bitfld.long 0x4 2. "GPB_MFP2,PB.2 Pin Function Selection\n" "0,1"
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bitfld.long 0x4 1. "GPB_MFP1,PB.1 Pin Function Selection\n" "0: GPIOB[1] is selected to the pin PB.1,1: UART0_TXD function is selected to the pin PB.1"
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bitfld.long 0x4 0. "GPB_MFP0,PB.0 Pin Function Selection\n" "0: GPIOB[0] is selected to the pin PB.0,1: UART0_RXD function is selected to the pin PB.0"
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line.long 0x8 "GPC_MFP,GPIOC Multiple Function and Input Type Control Register"
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hexmask.long.word 0x8 16.--31. 1. "GPC_TYPEn"
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bitfld.long 0x8 15. "GPC_MFP15,PC.15 Pin Function Selection\n" "0,1"
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bitfld.long 0x8 14. "GPC_MFP14,PC.14 Pin Function Selection\n" "0,1"
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bitfld.long 0x8 13. "GPC_MFP13,PC.13 Pin Function Selection\n" "0: GPIOC[13] is selected to the pin PC.13,1: SPI1_MOSI1 (master output slave input pin-1).."
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bitfld.long 0x8 12. "GPC_MFP12,PC.12 Pin Function Selection\n" "0: GPIOC[12] is selected to the pin PC.12,1: SPI1_MISO1 (master input slave output pin-1).."
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bitfld.long 0x8 11. "GPC_MFP11,PC.11 Pin Function Selection\n" "0: GPIOC[11] selected to the pin PC.11,1: SPI1_MOSI0 (master output slave input pin-0).."
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newline
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bitfld.long 0x8 10. "GPC_MFP10,PC.10 Pin Function Selection\n" "0: GPIOC[10] is selected to the pin PC.10,1: SPI1_MISO0 (master input slave output pin-0).."
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bitfld.long 0x8 9. "GPC_MFP9,PC.9 Pin Function Selection\n" "0: GPIOC[9] selected to the pin PC.9,1: SPI1_CLK function selected to the pin PC.9"
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bitfld.long 0x8 8. "GPC_MFP8,PC.8 Pin Function Selection\n" "0: GPIOC[8] selected to the pin PC.8,1: SPI1_SS0 function selected to the pin PC.8"
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bitfld.long 0x8 7. "GPC_MFP7,PC.7 Pin Function Selection\n" "0,1"
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bitfld.long 0x8 6. "GPC_MFP6,PC.6 Pin Function Selection\n" "0,1"
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bitfld.long 0x8 5. "GPC_MFP5,PC.5 Pin Function Selection\n" "0: GPIOC[5] is selected to the pin PC.5,1: SPI0_MOSI1 (master output slave input pin-1).."
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bitfld.long 0x8 4. "GPC_MFP4,PC.4 Pin Function Selection\n" "0: GPIOC[4] is selected to the pin PC.4,1: SPI0_MISO1 (master input slave output pin-1).."
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bitfld.long 0x8 3. "GPC_MFP3,PC.3 Pin Function Selection\n" "0,1"
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newline
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bitfld.long 0x8 2. "GPC_MFP2,PC.2 Pin Function Selection\n" "0,1"
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bitfld.long 0x8 1. "GPC_MFP1,PC.1 Pin Function Selection\n" "0,1"
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newline
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bitfld.long 0x8 0. "GPC_MFP0,PC.0 Pin Function Selection\n" "0,1"
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line.long 0xC "GPD_MFP,GPIOD Multiple Function and Input Type Control Register"
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hexmask.long.word 0xC 16.--31. 1. "GPD_TYPEn"
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bitfld.long 0xC 15. "GPD_MFP15,PD.15 Pin Function Selection \n" "0: GPIOD[15] selected to the pin PD.15,1: UART2_TXD function is selected to the pin PD.15"
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bitfld.long 0xC 14. "GPD_MFP14,PD.14 Pin Function Selection \n" "0: GPIOD[14] selected to the pin PD.14,1: UART2_RXD function is selected to the pin PD.14"
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bitfld.long 0xC 13. "GPD_MFP13,PD.13 Pin Function Selection \n" "0: GPIOD[13] is selected to the pin PD.13,1: SPI3_MOSI1 (master output slave input pin-1).."
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newline
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bitfld.long 0xC 12. "GPD_MFP12,PD.12 Pin Function Selection \n" "0: GPIOD[12] is selected to the pin PD.12,1: SPI3_MISO1 (master input slave output pin-1).."
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bitfld.long 0xC 11. "GPD_MFP11,PD.11 Pin Function Selection\n" "0: GPIOD[11] is selected to the pin PD.11,1: SPI3_MOSI0 (master output slave input pin-0).."
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newline
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bitfld.long 0xC 10. "GPD_MFP10,PD.10 Pin Function Selection \n" "0: GPIOD[10] is selected to the pin PD.10,1: SPI3_MISO0 (master input slave output pin-0).."
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bitfld.long 0xC 9. "GPD_MFP9,PD.9 Pin Function Selection\n" "0: GPIOD[9] is selected to the pin PD.9,1: SPI3_CLK function is selected to the pin PD.9"
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newline
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bitfld.long 0xC 8. "GPD_MFP8,PD.8 Pin Function Selection\n" "0: GPIOD[8] is selected to the pin PD8,1: SPI3_SS0 function is selected to the pin PD8"
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bitfld.long 0xC 7. "GPD_MFP7,PD.7 Pin Function Selection \nReserved" "0,1"
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newline
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bitfld.long 0xC 6. "GPD_MFP6,PD.6 Pin Function Selection\nReserved" "0,1"
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bitfld.long 0xC 5. "GPD_MFP5,PD.5 Pin Function Selection \n" "0: GPIOD[5] is selected to the pin PD.5,1: SPI2_MOSI1 (master output slave input pin-1).."
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newline
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bitfld.long 0xC 4. "GPD_MFP4,PD.4 Pin Function Selection \n" "0: GPIOD[4]is selected to the pin PD.4,1: SPI2_MISO1 (master input slave output pin-1).."
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bitfld.long 0xC 3. "GPD_MFP3,PD.3 Pin Function Selection\n" "0: GPIOD[3] selected to the pin PD.3,1: SPI2_MOSI0 (master output slave input pin-0).."
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newline
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bitfld.long 0xC 2. "GPD_MFP2,PD.2 Pin Function Selection\n" "0: GPIOD[2] selected to the pin PD.2,1: SPI2_MISO0 (master input slave output pin-0).."
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bitfld.long 0xC 1. "GPD_MFP1,PD.1 Pin Function Selection\n" "0: GPIOD[1] selected to the pin PD.1,1: SPI2_SPICLK function selected to the pin PD.1"
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bitfld.long 0xC 0. "GPD_MFP0,PD.0 Pin Function Selection\n" "0: GPIOD[0] selected to the pin PD.0,1: SPI2_SS0 function selected to the pin PD.0"
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line.long 0x10 "GPE_MFP,GPIOE Multiple Function and Input Type Control Register"
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hexmask.long.word 0x10 16.--31. 1. "GPE_TYPEn"
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bitfld.long 0x10 5. "GPE_MFP5,PE.5 Pin Function Selection\n" "0,1"
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bitfld.long 0x10 1. "GPE_MFP1,PE.1 Pin Function Selection \n" "0: GPIOE[1] is selected to the pin PE.1,1: PWM7 function is selected to the pin PE.1"
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bitfld.long 0x10 0. "GPE_MFP0,PE.0 Pin Function Selection\n" "0: GPIOE[0] is selected to the pin PE.0,1: PWM6 function is selected to the pin PE.0"
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line.long 0x14 "GPF_MFP,GPIOF Multiple Function and Input Type Control Register"
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hexmask.long.byte 0x14 16.--19. 1. "GPF_TYPEn"
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bitfld.long 0x14 3. "GPF_MFP3,PF.3 Pin Function Selection \n" "0: GPIOF[3] is selected to the pin PF.3,1: PS2_CLK function is selected to the pin PF.3"
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newline
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bitfld.long 0x14 2. "GPF_MFP2,PF.2 Pin Function Selection\n" "0: GPIOF[2] is selected to the pin PF.2,1: PS2_DAT function is selected to the pin PF.2"
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bitfld.long 0x14 1. "GPF_MFP1,PF.1 Pin Function Selection \nNote: This bit is read only and is decided by user configuration CGPFMFP (Config0[27])." "0: GPIOF[1] is selected to the pin PF.1,1: XT1_IN function is selected to the pin PF.1"
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bitfld.long 0x14 0. "GPF_MFP0,PF.0 Pin Function Selection\nNote: This bit is read only and is decided by user configuration CGPFMFP (Config0[27])." "0: GPIOF[0] is selected to the pin PF.0,1: XT1_OUT function is selected to the pin PF.0"
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group.long 0x50++0x3
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line.long 0x0 "ALT_MFP,Alternative Multiple Function Pin Control Register"
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bitfld.long 0x0 30. "PB2_CPO0,Bits PB2_CPO0 (ALT_MFP[30]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] Determine the PB.2 Function\n" "0,1"
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bitfld.long 0x0 29. "PB8_CLKO,Bits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] Determine the PB.8 Function\n" "0,1"
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bitfld.long 0x0 27. "PB3_T3EX,Bits PB3_SC2CD (ALT_MFP1[14]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] Determine the PB.3 Function\n" "0,1"
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bitfld.long 0x0 26. "PB2_T2EX,Bits PB2_CPO0 (ALT_MFP[30]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] Determine the PB.2 Function\n" "0,1"
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bitfld.long 0x0 25. "PE5_T1EX,Bits GPE_MFP5 and PE5_T1EX (ALT_MFP[25]) Determine the PE.5 Function\n" "0,1"
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bitfld.long 0x0 24. "PB15_T0EX,Bits PB15_T0EX (ALT_MFP[24]) and GPB_MFP[15] Determine the PB.15 Function\n" "0,1"
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bitfld.long 0x0 9. "PA15_I2SMCLK,Bits PA15_SC2PWR (ALT_MFP1[12]) PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] Determine the PA.15 Function\n" "0,1"
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bitfld.long 0x0 8. "PC3_I2SDO,Bits PC3_I2SDO and GPC_MFP[3] Determine the PC.3 Function\n" "0,1"
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bitfld.long 0x0 7. "PC2_I2SDI,Bits PC2_I2SDI and GPC_MFP[2] Determine the PC.2 Function\n" "0,1"
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bitfld.long 0x0 6. "PC1_I2SBCLK,Bits PC1_I2SBCLK and GPC_MFP[1] Determine the PC.1 Function\n" "0,1"
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bitfld.long 0x0 5. "PC0_I2SLRCLK,Bits PC0_I2SLRCLK and GPC_MFP[0] Determine the PC.0 Function\n" "0,1"
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bitfld.long 0x0 4. "PB11_PWM4,Bits PB11_PWM4 and GPB_MFP[11] Determine the PB.11 Function\n" "0,1"
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newline
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bitfld.long 0x0 3. "PB14_S31,Bits PB14_S31 and GPB_MFP[14] Determine the PB.14 Function\n" "0,1"
|
|
bitfld.long 0x0 2. "PA7_S21,Bits PA7_SC1DAT (ALT_MFP1[6]) PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] Determine the PA.7 Function\n" "0,1"
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bitfld.long 0x0 1. "PB9_S11,Bits PB9_S11 and GPB_MFP[9] Determine the PB.9 Function\n" "0,1"
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bitfld.long 0x0 0. "PB10_S01,Bits PB10_S01 and GPB_MFP[10] Determine the PB.10 Function\n" "0,1"
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group.long 0x58++0x3
|
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line.long 0x0 "ALT_MFP1,Alternative Multiple Function Pin Control Register 1"
|
|
bitfld.long 0x0 14. "PB3_SC2CD,Bits PB3_SC2CD (ALT_MFP1[14]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] Determine the PB.3 Function\n" "0,1"
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bitfld.long 0x0 13. "PA14_SC2RST,Bits PA14_SC2RST (ALT_MFP1[13]) and GPA_MFP[14] Determine the PA.14 Function\n" "0,1"
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bitfld.long 0x0 12. "PA15_SC2PWR,Bits PA15_SC2PWR (ALT_MFP1[12]) PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] Determine the PA.15 Function\n" "0,1"
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bitfld.long 0x0 11. "PA12_SC2DAT,Bits PA12_SC2DAT (ALT_MFP1[11]) and GPA_MFP[12] Determine the PA.12 Function\n" "0,1"
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bitfld.long 0x0 10. "PA13_SC2CLK,Bits PA13_SC2CLK (ALT_MFP1[10]) and GPA_MFP[13] Determine the PA.13 Function\n" "0,1"
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bitfld.long 0x0 9. "PC7_SC1CD,Bits PC7_SC1CD (ALT_MFP1[9]) and GPC_MFP[7] Determine the PC.7 Function\n" "0,1"
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bitfld.long 0x0 8. "PA5_SC1RST,Bits PA5_SC1RST (ALT_MFP1[8]) and GPA_MFP[5] Determine the PA.5 Function\n" "0,1"
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bitfld.long 0x0 7. "PA4_SC1PWR,Bits PA4_SC1PWR (ALT_MFP1[7]) and GPA_MFP[4] Determine the PA.4 Function\n" "0,1"
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bitfld.long 0x0 6. "PA7_SC1DAT,Bits PA7_SC1DAT (ALT_MFP1[6]) PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] Determine the PA.7 Function\n" "0,1"
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bitfld.long 0x0 5. "PA6_SC1CLK,Bits PA6_SC1CLK (ALT_MFP1[5]) and GPA_MFP[6] Determine the PA.6 Function\n" "0,1"
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bitfld.long 0x0 4. "PC6_SC0CD,Bits PC6_SC0CD (ALT_MFP1[4]) and GPC_MFP[6] Determine the PC.6 Function\n" "0,1"
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bitfld.long 0x0 3. "PA1_SC0RST,Bits PA1_SC0RST (ALT_MFP1[3]) and GPA_MFP[1] Determine the PA.1 Function\n" "0,1"
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bitfld.long 0x0 2. "PA0_SC0PWR,Bits PA0_SC0PWR (ALT_MFP1[2]) and GPA_MFP[0] Determine the PA.0 Function\n" "0,1"
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|
bitfld.long 0x0 1. "PA3_SC0DAT,Bits PA3_SC0DAT (ALT_MFP1[1]) and GPA_MFP[3] Determine the PA.3 Function\n" "0,1"
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newline
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bitfld.long 0x0 0. "PA2_SC0CLK,Bits PA2_SC0CLK (ALT_MFP1[0]) and GPA_MFP[2] Determine the PA.2 Function\n" "0,1"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "IRCTRIMCTL,IRC Trim Control Register"
|
|
bitfld.long 0x0 8. "CLKERR_STOP_EN,Clock Error Stop Enable\nWhen this bit is set to 1 the trim operation is stopped if clock is inaccuracy.\nWhen this bit is set to 0 the trim operation is keep going if clock is inaccuracy." "0,1"
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bitfld.long 0x0 6.--7. "TRIM_RETRY_CNT,Trim Value Update Limitation Count\nThe field defines that how many times of HIRC trim value is updated by auto trim circuit before the HIRC frequency locked..\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64,1: Trim retry count limitation is 128,?,?"
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bitfld.long 0x0 4.--5. "TRIM_LOOP,Trim Calculation Loop\nThis field defines that trim value calculation is based on how many 32.768 kHz clocks in.\nFor example if TRIM_LOOP is set as 00 auto trim circuit will calculate trim value based on the average frequency difference in 4.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
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bitfld.long 0x0 0.--1. "TRIM_SEL,Trim Frequency Selection\nThis field indicates the target frequency of internal 22.1184 MHz high speed oscillator will trim to precise 22.1184MHz or 24MHz automatically.\nIf no any target frequency is selected (TRIM_SEL is 00) the HIRC auto.." "0: HIRC auto trim function Disabled,1: HIRC auto trim function Enabled and HIRC trimmed..,?,?"
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line.long 0x4 "IRCTRIMIEN,IRC Trim Interrupt Enable Register"
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bitfld.long 0x4 2. "CLKERR_IEN,Clock Error Interrupt Enable\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERR_INT is set during auto trim operation. An interrupt will be triggered to.." "0: CLKERR_INT status to trigger an interrupt to CPU..,1: CLKERR_INT status to trigger an interrupt to CPU.."
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bitfld.long 0x4 1. "TRIM_FAIL_IEN,Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL.\nIf this bit is high and.." "0: TRIM_FAIL_INT status to trigger an interrupt to..,1: TRIM_FAIL_INT status to trigger an interrupt to.."
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line.long 0x8 "IRCTRIMINT,IRC Trim Interrupt Status Register"
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bitfld.long 0x8 2. "CLKERR_INT,Clock Error Interrupt Status\nWhen the frequency of external 32.768 kHz low speed crystal or internal 22.1184 MHz high speed oscillator is shift larger to unreasonable value this bit will be set and to be an indicate that clock frequency is.." "0: Clock frequency is accurate,1: Clock frequency is inaccurate"
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bitfld.long 0x8 1. "TRIM_FAIL_INT,Trim Failure Interrupt Status\nThis bit indicates that internal 22.1184 MHz high speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high speed oscillator clock frequency still doesn't be locked. Once.." "0: Trim value update limitation count did not reach,1: Trim value update limitation count reached and.."
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bitfld.long 0x8 0. "FREQ_LOCK,HIRC Frequency Lock Status\nThis bit indicates the internal 22.1184 MHz high speed oscillator frequency is locked.\nThis is a status bit and doesn't trigger any interrupt." "0,1"
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group.long 0x100++0x3
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line.long 0x0 "REGWRPROT,Register Write Protection Register"
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hexmask.long.byte 0x0 0.--7. 1. "REGWRPROT,Register Write-protection Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is.."
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tree.end
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tree "GPIO (General Purpose I/Os)"
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base ad:0x50004000
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group.long 0x0++0xF
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line.long 0x0 "GPIOA_PMD,GPIO Port A Pin I/O Mode Control"
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bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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line.long 0x4 "GPIOA_OFFD,GPIO Port A Pin Digital Input Path Disable Control"
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hexmask.long.word 0x4 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid creepage\n"
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line.long 0x8 "GPIOA_DOUT,GPIO Port A Data Output Value"
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bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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line.long 0xC "GPIOA_DMASK,GPIO Port A Data Output Write Mask"
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bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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rgroup.long 0x10++0x3
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line.long 0x0 "GPIOA_PIN,GPIO Port A Pin Value"
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bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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group.long 0x14++0xF
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line.long 0x0 "GPIOA_DBEN,GPIO Port A De-bounce Enable"
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bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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line.long 0x4 "GPIOA_IMD,GPIO Port A Interrupt Mode Control"
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bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "GPIOA_IEN,GPIO Port A Interrupt Enable"
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bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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line.long 0xC "GPIOA_ISRC,GPIO Port A Interrupt Source Flag"
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bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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group.long 0x40++0xF
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line.long 0x0 "GPIOB_PMD,GPIO Port B Pin I/O Mode Control"
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bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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line.long 0x4 "GPIOB_OFFD,GPIO Port B Pin Digital Input Path Disable Control"
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hexmask.long.word 0x4 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid creepage\n"
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line.long 0x8 "GPIOB_DOUT,GPIO Port B Data Output Value"
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bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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line.long 0xC "GPIOB_DMASK,GPIO Port B Data Output Write Mask"
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bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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rgroup.long 0x50++0x3
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line.long 0x0 "GPIOB_PIN,GPIO Port B Pin Value"
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bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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group.long 0x54++0xF
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line.long 0x0 "GPIOB_DBEN,GPIO Port B De-bounce Enable"
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bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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line.long 0x4 "GPIOB_IMD,GPIO Port B Interrupt Mode Control"
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bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "GPIOB_IEN,GPIO Port B Interrupt Enable"
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bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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line.long 0xC "GPIOB_ISRC,GPIO Port B Interrupt Source Flag"
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bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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group.long 0x80++0xF
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line.long 0x0 "GPIOC_PMD,GPIO Port C Pin I/O Mode Control"
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bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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line.long 0x4 "GPIOC_OFFD,GPIO Port C Pin Digital Input Path Disable Control"
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hexmask.long.word 0x4 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid creepage\n"
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line.long 0x8 "GPIOC_DOUT,GPIO Port C Data Output Value"
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bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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line.long 0xC "GPIOC_DMASK,GPIO Port C Data Output Write Mask"
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bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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rgroup.long 0x90++0x3
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line.long 0x0 "GPIOC_PIN,GPIO Port C Pin Value"
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bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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group.long 0x94++0xF
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line.long 0x0 "GPIOC_DBEN,GPIO Port C De-bounce Enable"
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bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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line.long 0x4 "GPIOC_IMD,GPIO Port C Interrupt Mode Control"
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bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "GPIOC_IEN,GPIO Port C Interrupt Enable"
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bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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line.long 0xC "GPIOC_ISRC,GPIO Port C Interrupt Source Flag"
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bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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group.long 0xC0++0xF
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line.long 0x0 "GPIOD_PMD,GPIO Port D Pin I/O Mode Control"
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bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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line.long 0x4 "GPIOD_OFFD,GPIO Port D Pin Digital Input Path Disable Control"
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hexmask.long.word 0x4 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid creepage\n"
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line.long 0x8 "GPIOD_DOUT,GPIO Port D Data Output Value"
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bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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line.long 0xC "GPIOD_DMASK,GPIO Port D Data Output Write Mask"
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bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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rgroup.long 0xD0++0x3
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line.long 0x0 "GPIOD_PIN,GPIO Port D Pin Value"
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bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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group.long 0xD4++0xF
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line.long 0x0 "GPIOD_DBEN,GPIO Port D De-bounce Enable"
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bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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line.long 0x4 "GPIOD_IMD,GPIO Port D Interrupt Mode Control"
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bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "GPIOD_IEN,GPIO Port D Interrupt Enable"
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bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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line.long 0xC "GPIOD_ISRC,GPIO Port D Interrupt Source Flag"
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bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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group.long 0x100++0xF
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line.long 0x0 "GPIOE_PMD,GPIO Port E Pin I/O Mode Control"
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bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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line.long 0x4 "GPIOE_OFFD,GPIO Port E Pin Digital Input Path Disable Control"
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hexmask.long.word 0x4 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid creepage\n"
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line.long 0x8 "GPIOE_DOUT,GPIO Port E Data Output Value"
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bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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line.long 0xC "GPIOE_DMASK,GPIO Port E Data Output Write Mask"
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bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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rgroup.long 0x110++0x3
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line.long 0x0 "GPIOE_PIN,GPIO Port E Pin Value"
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bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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group.long 0x114++0xF
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line.long 0x0 "GPIOE_DBEN,GPIO Port E De-bounce Enable"
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bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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line.long 0x4 "GPIOE_IMD,GPIO Port E Interrupt Mode Control"
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bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "GPIOE_IEN,GPIO Port E Interrupt Enable"
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bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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line.long 0xC "GPIOE_ISRC,GPIO Port E Interrupt Source Flag"
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bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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group.long 0x140++0xF
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line.long 0x0 "GPIOF_PMD,GPIO Port F Pin I/O Mode Control"
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bitfld.long 0x0 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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bitfld.long 0x0 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after.." "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,?,?"
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line.long 0x4 "GPIOF_OFFD,GPIO Port F Pin Digital Input Path Disable Control"
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hexmask.long.word 0x4 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal users can disable GPIO digital input path to avoid creepage\n"
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line.long 0x8 "GPIOF_DOUT,GPIO Port F Data Output Value"
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bitfld.long 0x8 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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bitfld.long 0x8 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or Quasi-bidirectional mode.\n" "0: GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if..,1: GPIO port [A/B/C/D/E/F] Pin[n] will drive High.."
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line.long 0xC "GPIOF_DMASK,GPIO Port F Data Output Write Mask"
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bitfld.long 0xC 15. "DMASK15,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 14. "DMASK14,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 13. "DMASK13,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 12. "DMASK12,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 11. "DMASK11,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 10. "DMASK10,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 9. "DMASK9,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 8. "DMASK8,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 7. "DMASK7,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 6. "DMASK6,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 5. "DMASK5,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 4. "DMASK4,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 3. "DMASK3,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 2. "DMASK2,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 1. "DMASK1,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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bitfld.long 0xC 0. "DMASK0,Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1 the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked write.." "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
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rgroup.long 0x150++0x3
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line.long 0x0 "GPIOF_PIN,GPIO Port F Pin Value"
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bitfld.long 0x0 15. "PIN15,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 14. "PIN14,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 13. "PIN13,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 12. "PIN12,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 11. "PIN11,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 10. "PIN10,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 9. "PIN9,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 8. "PIN8,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 7. "PIN7,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 6. "PIN6,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 4. "PIN4,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 2. "PIN2,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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bitfld.long 0x0 0. "PIN0,Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1 it indicates the corresponding pin status is high else the pin status is low\n" "0,1"
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group.long 0x154++0xF
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line.long 0x0 "GPIOF_DBEN,GPIO Port F De-bounce Enable"
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bitfld.long 0x0 15. "DBEN15,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition.." "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
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line.long 0x4 "GPIOF_IMD,GPIO Port F Interrupt Mode Control"
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bitfld.long 0x4 15. "IMD15,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "IMD14,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "IMD13,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "IMD12,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "IMD11,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "IMD10,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "IMD9,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "IMD8,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "IMD7,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "IMD6,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "IMD5,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "IMD4,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "IMD3,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "IMD2,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "IMD1,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "IMD0,Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be controlled by de-bounce. If the interrupt is.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "GPIOF_IEN,GPIO Port F Interrupt Enable"
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bitfld.long 0x8 31. "IR_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 30. "IR_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 29. "IR_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 28. "IR_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 27. "IR_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 26. "IR_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 25. "IR_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 24. "IR_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 23. "IR_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 22. "IR_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 21. "IR_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 20. "IR_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 19. "IR_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 18. "IR_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 17. "IR_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 16. "IR_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit.." "0: PIN[n] level-high or low-to-high interrupt..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 15. "IF_EN15,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 14. "IF_EN14,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 13. "IF_EN13,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 12. "IF_EN12,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 11. "IF_EN11,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 10. "IF_EN10,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 9. "IF_EN9,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 8. "IF_EN8,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 7. "IF_EN7,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 6. "IF_EN6,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 5. "IF_EN5,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 4. "IF_EN4,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 3. "IF_EN3,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 2. "IF_EN2,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 1. "IF_EN1,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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bitfld.long 0x8 0. "IF_EN0,Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n].." "0: PIN[n] state low-level or high-to-low change..,1: \nIf the interrupt is level trigger"
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line.long 0xC "GPIOF_ISRC,GPIO Port F Interrupt Source Flag"
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bitfld.long 0xC 15. "ISRC15,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 14. "ISRC14,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 13. "ISRC13,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 12. "ISRC12,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 11. "ISRC11,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 10. "ISRC10,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 9. "ISRC9,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 8. "ISRC8,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 7. "ISRC7,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 6. "ISRC6,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 5. "ISRC5,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 4. "ISRC4,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 3. "ISRC3,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 2. "ISRC2,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 1. "ISRC1,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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bitfld.long 0xC 0. "ISRC0,Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
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group.long 0x180++0x3
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line.long 0x0 "DBNCECON,External Interrupt De-bounce Control"
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bitfld.long 0x0 5. "ICLK_ON,Interrupt Clock On Mode\nIt is recommended to turn off this bit to save system power if no special application concern." "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x0 4. "DBCLKSRC,De-bounce Counter Clock Source Selection\n" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the internal.."
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hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection\n"
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group.long 0x200++0x14F
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line.long 0x0 "PA0_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x4 "PA1_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x8 "PA2_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xC "PA3_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0xC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x10 "PA4_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x10 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x14 "PA5_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x14 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x18 "PA6_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x18 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x1C "PA7_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x1C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x20 "PA8_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x20 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x24 "PA9_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x24 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x28 "PA10_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x28 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x2C "PA11_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x2C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x30 "PA12_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x30 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x34 "PA13_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x34 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x38 "PA14_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x38 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x3C "PA15_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x3C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x40 "PB0_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x40 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x44 "PB1_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x44 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x48 "PB2_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x48 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x4C "PB3_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x4C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x50 "PB4_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x50 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x54 "PB5_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x54 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x58 "PB6_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x58 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x5C "PB7_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x5C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x60 "PB8_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x60 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x64 "PB9_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x64 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x68 "PB10_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x68 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x6C "PB11_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x6C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x70 "PB12_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x70 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x74 "PB13_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x74 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x78 "PB14_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x78 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x7C "PB15_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x7C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x80 "PC0_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x80 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x84 "PC1_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x84 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x88 "PC2_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x88 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x8C "PC3_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x8C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x90 "PC4_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x90 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x94 "PC5_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x94 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x98 "PC6_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x98 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x9C "PC7_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x9C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xA0 "PC8_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xA0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xA4 "PC9_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xA4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xA8 "PC10_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xA8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xAC "PC11_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xAC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xB0 "PC12_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xB0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xB4 "PC13_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xB4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xB8 "PC14_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xB8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xBC "PC15_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xBC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xC0 "PD0_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xC0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xC4 "PD1_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xC4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xC8 "PD2_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xC8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xCC "PD3_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xCC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xD0 "PD4_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xD0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xD4 "PD5_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xD4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xD8 "PD6_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xD8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xDC "PD7_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xDC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xE0 "PD8_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xE0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xE4 "PD9_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xE4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xE8 "PD10_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xE8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xEC "PD11_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xEC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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|
line.long 0xF0 "PD12_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xF0 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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|
line.long 0xF4 "PD13_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xF4 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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|
line.long 0xF8 "PD14_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xF8 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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|
line.long 0xFC "PD15_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xFC 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x100 "PE0_PDIO,GPIO PE.n Pin Data Input/Output"
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|
bitfld.long 0x100 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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|
line.long 0x104 "PE1_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x104 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x108 "PE2_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x108 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x10C "PE3_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x10C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x110 "PE4_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x110 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x114 "PE5_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x114 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x118 "PE6_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x118 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x11C "PE7_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x11C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x120 "PE8_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x120 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x124 "PE9_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x124 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x128 "PE10_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x128 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x12C "PE11_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x12C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x130 "PE12_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x130 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x134 "PE13_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x134 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x138 "PE14_PDIO,GPIO PE.n Pin Data Input/Output"
|
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bitfld.long 0x138 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x13C "PE15_PDIO,GPIO PE.n Pin Data Input/Output"
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bitfld.long 0x13C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x140 "PF0_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x140 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x144 "PF1_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x144 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x148 "PF2_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x148 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x14C "PF3_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x14C 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0] read PA0_PDIO will return the.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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tree.end
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tree "I2C (Inter-Integrated Circuit Serial Interface Controller)"
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base ad:0x0
|
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tree "I2C0"
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base ad:0x40020000
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group.long 0x0++0xB
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line.long 0x0 "I2CON,I2C Control Register"
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bitfld.long 0x0 7. "EI,Enable Interrupt\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "ENS1,I2C Controller Enable Bit\n" "0: Disabled,1: Enabled"
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bitfld.long 0x0 5. "STA,I2C START Control Bit\nSet STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control Bit\nIn Master mode set STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode setting STO resets I2C.." "0,1"
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newline
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit\n" "0,1"
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line.long 0x4 "I2CADDR0,I2C Slave Address Register0"
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hexmask.long.byte 0x4 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched."
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bitfld.long 0x4 0. "GC,General Call Function\n" "0: General Call function Disabled,1: General Call function Enabled"
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line.long 0x8 "I2CDAT,I2C Data Register"
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hexmask.long.byte 0x8 0.--7. 1. "I2CDAT,I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port."
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rgroup.long 0xC++0x3
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line.long 0x0 "I2CSTATUS,I2C Status Register"
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hexmask.long.byte 0x0 0.--7. 1. "I2CSTATUS,I2C Status Register\nThe status register of I2C:\n"
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group.long 0x10++0x23
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line.long 0x0 "I2CLK,I2C Clock Divided Register"
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hexmask.long.byte 0x0 0.--7. 1. "I2CLK,I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4."
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line.long 0x4 "I2CTOC,I2C Time-out Counter Register"
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bitfld.long 0x4 2. "ENTI,Time-out Counter Enable\nWhen Enabled the 14-bit time-out counter will start counting when SI is cleared. Writing 1 to the SI flag will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 1. "DIV4,Time-out Counter Input Clock Is Divided by 4\nWhen Enabled the time-out period is extended 4 times." "0: The time-out counter input clock divided by 4..,1: The time-out counter input clock divided by 4.."
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bitfld.long 0x4 0. "TIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nSoftware can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2CADDR1,I2C Slave Address Register1"
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hexmask.long.byte 0x8 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched."
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bitfld.long 0x8 0. "GC,General Call Function\n" "0: General Call function Disabled,1: General Call function Enabled"
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line.long 0xC "I2CADDR2,I2C Slave Address Register2"
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hexmask.long.byte 0xC 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched."
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bitfld.long 0xC 0. "GC,General Call Function\n" "0: General Call function Disabled,1: General Call function Enabled"
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line.long 0x10 "I2CADDR3,I2C Slave Address Register3"
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hexmask.long.byte 0x10 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched."
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bitfld.long 0x10 0. "GC,General Call Function\n" "0: General Call function Disabled,1: General Call function Enabled"
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line.long 0x14 "I2CADM0,I2C Slave Address Mask Register0"
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hexmask.long.byte 0x14 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.."
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line.long 0x18 "I2CADM1,I2C Slave Address Mask Register1"
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hexmask.long.byte 0x18 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.."
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line.long 0x1C "I2CADM2,I2C Slave Address Mask Register2"
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hexmask.long.byte 0x1C 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.."
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line.long 0x20 "I2CADM3,I2C Slave Address Mask Register3"
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hexmask.long.byte 0x20 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.."
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group.long 0x3C++0x7
|
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line.long 0x0 "I2CWKUPCON,I2C Wake-up Control Register"
|
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bitfld.long 0x0 0. "WKUPEN,I2C Wake-up Function Enable\n" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
|
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line.long 0x4 "I2CWKUPSTS,I2C Wake-up Status Register"
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bitfld.long 0x4 0. "WKUPIF,I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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tree.end
|
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tree "I2C1"
|
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base ad:0x40120000
|
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group.long 0x0++0xB
|
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line.long 0x0 "I2CON,I2C Control Register"
|
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bitfld.long 0x0 7. "EI,Enable Interrupt\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
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bitfld.long 0x0 6. "ENS1,I2C Controller Enable Bit\n" "0: Disabled,1: Enabled"
|
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bitfld.long 0x0 5. "STA,I2C START Control Bit\nSet STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control Bit\nIn Master mode set STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode setting STO resets I2C.." "0,1"
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newline
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit\n" "0,1"
|
|
line.long 0x4 "I2CADDR0,I2C Slave Address Register0"
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hexmask.long.byte 0x4 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched."
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bitfld.long 0x4 0. "GC,General Call Function\n" "0: General Call function Disabled,1: General Call function Enabled"
|
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line.long 0x8 "I2CDAT,I2C Data Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "I2CDAT,I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port."
|
|
rgroup.long 0xC++0x3
|
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line.long 0x0 "I2CSTATUS,I2C Status Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "I2CSTATUS,I2C Status Register\nThe status register of I2C:\n"
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group.long 0x10++0x23
|
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line.long 0x0 "I2CLK,I2C Clock Divided Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "I2CLK,I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4."
|
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line.long 0x4 "I2CTOC,I2C Time-out Counter Register"
|
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bitfld.long 0x4 2. "ENTI,Time-out Counter Enable\nWhen Enabled the 14-bit time-out counter will start counting when SI is cleared. Writing 1 to the SI flag will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 1. "DIV4,Time-out Counter Input Clock Is Divided by 4\nWhen Enabled the time-out period is extended 4 times." "0: The time-out counter input clock divided by 4..,1: The time-out counter input clock divided by 4.."
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bitfld.long 0x4 0. "TIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nSoftware can write 1 to clear this bit." "0,1"
|
|
line.long 0x8 "I2CADDR1,I2C Slave Address Register1"
|
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hexmask.long.byte 0x8 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched."
|
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bitfld.long 0x8 0. "GC,General Call Function\n" "0: General Call function Disabled,1: General Call function Enabled"
|
|
line.long 0xC "I2CADDR2,I2C Slave Address Register2"
|
|
hexmask.long.byte 0xC 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched."
|
|
bitfld.long 0xC 0. "GC,General Call Function\n" "0: General Call function Disabled,1: General Call function Enabled"
|
|
line.long 0x10 "I2CADDR3,I2C Slave Address Register3"
|
|
hexmask.long.byte 0x10 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched."
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bitfld.long 0x10 0. "GC,General Call Function\n" "0: General Call function Disabled,1: General Call function Enabled"
|
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line.long 0x14 "I2CADM0,I2C Slave Address Mask Register0"
|
|
hexmask.long.byte 0x14 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.."
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line.long 0x18 "I2CADM1,I2C Slave Address Mask Register1"
|
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hexmask.long.byte 0x18 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.."
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line.long 0x1C "I2CADM2,I2C Slave Address Mask Register2"
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hexmask.long.byte 0x1C 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.."
|
|
line.long 0x20 "I2CADM3,I2C Slave Address Mask Register3"
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hexmask.long.byte 0x20 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the.."
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group.long 0x3C++0x7
|
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line.long 0x0 "I2CWKUPCON,I2C Wake-up Control Register"
|
|
bitfld.long 0x0 0. "WKUPEN,I2C Wake-up Function Enable\n" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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line.long 0x4 "I2CWKUPSTS,I2C Wake-up Status Register"
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bitfld.long 0x4 0. "WKUPIF,I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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tree.end
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tree.end
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tree "I2S (Inter-IC Sound)"
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base ad:0x401A0000
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group.long 0x0++0xF
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line.long 0x0 "I2SCON,I2S Control Register"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable\n" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x0 21. "RXDMA,Enable Receive DMA\nWhen RX DMA is enabled I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.\n" "0: RX DMA Disabled,1: RX DMA Enabled"
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newline
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bitfld.long 0x0 20. "TXDMA,Enable Transmit DMA\nWhen TX DMA is enables I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.\n" "0: TX DMA Disabled,1: TX DMA Enabled"
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bitfld.long 0x0 19. "CLR_RXFIFO,Clear Receive FIFO\nWrite 1 to clear receive FIFO internal pointer is reset to FIFO start point and RXFIFO_LEVEL[3:0] returns 0 and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically. Returns 0 on read." "0,1"
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newline
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bitfld.long 0x0 18. "CLR_TXFIFO,Clear Transmit FIFO\nWrite 1 to clear transmit FIFO internal pointer is reset to FIFO start point and TXFIFO_LEVEL[3:0] returns to 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is cleared by hardware.." "0,1"
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bitfld.long 0x0 17. "LCHZCEN,Left Channel Zero Cross Detect Enable\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCF flag in I2SSTATUS register is set to 1. This function is only available in transmit operation.\n" "0: Left channel zero cross detect Disabled,1: Left channel zero cross detect Enabled"
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newline
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bitfld.long 0x0 16. "RCHZCEN,Right Channel Zero Cross Detect Enable\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCF flag in I2SSTATUS register is set to 1. This function is only available in transmit operation.\n" "0: Right channel zero cross detect Disabled,1: Right channel zero cross detect Enabled"
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable\nIf MCLKEN is set to 1 I2S controller will generate master clock on I2SMCLK pin for external audio devices.\n" "0: Master clock Disabled,1: Master clock Enabled"
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newline
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bitfld.long 0x0 12.--14. "RXTH,Receive FIFO Threshold Level\nWhen received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set.\n" "0: 1 word data in receive FIFO,1: 2 word data in receive FIFO,?,?,?,?,?,?"
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bitfld.long 0x0 9.--11. "TXTH,Transmit FIFO Threshold Level\nIf remaining data word (32 bits) in transmit FIFO is the same or less than threshold level then TXTHF flag is set.\n" "0: 0 word data in transmit FIFO,1: 1 word data in transmit FIFO,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 8. "SLAVE,Slave Mode\nI2S can operate as master or slave. For Master mode I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC200 series to Audio CODEC chip. In Slave mode I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK.." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 7. "FORMAT,Data Format\n" "0: I2S data format,1: MSB justified data format"
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newline
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bitfld.long 0x0 6. "MONO,Monaural Data\n" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x0 4.--5. "WORDWIDTH,Word Width\n" "0: data is 8-bit,1: data is 16-bit,?,?"
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newline
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable\n" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x0 2. "RXEN,Receive Enable\n" "0: Data receiving Disabled,1: Data receiving Enabled"
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newline
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bitfld.long 0x0 1. "TXEN,Transmit Enable\n" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x0 0. "I2SEN,I2S Controller Enable \n" "0: Disabled,1: Enabled"
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line.long 0x4 "I2SCLKDIV,I2S Clock Divider Control Register"
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hexmask.long.byte 0x4 8.--15. 1. "BCLK_DIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The bit clock rate F_BCLK is determined by the following expression.\n"
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bitfld.long 0x4 0.--2. "MCLK_DIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The master clock rate F_MCLK is determined by the following expressions.\nF_I2SCLK is the frequency of I2S clock.\nIn general .." "0,1,2,3,4,5,6,7"
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line.long 0x8 "I2SIE,I2S Interrupt Enable Register"
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bitfld.long 0x8 12. "LZCIE,Left Channel Zero-cross Interrupt Enable\nInterrupt occurs if this bit is set to 1 and left channel zero-cross.\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 11. "RZCIE,Right Channel Zero-cross Interrupt Enable\nInterrupt occurs if this bit is set to 1 and right channel zero-cross.\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x8 10. "TXTHIE,Transmit FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 9. "TXOVFIE,Transmit FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and the transmit FIFO overflow flag is set to 1\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x8 8. "TXUDFIE,Transmit FIFO Underflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and the transmit FIFO underflow flag is set to 1.\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 2. "RXTHIE,Receive FIFO Threshold Level Interrupt Enable\nWhen data word in receive FIFO is equal to or higher then RXTH[2:0] and the RXTHF bit is set to 1. If RXTHIE bit is enabled interrupt occurs.\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x8 1. "RXOVFIE,Receive FIFO Overflow Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x8 0. "RXUDFIE,Receive FIFO Underflow Interrupt Enable\nIf software read receive FIFO when it is empty then RXUDF flag in I2SSTATUS register is set to 1.\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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line.long 0xC "I2SSTATUS,I2S Status Register"
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hexmask.long.byte 0xC 28.--31. 1. "TX_LEVEL,Transmit FIFO Level\nThese bits indicate word number in transmit FIFO\n"
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hexmask.long.byte 0xC 24.--27. 1. "RX_LEVEL,Receive FIFO Level\nThese bits indicate word number in receive FIFO\n"
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newline
|
|
bitfld.long 0xC 23. "LZCF,Left Channel Zero-cross Flag\nIt indicates left channel next sample data sign bit is changed or all data bits are 0.\nWrite 1 to clear this bit to 0." "0: No zero-cross,1: Left channel zero-cross is detected"
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bitfld.long 0xC 22. "RZCF,Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are 0.\nWrite 1 to clear this bit to 0" "0: No zero-cross,1: Right channel zero-cross is detected"
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newline
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bitfld.long 0xC 21. "TXBUSY,Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer. \nThis bit is read only." "0: Transmit shift buffer is empty,1: Transmit shift buffer is busy"
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bitfld.long 0xC 20. "TXEMPTY,Transmit FIFO Empty\nThis bit reflects data word number in transmit FIFO is 0\nThis bit is read only." "0: Not empty,1: Empty"
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newline
|
|
bitfld.long 0xC 19. "TXFULL,Transmit FIFO Full\nThis bit reflects data word number in transmit FIFO is 8\nThis bit is read only" "0: Not full,1: Full"
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bitfld.long 0xC 18. "TXTHF,Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal to or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software writes TXFIFO.." "0: Data word(s) in FIFO is higher than threshold..,1: Data word(s) in FIFO is equal to or lower than.."
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newline
|
|
bitfld.long 0xC 17. "TXOVF,Transmit FIFO Overflow Flag\nThis bit will be set to 1 if writes data to transmit FIFO when transmit FIFO is full.\nWrite 1 to clear this bit to 0" "0: No overflow,1: Overflow"
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bitfld.long 0xC 16. "TXUDF,Transmit FIFO Underflow Flag\nWhen transmit FIFO is empty and shift logic hardware read data from transmit FIFO causes this set to 1.\nSoftware can write 1 to clear this bit to 0" "0: No underflow,1: Underflow"
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newline
|
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bitfld.long 0xC 12. "RXEMPTY,Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is 0\nThis bit is read only." "0: Not empty,1: Empty"
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bitfld.long 0xC 11. "RXFULL,Receive FIFO Full\nThis bit reflects data words number in receive FIFO is 8\nThis bit is read only." "0: Not full,1: Full"
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newline
|
|
bitfld.long 0xC 10. "RXTHF,Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal to or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] is less than RXTH[1:0] after software read RXFIFO.." "0: Data word(s) in FIFO is lower than threshold level,1: Data word(s) in FIFO is equal to or higher than.."
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bitfld.long 0xC 9. "RXOVF,Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1 data in 1st buffer is overwrote.\nWrite 1 to clear this bit to 0." "0: No overflow,1: Overflow"
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newline
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bitfld.long 0xC 8. "RXUDF,Receive FIFO Underflow Flag\nRead receive FIFO when it is empty this bit set to 1 indicate underflow occurs.\nWrite 1 to clear this bit to 0." "0: No underflow,1: Underflow"
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bitfld.long 0xC 3. "RIGHT,Right Channel\nThis bit indicates current transmit data is belong to right channel\nThis bit is read only" "0: Left channel,1: Right channel"
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newline
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bitfld.long 0xC 2. "I2STXINT,I2S Transmit Interrupt\nThis bit is read only" "0: No transmit interrupt,1: Transmit interrupt"
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bitfld.long 0xC 1. "I2SRXINT,I2S Receive Interrupt\nThis bit is read only" "0: No receive interrupt,1: Receive interrupt"
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newline
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bitfld.long 0xC 0. "I2SINT,I2S Interrupt Flag\nIt is wire-OR of I2STXINT and I2SRXINT bits.\nThis bit is read only." "0: No I2S interrupt,1: I2S interrupt"
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wgroup.long 0x10++0x3
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line.long 0x0 "I2STXFIFO,I2S Transmit FIFO Register"
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hexmask.long 0x0 0.--31. 1. "TXFIFO,Transmit FIFO Register\nI2S contains 8 words (8x32 bits) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TX_LEVEL[3:0] in I2SSTATUS register"
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rgroup.long 0x14++0x3
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line.long 0x0 "I2SRXFIFO,I2S Receive FIFO Register"
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hexmask.long 0x0 0.--31. 1. "RXFIFO,Receive FIFO Register\nI2S contains 8 words (8x32 bits) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in I2SSTATUS register."
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tree.end
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tree "INT (Interrupt Controller)"
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base ad:0x50000300
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rgroup.long 0x0++0x7F
|
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line.long 0x0 "IRQ0_SRC,IRQ0 (BOD) Interrupt Source Identity"
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bitfld.long 0x0 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: BOD_INT" "0,1,2,3,4,5,6,7"
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line.long 0x4 "IRQ1_SRC,IRQ1 (WDT) Interrupt Source Identity"
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bitfld.long 0x4 0.--2. "INT_SRC,Bit2: 0\nBit1: WWDT_INT\nBit0: WDT_INT" "0,1,2,3,4,5,6,7"
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line.long 0x8 "IRQ2_SRC,IRQ2 (EINT0) Interrupt Source Identity"
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bitfld.long 0x8 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: EINT0 - external interrupt 0" "0,1,2,3,4,5,6,7"
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line.long 0xC "IRQ3_SRC,IRQ3 (EINT1) Interrupt Source Identity"
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bitfld.long 0xC 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: EINT1 - external interrupt 1" "0,1,2,3,4,5,6,7"
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line.long 0x10 "IRQ4_SRC,IRQ4 (GPA/GPB) Interrupt Source Identity"
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bitfld.long 0x10 0.--2. "INT_SRC,Bit2: 0\nBit1: GPB_INT\nBit0: GPA_INT" "0,1,2,3,4,5,6,7"
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line.long 0x14 "IRQ5_SRC,IRQ5 (GPC/GPD/GPE/GPF) Interrupt Source Identity"
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bitfld.long 0x14 0.--2. "INT_SRC,Bit3: GPF_INT\nBit2: GPE_INT\nBit1: GPD_INT\nBit0: GPC_INT" "0,1,2,3,4,5,6,7"
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line.long 0x18 "IRQ6_SRC,IRQ6 (PWMA) Interrupt Source Identity"
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hexmask.long.byte 0x18 0.--3. 1. "INT_SRC,Bit3: PWM3_INT\nBit2: PWM2_INT\nBit1: PWM1_INT\nBit0: PWM0_INT"
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line.long 0x1C "IRQ7_SRC,IRQ7 (PWMB) Interrupt Source Identity"
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hexmask.long.byte 0x1C 0.--3. 1. "INT_SRC,Bit3: PWM7_INT\nBit2: PWM6_INT\nBit1: PWM5_INT\nBit0: PWM4_INT"
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line.long 0x20 "IRQ8_SRC,IRQ8 (TMR0) Interrupt Source Identity"
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bitfld.long 0x20 0.--2. "INT_SRC,Bit2: 0\nBit1: 0 \nBit0: TMR0_INT" "0,1,2,3,4,5,6,7"
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line.long 0x24 "IRQ9_SRC,IRQ9 (TMR1) Interrupt Source Identity"
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bitfld.long 0x24 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: TMR1_INT" "0,1,2,3,4,5,6,7"
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line.long 0x28 "IRQ10_SRC,IRQ10 (TMR2) Interrupt Source Identity"
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bitfld.long 0x28 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: TMR2_INT" "0,1,2,3,4,5,6,7"
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line.long 0x2C "IRQ11_SRC,IRQ11 (TMR3) Interrupt Source Identity"
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bitfld.long 0x2C 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: TMR3_INT" "0,1,2,3,4,5,6,7"
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line.long 0x30 "IRQ12_SRC,IRQ12 (UART0/UART2) Interrupt Source Identity"
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bitfld.long 0x30 0.--2. "INT_SRC,Bit2: 0 \nBit1: UART2_INT\nBit0: UART0_INT" "0,1,2,3,4,5,6,7"
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line.long 0x34 "IRQ13_SRC,IRQ13 (UART1) Interrupt Source Identity"
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bitfld.long 0x34 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: UART1_INT" "0,1,2,3,4,5,6,7"
|
|
line.long 0x38 "IRQ14_SRC,IRQ14 (SPI0) Interrupt Source Identity"
|
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bitfld.long 0x38 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: SPI0_INT" "0,1,2,3,4,5,6,7"
|
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line.long 0x3C "IRQ15_SRC,IRQ15 (SPI1) Interrupt Source Identity"
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bitfld.long 0x3C 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: SPI1_INT" "0,1,2,3,4,5,6,7"
|
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line.long 0x40 "IRQ16_SRC,IRQ16 (SPI2) Interrupt Source Identity"
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bitfld.long 0x40 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: SPI2_INT" "0,1,2,3,4,5,6,7"
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line.long 0x44 "IRQ17_SRC,IRQ17 (SPI3) Interrupt Source Identity"
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bitfld.long 0x44 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: SPI3_INT" "0,1,2,3,4,5,6,7"
|
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line.long 0x48 "IRQ18_SRC,IRQ18 (I2C0) Interrupt Source Identity"
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bitfld.long 0x48 0.--2. "INT_SRC,Bit2: 0 \nBit1: 0\nBit0: I2C0_INT" "0,1,2,3,4,5,6,7"
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line.long 0x4C "IRQ19_SRC,IRQ19 (I2C1) Interrupt Source Identity"
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bitfld.long 0x4C 0.--2. "INT_SRC,Bit2: 0 \nBit1: 0\nBit0: I2C1_INT" "0,1,2,3,4,5,6,7"
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line.long 0x50 "IRQ20_SRC,Reserved"
|
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line.long 0x54 "IRQ21_SRC,Reserved"
|
|
line.long 0x58 "IRQ22_SRC,IRQ22 (SC0/SC1/SC2) Interrupt Source Identity"
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bitfld.long 0x58 0.--2. "INT_SRC,Bit2: SC2_INT \nBit1: SC1_INT\nBit0: SC0_INT" "0,1,2,3,4,5,6,7"
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line.long 0x5C "IRQ23_SRC,IRQ23 (USB) Interrupt Source Identity"
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bitfld.long 0x5C 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: USB_INT" "0,1,2,3,4,5,6,7"
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line.long 0x60 "IRQ24_SRC,IRQ24 (PS/2) Interrupt Source Identity"
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bitfld.long 0x60 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: PS2_INT" "0,1,2,3,4,5,6,7"
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line.long 0x64 "IRQ25_SRC,IRQ25 (ACMP) Interrupt Source Identity"
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bitfld.long 0x64 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: ACMP_INT" "0,1,2,3,4,5,6,7"
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line.long 0x68 "IRQ26_SRC,IRQ26 (PDMA) Interrupt Source Identity"
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bitfld.long 0x68 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: PDMA_INT" "0,1,2,3,4,5,6,7"
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line.long 0x6C "IRQ27_SRC,IRQ27 (I2S) Interrupt Source Identity"
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bitfld.long 0x6C 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: I2S_INT" "0,1,2,3,4,5,6,7"
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line.long 0x70 "IRQ28_SRC,IRQ28 (PWRWU) Interrupt Source Identity"
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bitfld.long 0x70 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: PWRWU_INT" "0,1,2,3,4,5,6,7"
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|
line.long 0x74 "IRQ29_SRC,IRQ29 (ADC) Interrupt Source Identity"
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bitfld.long 0x74 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: ADC_INT" "0,1,2,3,4,5,6,7"
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line.long 0x78 "IRQ30_SRC,IRQ30 (IRCT) Interrupt Source Identity"
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bitfld.long 0x78 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: IRCT_INT" "0,1,2,3,4,5,6,7"
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line.long 0x7C "IRQ31_SRC,IRQ31 (RTC) Interrupt Source Identity"
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bitfld.long 0x7C 0.--2. "INT_SRC,Bit2: 0\nBit1: 0\nBit0: RTC_INT" "0,1,2,3,4,5,6,7"
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group.long 0x80++0x7
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line.long 0x0 "NMI_SEL,NMI Source Interrupt Select Control Register"
|
|
bitfld.long 0x0 8. "NMI_EN,NMI Interrupt Enable Bit (Write Protect)\nNote: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100." "0: NMI interrupt Disabled,1: NMI interrupt Enabled"
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|
hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL."
|
|
line.long 0x4 "MCU_IRQ,MCU Interrupt Request Source Register"
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hexmask.long 0x4 0.--31. 1. "MCU_IRQ,MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0 the normal mode and test mode.\nThe MCU_IRQ.."
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tree.end
|
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tree "NVIC (Nested Vectored Interrupt Controller)"
|
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base ad:0xE000E000
|
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group.long 0x100++0x3
|
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line.long 0x0 "NVIC_ISER,IRQ0 ~ IRQ31 Set-enable Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETENA,Enable one or more interrupts within a group of 32. Each Bit Represents an Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47)\nThe register reads back with the current enable state."
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group.long 0x180++0x3
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line.long 0x0 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-enable Control Register"
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hexmask.long 0x0 0.--31. 1. "CLRENA,Disable one or more interrupts within a group of 32. Each Bit Represents an Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47)\nThe register reads back with the current enable state."
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group.long 0x200++0x3
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line.long 0x0 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-pending Control Register"
|
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hexmask.long 0x0 0.--31. 1. "SETPEND,The register reads back with the current pending state."
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group.long 0x280++0x3
|
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line.long 0x0 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-pending Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "CLRPEND,The register reads back with the current pending state."
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group.long 0x400++0x1F
|
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line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ3 Priority Control Register"
|
|
bitfld.long 0x0 30.--31. "PRI_3,Priority of IRQ3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "PRI_2,Priority of IRQ2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "PRI_1,Priority of IRQ1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PRI_0,Priority of IRQ0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x4 "NVIC_IPR1,IRQ4 ~ IRQ7 Priority Control Register"
|
|
bitfld.long 0x4 30.--31. "PRI_7,Priority of IRQ7\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PRI_6,Priority of IRQ6\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "PRI_5,Priority of IRQ5\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PRI_4,Priority of IRQ4\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x8 "NVIC_IPR2,IRQ8 ~ IRQ11 Priority Control Register"
|
|
bitfld.long 0x8 30.--31. "PRI_11,Priority of IRQ11\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PRI_10,Priority of IRQ10\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PRI_9,Priority of IRQ9\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "PRI_8,Priority of IRQ8\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0xC "NVIC_IPR3,IRQ12 ~ IRQ15 Priority Control Register"
|
|
bitfld.long 0xC 30.--31. "PRI_15,Priority of IRQ15\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PRI_14,Priority of IRQ14\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PRI_13,Priority of IRQ13\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PRI_12,Priority of IRQ12\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x10 "NVIC_IPR4,IRQ16 ~ IRQ19 Priority Control Register"
|
|
bitfld.long 0x10 30.--31. "PRI_19,Priority of IRQ19\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "PRI_18,Priority of IRQ18\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "PRI_17,Priority of IRQ17\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "PRI_16,Priority of IRQ16\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x14 "NVIC_IPR5,IRQ20 ~ IRQ23 Priority Control Register"
|
|
bitfld.long 0x14 30.--31. "PRI_23,Priority of IRQ23\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. "PRI_22,Priority of IRQ22\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "PRI_21,Priority of IRQ21\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "PRI_20,Priority of IRQ20\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x18 "NVIC_IPR6,IRQ24 ~ IRQ27 Priority Control Register"
|
|
bitfld.long 0x18 30.--31. "PRI_27,Priority of IRQ27\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. "PRI_26,Priority of IRQ26\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. "PRI_25,Priority of IRQ25\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "PRI_24,Priority of IRQ24\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
line.long 0x1C "NVIC_IPR7,IRQ28 ~ IRQ31 Priority Control Register"
|
|
bitfld.long 0x1C 30.--31. "PRI_31,Priority of IRQ31\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. "PRI_30,Priority of IRQ30\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. "PRI_29,Priority of IRQ29\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. "PRI_28,Priority of IRQ28\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
tree.end
|
|
tree "PDMA (Peripheral Direct Memory Access)"
|
|
base ad:0x0
|
|
tree "CRC"
|
|
base ad:0x50008E00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CRC_CTL,CRC Control Register"
|
|
bitfld.long 0x0 30.--31. "CRC_MODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode.\n" "0: CRC-CCITT Polynomial Mode,1: CRC-8 Polynomial Mode,?,?"
|
|
bitfld.long 0x0 28.--29. "CPU_WDLEN,CPU Write Data Length\nThis field indicates the CPU write data length only when operating in CPU PIO mode.\nNote1: This field is only valid when operating in CPU PIO mode.\nNote2: When the write data length is 8-bit mode the valid data in.." "0: The write data length is 8-bit mode,1: The write data length is 16-bit mode,?,?"
|
|
newline
|
|
bitfld.long 0x0 27. "CHECKSUM_COM,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.\n" "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled"
|
|
bitfld.long 0x0 26. "WDATA_COM,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_WDTAT register.\n" "0: 1's complement for CRC write data in Disabled,1: 1's complement for CRC write data in Enabled"
|
|
newline
|
|
bitfld.long 0x0 25. "CHECKSUM_RVS,Checksum Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.\nNote: If the checksum result is 0XDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB" "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled"
|
|
bitfld.long 0x0 24. "WDATA_RVS,Write Data Order Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_WDTAT register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: Bit order reverse for CRC write data in Disabled,1: Bit order reverse for CRC write data in Enabled.."
|
|
newline
|
|
bitfld.long 0x0 23. "TRIG_EN,Trigger Enable\nThis bit is used to trigger the CRC DMA transfer.\nNote1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode do not fill in any data in CRC_WDATA register.\nNote2: When CRC DMA transfer completed this.." "0: No effect,1: CRC DMA data read or write transfer Enabled"
|
|
bitfld.long 0x0 1. "CRC_RST,CRC Engine Reset\nNote: When operated in CPU PIO mode setting this bit will reload the initial seed value (CRC_SEED register)." "0: No effect,1: Reset the internal CRC state machine and.."
|
|
newline
|
|
bitfld.long 0x0 0. "CRCCEN,CRC Channel Enable\nSetting this bit to 1 enables CRC operation.\n" "0,1"
|
|
line.long 0x4 "CRC_DMASAR,CRC DMA Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "CRC_DMASAR,CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CRC_DMABCR,CRC DMA Transfer Byte Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CRC_DMABCR,CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit total transfer byte count number of CRC DMA\n"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CRC_DMACSAR,CRC DMA Current Source Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_DMACSAR,CRC DMA Current Source Address Register (Read Only)\nThis field indicates the current source address where the CRC DMA transfer just occurs.\n"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CRC_DMACBCR,CRC DMA Current Transfer Byte Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CRC_DMACBCR,CRC DMA Current Remained Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC DMA.\nNote: Setting CRC_RST bit to 1 will clear this register value."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "CRC_DMAIER,CRC DMA Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "CRC_BLKD_IE,CRC DMA Block Transfer Done Interrupt Enable\nEnable this bit will generate the CRC DMA Transfer Done interrupt signal while CRC_BLKD_IF bit (CRCDMAISR [1] CRC DMA Block Transfer Done Interrupt Flag) is set to 1.\n" "0: Interrupt generator Disabled when CRC DMA..,1: Interrupt generator Enabled when CRC DMA.."
|
|
bitfld.long 0x0 0. "CRC_TABORT_IE,CRC DMA Read/Write Target Abort Interrupt Enable\nEnable this bit will generate the CRC DMA Target Abort interrupt signal while CRC_TARBOT_IF bit (CRCDMAISR [0] CRC DMA Read/Write Target Abort Interrupt Flag) is set to 1.\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
|
|
line.long 0x4 "CRC_DMAISR,CRC DMA Interrupt Status Register"
|
|
bitfld.long 0x4 1. "CRC_BLKD_IF,CRC DMA Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA transfer has finished or not.\nIt is cleared by writing 1 to it through software..\n(When CRC DMA transfer done TRIG_EN bit will be cleared automatically)" "0: Not finished if TRIG_EN bit has enabled,1: CRC transfer done if TRIG_EN bit has enabled"
|
|
bitfld.long 0x4 0. "CRC_TABORT_IF,CRC DMA Read/Write Target Abort Interrupt Flag\nThis bit indicates that CRC bus has error or not during CRC DMA transfer.\nIt is cleared by writing 1 to it through software." "0: No bus error response received during CRC DMA..,1: Bus error response received during CRC DMA.."
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "CRC_WDATA,CRC Write Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_WDATA,CRC Write Data Register\nWhen operating in CPU PIO mode software can write data to this field to perform CRC operation.\nWhen operating in DMA mode this field indicates the DMA read data from memory and cannot be written.\nNote: When the.."
|
|
line.long 0x4 "CRC_SEED,CRC Seed Register"
|
|
hexmask.long 0x4 0.--31. 1. "CRC_SEED,CRC Seed Register\nThis field indicates the CRC seed value."
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "CRC_CHECKSUM,CRC Checksum Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_CHECKSUM,CRC Checksum Register\nThis fields indicates the CRC checksum result"
|
|
tree.end
|
|
tree "PDMA_CH0"
|
|
base ad:0x50008000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CSRx,PDMA Channel x Control Register"
|
|
bitfld.long 0x0 23. "TRIG_EN,Trigger Enable\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled"
|
|
bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer destination address is increasing..,1: Reserved,?,?"
|
|
bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer source address is increasing successively,1: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?"
|
|
bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine pointers and.."
|
|
newline
|
|
bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1"
|
|
line.long 0x4 "PDMA_SARx,PDMA Channel x Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment."
|
|
line.long 0x8 "PDMA_DARx,PDMA Channel x Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment."
|
|
line.long 0xC "PDMA_BCRx,PDMA Channel x Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_POINTx,PDMA Channel x Internal Buffer Pointer Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer."
|
|
line.long 0x4 "PDMA_CSARx,PDMA Channel x Current Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred."
|
|
line.long 0x8 "PDMA_CDARx,PDMA Channel x Current Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred."
|
|
line.long 0xC "PDMA_CBCRx,PDMA Channel x Current Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0 when software set PDMA_CSRx[SW_RST] to '1'."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_IERx,PDMA Channel x Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.."
|
|
bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
|
|
line.long 0x4 "PDMA_ISRx,PDMA Channel x Interrupt Status Register"
|
|
bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0." "0: Not finished,1: Done"
|
|
bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "PDMA_SBUF0_Cx,PDMA Channel x Shared Buffer FIFO 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer."
|
|
tree.end
|
|
tree "PDMA_CH1"
|
|
base ad:0x50008100
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CSRx,PDMA Channel x Control Register"
|
|
bitfld.long 0x0 23. "TRIG_EN,Trigger Enable\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled"
|
|
bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer destination address is increasing..,1: Reserved,?,?"
|
|
bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer source address is increasing successively,1: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?"
|
|
bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine pointers and.."
|
|
newline
|
|
bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1"
|
|
line.long 0x4 "PDMA_SARx,PDMA Channel x Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment."
|
|
line.long 0x8 "PDMA_DARx,PDMA Channel x Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment."
|
|
line.long 0xC "PDMA_BCRx,PDMA Channel x Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_POINTx,PDMA Channel x Internal Buffer Pointer Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer."
|
|
line.long 0x4 "PDMA_CSARx,PDMA Channel x Current Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred."
|
|
line.long 0x8 "PDMA_CDARx,PDMA Channel x Current Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred."
|
|
line.long 0xC "PDMA_CBCRx,PDMA Channel x Current Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0 when software set PDMA_CSRx[SW_RST] to '1'."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_IERx,PDMA Channel x Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.."
|
|
bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
|
|
line.long 0x4 "PDMA_ISRx,PDMA Channel x Interrupt Status Register"
|
|
bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0." "0: Not finished,1: Done"
|
|
bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "PDMA_SBUF0_Cx,PDMA Channel x Shared Buffer FIFO 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer."
|
|
tree.end
|
|
tree "PDMA_CH2"
|
|
base ad:0x50008200
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CSRx,PDMA Channel x Control Register"
|
|
bitfld.long 0x0 23. "TRIG_EN,Trigger Enable\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled"
|
|
bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer destination address is increasing..,1: Reserved,?,?"
|
|
bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer source address is increasing successively,1: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?"
|
|
bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine pointers and.."
|
|
newline
|
|
bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1"
|
|
line.long 0x4 "PDMA_SARx,PDMA Channel x Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment."
|
|
line.long 0x8 "PDMA_DARx,PDMA Channel x Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment."
|
|
line.long 0xC "PDMA_BCRx,PDMA Channel x Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_POINTx,PDMA Channel x Internal Buffer Pointer Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer."
|
|
line.long 0x4 "PDMA_CSARx,PDMA Channel x Current Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred."
|
|
line.long 0x8 "PDMA_CDARx,PDMA Channel x Current Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred."
|
|
line.long 0xC "PDMA_CBCRx,PDMA Channel x Current Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0 when software set PDMA_CSRx[SW_RST] to '1'."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_IERx,PDMA Channel x Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.."
|
|
bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
|
|
line.long 0x4 "PDMA_ISRx,PDMA Channel x Interrupt Status Register"
|
|
bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0." "0: Not finished,1: Done"
|
|
bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "PDMA_SBUF0_Cx,PDMA Channel x Shared Buffer FIFO 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer."
|
|
tree.end
|
|
tree "PDMA_CH3"
|
|
base ad:0x50008300
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CSRx,PDMA Channel x Control Register"
|
|
bitfld.long 0x0 23. "TRIG_EN,Trigger Enable\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled"
|
|
bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer destination address is increasing..,1: Reserved,?,?"
|
|
bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer source address is increasing successively,1: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?"
|
|
bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine pointers and.."
|
|
newline
|
|
bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1"
|
|
line.long 0x4 "PDMA_SARx,PDMA Channel x Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment."
|
|
line.long 0x8 "PDMA_DARx,PDMA Channel x Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment."
|
|
line.long 0xC "PDMA_BCRx,PDMA Channel x Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_POINTx,PDMA Channel x Internal Buffer Pointer Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer."
|
|
line.long 0x4 "PDMA_CSARx,PDMA Channel x Current Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred."
|
|
line.long 0x8 "PDMA_CDARx,PDMA Channel x Current Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred."
|
|
line.long 0xC "PDMA_CBCRx,PDMA Channel x Current Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0 when software set PDMA_CSRx[SW_RST] to '1'."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_IERx,PDMA Channel x Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.."
|
|
bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
|
|
line.long 0x4 "PDMA_ISRx,PDMA Channel x Interrupt Status Register"
|
|
bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0." "0: Not finished,1: Done"
|
|
bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "PDMA_SBUF0_Cx,PDMA Channel x Shared Buffer FIFO 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer."
|
|
tree.end
|
|
tree "PDMA_CH4"
|
|
base ad:0x50008400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CSRx,PDMA Channel x Control Register"
|
|
bitfld.long 0x0 23. "TRIG_EN,Trigger Enable\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled"
|
|
bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer destination address is increasing..,1: Reserved,?,?"
|
|
bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer source address is increasing successively,1: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?"
|
|
bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine pointers and.."
|
|
newline
|
|
bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1"
|
|
line.long 0x4 "PDMA_SARx,PDMA Channel x Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment."
|
|
line.long 0x8 "PDMA_DARx,PDMA Channel x Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment."
|
|
line.long 0xC "PDMA_BCRx,PDMA Channel x Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_POINTx,PDMA Channel x Internal Buffer Pointer Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer."
|
|
line.long 0x4 "PDMA_CSARx,PDMA Channel x Current Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred."
|
|
line.long 0x8 "PDMA_CDARx,PDMA Channel x Current Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred."
|
|
line.long 0xC "PDMA_CBCRx,PDMA Channel x Current Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0 when software set PDMA_CSRx[SW_RST] to '1'."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_IERx,PDMA Channel x Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.."
|
|
bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
|
|
line.long 0x4 "PDMA_ISRx,PDMA Channel x Interrupt Status Register"
|
|
bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0." "0: Not finished,1: Done"
|
|
bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "PDMA_SBUF0_Cx,PDMA Channel x Shared Buffer FIFO 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer."
|
|
tree.end
|
|
tree "PDMA_CH5"
|
|
base ad:0x50008500
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CSRx,PDMA Channel x Control Register"
|
|
bitfld.long 0x0 23. "TRIG_EN,Trigger Enable\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled"
|
|
bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer destination address is increasing..,1: Reserved,?,?"
|
|
bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer source address is increasing successively,1: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?"
|
|
bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine pointers and.."
|
|
newline
|
|
bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1"
|
|
line.long 0x4 "PDMA_SARx,PDMA Channel x Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment."
|
|
line.long 0x8 "PDMA_DARx,PDMA Channel x Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment."
|
|
line.long 0xC "PDMA_BCRx,PDMA Channel x Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_POINTx,PDMA Channel x Internal Buffer Pointer Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer."
|
|
line.long 0x4 "PDMA_CSARx,PDMA Channel x Current Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred."
|
|
line.long 0x8 "PDMA_CDARx,PDMA Channel x Current Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred."
|
|
line.long 0xC "PDMA_CBCRx,PDMA Channel x Current Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0 when software set PDMA_CSRx[SW_RST] to '1'."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_IERx,PDMA Channel x Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.."
|
|
bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
|
|
line.long 0x4 "PDMA_ISRx,PDMA Channel x Interrupt Status Register"
|
|
bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0." "0: Not finished,1: Done"
|
|
bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "PDMA_SBUF0_Cx,PDMA Channel x Shared Buffer FIFO 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer."
|
|
tree.end
|
|
tree "PDMA_CH6"
|
|
base ad:0x50008600
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CSRx,PDMA Channel x Control Register"
|
|
bitfld.long 0x0 23. "TRIG_EN,Trigger Enable\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled"
|
|
bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer destination address is increasing..,1: Reserved,?,?"
|
|
bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer source address is increasing successively,1: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?"
|
|
bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine pointers and.."
|
|
newline
|
|
bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1"
|
|
line.long 0x4 "PDMA_SARx,PDMA Channel x Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment."
|
|
line.long 0x8 "PDMA_DARx,PDMA Channel x Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment."
|
|
line.long 0xC "PDMA_BCRx,PDMA Channel x Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_POINTx,PDMA Channel x Internal Buffer Pointer Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer."
|
|
line.long 0x4 "PDMA_CSARx,PDMA Channel x Current Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred."
|
|
line.long 0x8 "PDMA_CDARx,PDMA Channel x Current Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred."
|
|
line.long 0xC "PDMA_CBCRx,PDMA Channel x Current Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0 when software set PDMA_CSRx[SW_RST] to '1'."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_IERx,PDMA Channel x Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.."
|
|
bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
|
|
line.long 0x4 "PDMA_ISRx,PDMA Channel x Interrupt Status Register"
|
|
bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0." "0: Not finished,1: Done"
|
|
bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "PDMA_SBUF0_Cx,PDMA Channel x Shared Buffer FIFO 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer."
|
|
tree.end
|
|
tree "PDMA_CH7"
|
|
base ad:0x50008700
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CSRx,PDMA Channel x Control Register"
|
|
bitfld.long 0x0 23. "TRIG_EN,Trigger Enable\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled"
|
|
bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer destination address is increasing..,1: Reserved,?,?"
|
|
bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer source address is increasing successively,1: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?"
|
|
bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine pointers and.."
|
|
newline
|
|
bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1"
|
|
line.long 0x4 "PDMA_SARx,PDMA Channel x Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment."
|
|
line.long 0x8 "PDMA_DARx,PDMA Channel x Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment."
|
|
line.long 0xC "PDMA_BCRx,PDMA Channel x Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_POINTx,PDMA Channel x Internal Buffer Pointer Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer."
|
|
line.long 0x4 "PDMA_CSARx,PDMA Channel x Current Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred."
|
|
line.long 0x8 "PDMA_CDARx,PDMA Channel x Current Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred."
|
|
line.long 0xC "PDMA_CBCRx,PDMA Channel x Current Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0 when software set PDMA_CSRx[SW_RST] to '1'."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_IERx,PDMA Channel x Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.."
|
|
bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
|
|
line.long 0x4 "PDMA_ISRx,PDMA Channel x Interrupt Status Register"
|
|
bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0." "0: Not finished,1: Done"
|
|
bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "PDMA_SBUF0_Cx,PDMA Channel x Shared Buffer FIFO 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer."
|
|
tree.end
|
|
tree "PDMA_CH8"
|
|
base ad:0x50008800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CSRx,PDMA Channel x Control Register"
|
|
bitfld.long 0x0 23. "TRIG_EN,Trigger Enable\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped. Software must reset all PDMA channel and then trigger again." "0: No effect,1: PDMA data read or write transfer Enabled"
|
|
bitfld.long 0x0 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)." "0: One word (32-bit) is transferred for every PDMA..,1: One byte (8-bit) is transferred for every PDMA..,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection\n" "0: Transfer destination address is increasing..,1: Reserved,?,?"
|
|
bitfld.long 0x0 4.--5. "SAD_SEL,Transfer Source Address Direction Selection\n" "0: Transfer source address is increasing successively,1: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE_SEL,PDMA Mode Selection\n" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode (Peripheral-to-Memory),?,?"
|
|
bitfld.long 0x0 1. "SW_RST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine pointers and.."
|
|
newline
|
|
bitfld.long 0x0 0. "PDMACEN,PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n" "0,1"
|
|
line.long 0x4 "PDMA_SARx,PDMA Channel x Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment."
|
|
line.long 0x8 "PDMA_DARx,PDMA Channel x Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment."
|
|
line.long 0xC "PDMA_BCRx,PDMA Channel x Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_POINTx,PDMA Channel x Internal Buffer Pointer Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer."
|
|
line.long 0x4 "PDMA_CSARx,PDMA Channel x Current Source Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred."
|
|
line.long 0x8 "PDMA_CDARx,PDMA Channel x Current Destination Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred."
|
|
line.long 0xC "PDMA_CBCRx,PDMA Channel x Current Transfer Byte Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0 when software set PDMA_CSRx[SW_RST] to '1'."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_IERx,PDMA Channel x Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable\n" "0: Interrupt generator Disabled when PDMA transfer..,1: Interrupt generator Enabled when PDMA transfer.."
|
|
bitfld.long 0x0 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
|
|
line.long 0x4 "PDMA_ISRx,PDMA Channel x Interrupt Status Register"
|
|
bitfld.long 0x4 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0." "0: Not finished,1: Done"
|
|
bitfld.long 0x4 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "PDMA_SBUF0_Cx,PDMA Channel x Shared Buffer FIFO 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer."
|
|
tree.end
|
|
tree "PDMA_GCR"
|
|
base ad:0x50008F00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "PDMA_GCRCSR,PDMA Global Control Register"
|
|
bitfld.long 0x0 24. "CRC_CLK_EN,CRC Controller Clock Enable Control\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 16. "CLK8_EN,PDMA Controller Channel 8 Clock Enable Control \n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 15. "CLK7_EN,PDMA Controller Channel 7 Clock Enable Control\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 14. "CLK6_EN,PDMA Controller Channel 6 Clock Enable Control\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 13. "CLK5_EN,PDMA Controller Channel 5 Clock Enable Control\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "CLK4_EN,PDMA Controller Channel 4 Clock Enable Control\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "CLK3_EN,PDMA Controller Channel 3 Clock Enable Control\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 10. "CLK2_EN,PDMA Controller Channel 2 Clock Enable Control \n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 9. "CLK1_EN,PDMA Controller Channel 1 Clock Enable Control\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 8. "CLK0_EN,PDMA Controller Channel 0 Clock Enable Control\n" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "PDMA_PDSSR0,PDMA Service Selection Control Register 0"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SPI3_TXSEL,PDMA SPI3 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI3 TX. Software can configure the TX channel setting by SPI3_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer.."
|
|
hexmask.long.byte 0x4 24.--27. 1. "SPI3_RXSEL,PDMA SPI3 RX Selection \nThis field defines which PDMA channel is connected to the on-chip peripheral SPI3 RX. Software can configure the RX channel setting by SPI3_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer.."
|
|
hexmask.long.byte 0x4 20.--23. 1. "SPI2_TXSEL,PDMA SPI2 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by SPI2_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer.."
|
|
hexmask.long.byte 0x4 16.--19. 1. "SPI2_RXSEL,PDMA SPI2 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by SPI2_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer.."
|
|
hexmask.long.byte 0x4 12.--15. 1. "SPI1_TXSEL,PDMA SPI1 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by SPI1_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer.."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "SPI1_RXSEL,PDMA SPI1 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by SPI1_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer.."
|
|
hexmask.long.byte 0x4 4.--7. 1. "SPI0_TXSEL,PDMA SPI0 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by SPI0_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer.."
|
|
hexmask.long.byte 0x4 0.--3. 1. "SPI0_RXSEL,PDMA SPI0 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI0 RX. Software can change the channel RX setting by SPI0_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4.."
|
|
line.long 0x8 "PDMA_PDSSR1,PDMA Service Selection Control Register 1"
|
|
hexmask.long.byte 0x8 24.--27. 1. "ADC_RXSEL,PDMA ADC RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by ADC_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to.."
|
|
hexmask.long.byte 0x8 12.--15. 1. "UART1_TXSEL,PDMA UART1 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by UART1_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please.."
|
|
hexmask.long.byte 0x8 8.--11. 1. "UART1_RXSEL,PDMA UART1 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by UART1_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please.."
|
|
hexmask.long.byte 0x8 4.--7. 1. "UART0_TXSEL,PDMA UART0 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by UART0_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please.."
|
|
hexmask.long.byte 0x8 0.--3. 1. "UART0_RXSEL,PDMA UART0 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART0 RX. Software can change the channel RX setting by UART0_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4.."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "PDMA_GCRISR,PDMA Global Interrupt Status Register"
|
|
bitfld.long 0x0 31. "INTR,Interrupt Status\nThis bit is the interrupt status of PDMA controller.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x0 16. "INTRCRC,Interrupt Status of CRC Controller\nThis bit is the interrupt status of CRC controller\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x0 8. "INTR8,Interrupt Status of Channel 8 \nThis bit is the interrupt status of PDMA channel8.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x0 7. "INTR7,Interrupt Status of Channel 7 \nThis bit is the interrupt status of PDMA channel7.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x0 6. "INTR6,Interrupt Status of Channel 6 \nThis bit is the interrupt status of PDMA channel6.\nNote: This bit is read only" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INTR5,Interrupt Status of Channel 5 \nThis bit is the interrupt status of PDMA channel5.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x0 4. "INTR4,Interrupt Status of Channel 4\nThis bit is the interrupt status of PDMA channel4.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x0 3. "INTR3,Interrupt Status of Channel 3\nThis bit is the interrupt status of PDMA channel3.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x0 2. "INTR2,Interrupt Status of Channel 2\nThis bit is the interrupt status of PDMA channel2.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x0 1. "INTR1,Interrupt Status of Channel 1\nThis bit is the interrupt status of PDMA channel1.\nNote: This bit is read only" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INTR0,Interrupt Status of Channel 0\nThis bit is the interrupt status of PDMA channel0.\nNote: This bit is read only" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PDMA_PDSSR2,PDMA Service Selection Control Register 2"
|
|
hexmask.long.byte 0x0 4.--7. 1. "I2S_TXSEL,PDMA I2S TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral I2S TX. Software can configure the TX channel setting by I2S_TXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to.."
|
|
hexmask.long.byte 0x0 0.--3. 1. "I2S_RXSEL,PDMA I2S RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral I2S RX. Software can change the channel RX setting by I2S_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3\n4'b0100: CH4\n4'b0101:.."
|
|
tree.end
|
|
tree.end
|
|
tree "PS2 (PS/2 Device Controller)"
|
|
base ad:0x40100000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "PS2CON,PS/2 Control Register"
|
|
bitfld.long 0x0 11. "FPS2DAT,Force PS2_DAT Line\nIt forces PS2_DAT high or low regardless of the internal state of the device controller if OVERRIDE is set to 1.\n" "0: Force PS2_DAT low,1: Force PS2_DAT high"
|
|
bitfld.long 0x0 10. "FPS2CLK,Force PS2_CLK Line\nIt forces PS2_CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to 1.\n" "0: Force PS2_CLK line low,1: Force PS2_CLK line high"
|
|
newline
|
|
bitfld.long 0x0 9. "OVERRIDE,Software Override PS2 CLK/DAT Pin State\n" "0: PS2_CLK and PS2_DAT pins are controlled by..,1: PS2_CLK and PS2_DAT pins are controlled by.."
|
|
bitfld.long 0x0 8. "CLRFIFO,Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been.." "0: Not active,1: Clear FIFO"
|
|
newline
|
|
bitfld.long 0x0 7. "ACK,Acknowledge Enable\n" "0: Always send acknowledge to host at 12th clock..,1: If parity bit error or stop bit is not received.."
|
|
hexmask.long.byte 0x0 3.--6. 1. "TXFIFO_DEPTH,Transmit Data FIFO Depth\nThere are 16 bytes buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depends on application needs.\n"
|
|
newline
|
|
bitfld.long 0x0 2. "RXINTEN,Enable Receive Interrupt\n" "0: Data receive complete interrupt Disabled,1: Data receive complete interrupt Enabled"
|
|
bitfld.long 0x0 1. "TXINTEN,Enable Transmit Interrupt\n" "0: Data transmit complete interrupt Disabled,1: Data transmit complete interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "PS2EN,Enable PS/2 Device\nEnable PS/2 device controller\n" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "PS2TXDATA0,PS/2 Transmit Data Register 0"
|
|
hexmask.long 0x4 0.--31. 1. "PS2TXDATAx,Transmit Data\nWriting data to this register starts in device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer."
|
|
line.long 0x8 "PS2TXDATA1,PS/2 Transmit Data Register 1"
|
|
hexmask.long 0x8 0.--31. 1. "PS2TXDATAx,Transmit Data\nWriting data to this register starts in device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer."
|
|
line.long 0xC "PS2TXDATA2,PS/2 Transmit Data Register 2"
|
|
hexmask.long 0xC 0.--31. 1. "PS2TXDATAx,Transmit Data\nWriting data to this register starts in device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer."
|
|
line.long 0x10 "PS2TXDATA3,PS/2 Transmit Data Register 3"
|
|
hexmask.long 0x10 0.--31. 1. "PS2TXDATAx,Transmit Data\nWriting data to this register starts in device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "PS2RXDATA,PS/2 Receive Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA,Received Data\nFor host to device communication after acknowledge bit is sent the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete; otherwise the data will.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "PS2STATUS,PS/2 Status Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "BYTEIDX,Byte Index\n"
|
|
bitfld.long 0x0 7. "TXEMPTY,TX FIFO Empty\nWhen software writes data to PS2TXDATA0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\nThis bit is read only." "0: There is data to be transmitted,1: FIFO is empty"
|
|
newline
|
|
bitfld.long 0x0 6. "RXOVF,RX Buffer Overwrite\nWrite 1 to clear this bit." "0: No overwrite,1: Data in PS2RXDATA register is overwritten by new.."
|
|
bitfld.long 0x0 5. "TXBUSY,Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nThis bit is read only." "0: Idle,1: Currently sending data"
|
|
newline
|
|
bitfld.long 0x0 4. "RXBUSY,Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nThis bit is read only." "0: Idle,1: Currently receiving data"
|
|
bitfld.long 0x0 3. "RXPARITY,Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nThis bit is read only." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FRAMERR,Frame Error\nFor host to device communication this bit sets to 1 if STOP bit (logic 1) is not received. If frame error occurs the DATA line may keep at low state after 12th clock. At this moment software overrides PS2_CLK to send clock till.." "0: No frame error,1: Frame error occur"
|
|
bitfld.long 0x0 1. "PS2DATA,DATA Pin State\nThis bit reflects the status of the PS2_DAT line after synchronizing and sampling." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PS2CLK,CLK Pin State\nThis bit reflects the status of the PS2_CLK line after synchronizing." "0,1"
|
|
line.long 0x4 "PS2INTID,PS/2 Interrupt Identification Register"
|
|
bitfld.long 0x4 1. "TXINT,Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occur if TXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0." "0: No interrupt,1: Transmit interrupt occurs"
|
|
bitfld.long 0x4 0. "RXINT,Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0." "0: No interrupt,1: Receive interrupt occurs"
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Generator and Capture Timer)"
|
|
base ad:0x0
|
|
tree "PWMA"
|
|
base ad:0x40040000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "PPR,PWM Prescaler Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DZI23,Dead-zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DZI01,Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock Prescaler 2 (PWM-timer2 / 3 for Group A and PWM-timer 6 / 7 for Group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer\n"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock Prescaler 0 (PWM-timer 0 / 1 for Group A and PWM-timer 4 / 5 for Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer\n"
|
|
line.long 0x4 "CSR,PWM Clock Source Divider Select Register"
|
|
bitfld.long 0x4 12.--14. "CSR3,PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 8.--10. "CSR2,PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 4.--6. "CSR1,PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0.--2. "CSR0,PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
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line.long 0x8 "PCR,PWM Control Register"
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bitfld.long 0x8 31. "PWM23TYPE,PWM23 Aligned Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\n" "0: Edge-aligned type,1: Center-aligned type"
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bitfld.long 0x8 30. "PWM01TYPE,PWM01 Aligned Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\n" "0: Edge-aligned type,1: Center-aligned type"
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bitfld.long 0x8 27. "CH3MOD,PWM-timer 3 Auto-reload/One-shot Mode (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\nNote: If there is a transition at this bit it will cause CNR3 and CMR3 be cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 26. "CH3INV,PWM-timer 3 Output Inverter Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled"
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bitfld.long 0x8 25. "CH3PINV,PWM-timer 3 Output Polar Inverse Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0: PWM3 output polar inverse Disable,1: PWM3 output polar inverse Enable"
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bitfld.long 0x8 24. "CH3EN,PWM-timer 3 Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
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bitfld.long 0x8 19. "CH2MOD,PWM-timer 2 Auto-reload/One-shot Mode (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nNote: If there is a transition at this bit it will cause CNR2 and CMR2 be cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 18. "CH2INV,PWM-timer 2 Output Inverter Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled"
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bitfld.long 0x8 17. "CH2PINV,PWM-timer 2 Output Polar Inverse Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n" "0: PWM2 output polar inverse Disabled,1: PWM2 output polar inverse Enabled"
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bitfld.long 0x8 16. "CH2EN,PWM-timer 2 Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
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bitfld.long 0x8 11. "CH1MOD,PWM-timer 1 Auto-reload/One-shot Mode (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nNote: If there is a transition at this bit it will cause CNR1 and CMR1 be cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 10. "CH1INV,PWM-timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n" "0: Inverter Disable,1: Inverter Enable"
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bitfld.long 0x8 9. "CH1PINV,PWM-timer 1 Output Polar Inverse Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n" "0: PWM1 output polar inverse Disabled,1: PWM1 output polar inverse Enabled"
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bitfld.long 0x8 8. "CH1EN,PWM-timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
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bitfld.long 0x8 5. "DZEN23,Dead-zone 2 Generator Enable (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7.." "0: Disabled,1: Enabled"
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bitfld.long 0x8 4. "DZEN01,Dead-zone 0 Generator Enable (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5.." "0: Disabled,1: Enabled"
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bitfld.long 0x8 3. "CH0MOD,PWM-timer 0 Auto-reload/One-shot Mode (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit it will cause CNR0 and CMR0 be cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 2. "CH0INV,PWM-timer 0 Output Inverter Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled"
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bitfld.long 0x8 1. "CH0PINV,PWM-timer 0 Output Polar Inverse Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n" "0: PWM0 output polar inverse Disabled,1: PWM0 output polar inverse Enabled"
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bitfld.long 0x8 0. "CH0EN,PWM-timer 0 Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n" "0: The corresponding PWM-Timer stops running,1: The corresponding PWM-Timer starts running"
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line.long 0xC "CNR0,PWM Counter Register 0"
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hexmask.long.word 0xC 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.."
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line.long 0x10 "CMR0,PWM Comparator Register 0"
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hexmask.long.word 0x10 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle."
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rgroup.long 0x14++0x3
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line.long 0x0 "PDR0,PWM Data Register 0"
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hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter."
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group.long 0x18++0x7
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line.long 0x0 "CNR1,PWM Counter Register 1"
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hexmask.long.word 0x0 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.."
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line.long 0x4 "CMR1,PWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle."
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rgroup.long 0x20++0x3
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line.long 0x0 "PDR1,PWM Data Register 1"
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hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter."
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group.long 0x24++0x7
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line.long 0x0 "CNR2,PWM Counter Register 2"
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hexmask.long.word 0x0 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.."
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line.long 0x4 "CMR2,PWM Comparator Register 2"
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hexmask.long.word 0x4 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle."
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rgroup.long 0x2C++0x3
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line.long 0x0 "PDR2,PWM Data Register 2"
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hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter."
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group.long 0x30++0x7
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line.long 0x0 "CNR3,PWM Counter Register 3"
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hexmask.long.word 0x0 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.."
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line.long 0x4 "CMR3,PWM Comparator Register 3"
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hexmask.long.word 0x4 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle."
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rgroup.long 0x38++0x3
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line.long 0x0 "PDR3,PWM Data Register 3"
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hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter."
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group.long 0x3C++0xB
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line.long 0x0 "PBCR,PWM Backward Compatible Register"
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bitfld.long 0x0 0. "BCn,PWM Backward Compatible Register\nRefer to the CCR0/CCR2 register bit 6 7 22 23 description\nNote: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being cleared when writing CCR0/CCR2." "0: Configure write 0 to clear CFLRI0~3 and CRLRI0~3,1: Configure write 1 to clear CFLRI0~3 and CRLRI0~3"
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line.long 0x4 "PIER,PWM Interrupt Enable Register"
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bitfld.long 0x4 17. "INT23TYPE,PWM23 Interrupt Period Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only." "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches CNRn.."
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bitfld.long 0x4 16. "INT01TYPE,PWM01 Interrupt Period Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only." "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches CNRn.."
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bitfld.long 0x4 11. "PWMDIE3,PWM Channel 3 Duty Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 10. "PWMDIE2,PWM Channel 2 Duty Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 9. "PWMDIE1,PWM Channel 1 Duty Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 8. "PWMDIE0,PWM Channel 0 Duty Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 3. "PWMIE3,PWM Channel 3 Period Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 2. "PWMIE2,PWM Channel 2 Period Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 1. "PWMIE1,PWM Channel 1 Period Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 0. "PWMIE0,PWM Channel 0 Period Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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line.long 0x8 "PIIR,PWM Interrupt Indication Register"
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bitfld.long 0x8 11. "PWMDIF3,PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
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bitfld.long 0x8 10. "PWMDIF2,PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
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bitfld.long 0x8 9. "PWMDIF1,PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
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bitfld.long 0x8 8. "PWMDIF0,PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
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bitfld.long 0x8 3. "PWMIF3,PWM Channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1"
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bitfld.long 0x8 2. "PWMIF2,PWM Channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1"
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bitfld.long 0x8 1. "PWMIF1,PWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1"
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bitfld.long 0x8 0. "PWMIF0,PWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1"
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group.long 0x50++0x7
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line.long 0x0 "CCR0,PWM Capture Control Register 0"
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bitfld.long 0x0 23. "CFLRI1,CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1"
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bitfld.long 0x0 22. "CRLRI1,CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1"
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bitfld.long 0x0 20. "CAPIF1,Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0." "0,1"
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bitfld.long 0x0 19. "CAPCH1EN,Channel 1 Capture Function Enable\nWhen Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 1 Interrupt." "0: Capture function on PWM group channel 1 Disabled,1: Capture function on PWM group channel 1 Enabled"
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bitfld.long 0x0 18. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 1 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
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bitfld.long 0x0 17. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 1 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
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bitfld.long 0x0 16. "INV1,Channel 1 Inverter Enable\n" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.."
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bitfld.long 0x0 7. "CFLRI0,CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can.." "0,1"
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bitfld.long 0x0 6. "CRLRI0,CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can.." "0,1"
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bitfld.long 0x0 4. "CAPIF0,Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0." "0,1"
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bitfld.long 0x0 3. "CAPCH0EN,Channel 0 Capture Function Enable\nWhen Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 0 Interrupt." "0: Capture function on PWM group channel 0 Disabled,1: Capture function on PWM group channel 0 Enabled"
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bitfld.long 0x0 2. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 0 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
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bitfld.long 0x0 1. "CRL_IE0,Channel 0 Rising Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 0 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
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bitfld.long 0x0 0. "INV0,Channel 0 Inverter Enable\n" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.."
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line.long 0x4 "CCR2,PWM Capture Control Register 2"
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bitfld.long 0x4 23. "CFLRI3,CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can.." "0,1"
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bitfld.long 0x4 22. "CRLRI3,CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can.." "0,1"
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bitfld.long 0x4 20. "CAPIF3,Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0" "0,1"
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bitfld.long 0x4 19. "CAPCH3EN,Channel 3 Capture Function Enable\nWhen Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 3 Interrupt." "0: Capture function on PWM group channel 3 Disabled,1: Capture function on PWM group channel 3 Enabled"
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bitfld.long 0x4 18. "CFL_IE3,Channel 3 Falling Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 3 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
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bitfld.long 0x4 17. "CRL_IE3,Channel 3 Rising Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 3 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
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bitfld.long 0x4 16. "INV3,Channel 3 Inverter Enable\n" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.."
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bitfld.long 0x4 7. "CFLRI2,CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1"
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bitfld.long 0x4 6. "CRLRI2,CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can.." "0,1"
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bitfld.long 0x4 4. "CAPIF2,Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0" "0,1"
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bitfld.long 0x4 3. "CAPCH2EN,Channel 2 Capture Function Enable\nWhen Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 2 Interrupt." "0: Capture function on PWM group channel 2 Disabled,1: Capture function on PWM group channel 2 Enabled"
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bitfld.long 0x4 2. "CFL_IE2,Channel 2 Falling Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 2 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
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bitfld.long 0x4 1. "CRL_IE2,Channel 2 Rising Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 2 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
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bitfld.long 0x4 0. "INV2,Channel 2 Inverter Enable\n" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.."
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rgroup.long 0x58++0x1F
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line.long 0x0 "CRLR0,PWM Capture Rising Latch Register (Channel 0)"
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hexmask.long.word 0x0 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition."
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line.long 0x4 "CFLR0,PWM Capture Falling Latch Register (Channel 0)"
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hexmask.long.word 0x4 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition."
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line.long 0x8 "CRLR1,PWM Capture Rising Latch Register (Channel 1)"
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hexmask.long.word 0x8 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition."
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line.long 0xC "CFLR1,PWM Capture Falling Latch Register (Channel 1)"
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hexmask.long.word 0xC 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition."
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line.long 0x10 "CRLR2,PWM Capture Rising Latch Register (Channel 2)"
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hexmask.long.word 0x10 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition."
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line.long 0x14 "CFLR2,PWM Capture Falling Latch Register (Channel 2)"
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hexmask.long.word 0x14 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition."
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line.long 0x18 "CRLR3,PWM Capture Rising Latch Register (Channel 3)"
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hexmask.long.word 0x18 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition."
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line.long 0x1C "CFLR3,PWM Capture Falling Latch Register (Channel 3)"
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hexmask.long.word 0x1C 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition."
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group.long 0x78++0xF
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line.long 0x0 "CAPENR,PWM Capture Input 0~3 Enable Register"
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bitfld.long 0x0 3. "CINEN3,Channel 3 Capture Input Enable\n" "0: PWM Channel 3 capture input path Disabled. The..,1: PWM Channel 3 capture input path Enabled. The.."
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bitfld.long 0x0 2. "CINEN2,Channel 2 Capture Input Enable\n" "0: PWM Channel 2 capture input path Disabled. The..,1: PWM Channel 2 capture input path Enabled. The.."
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bitfld.long 0x0 1. "CINEN1,Channel 1 Capture Input Enable\n" "0: PWM Channel 1 capture input path Disabled. The..,1: PWM Channel 1 capture input path Enabled. The.."
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bitfld.long 0x0 0. "CINEN0,Channel 0 Capture Input Enable\n" "0: PWM Channel 0 capture input path Disabled. The..,1: PWM Channel 0 capture input path Enabled. The.."
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line.long 0x4 "POE,PWM Output Enable for Channel 0~3"
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bitfld.long 0x4 3. "POE3,Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled"
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bitfld.long 0x4 2. "POE2,Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled"
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bitfld.long 0x4 1. "POE1,Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled"
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bitfld.long 0x4 0. "POE0,Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled"
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line.long 0x8 "TCON,PWM Trigger Control for Channel 0~3"
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bitfld.long 0x8 3. "PWM3TEN,Channel 3 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 3 trigger ADC function Disabled,1: PWM channel 3 trigger ADC function Enabled"
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bitfld.long 0x8 2. "PWM2TEN,Channel 2 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 2 trigger ADC function Disabled,1: PWM channel 2 trigger ADC function Enabled"
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bitfld.long 0x8 1. "PWM1TEN,Channel 1 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 1 trigger ADC function Disabled,1: PWM channel 1 trigger ADC function Enabled"
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bitfld.long 0x8 0. "PWM0TEN,Channel 0 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 0 trigger ADC function Disabled,1: PWM channel 0 trigger ADC function Enabled"
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line.long 0xC "TSTATUS,PWM Trigger Status Register"
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bitfld.long 0xC 3. "PWM3TF,Channel 3 Center-aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1"
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bitfld.long 0xC 2. "PWM2TF,Channel 2 Center-aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1"
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bitfld.long 0xC 1. "PWM1TF,Channel 1 Center-aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1"
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bitfld.long 0xC 0. "PWM0TF,Channel 0 Center-aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM0TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1"
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rgroup.long 0x88++0xF
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line.long 0x0 "SYNCBUSY0,PWM0 Synchronous Busy Status Register"
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bitfld.long 0x0 0. "S_BUSY,PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check.." "0,1"
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line.long 0x4 "SYNCBUSY1,PWM1 Synchronous Busy Status Register"
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bitfld.long 0x4 0. "S_BUSY,PWM Synchronous Busy\nWhen software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check.." "0,1"
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line.long 0x8 "SYNCBUSY2,PWM2 Synchronous Busy Status Register"
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bitfld.long 0x8 0. "S_BUSY,PWM Synchronous Busy\nWhen software writes CNR2/CMR2/PPR or switches PWM2 operation mode (PCR[19]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software need to check.." "0,1"
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line.long 0xC "SYNCBUSY3,PWM3 Synchronous Busy Status Register"
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bitfld.long 0xC 0. "S_BUSY,PWM Synchronous Busy\nWhen software writes CNR3/CMR3/PPR or switches PWM3 operation mode (PCR[27]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check.." "0,1"
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tree.end
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tree "PWMB"
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base ad:0x40140000
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group.long 0x0++0x13
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line.long 0x0 "PPR,PWM Prescaler Register"
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hexmask.long.byte 0x0 24.--31. 1. "DZI23,Dead-zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n"
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hexmask.long.byte 0x0 16.--23. 1. "DZI01,Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n"
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hexmask.long.byte 0x0 8.--15. 1. "CP23,Clock Prescaler 2 (PWM-timer2 / 3 for Group A and PWM-timer 6 / 7 for Group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer\n"
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hexmask.long.byte 0x0 0.--7. 1. "CP01,Clock Prescaler 0 (PWM-timer 0 / 1 for Group A and PWM-timer 4 / 5 for Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer\n"
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line.long 0x4 "CSR,PWM Clock Source Divider Select Register"
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bitfld.long 0x4 12.--14. "CSR3,PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 8.--10. "CSR2,PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 4.--6. "CSR1,PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0.--2. "CSR0,PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
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line.long 0x8 "PCR,PWM Control Register"
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bitfld.long 0x8 31. "PWM23TYPE,PWM23 Aligned Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\n" "0: Edge-aligned type,1: Center-aligned type"
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bitfld.long 0x8 30. "PWM01TYPE,PWM01 Aligned Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\n" "0: Edge-aligned type,1: Center-aligned type"
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bitfld.long 0x8 27. "CH3MOD,PWM-timer 3 Auto-reload/One-shot Mode (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\nNote: If there is a transition at this bit it will cause CNR3 and CMR3 be cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 26. "CH3INV,PWM-timer 3 Output Inverter Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled"
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bitfld.long 0x8 25. "CH3PINV,PWM-timer 3 Output Polar Inverse Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0: PWM3 output polar inverse Disable,1: PWM3 output polar inverse Enable"
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bitfld.long 0x8 24. "CH3EN,PWM-timer 3 Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
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bitfld.long 0x8 19. "CH2MOD,PWM-timer 2 Auto-reload/One-shot Mode (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nNote: If there is a transition at this bit it will cause CNR2 and CMR2 be cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 18. "CH2INV,PWM-timer 2 Output Inverter Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled"
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bitfld.long 0x8 17. "CH2PINV,PWM-timer 2 Output Polar Inverse Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n" "0: PWM2 output polar inverse Disabled,1: PWM2 output polar inverse Enabled"
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bitfld.long 0x8 16. "CH2EN,PWM-timer 2 Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
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bitfld.long 0x8 11. "CH1MOD,PWM-timer 1 Auto-reload/One-shot Mode (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nNote: If there is a transition at this bit it will cause CNR1 and CMR1 be cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 10. "CH1INV,PWM-timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n" "0: Inverter Disable,1: Inverter Enable"
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bitfld.long 0x8 9. "CH1PINV,PWM-timer 1 Output Polar Inverse Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n" "0: PWM1 output polar inverse Disabled,1: PWM1 output polar inverse Enabled"
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bitfld.long 0x8 8. "CH1EN,PWM-timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
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bitfld.long 0x8 5. "DZEN23,Dead-zone 2 Generator Enable (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7.." "0: Disabled,1: Enabled"
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bitfld.long 0x8 4. "DZEN01,Dead-zone 0 Generator Enable (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5.." "0: Disabled,1: Enabled"
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bitfld.long 0x8 3. "CH0MOD,PWM-timer 0 Auto-reload/One-shot Mode (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit it will cause CNR0 and CMR0 be cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 2. "CH0INV,PWM-timer 0 Output Inverter Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n" "0: Inverter Disabled,1: Inverter Enabled"
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bitfld.long 0x8 1. "CH0PINV,PWM-timer 0 Output Polar Inverse Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n" "0: PWM0 output polar inverse Disabled,1: PWM0 output polar inverse Enabled"
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bitfld.long 0x8 0. "CH0EN,PWM-timer 0 Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n" "0: The corresponding PWM-Timer stops running,1: The corresponding PWM-Timer starts running"
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line.long 0xC "CNR0,PWM Counter Register 0"
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hexmask.long.word 0xC 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.."
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line.long 0x10 "CMR0,PWM Comparator Register 0"
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hexmask.long.word 0x10 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle."
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rgroup.long 0x14++0x3
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line.long 0x0 "PDR0,PWM Data Register 0"
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hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter."
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group.long 0x18++0x7
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line.long 0x0 "CNR1,PWM Counter Register 1"
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hexmask.long.word 0x0 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.."
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line.long 0x4 "CMR1,PWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle."
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rgroup.long 0x20++0x3
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line.long 0x0 "PDR1,PWM Data Register 1"
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hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter."
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group.long 0x24++0x7
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line.long 0x0 "CNR2,PWM Counter Register 2"
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hexmask.long.word 0x0 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.."
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line.long 0x4 "CMR2,PWM Comparator Register 2"
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hexmask.long.word 0x4 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle."
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rgroup.long 0x2C++0x3
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line.long 0x0 "PDR2,PWM Data Register 2"
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hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter."
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group.long 0x30++0x7
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line.long 0x0 "CNR3,PWM Counter Register 3"
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hexmask.long.word 0x0 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF the PWM.."
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line.long 0x4 "CMR3,PWM Comparator Register 3"
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hexmask.long.word 0x4 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle."
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rgroup.long 0x38++0x3
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line.long 0x0 "PDR3,PWM Data Register 3"
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hexmask.long.word 0x0 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter."
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group.long 0x3C++0xB
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line.long 0x0 "PBCR,PWM Backward Compatible Register"
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bitfld.long 0x0 0. "BCn,PWM Backward Compatible Register\nRefer to the CCR0/CCR2 register bit 6 7 22 23 description\nNote: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being cleared when writing CCR0/CCR2." "0: Configure write 0 to clear CFLRI0~3 and CRLRI0~3,1: Configure write 1 to clear CFLRI0~3 and CRLRI0~3"
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line.long 0x4 "PIER,PWM Interrupt Enable Register"
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bitfld.long 0x4 17. "INT23TYPE,PWM23 Interrupt Period Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A PWM6 and PWM7 Pair for PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only." "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches CNRn.."
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bitfld.long 0x4 16. "INT01TYPE,PWM01 Interrupt Period Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A PWM4 and PWM5 Pair for PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only." "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches CNRn.."
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bitfld.long 0x4 11. "PWMDIE3,PWM Channel 3 Duty Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 10. "PWMDIE2,PWM Channel 2 Duty Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 9. "PWMDIE1,PWM Channel 1 Duty Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 8. "PWMDIE0,PWM Channel 0 Duty Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 3. "PWMIE3,PWM Channel 3 Period Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 2. "PWMIE2,PWM Channel 2 Period Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 1. "PWMIE1,PWM Channel 1 Period Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x4 0. "PWMIE0,PWM Channel 0 Period Interrupt Enable\n" "0: Interrupt Disabled,1: Interrupt Enabled"
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line.long 0x8 "PIIR,PWM Interrupt Indication Register"
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bitfld.long 0x8 11. "PWMDIF3,PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
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bitfld.long 0x8 10. "PWMDIF2,PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
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bitfld.long 0x8 9. "PWMDIF1,PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
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bitfld.long 0x8 8. "PWMDIF0,PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
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bitfld.long 0x8 3. "PWMIF3,PWM Channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1"
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bitfld.long 0x8 2. "PWMIF2,PWM Channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1"
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bitfld.long 0x8 1. "PWMIF1,PWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1"
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bitfld.long 0x8 0. "PWMIF0,PWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0." "0,1"
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group.long 0x50++0x7
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line.long 0x0 "CCR0,PWM Capture Control Register 0"
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bitfld.long 0x0 23. "CFLRI1,CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1"
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bitfld.long 0x0 22. "CRLRI1,CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1"
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bitfld.long 0x0 20. "CAPIF1,Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0." "0,1"
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bitfld.long 0x0 19. "CAPCH1EN,Channel 1 Capture Function Enable\nWhen Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 1 Interrupt." "0: Capture function on PWM group channel 1 Disabled,1: Capture function on PWM group channel 1 Enabled"
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bitfld.long 0x0 18. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 1 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
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bitfld.long 0x0 17. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 1 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
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bitfld.long 0x0 16. "INV1,Channel 1 Inverter Enable\n" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.."
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bitfld.long 0x0 7. "CFLRI0,CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can.." "0,1"
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bitfld.long 0x0 6. "CRLRI0,CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can.." "0,1"
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bitfld.long 0x0 4. "CAPIF0,Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0." "0,1"
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bitfld.long 0x0 3. "CAPCH0EN,Channel 0 Capture Function Enable\nWhen Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 0 Interrupt." "0: Capture function on PWM group channel 0 Disabled,1: Capture function on PWM group channel 0 Enabled"
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bitfld.long 0x0 2. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 0 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
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bitfld.long 0x0 1. "CRL_IE0,Channel 0 Rising Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 0 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
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bitfld.long 0x0 0. "INV0,Channel 0 Inverter Enable\n" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.."
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line.long 0x4 "CCR2,PWM Capture Control Register 2"
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bitfld.long 0x4 23. "CFLRI3,CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can.." "0,1"
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bitfld.long 0x4 22. "CRLRI3,CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can.." "0,1"
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bitfld.long 0x4 20. "CAPIF3,Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0" "0,1"
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bitfld.long 0x4 19. "CAPCH3EN,Channel 3 Capture Function Enable\nWhen Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 3 Interrupt." "0: Capture function on PWM group channel 3 Disabled,1: Capture function on PWM group channel 3 Enabled"
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bitfld.long 0x4 18. "CFL_IE3,Channel 3 Falling Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 3 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
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bitfld.long 0x4 17. "CRL_IE3,Channel 3 Rising Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 3 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
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bitfld.long 0x4 16. "INV3,Channel 3 Inverter Enable\n" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.."
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bitfld.long 0x4 7. "CFLRI2,CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1"
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bitfld.long 0x4 6. "CRLRI2,CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can.." "0,1"
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bitfld.long 0x4 4. "CAPIF2,Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0" "0,1"
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bitfld.long 0x4 3. "CAPCH2EN,Channel 2 Capture Function Enable\nWhen Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 2 Interrupt." "0: Capture function on PWM group channel 2 Disabled,1: Capture function on PWM group channel 2 Enabled"
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bitfld.long 0x4 2. "CFL_IE2,Channel 2 Falling Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 2 has falling transition Capture will issue an Interrupt." "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
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bitfld.long 0x4 1. "CRL_IE2,Channel 2 Rising Latch Interrupt Enable\nWhen Enabled if Capture detects PWM group channel 2 has rising transition Capture will issue an Interrupt." "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
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bitfld.long 0x4 0. "INV2,Channel 2 Inverter Enable\n" "0: Inverter Disabled,1: Inverter Enabled. Reverse the input signal from.."
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rgroup.long 0x58++0x1F
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line.long 0x0 "CRLR0,PWM Capture Rising Latch Register (Channel 0)"
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hexmask.long.word 0x0 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition."
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line.long 0x4 "CFLR0,PWM Capture Falling Latch Register (Channel 0)"
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hexmask.long.word 0x4 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition."
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line.long 0x8 "CRLR1,PWM Capture Rising Latch Register (Channel 1)"
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hexmask.long.word 0x8 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition."
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line.long 0xC "CFLR1,PWM Capture Falling Latch Register (Channel 1)"
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hexmask.long.word 0xC 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition."
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line.long 0x10 "CRLR2,PWM Capture Rising Latch Register (Channel 2)"
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hexmask.long.word 0x10 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition."
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line.long 0x14 "CFLR2,PWM Capture Falling Latch Register (Channel 2)"
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hexmask.long.word 0x14 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition."
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line.long 0x18 "CRLR3,PWM Capture Rising Latch Register (Channel 3)"
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hexmask.long.word 0x18 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition."
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line.long 0x1C "CFLR3,PWM Capture Falling Latch Register (Channel 3)"
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hexmask.long.word 0x1C 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition."
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group.long 0x78++0xF
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line.long 0x0 "CAPENR,PWM Capture Input 0~3 Enable Register"
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bitfld.long 0x0 3. "CINEN3,Channel 3 Capture Input Enable\n" "0: PWM Channel 3 capture input path Disabled. The..,1: PWM Channel 3 capture input path Enabled. The.."
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bitfld.long 0x0 2. "CINEN2,Channel 2 Capture Input Enable\n" "0: PWM Channel 2 capture input path Disabled. The..,1: PWM Channel 2 capture input path Enabled. The.."
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bitfld.long 0x0 1. "CINEN1,Channel 1 Capture Input Enable\n" "0: PWM Channel 1 capture input path Disabled. The..,1: PWM Channel 1 capture input path Enabled. The.."
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bitfld.long 0x0 0. "CINEN0,Channel 0 Capture Input Enable\n" "0: PWM Channel 0 capture input path Disabled. The..,1: PWM Channel 0 capture input path Enabled. The.."
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line.long 0x4 "POE,PWM Output Enable for Channel 0~3"
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bitfld.long 0x4 3. "POE3,Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled"
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bitfld.long 0x4 2. "POE2,Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled"
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bitfld.long 0x4 1. "POE1,Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled"
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bitfld.long 0x4 0. "POE0,Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled"
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line.long 0x8 "TCON,PWM Trigger Control for Channel 0~3"
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bitfld.long 0x8 3. "PWM3TEN,Channel 3 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 3 trigger ADC function Disabled,1: PWM channel 3 trigger ADC function Enabled"
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bitfld.long 0x8 2. "PWM2TEN,Channel 2 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 2 trigger ADC function Disabled,1: PWM channel 2 trigger ADC function Enabled"
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bitfld.long 0x8 1. "PWM1TEN,Channel 1 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 1 trigger ADC function Disabled,1: PWM channel 1 trigger ADC function Enabled"
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bitfld.long 0x8 0. "PWM0TEN,Channel 0 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 0 trigger ADC function Disabled,1: PWM channel 0 trigger ADC function Enabled"
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line.long 0xC "TSTATUS,PWM Trigger Status Register"
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bitfld.long 0xC 3. "PWM3TF,Channel 3 Center-aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1"
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bitfld.long 0xC 2. "PWM2TF,Channel 2 Center-aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1"
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bitfld.long 0xC 1. "PWM1TF,Channel 1 Center-aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1"
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bitfld.long 0xC 0. "PWM0TF,Channel 0 Center-aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM0TEN bit is set to 1. After this bit is set to 1 ADC will start conversion if ADC triggered source.." "0,1"
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rgroup.long 0x88++0xF
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line.long 0x0 "SYNCBUSY0,PWM0 Synchronous Busy Status Register"
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bitfld.long 0x0 0. "S_BUSY,PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check.." "0,1"
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line.long 0x4 "SYNCBUSY1,PWM1 Synchronous Busy Status Register"
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bitfld.long 0x4 0. "S_BUSY,PWM Synchronous Busy\nWhen software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check.." "0,1"
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line.long 0x8 "SYNCBUSY2,PWM2 Synchronous Busy Status Register"
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bitfld.long 0x8 0. "S_BUSY,PWM Synchronous Busy\nWhen software writes CNR2/CMR2/PPR or switches PWM2 operation mode (PCR[19]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software need to check.." "0,1"
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line.long 0xC "SYNCBUSY3,PWM3 Synchronous Busy Status Register"
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bitfld.long 0xC 0. "S_BUSY,PWM Synchronous Busy\nWhen software writes CNR3/CMR3/PPR or switches PWM3 operation mode (PCR[27]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check.." "0,1"
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tree.end
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tree.end
|
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tree "RTC (Real Time Clock)"
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base ad:0x40008000
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group.long 0x0++0x23
|
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line.long 0x0 "INIR,RTC Initiation Register"
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hexmask.long 0x0 0.--31. 1. "INIR,RTC Initiation\nRead return current RTC active status\nA write of 0xa5eb1357 to make RTC leaving reset state.\nWhen RTC block is powered on RTC is in reset state. User has to write a number 0x a5eb1357 to INIR register to make RTC leave reset.."
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line.long 0x4 "AER,RTC Access Enable Register"
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rbitfld.long 0x4 16. "ENF,RTC Register Access Enable Flag (Read Only)\n" "0: RTC register read/write access Disabled,1: RTC register read/write access Enabled"
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hexmask.long.word 0x4 0.--15. 1. "AER,RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC registers read/write access and keep 1024 RTC clocks."
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line.long 0x8 "FCR,RTC Frequency Compensation Register"
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hexmask.long.byte 0x8 8.--11. 1. "INTEGER,Integer Part\n"
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hexmask.long.byte 0x8 0.--5. 1. "FRACTION,Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number. Refer to 6.11.4.4 for the examples."
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line.long 0xC "TLR,RTC Time Loading Register"
|
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bitfld.long 0xC 20.--21. "_10HR,10-Hour Time Digit (0~3)" "0,1,2,3"
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hexmask.long.byte 0xC 16.--19. 1. "_1HR,1-Hour Time Digit (0~9)"
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bitfld.long 0xC 12.--14. "_10MIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 8.--11. 1. "_1MIN,1-Min Time Digit (0~9)"
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bitfld.long 0xC 4.--6. "_10SEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 0.--3. 1. "_1SEC,1-Sec Time Digit (0~9)"
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line.long 0x10 "CLR,RTC Calendar Loading Register"
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hexmask.long.byte 0x10 20.--23. 1. "_10YEAR,10-Year Calendar Digit (0~9)"
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hexmask.long.byte 0x10 16.--19. 1. "_1YEAR,1-Year Calendar Digit (0~9)"
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bitfld.long 0x10 12. "_10MON,10-Month Calendar Digit (0~1)" "0,1"
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hexmask.long.byte 0x10 8.--11. 1. "_1MON,1-Month Calendar Digit (0~9)"
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bitfld.long 0x10 4.--5. "_10DAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
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hexmask.long.byte 0x10 0.--3. 1. "_1DAY,1-Day Calendar Digit (0~9)"
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line.long 0x14 "TSSR,RTC Time Scale Selection Register"
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bitfld.long 0x14 0. "_24H_12H,24-hour / 12-hour Time Scale Selection\n" "0: Selected as 12-hour time scale with AM and PM..,1: Selected as 24-hour time scale"
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line.long 0x18 "DWR,RTC Day of the Week Register"
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bitfld.long 0x18 0.--2. "DWR,Day of the Week Register \n" "0,1,2,3,4,5,6,7"
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line.long 0x1C "TAR,RTC Time Alarm Register"
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bitfld.long 0x1C 20.--21. "_10HR,10-Hour Time Digit of Alarm Setting (0~3)" "0,1,2,3"
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hexmask.long.byte 0x1C 16.--19. 1. "_1HR,1-Hour Time Digit of Alarm Setting (0~9)"
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bitfld.long 0x1C 12.--14. "_10MIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x1C 8.--11. 1. "_1MIN,1-Min Time Digit of Alarm Setting (0~9)"
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bitfld.long 0x1C 4.--6. "_10SEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x1C 0.--3. 1. "_1SEC,1-Sec Time Digit of Alarm Setting (0~9)"
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line.long 0x20 "CAR,RTC Calendar Alarm Register"
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hexmask.long.byte 0x20 20.--23. 1. "_10YEAR,10-Year Calendar Digit of Alarm Setting (0~9)"
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hexmask.long.byte 0x20 16.--19. 1. "_1YEAR,1-Year Calendar Digit of Alarm Setting (0~9)"
|
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bitfld.long 0x20 12. "_10MON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
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hexmask.long.byte 0x20 8.--11. 1. "_1MON,1-Month Calendar Digit of Alarm Setting (0~9)"
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bitfld.long 0x20 4.--5. "_10DAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
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newline
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hexmask.long.byte 0x20 0.--3. 1. "_1DAY,1-Day Calendar Digit of Alarm Setting (0~9)"
|
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rgroup.long 0x24++0x3
|
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line.long 0x0 "LIR,RTC Leap Year Indication Register"
|
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bitfld.long 0x0 0. "LIR,Leap Year Indication Register (Read Only)\nThis bit indicates RTC current year is a leap year or not.\n" "0: This year is not a leap year,1: This year is a leap year"
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group.long 0x28++0xB
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line.long 0x0 "RIER,RTC Interrupt Enable Register"
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bitfld.long 0x0 1. "TIER,Time Tick Interrupt Enable\nThis bit is used to enable/disable RTC Time Tick Interrupt and generate an interrupt signal if TIF (RIIR [1] RTC Time Tick Interrupt Flag) is set to 1.\nThis bit will also trigger a wake-up event while system runs in.." "0: RTC Time Tick Interrupt Disabled,1: RTC Time Tick Interrupt Enabled"
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bitfld.long 0x0 0. "AIER,Alarm Interrupt Enable\nThis bit is used to enable/disable RTC Alarm Interrupt and generate an interrupt signal if AIF (RIIR [0] RTC Alarm Interrupt Flag) is set to 1.\nThis bit will also trigger a wake-up event while system runs in Idle/Power-Down.." "0: RTC Alarm Interrupt Disabled,1: RTC Alarm Interrupt Enabled"
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line.long 0x4 "RIIR,RTC Interrupt Indication Register"
|
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bitfld.long 0x4 1. "TIF,RTC Time Tick Interrupt Flag\nWhen RTC Time Tick time-out happened this bit will be set to 1 and an interrupt signal will be generated if TIER bit is set to 1.\nSoftware can clear this bit by writing 1 to it." "0,1"
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bitfld.long 0x4 0. "AIF,RTC Alarm Interrupt Flag\nWhen RTC real time counters TLR and CLR reach the alarm time setting registers TAR and CAR this bit will be set to 1 and an interrupt signal will be generated if AIER bit is set to 1. \nSoftware can clear this bit by.." "0,1"
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line.long 0x8 "TTR,RTC Time Tick Register"
|
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bitfld.long 0x8 0.--2. "TTR,Time Tick Register\n" "0,1,2,3,4,5,6,7"
|
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tree.end
|
|
tree "SC (Smart Card Host Interface)"
|
|
base ad:0x0
|
|
tree "SC0"
|
|
base ad:0x40190000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SC_RBR,SC Receiving Buffer Register."
|
|
hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register\nBy reading this register the SC will return an 8-bit received data."
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "SC_THR,SC Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the SC will send out an 8-bit data.\nNote: If SC_CTL[SC_CEN] not enabled this register cannot be programmed."
|
|
group.long 0x4++0x17
|
|
line.long 0x0 "SC_CTL,SC Control Register"
|
|
bitfld.long 0x0 24.--25. "CD_DEB_SEL,Card Detect De-bounce Select Register\n" "0,1,2,3"
|
|
bitfld.long 0x0 23. "TX_ERETRY_EN,TX Error Retry Enable Register\nThis bit enables transmitter retry function when parity error has occurred.\nNote: Software must fill TX_ERETRY value before enabling this bit." "0: TX error retry function Disabled,1: TX error retry function Enabled"
|
|
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bitfld.long 0x0 20.--22. "TX_ERETRY,TX Error Retry Count Register\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1 8 is the maximum retry number.\nNote2: This field.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 19. "RX_ERETRY_EN,RX Error Retry Enable Register\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill RX_ERETRY value before enabling this bit." "0: RX error retry function Disabled,1: RX error retry function Enabled"
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|
newline
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bitfld.long 0x0 16.--18. "RX_ERETRY,RX Error Retry Count Register\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred.\nNote1: The real maximum retry number is RX_ERETRY + 1 so 8 is the maximum retry number.\nNote2: This.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 15. "SLEN,Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2." "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
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bitfld.long 0x0 13.--14. "TMR_SEL,Timer Selection \n" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "BGT,Block Guard Time (BGT)\nIn TX mode hardware will auto hold off first character until BGT has elapsed regardless of the TX data.\n\nIn RX mode software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing. If the incoming.."
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newline
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bitfld.long 0x0 6.--7. "RX_FTRI_LEV,Rx Buffer Trigger Level \n" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "CON_SEL,Convention Selection\nNote: If AUTO_CON_EN enabled this fields must be ignored." "0: Direct convention,1: Reserved,?,?"
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newline
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bitfld.long 0x0 3. "AUTO_CON_EN,Auto Convention Enable\n" "0: Auto-convention Disabled,1: Auto-convention Enabled"
|
|
bitfld.long 0x0 2. "DIS_TX,TX Transition Disable\n" "0: Transceiver Enabled,1: Transceiver Disabled"
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|
newline
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bitfld.long 0x0 1. "DIS_RX,RX Transition Disable\nNote: If AUTO_CON_EN enabled this fields must be ignored." "0: Receiver Enabled,1: Receiver Disabled"
|
|
bitfld.long 0x0 0. "SC_CEN,SC Engine Enable\nSetting this bit to '1' will enable SC operation. If this bit is cleared SC will force all transition to IDLE state." "0,1"
|
|
line.long 0x4 "SC_ALTCTL,SC Alternate Control State Register"
|
|
rbitfld.long 0x4 15. "TMR2_ATV,Internal Timer2 Active State (Read Only)\nThis bit indicates the Timer2 counter status.\n" "0: Timer2 is not active,1: Timer2 is active"
|
|
rbitfld.long 0x4 14. "TMR1_ATV,Internal Timer1 Active State (Read Only)\nThis bit indicates the Timer1 counter status.\n" "0: Timer1 is not active,1: Timer1 is active"
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newline
|
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rbitfld.long 0x4 13. "TMR0_ATV,Internal Timer0 Active State (Read Only)\nThis bit indicates the Timer0 counter status.\n" "0: Timer0 is not active,1: Timer0 is active"
|
|
bitfld.long 0x4 12. "RX_BGT_EN,Check Receiver Block Guard Time Function Enable\n" "0: Check receiver block guard time function Disabled,1: Check receiver block guard time function Enabled"
|
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newline
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bitfld.long 0x4 8.--9. "INIT_SEL,Initial Timing Selection\n" "0,1,2,3"
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bitfld.long 0x4 7. "TMR2_SEN,Internal Timer2 Start Enable\nThis bit enables Timer2 to start counting. Software can fill '0' to stop it and set '1' to reload and count.\nNote3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL [RX_RST] to 1. So.." "0: Stops counting,1: Starts counting"
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bitfld.long 0x4 6. "TMR1_SEN,Internal Timer1 Start Enable\nThis bit enables Timer1 to start counting. Software can fill '0' to stop it and set '1' to reload and count.\nNote3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1 so don't.." "0: Stops counting,1: Starts counting"
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bitfld.long 0x4 5. "TMR0_SEN,Internal Timer0 Start Enable\nThis bit enables Timer0 to start counting. Software can fill '0' to stop it and set '1' to reload and count.\nNote3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't.." "0: Stops counting,1: Starts counting"
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bitfld.long 0x4 4. "WARST_EN,Warm Reset Sequence Generator Enable\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the SC_ISR[INIT_IS] will be set to.." "0: No effect,1: Warm reset sequence generator Enabled"
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bitfld.long 0x4 3. "ACT_EN,Activation Sequence Generator Enable\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to.." "0: No effect,1: Activation sequence generator Enabled"
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bitfld.long 0x4 2. "DACT_EN,Deactivation Sequence Generator Enable\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to.." "0: No effect,1: Deactivation sequence generator Enabled"
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bitfld.long 0x4 1. "RX_RST,Rx Software Reset\nWhen RX_RST is set all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles." "0: No effect,1: Reset the Rx internal state machine and pointers"
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bitfld.long 0x4 0. "TX_RST,TX Software Reset\nWhen TX_RST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers"
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line.long 0x8 "SC_EGTR,SC Extend Guard Time Register"
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hexmask.long.byte 0x8 0.--7. 1. "EGT,Extended Guard Time\nThis field indicates the extended guard time value.\n\nNote: The counter is ETU based and the real extended guard time is EGT."
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line.long 0xC "SC_RFTMR,SC Receiver Buffer Time-out Register"
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hexmask.long.word 0xC 0.--8. 1. "RFTM,SC Receiver Buffer Time-out Register (ETU Based)\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5\nNote2: Filling all '0' to this field indicates to disable this function."
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line.long 0x10 "SC_ETUCR,SC ETU Control Register"
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bitfld.long 0x10 15. "COMPEN_EN,Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled hardware will alternate between n-1 clock cycles and n clock cycles where n is the value to be written into the ETU_RDIV register.\n" "0: Compensation function Disabled,1: Compensation function Enabled"
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hexmask.long.word 0x10 0.--11. 1. "ETU_RDIV,ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote1: Software can configure this field but this field must be greater than 0x04.\nNote2: Software can configure this field but if the error rate is.."
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line.long 0x14 "SC_IER,SC Interrupt Enable Register"
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bitfld.long 0x14 10. "ACON_ERR_IE,Auto Convention Error Interrupt Enable \nThis field is used for auto-convention error interrupt enable.\n" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x14 9. "RTMR_IE,Receiver Buffer Time-out Interrupt Enable \nThis field is used for receiver buffer time-out interrupt enable.\n" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x14 8. "INIT_IE,Initial End Interrupt Enable\nThis field is used for activation (SC_ALTCTL [ACT_EN]) deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable.\n" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x14 7. "CD_IE,Card Detect Interrupt Enable\nThis field is used for card detect interrupt enable. The card detect status register is SC_PINCSR[CD_INS_F] and SC_PINCSR[CD_REM_F].\n" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x14 6. "BGT_IE,Block Guard Time Interrupt Enable\nThis field is used for block guard time interrupt enable.\n" "0: Block guard time Disabled,1: Block guard time Enabled"
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bitfld.long 0x14 5. "TMR2_IE,Timer2 Interrupt Enable\nThis field is used for TMR2 interrupt enable.\n" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x14 4. "TMR1_IE,Timer1 Interrupt Enable\nThis field is used for TMR1 interrupt enable.\n" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x14 3. "TMR0_IE,Timer0 Interrupt Enable\nThis field is used for TMR0 interrupt enable.\n" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x14 2. "TERR_IE,Transfer Error Interrupt Enable\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F) frame error (RX_EFR_F) parity error (RX_EPA_F) receiver.." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x14 1. "TBE_IE,Transmit Buffer Empty Interrupt Enable\nThis field is used for transmit buffer empty interrupt enable.\n" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x14 0. "RDA_IE,Receive Data Reach Interrupt Enable\nThis field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable.\n" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt Enabled"
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rgroup.long 0x1C++0x7
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line.long 0x0 "SC_ISR,SC Interrupt Status Register"
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bitfld.long 0x0 10. "ACON_ERR_IS,Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is not 0x3B or 0x3F this bit will be set.\nNote: This bit is read only but can be cleared by.." "0,1"
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bitfld.long 0x0 9. "RTMR_IS,Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit .." "0,1"
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bitfld.long 0x0 8. "INIT_IS,Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (SC_ALTCTL [ACT_EN]) deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag.\nNote: This bit is read only but it.." "0,1"
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bitfld.long 0x0 7. "CD_IS,Card Detect Interrupt Status Flag (Read Only)\nNote: If software wants to clear this field software must clear SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F]." "0,1"
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bitfld.long 0x0 6. "BGT_IS,Block Guard Time Interrupt Status Flag (Read Only)\nThis field is used for block guard time interrupt status flag.\nNote1: This bit is valid when SC_ALTCTL[RX_BGT_EN] is enabled.\nNote2: This bit is read only but it can be cleared by writing '1'.." "0,1"
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bitfld.long 0x0 5. "TMR2_IS,Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 4. "TMR1_IS,Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 3. "TMR0_IS,Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 2. "TERR_IS,Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error status is at the SC_TRSR register which includes receiver break error (RX_EBR_F) frame error (RX_EFR_F) parity.." "0,1"
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bitfld.long 0x0 1. "TBE_IS,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit software must.." "0,1"
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bitfld.long 0x0 0. "RDA_IS,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level (SC_CTL[RX_FTRI_LEV]) interrupt status flag.\nNote: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV]. If.." "0,1"
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line.long 0x4 "SC_TRSR,SC Transfer Status Register"
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bitfld.long 0x4 31. "TX_ATV,Transmit In Active Status Flag (Read Only)\nThis bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has not been transmitted.\nThis bit is cleared automatically when TX transfer is finished or the last byte.." "0,1"
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bitfld.long 0x4 30. "TX_OVER_REERR,Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x4 29. "TX_REERR,Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU." "0,1"
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bitfld.long 0x4 24.--25. "TX_POINT_F,Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register .." "0,1,2,3"
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bitfld.long 0x4 23. "RX_ATV,Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished." "0,1"
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bitfld.long 0x4 22. "RX_OVER_REERR,Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: If CPU enables receiver retries.." "0,1"
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bitfld.long 0x4 21. "RX_REERR,Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2 This bit is a flag and cannot generate any interrupt to.." "0,1"
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bitfld.long 0x4 16.--17. "RX_POINT_F,Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device RX_POINT_F increases one. When one byte of RX buffer is read by CPU RX_POINT_F decreases.." "0,1,2,3"
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bitfld.long 0x4 10. "TX_FULL_F,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.\nThis bit is set when TX pointer is equal to 4 otherwise is cleared by hardware." "0,1"
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bitfld.long 0x4 9. "TX_EMPTY_F,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data.." "0,1"
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bitfld.long 0x4 8. "TX_OVER_F,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full an additional write to SC_THR will cause this bit be set to '1' by hardware. \nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x4 6. "RX_EBR_F,Receiver Break Error Status Flag (Read Only)\nThis bit is set to '1' whenever the received data input (RX) held in the 'spacing state' (logic '0') is longer than a full word transmission time (that is the total time of 'start bit' + data bits +.." "0,1"
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bitfld.long 0x4 5. "RX_EFR_F,Receiver Frame Error Status Flag (Read Only)\nThis bit is set to '1' whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit is.." "0,1"
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bitfld.long 0x4 4. "RX_EPA_F,Receiver Parity Error Status Flag (Read Only)\nThis bit is set to '1' whenever the received character does not have a valid 'parity bit'.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: If CPU sets receiver.." "0,1"
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bitfld.long 0x4 2. "RX_FULL_F,Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4 otherwise it is cleared by hardware." "0,1"
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bitfld.long 0x4 1. "RX_EMPTY_F,Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of RX buffer has been read by CPU hardware set this bit to '1'. It will be cleared by hardware when SC receives any new data." "0,1"
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bitfld.long 0x4 0. "RX_OVER_F,RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes) this bit will be set.\nNote: This bit is read only but it can be cleared by writing.." "0,1"
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group.long 0x24++0xF
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line.long 0x0 "SC_PINCSR,SC Pin Control State Register"
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rbitfld.long 0x0 16. "SC_DATA_I_ST,SC Data Pin Status (Read Only)\nThis bit is the pin status of SC_DAT\n" "0: The SC_DAT pin is low,1: The SC_DAT pin is high"
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bitfld.long 0x0 11. "POW_INV,SC_PWR Pin Inverse\n" "0,1"
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bitfld.long 0x0 10. "CD_LEV,Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine is enabled." "0: When hardware detects the card detect pin from..,1: When hardware detects the card detect pin from.."
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bitfld.long 0x0 9. "SC_DATA_O,SC Data Output Pin \nThis bit is the pin status of SC_DAT but user can drive SC_DAT pin to high or low by setting this bit.\nWrite this field to drive SC_DAT pin.\nNote: When SC is at activation warm reset or deactivation mode this bit will.." "0: Drive SC_DAT pin to low.\nSC_DAT pin status is low,1: Drive SC_DAT pin to high.\nSC_DAT pin status is.."
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rbitfld.long 0x0 8. "SC_OEN_ST,SC Data Output Enable Pin Status (Read Only)\nThis bit is the output enable status of the SC_DAT pin.\n" "0: The SC_DAT pin state is output,1: The SC_DAT pin state is not output"
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bitfld.long 0x0 7. "ADAC_CD_EN,Auto Deactivation When Card Removal\nNote: When the card is removed hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an initial end interrupt to CPU." "0: Auto deactivation Disabled when hardware..,1: Auto deactivation Enabled when hardware detected.."
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bitfld.long 0x0 6. "CLK_KEEP,SC Clock Enable\nNote: When operating at activation warm reset or deactivation mode this bit will be changed automatically. So don't fill this field when operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running"
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rbitfld.long 0x0 4. "CD_PIN_ST,Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n" "0: The SC_CD pin state at low,1: The SC_CD pin state at high"
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rbitfld.long 0x0 3. "CD_INS_F,Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: The card detect engine will start after SC_CTL[SC_CEN] set." "0: No effect,1: Card insert"
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rbitfld.long 0x0 2. "CD_REM_F,Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever a card has been removed.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SC_CTL[SC_CEN] set." "0: No effect,1: Card removed"
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bitfld.long 0x0 1. "SC_RST,SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be.." "0: Drive SC_RST pin to low.\nSC_RST pin status is low,1: Drive SC_RST pin to high.\nSC_RST pin status is.."
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bitfld.long 0x0 0. "POW_EN,SC_POW_EN Pin Signal\n" "0: SC_PWR pin status is low,1: SC_PWR pin status is high"
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line.long 0x4 "SC_TMR0,SC Internal Timer Control Register 0"
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hexmask.long.byte 0x4 24.--27. 1. "MODE,Timer 0 Operation Mode Selection\n"
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hexmask.long.tbyte 0x4 0.--23. 1. "CNT,Timer 0 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values."
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line.long 0x8 "SC_TMR1,SC Internal Timer Control Register 1"
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hexmask.long.byte 0x8 24.--27. 1. "MODE,Timer 1 Operation Mode Selection\n"
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hexmask.long.byte 0x8 0.--7. 1. "CNT,Timer 1 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values."
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line.long 0xC "SC_TMR2,SC Internal Timer Control Register 2"
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hexmask.long.byte 0xC 24.--27. 1. "MODE,Timer 2 Operation Mode Selection\n"
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hexmask.long.byte 0xC 0.--7. 1. "CNT,Timer 2 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values."
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rgroup.long 0x38++0x7
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line.long 0x0 "SC_TDRA,SC Timer Current Data Register A"
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hexmask.long.tbyte 0x0 0.--23. 1. "TDR0,Timer0 Current Data Register (Read Only)\nThis field indicates the current count values of timer0."
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line.long 0x4 "SC_TDRB,SC Timer Current Data Register B"
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hexmask.long.byte 0x4 8.--15. 1. "TDR2,Timer2 Current Data Register (Read Only)\nThis field indicates the current count values of timer2."
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hexmask.long.byte 0x4 0.--7. 1. "TDR1,Timer1 Current Data Register (Read Only)\nThis field indicates the current count values of timer1."
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tree.end
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tree "SC1"
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base ad:0x40194000
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rgroup.long 0x0++0x3
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line.long 0x0 "SC_RBR,SC Receiving Buffer Register."
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hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register\nBy reading this register the SC will return an 8-bit received data."
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wgroup.long 0x0++0x3
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line.long 0x0 "SC_THR,SC Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the SC will send out an 8-bit data.\nNote: If SC_CTL[SC_CEN] not enabled this register cannot be programmed."
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group.long 0x4++0x17
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line.long 0x0 "SC_CTL,SC Control Register"
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bitfld.long 0x0 24.--25. "CD_DEB_SEL,Card Detect De-bounce Select Register\n" "0,1,2,3"
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bitfld.long 0x0 23. "TX_ERETRY_EN,TX Error Retry Enable Register\nThis bit enables transmitter retry function when parity error has occurred.\nNote: Software must fill TX_ERETRY value before enabling this bit." "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x0 20.--22. "TX_ERETRY,TX Error Retry Count Register\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1 8 is the maximum retry number.\nNote2: This field.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 19. "RX_ERETRY_EN,RX Error Retry Enable Register\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill RX_ERETRY value before enabling this bit." "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x0 16.--18. "RX_ERETRY,RX Error Retry Count Register\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred.\nNote1: The real maximum retry number is RX_ERETRY + 1 so 8 is the maximum retry number.\nNote2: This.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 15. "SLEN,Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2." "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
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bitfld.long 0x0 13.--14. "TMR_SEL,Timer Selection \n" "0,1,2,3"
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hexmask.long.byte 0x0 8.--12. 1. "BGT,Block Guard Time (BGT)\nIn TX mode hardware will auto hold off first character until BGT has elapsed regardless of the TX data.\n\nIn RX mode software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing. If the incoming.."
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bitfld.long 0x0 6.--7. "RX_FTRI_LEV,Rx Buffer Trigger Level \n" "0,1,2,3"
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bitfld.long 0x0 4.--5. "CON_SEL,Convention Selection\nNote: If AUTO_CON_EN enabled this fields must be ignored." "0: Direct convention,1: Reserved,?,?"
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bitfld.long 0x0 3. "AUTO_CON_EN,Auto Convention Enable\n" "0: Auto-convention Disabled,1: Auto-convention Enabled"
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bitfld.long 0x0 2. "DIS_TX,TX Transition Disable\n" "0: Transceiver Enabled,1: Transceiver Disabled"
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bitfld.long 0x0 1. "DIS_RX,RX Transition Disable\nNote: If AUTO_CON_EN enabled this fields must be ignored." "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x0 0. "SC_CEN,SC Engine Enable\nSetting this bit to '1' will enable SC operation. If this bit is cleared SC will force all transition to IDLE state." "0,1"
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line.long 0x4 "SC_ALTCTL,SC Alternate Control State Register"
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rbitfld.long 0x4 15. "TMR2_ATV,Internal Timer2 Active State (Read Only)\nThis bit indicates the Timer2 counter status.\n" "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x4 14. "TMR1_ATV,Internal Timer1 Active State (Read Only)\nThis bit indicates the Timer1 counter status.\n" "0: Timer1 is not active,1: Timer1 is active"
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rbitfld.long 0x4 13. "TMR0_ATV,Internal Timer0 Active State (Read Only)\nThis bit indicates the Timer0 counter status.\n" "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x4 12. "RX_BGT_EN,Check Receiver Block Guard Time Function Enable\n" "0: Check receiver block guard time function Disabled,1: Check receiver block guard time function Enabled"
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bitfld.long 0x4 8.--9. "INIT_SEL,Initial Timing Selection\n" "0,1,2,3"
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bitfld.long 0x4 7. "TMR2_SEN,Internal Timer2 Start Enable\nThis bit enables Timer2 to start counting. Software can fill '0' to stop it and set '1' to reload and count.\nNote3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL [RX_RST] to 1. So.." "0: Stops counting,1: Starts counting"
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bitfld.long 0x4 6. "TMR1_SEN,Internal Timer1 Start Enable\nThis bit enables Timer1 to start counting. Software can fill '0' to stop it and set '1' to reload and count.\nNote3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1 so don't.." "0: Stops counting,1: Starts counting"
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bitfld.long 0x4 5. "TMR0_SEN,Internal Timer0 Start Enable\nThis bit enables Timer0 to start counting. Software can fill '0' to stop it and set '1' to reload and count.\nNote3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't.." "0: Stops counting,1: Starts counting"
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bitfld.long 0x4 4. "WARST_EN,Warm Reset Sequence Generator Enable\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the SC_ISR[INIT_IS] will be set to.." "0: No effect,1: Warm reset sequence generator Enabled"
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bitfld.long 0x4 3. "ACT_EN,Activation Sequence Generator Enable\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to.." "0: No effect,1: Activation sequence generator Enabled"
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bitfld.long 0x4 2. "DACT_EN,Deactivation Sequence Generator Enable\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to.." "0: No effect,1: Deactivation sequence generator Enabled"
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bitfld.long 0x4 1. "RX_RST,Rx Software Reset\nWhen RX_RST is set all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles." "0: No effect,1: Reset the Rx internal state machine and pointers"
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bitfld.long 0x4 0. "TX_RST,TX Software Reset\nWhen TX_RST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers"
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line.long 0x8 "SC_EGTR,SC Extend Guard Time Register"
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hexmask.long.byte 0x8 0.--7. 1. "EGT,Extended Guard Time\nThis field indicates the extended guard time value.\n\nNote: The counter is ETU based and the real extended guard time is EGT."
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line.long 0xC "SC_RFTMR,SC Receiver Buffer Time-out Register"
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hexmask.long.word 0xC 0.--8. 1. "RFTM,SC Receiver Buffer Time-out Register (ETU Based)\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5\nNote2: Filling all '0' to this field indicates to disable this function."
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line.long 0x10 "SC_ETUCR,SC ETU Control Register"
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bitfld.long 0x10 15. "COMPEN_EN,Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled hardware will alternate between n-1 clock cycles and n clock cycles where n is the value to be written into the ETU_RDIV register.\n" "0: Compensation function Disabled,1: Compensation function Enabled"
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hexmask.long.word 0x10 0.--11. 1. "ETU_RDIV,ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote1: Software can configure this field but this field must be greater than 0x04.\nNote2: Software can configure this field but if the error rate is.."
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line.long 0x14 "SC_IER,SC Interrupt Enable Register"
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bitfld.long 0x14 10. "ACON_ERR_IE,Auto Convention Error Interrupt Enable \nThis field is used for auto-convention error interrupt enable.\n" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x14 9. "RTMR_IE,Receiver Buffer Time-out Interrupt Enable \nThis field is used for receiver buffer time-out interrupt enable.\n" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x14 8. "INIT_IE,Initial End Interrupt Enable\nThis field is used for activation (SC_ALTCTL [ACT_EN]) deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable.\n" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x14 7. "CD_IE,Card Detect Interrupt Enable\nThis field is used for card detect interrupt enable. The card detect status register is SC_PINCSR[CD_INS_F] and SC_PINCSR[CD_REM_F].\n" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x14 6. "BGT_IE,Block Guard Time Interrupt Enable\nThis field is used for block guard time interrupt enable.\n" "0: Block guard time Disabled,1: Block guard time Enabled"
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bitfld.long 0x14 5. "TMR2_IE,Timer2 Interrupt Enable\nThis field is used for TMR2 interrupt enable.\n" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x14 4. "TMR1_IE,Timer1 Interrupt Enable\nThis field is used for TMR1 interrupt enable.\n" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x14 3. "TMR0_IE,Timer0 Interrupt Enable\nThis field is used for TMR0 interrupt enable.\n" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x14 2. "TERR_IE,Transfer Error Interrupt Enable\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F) frame error (RX_EFR_F) parity error (RX_EPA_F) receiver.." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x14 1. "TBE_IE,Transmit Buffer Empty Interrupt Enable\nThis field is used for transmit buffer empty interrupt enable.\n" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x14 0. "RDA_IE,Receive Data Reach Interrupt Enable\nThis field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable.\n" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt Enabled"
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rgroup.long 0x1C++0x7
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line.long 0x0 "SC_ISR,SC Interrupt Status Register"
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bitfld.long 0x0 10. "ACON_ERR_IS,Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is not 0x3B or 0x3F this bit will be set.\nNote: This bit is read only but can be cleared by.." "0,1"
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bitfld.long 0x0 9. "RTMR_IS,Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit .." "0,1"
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bitfld.long 0x0 8. "INIT_IS,Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (SC_ALTCTL [ACT_EN]) deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag.\nNote: This bit is read only but it.." "0,1"
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bitfld.long 0x0 7. "CD_IS,Card Detect Interrupt Status Flag (Read Only)\nNote: If software wants to clear this field software must clear SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F]." "0,1"
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bitfld.long 0x0 6. "BGT_IS,Block Guard Time Interrupt Status Flag (Read Only)\nThis field is used for block guard time interrupt status flag.\nNote1: This bit is valid when SC_ALTCTL[RX_BGT_EN] is enabled.\nNote2: This bit is read only but it can be cleared by writing '1'.." "0,1"
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bitfld.long 0x0 5. "TMR2_IS,Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 4. "TMR1_IS,Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 3. "TMR0_IS,Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 2. "TERR_IS,Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error status is at the SC_TRSR register which includes receiver break error (RX_EBR_F) frame error (RX_EFR_F) parity.." "0,1"
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bitfld.long 0x0 1. "TBE_IS,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit software must.." "0,1"
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bitfld.long 0x0 0. "RDA_IS,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level (SC_CTL[RX_FTRI_LEV]) interrupt status flag.\nNote: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV]. If.." "0,1"
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line.long 0x4 "SC_TRSR,SC Transfer Status Register"
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bitfld.long 0x4 31. "TX_ATV,Transmit In Active Status Flag (Read Only)\nThis bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has not been transmitted.\nThis bit is cleared automatically when TX transfer is finished or the last byte.." "0,1"
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bitfld.long 0x4 30. "TX_OVER_REERR,Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x4 29. "TX_REERR,Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU." "0,1"
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bitfld.long 0x4 24.--25. "TX_POINT_F,Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register .." "0,1,2,3"
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bitfld.long 0x4 23. "RX_ATV,Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished." "0,1"
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bitfld.long 0x4 22. "RX_OVER_REERR,Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: If CPU enables receiver retries.." "0,1"
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bitfld.long 0x4 21. "RX_REERR,Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2 This bit is a flag and cannot generate any interrupt to.." "0,1"
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bitfld.long 0x4 16.--17. "RX_POINT_F,Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device RX_POINT_F increases one. When one byte of RX buffer is read by CPU RX_POINT_F decreases.." "0,1,2,3"
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bitfld.long 0x4 10. "TX_FULL_F,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.\nThis bit is set when TX pointer is equal to 4 otherwise is cleared by hardware." "0,1"
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bitfld.long 0x4 9. "TX_EMPTY_F,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data.." "0,1"
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bitfld.long 0x4 8. "TX_OVER_F,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full an additional write to SC_THR will cause this bit be set to '1' by hardware. \nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x4 6. "RX_EBR_F,Receiver Break Error Status Flag (Read Only)\nThis bit is set to '1' whenever the received data input (RX) held in the 'spacing state' (logic '0') is longer than a full word transmission time (that is the total time of 'start bit' + data bits +.." "0,1"
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bitfld.long 0x4 5. "RX_EFR_F,Receiver Frame Error Status Flag (Read Only)\nThis bit is set to '1' whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit is.." "0,1"
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bitfld.long 0x4 4. "RX_EPA_F,Receiver Parity Error Status Flag (Read Only)\nThis bit is set to '1' whenever the received character does not have a valid 'parity bit'.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: If CPU sets receiver.." "0,1"
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bitfld.long 0x4 2. "RX_FULL_F,Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4 otherwise it is cleared by hardware." "0,1"
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bitfld.long 0x4 1. "RX_EMPTY_F,Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of RX buffer has been read by CPU hardware set this bit to '1'. It will be cleared by hardware when SC receives any new data." "0,1"
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bitfld.long 0x4 0. "RX_OVER_F,RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes) this bit will be set.\nNote: This bit is read only but it can be cleared by writing.." "0,1"
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group.long 0x24++0xF
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line.long 0x0 "SC_PINCSR,SC Pin Control State Register"
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rbitfld.long 0x0 16. "SC_DATA_I_ST,SC Data Pin Status (Read Only)\nThis bit is the pin status of SC_DAT\n" "0: The SC_DAT pin is low,1: The SC_DAT pin is high"
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bitfld.long 0x0 11. "POW_INV,SC_PWR Pin Inverse\n" "0,1"
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bitfld.long 0x0 10. "CD_LEV,Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine is enabled." "0: When hardware detects the card detect pin from..,1: When hardware detects the card detect pin from.."
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bitfld.long 0x0 9. "SC_DATA_O,SC Data Output Pin \nThis bit is the pin status of SC_DAT but user can drive SC_DAT pin to high or low by setting this bit.\nWrite this field to drive SC_DAT pin.\nNote: When SC is at activation warm reset or deactivation mode this bit will.." "0: Drive SC_DAT pin to low.\nSC_DAT pin status is low,1: Drive SC_DAT pin to high.\nSC_DAT pin status is.."
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rbitfld.long 0x0 8. "SC_OEN_ST,SC Data Output Enable Pin Status (Read Only)\nThis bit is the output enable status of the SC_DAT pin.\n" "0: The SC_DAT pin state is output,1: The SC_DAT pin state is not output"
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bitfld.long 0x0 7. "ADAC_CD_EN,Auto Deactivation When Card Removal\nNote: When the card is removed hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an initial end interrupt to CPU." "0: Auto deactivation Disabled when hardware..,1: Auto deactivation Enabled when hardware detected.."
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bitfld.long 0x0 6. "CLK_KEEP,SC Clock Enable\nNote: When operating at activation warm reset or deactivation mode this bit will be changed automatically. So don't fill this field when operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running"
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rbitfld.long 0x0 4. "CD_PIN_ST,Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n" "0: The SC_CD pin state at low,1: The SC_CD pin state at high"
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rbitfld.long 0x0 3. "CD_INS_F,Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: The card detect engine will start after SC_CTL[SC_CEN] set." "0: No effect,1: Card insert"
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rbitfld.long 0x0 2. "CD_REM_F,Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever a card has been removed.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SC_CTL[SC_CEN] set." "0: No effect,1: Card removed"
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bitfld.long 0x0 1. "SC_RST,SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be.." "0: Drive SC_RST pin to low.\nSC_RST pin status is low,1: Drive SC_RST pin to high.\nSC_RST pin status is.."
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bitfld.long 0x0 0. "POW_EN,SC_POW_EN Pin Signal\n" "0: SC_PWR pin status is low,1: SC_PWR pin status is high"
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line.long 0x4 "SC_TMR0,SC Internal Timer Control Register 0"
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hexmask.long.byte 0x4 24.--27. 1. "MODE,Timer 0 Operation Mode Selection\n"
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hexmask.long.tbyte 0x4 0.--23. 1. "CNT,Timer 0 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values."
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line.long 0x8 "SC_TMR1,SC Internal Timer Control Register 1"
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hexmask.long.byte 0x8 24.--27. 1. "MODE,Timer 1 Operation Mode Selection\n"
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hexmask.long.byte 0x8 0.--7. 1. "CNT,Timer 1 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values."
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line.long 0xC "SC_TMR2,SC Internal Timer Control Register 2"
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hexmask.long.byte 0xC 24.--27. 1. "MODE,Timer 2 Operation Mode Selection\n"
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hexmask.long.byte 0xC 0.--7. 1. "CNT,Timer 2 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values."
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rgroup.long 0x38++0x7
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line.long 0x0 "SC_TDRA,SC Timer Current Data Register A"
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hexmask.long.tbyte 0x0 0.--23. 1. "TDR0,Timer0 Current Data Register (Read Only)\nThis field indicates the current count values of timer0."
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line.long 0x4 "SC_TDRB,SC Timer Current Data Register B"
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hexmask.long.byte 0x4 8.--15. 1. "TDR2,Timer2 Current Data Register (Read Only)\nThis field indicates the current count values of timer2."
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hexmask.long.byte 0x4 0.--7. 1. "TDR1,Timer1 Current Data Register (Read Only)\nThis field indicates the current count values of timer1."
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tree.end
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tree "SC2"
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base ad:0x40198000
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rgroup.long 0x0++0x3
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line.long 0x0 "SC_RBR,SC Receiving Buffer Register."
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hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register\nBy reading this register the SC will return an 8-bit received data."
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wgroup.long 0x0++0x3
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line.long 0x0 "SC_THR,SC Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the SC will send out an 8-bit data.\nNote: If SC_CTL[SC_CEN] not enabled this register cannot be programmed."
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group.long 0x4++0x17
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line.long 0x0 "SC_CTL,SC Control Register"
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bitfld.long 0x0 24.--25. "CD_DEB_SEL,Card Detect De-bounce Select Register\n" "0,1,2,3"
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bitfld.long 0x0 23. "TX_ERETRY_EN,TX Error Retry Enable Register\nThis bit enables transmitter retry function when parity error has occurred.\nNote: Software must fill TX_ERETRY value before enabling this bit." "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x0 20.--22. "TX_ERETRY,TX Error Retry Count Register\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1 8 is the maximum retry number.\nNote2: This field.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 19. "RX_ERETRY_EN,RX Error Retry Enable Register\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill RX_ERETRY value before enabling this bit." "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x0 16.--18. "RX_ERETRY,RX Error Retry Count Register\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred.\nNote1: The real maximum retry number is RX_ERETRY + 1 so 8 is the maximum retry number.\nNote2: This.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 15. "SLEN,Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2." "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
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bitfld.long 0x0 13.--14. "TMR_SEL,Timer Selection \n" "0,1,2,3"
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hexmask.long.byte 0x0 8.--12. 1. "BGT,Block Guard Time (BGT)\nIn TX mode hardware will auto hold off first character until BGT has elapsed regardless of the TX data.\n\nIn RX mode software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing. If the incoming.."
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bitfld.long 0x0 6.--7. "RX_FTRI_LEV,Rx Buffer Trigger Level \n" "0,1,2,3"
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bitfld.long 0x0 4.--5. "CON_SEL,Convention Selection\nNote: If AUTO_CON_EN enabled this fields must be ignored." "0: Direct convention,1: Reserved,?,?"
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bitfld.long 0x0 3. "AUTO_CON_EN,Auto Convention Enable\n" "0: Auto-convention Disabled,1: Auto-convention Enabled"
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bitfld.long 0x0 2. "DIS_TX,TX Transition Disable\n" "0: Transceiver Enabled,1: Transceiver Disabled"
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bitfld.long 0x0 1. "DIS_RX,RX Transition Disable\nNote: If AUTO_CON_EN enabled this fields must be ignored." "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x0 0. "SC_CEN,SC Engine Enable\nSetting this bit to '1' will enable SC operation. If this bit is cleared SC will force all transition to IDLE state." "0,1"
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line.long 0x4 "SC_ALTCTL,SC Alternate Control State Register"
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rbitfld.long 0x4 15. "TMR2_ATV,Internal Timer2 Active State (Read Only)\nThis bit indicates the Timer2 counter status.\n" "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x4 14. "TMR1_ATV,Internal Timer1 Active State (Read Only)\nThis bit indicates the Timer1 counter status.\n" "0: Timer1 is not active,1: Timer1 is active"
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rbitfld.long 0x4 13. "TMR0_ATV,Internal Timer0 Active State (Read Only)\nThis bit indicates the Timer0 counter status.\n" "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x4 12. "RX_BGT_EN,Check Receiver Block Guard Time Function Enable\n" "0: Check receiver block guard time function Disabled,1: Check receiver block guard time function Enabled"
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bitfld.long 0x4 8.--9. "INIT_SEL,Initial Timing Selection\n" "0,1,2,3"
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bitfld.long 0x4 7. "TMR2_SEN,Internal Timer2 Start Enable\nThis bit enables Timer2 to start counting. Software can fill '0' to stop it and set '1' to reload and count.\nNote3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL [RX_RST] to 1. So.." "0: Stops counting,1: Starts counting"
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bitfld.long 0x4 6. "TMR1_SEN,Internal Timer1 Start Enable\nThis bit enables Timer1 to start counting. Software can fill '0' to stop it and set '1' to reload and count.\nNote3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1 so don't.." "0: Stops counting,1: Starts counting"
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bitfld.long 0x4 5. "TMR0_SEN,Internal Timer0 Start Enable\nThis bit enables Timer0 to start counting. Software can fill '0' to stop it and set '1' to reload and count.\nNote3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't.." "0: Stops counting,1: Starts counting"
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bitfld.long 0x4 4. "WARST_EN,Warm Reset Sequence Generator Enable\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the SC_ISR[INIT_IS] will be set to.." "0: No effect,1: Warm reset sequence generator Enabled"
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bitfld.long 0x4 3. "ACT_EN,Activation Sequence Generator Enable\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to.." "0: No effect,1: Activation sequence generator Enabled"
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bitfld.long 0x4 2. "DACT_EN,Deactivation Sequence Generator Enable\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to.." "0: No effect,1: Deactivation sequence generator Enabled"
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bitfld.long 0x4 1. "RX_RST,Rx Software Reset\nWhen RX_RST is set all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles." "0: No effect,1: Reset the Rx internal state machine and pointers"
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bitfld.long 0x4 0. "TX_RST,TX Software Reset\nWhen TX_RST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers"
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line.long 0x8 "SC_EGTR,SC Extend Guard Time Register"
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hexmask.long.byte 0x8 0.--7. 1. "EGT,Extended Guard Time\nThis field indicates the extended guard time value.\n\nNote: The counter is ETU based and the real extended guard time is EGT."
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line.long 0xC "SC_RFTMR,SC Receiver Buffer Time-out Register"
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hexmask.long.word 0xC 0.--8. 1. "RFTM,SC Receiver Buffer Time-out Register (ETU Based)\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5\nNote2: Filling all '0' to this field indicates to disable this function."
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line.long 0x10 "SC_ETUCR,SC ETU Control Register"
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bitfld.long 0x10 15. "COMPEN_EN,Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled hardware will alternate between n-1 clock cycles and n clock cycles where n is the value to be written into the ETU_RDIV register.\n" "0: Compensation function Disabled,1: Compensation function Enabled"
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hexmask.long.word 0x10 0.--11. 1. "ETU_RDIV,ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote1: Software can configure this field but this field must be greater than 0x04.\nNote2: Software can configure this field but if the error rate is.."
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line.long 0x14 "SC_IER,SC Interrupt Enable Register"
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bitfld.long 0x14 10. "ACON_ERR_IE,Auto Convention Error Interrupt Enable \nThis field is used for auto-convention error interrupt enable.\n" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x14 9. "RTMR_IE,Receiver Buffer Time-out Interrupt Enable \nThis field is used for receiver buffer time-out interrupt enable.\n" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x14 8. "INIT_IE,Initial End Interrupt Enable\nThis field is used for activation (SC_ALTCTL [ACT_EN]) deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable.\n" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x14 7. "CD_IE,Card Detect Interrupt Enable\nThis field is used for card detect interrupt enable. The card detect status register is SC_PINCSR[CD_INS_F] and SC_PINCSR[CD_REM_F].\n" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x14 6. "BGT_IE,Block Guard Time Interrupt Enable\nThis field is used for block guard time interrupt enable.\n" "0: Block guard time Disabled,1: Block guard time Enabled"
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bitfld.long 0x14 5. "TMR2_IE,Timer2 Interrupt Enable\nThis field is used for TMR2 interrupt enable.\n" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x14 4. "TMR1_IE,Timer1 Interrupt Enable\nThis field is used for TMR1 interrupt enable.\n" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x14 3. "TMR0_IE,Timer0 Interrupt Enable\nThis field is used for TMR0 interrupt enable.\n" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x14 2. "TERR_IE,Transfer Error Interrupt Enable\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F) frame error (RX_EFR_F) parity error (RX_EPA_F) receiver.." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x14 1. "TBE_IE,Transmit Buffer Empty Interrupt Enable\nThis field is used for transmit buffer empty interrupt enable.\n" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x14 0. "RDA_IE,Receive Data Reach Interrupt Enable\nThis field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable.\n" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt Enabled"
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rgroup.long 0x1C++0x7
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line.long 0x0 "SC_ISR,SC Interrupt Status Register"
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bitfld.long 0x0 10. "ACON_ERR_IS,Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is not 0x3B or 0x3F this bit will be set.\nNote: This bit is read only but can be cleared by.." "0,1"
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bitfld.long 0x0 9. "RTMR_IS,Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit .." "0,1"
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bitfld.long 0x0 8. "INIT_IS,Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (SC_ALTCTL [ACT_EN]) deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag.\nNote: This bit is read only but it.." "0,1"
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bitfld.long 0x0 7. "CD_IS,Card Detect Interrupt Status Flag (Read Only)\nNote: If software wants to clear this field software must clear SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F]." "0,1"
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bitfld.long 0x0 6. "BGT_IS,Block Guard Time Interrupt Status Flag (Read Only)\nThis field is used for block guard time interrupt status flag.\nNote1: This bit is valid when SC_ALTCTL[RX_BGT_EN] is enabled.\nNote2: This bit is read only but it can be cleared by writing '1'.." "0,1"
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bitfld.long 0x0 5. "TMR2_IS,Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 4. "TMR1_IS,Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 3. "TMR0_IS,Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 2. "TERR_IS,Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error status is at the SC_TRSR register which includes receiver break error (RX_EBR_F) frame error (RX_EFR_F) parity.." "0,1"
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bitfld.long 0x0 1. "TBE_IS,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit software must.." "0,1"
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bitfld.long 0x0 0. "RDA_IS,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level (SC_CTL[RX_FTRI_LEV]) interrupt status flag.\nNote: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV]. If.." "0,1"
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line.long 0x4 "SC_TRSR,SC Transfer Status Register"
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bitfld.long 0x4 31. "TX_ATV,Transmit In Active Status Flag (Read Only)\nThis bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has not been transmitted.\nThis bit is cleared automatically when TX transfer is finished or the last byte.." "0,1"
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bitfld.long 0x4 30. "TX_OVER_REERR,Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x4 29. "TX_REERR,Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU." "0,1"
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bitfld.long 0x4 24.--25. "TX_POINT_F,Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register .." "0,1,2,3"
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bitfld.long 0x4 23. "RX_ATV,Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished." "0,1"
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bitfld.long 0x4 22. "RX_OVER_REERR,Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: If CPU enables receiver retries.." "0,1"
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bitfld.long 0x4 21. "RX_REERR,Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2 This bit is a flag and cannot generate any interrupt to.." "0,1"
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bitfld.long 0x4 16.--17. "RX_POINT_F,Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device RX_POINT_F increases one. When one byte of RX buffer is read by CPU RX_POINT_F decreases.." "0,1,2,3"
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bitfld.long 0x4 10. "TX_FULL_F,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.\nThis bit is set when TX pointer is equal to 4 otherwise is cleared by hardware." "0,1"
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bitfld.long 0x4 9. "TX_EMPTY_F,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data.." "0,1"
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bitfld.long 0x4 8. "TX_OVER_F,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full an additional write to SC_THR will cause this bit be set to '1' by hardware. \nNote: This bit is read only but it can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x4 6. "RX_EBR_F,Receiver Break Error Status Flag (Read Only)\nThis bit is set to '1' whenever the received data input (RX) held in the 'spacing state' (logic '0') is longer than a full word transmission time (that is the total time of 'start bit' + data bits +.." "0,1"
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bitfld.long 0x4 5. "RX_EFR_F,Receiver Frame Error Status Flag (Read Only)\nThis bit is set to '1' whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit is.." "0,1"
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bitfld.long 0x4 4. "RX_EPA_F,Receiver Parity Error Status Flag (Read Only)\nThis bit is set to '1' whenever the received character does not have a valid 'parity bit'.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: If CPU sets receiver.." "0,1"
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bitfld.long 0x4 2. "RX_FULL_F,Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4 otherwise it is cleared by hardware." "0,1"
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bitfld.long 0x4 1. "RX_EMPTY_F,Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of RX buffer has been read by CPU hardware set this bit to '1'. It will be cleared by hardware when SC receives any new data." "0,1"
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bitfld.long 0x4 0. "RX_OVER_F,RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes) this bit will be set.\nNote: This bit is read only but it can be cleared by writing.." "0,1"
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group.long 0x24++0xF
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line.long 0x0 "SC_PINCSR,SC Pin Control State Register"
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rbitfld.long 0x0 16. "SC_DATA_I_ST,SC Data Pin Status (Read Only)\nThis bit is the pin status of SC_DAT\n" "0: The SC_DAT pin is low,1: The SC_DAT pin is high"
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bitfld.long 0x0 11. "POW_INV,SC_PWR Pin Inverse\n" "0,1"
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bitfld.long 0x0 10. "CD_LEV,Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine is enabled." "0: When hardware detects the card detect pin from..,1: When hardware detects the card detect pin from.."
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bitfld.long 0x0 9. "SC_DATA_O,SC Data Output Pin \nThis bit is the pin status of SC_DAT but user can drive SC_DAT pin to high or low by setting this bit.\nWrite this field to drive SC_DAT pin.\nNote: When SC is at activation warm reset or deactivation mode this bit will.." "0: Drive SC_DAT pin to low.\nSC_DAT pin status is low,1: Drive SC_DAT pin to high.\nSC_DAT pin status is.."
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rbitfld.long 0x0 8. "SC_OEN_ST,SC Data Output Enable Pin Status (Read Only)\nThis bit is the output enable status of the SC_DAT pin.\n" "0: The SC_DAT pin state is output,1: The SC_DAT pin state is not output"
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bitfld.long 0x0 7. "ADAC_CD_EN,Auto Deactivation When Card Removal\nNote: When the card is removed hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an initial end interrupt to CPU." "0: Auto deactivation Disabled when hardware..,1: Auto deactivation Enabled when hardware detected.."
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bitfld.long 0x0 6. "CLK_KEEP,SC Clock Enable\nNote: When operating at activation warm reset or deactivation mode this bit will be changed automatically. So don't fill this field when operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running"
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rbitfld.long 0x0 4. "CD_PIN_ST,Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n" "0: The SC_CD pin state at low,1: The SC_CD pin state at high"
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rbitfld.long 0x0 3. "CD_INS_F,Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: The card detect engine will start after SC_CTL[SC_CEN] set." "0: No effect,1: Card insert"
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rbitfld.long 0x0 2. "CD_REM_F,Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever a card has been removed.\nNote1: This bit is read only but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SC_CTL[SC_CEN] set." "0: No effect,1: Card removed"
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bitfld.long 0x0 1. "SC_RST,SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be.." "0: Drive SC_RST pin to low.\nSC_RST pin status is low,1: Drive SC_RST pin to high.\nSC_RST pin status is.."
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bitfld.long 0x0 0. "POW_EN,SC_POW_EN Pin Signal\n" "0: SC_PWR pin status is low,1: SC_PWR pin status is high"
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line.long 0x4 "SC_TMR0,SC Internal Timer Control Register 0"
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hexmask.long.byte 0x4 24.--27. 1. "MODE,Timer 0 Operation Mode Selection\n"
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hexmask.long.tbyte 0x4 0.--23. 1. "CNT,Timer 0 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values."
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line.long 0x8 "SC_TMR1,SC Internal Timer Control Register 1"
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hexmask.long.byte 0x8 24.--27. 1. "MODE,Timer 1 Operation Mode Selection\n"
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hexmask.long.byte 0x8 0.--7. 1. "CNT,Timer 1 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values."
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line.long 0xC "SC_TMR2,SC Internal Timer Control Register 2"
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hexmask.long.byte 0xC 24.--27. 1. "MODE,Timer 2 Operation Mode Selection\n"
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hexmask.long.byte 0xC 0.--7. 1. "CNT,Timer 2 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values."
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rgroup.long 0x38++0x7
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line.long 0x0 "SC_TDRA,SC Timer Current Data Register A"
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hexmask.long.tbyte 0x0 0.--23. 1. "TDR0,Timer0 Current Data Register (Read Only)\nThis field indicates the current count values of timer0."
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line.long 0x4 "SC_TDRB,SC Timer Current Data Register B"
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hexmask.long.byte 0x4 8.--15. 1. "TDR2,Timer2 Current Data Register (Read Only)\nThis field indicates the current count values of timer2."
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hexmask.long.byte 0x4 0.--7. 1. "TDR1,Timer1 Current Data Register (Read Only)\nThis field indicates the current count values of timer1."
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tree.end
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tree.end
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tree "SCS (System Controller Space)"
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base ad:0xE000ED00
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rgroup.long 0xD00++0x3
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line.long 0x0 "CPUID,CPUID Register"
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hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER"
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hexmask.long.byte 0x0 16.--19. 1. "PART,Read as 0xC for ARMv6-M parts"
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hexmask.long.word 0x0 4.--15. 1. "PARTNO,Read as 0xC20."
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hexmask.long.byte 0x0 0.--3. 1. "REVISION,Read as 0x0"
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group.long 0xD04++0x3
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line.long 0x0 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x0 31. "NMIPENDSET,NMI Set-pending Bit\nWrite:\nBecause NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a.." "0: No effect.\nNMI exception not pending,1: Changes NMI exception state to pending.\nNMI.."
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bitfld.long 0x0 28. "PENDSVSET,PendSV Set-pending Bit\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending." "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
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bitfld.long 0x0 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite:\nThis is a write only bit. When you want to clear PENDSV bit you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time." "0: No effect,1: Removes the pending state from the PendSV.."
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bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite:\n" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
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bitfld.long 0x0 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite:\nThis is a write only bit. When you want to clear PENDST bit you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time." "0: No effect,1: Removes the pending state from the SysTick.."
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bitfld.long 0x0 23. "ISRPREEMPT,If Set a Pending Exception Will Be Serviced on Exit From the Debug Halt State\nThis bit is read only." "0,1"
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bitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults:\nThis bit is read only." "0: Interrupt not pending,1: Interrupt pending"
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hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Indicates the Exception Number of the Highest Priority Pending Enabled Exception:\n"
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hexmask.long.byte 0x0 0.--5. 1. "VECTACTIVE,Contains the Active Exception Number\n"
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group.long 0xD0C++0x7
|
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line.long 0x0 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x0 16.--31. 1. "VECTORKEY,When writing this register this field should be 0x05FA otherwise the write action will be unpredictable."
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bitfld.long 0x0 2. "SYSRESETREQ,Writing this Bit 1 Will Cause a Reset Signal to Be Asserted to the Chip to Indicate a Reset Is Requested\nThe bit is a write only bit and self-clears as part of the reset sequence." "0,1"
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bitfld.long 0x0 1. "VECTCLRACTIVE,Setting this Bit to 1 Will Clear All Active State Information for Fixed and Configurable Exceptions\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize.." "0,1"
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line.long 0x4 "SCR,System Control Register"
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bitfld.long 0x4 4. "SEVONPEND,Send Event on Pending Bit:\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE. If the processor is not waiting for an event the event is registered and affects the next WFE.\nThe processor also.." "0: Only enabled interrupts or events can wake-up..,1: Enabled events and all interrupts including.."
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bitfld.long 0x4 2. "SLEEPDEEP,Controls Whether the Processor Uses Sleep or Deep Sleep As Its Low Power Mode:\n" "0: Sleep,1: Deep sleep"
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bitfld.long 0x4 1. "SLEEPONEXIT,Indicates Sleep-on-exit When Returning From Handler Mode to Thread Mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application." "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR.."
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group.long 0xD1C++0x7
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line.long 0x0 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x0 30.--31. "PRI_11,Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x4 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x4 30.--31. "PRI_15,Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x4 22.--23. "PRI_14,Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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tree.end
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tree "SPI (Serial Peripheral Interface)"
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base ad:0x0
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tree "SPI0"
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base ad:0x40030000
|
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group.long 0x0++0xB
|
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line.long 0x0 "SPI_CNTRL,Control and Status Register"
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rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n" "0: Receive FIOF buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x0 23. "VARCLK_EN,Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1 the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)." "0: SPI clock output frequency is fixed and decided..,1: SPI clock output frequency is variable. The.."
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bitfld.long 0x0 22. "TWOB,2-bit Mode Enable\nNote: When 2-bit mode is enabled the serial transmitted 2-bit data are from SPI_TX1/0 and the received 2-bit data input are put in SPI_RX1/0." "0: 2-bit mode Disabled,1: 2-bit mode Enabled"
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bitfld.long 0x0 21. "FIFO,FIFO Mode Enable\nNote:\nBefore enabling FIFO mode the other related settings should be set in advance.\nIn Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer; the.." "0: FIFO mode Disabled,1: FIFO mode Enabled"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits.\nIn Slave mode with level-trigger configuration the slave select pin must be kept at active state during the byte.." "0: Byte reorder function Disabled,1: Byte reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Enable\n" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "IE,Unit Transfer Interrupt Enable\n" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 16. "IF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
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bitfld.long 0x0 11. "CLKP,Clock Polarity\n" "0: SPICLK is idle low,1: SPICLK is idle high"
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bitfld.long 0x0 10. "LSB,Send LSB First\n" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX0/1 register is sent.."
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hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n"
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bitfld.long 0x0 2. "TX_NEG,Transmit on Negative Edge\n" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RX_NEG,Receive on Negative Edge\n" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI is in.." "0: Data transfer stopped,1: In Master mode writing 1 to this bit to start.."
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line.long 0x4 "SPI_DIVIDER,Clock Divider Register"
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hexmask.long.byte 0x4 16.--23. 1. "DIVIDER2,Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit.."
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock fspi_eclk and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of.."
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line.long 0x8 "SPI_SSR,Slave Select Register"
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bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Accomplish Flag\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software the.." "0: Transferred bit length of one transaction does..,1: Transferred bit length meets the specified.."
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bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable (Slave Only)\n" "0: Slave select signal is edge-trigger. This is the..,1: Slave select signal is level-trigger. The SS_LVL.."
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)\n" "0: If this bit is cleared slave select signals will..,1: If this bit is set SPI_SS0/1 signals will be.."
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bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS0/1).\n" "0: The slave select signal SPI_SS0/1 is active on..,1: The slave select signal SPI_SS0/1 is active on.."
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bitfld.long 0x8 0.--1. "SSR,Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set writing 0 to any.." "0,1,2,3"
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rgroup.long 0x10++0x7
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line.long 0x0 "SPI_RX0,Data Receive Register 0"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.."
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line.long 0x4 "SPI_RX1,Data Receive Register 1"
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hexmask.long 0x4 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.."
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wgroup.long 0x20++0x7
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line.long 0x0 "SPI_TX0,Data Transmit Register 0"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example if TX_BIT_LEN is set to.."
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line.long 0x4 "SPI_TX1,Data Transmit Register 1"
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hexmask.long 0x4 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example if TX_BIT_LEN is set to.."
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group.long 0x34++0x13
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line.long 0x0 "SPI_VARCLK,Variable Clock Pattern Register"
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hexmask.long 0x0 0.--31. 1. "VARCLK,Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled this setting is unmeaning. Refer to the 'Variable Clock Function' paragraph for more detail description."
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line.long 0x4 "SPI_DMA,SPI DMA Control Register"
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bitfld.long 0x4 2. "PDMA_RST,PDMA Reset\n" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x4 1. "RX_DMA_GO,Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware.." "0,1"
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bitfld.long 0x4 0. "TX_DMA_GO,Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit.." "0,1"
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line.long 0x8 "SPI_CNTRL2,Control and Status Register 2"
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bitfld.long 0x8 31. "BCn,SPI Peripheral clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details." "0: Backward compatible clock configuration,1: Clock configuration is not backward compatible"
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bitfld.long 0x8 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n" "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
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bitfld.long 0x8 13. "DUAL_IO_EN,Dual I/O Mode Enable\n" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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bitfld.long 0x8 12. "DUAL_IO_DIR,Dual I/O Mode Direction Control\n" "0: Dual Input mode,1: Dual Output mode"
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bitfld.long 0x8 11. "SLV_START_INTSTS,Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n" "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode."
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bitfld.long 0x8 10. "SSTA_INTEN,Slave 3-wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start the user can.." "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled. It will be.."
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bitfld.long 0x8 9. "SLV_ABORT,Slave 3-wire Mode Abort Control\nIn normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock.." "0,1"
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bitfld.long 0x8 8. "NOSLVSEL,Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK SPI_MISO and SPI_MOSI.\nNote: In Slave 3-wire mode the SS_LTRIG SPI_SSR[4] will be.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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line.long 0xC "SPI_FIFO_CTL,SPI FIFO Control Register"
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bitfld.long 0xC 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 24.--26. "RX_THRESHOLD,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable \n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled"
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bitfld.long 0xC 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable\n" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0xC 3. "TX_INTEN,Transmit Threshold Interrupt Enable\n" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled"
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bitfld.long 0xC 2. "RX_INTEN,Receive Threshold Interrupt Enable\n" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled"
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bitfld.long 0xC 1. "TX_CLR,Clear Transmit FIFO Buffer\n" "0: No effect,1: Clear transmit FIFO buffer. The TX_FULL flag.."
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bitfld.long 0xC 0. "RX_CLR,Clear Receive FIFO Buffer\n" "0: No effect,1: Clear receive FIFO buffer. The RX_FULL flag will.."
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line.long 0x10 "SPI_STATUS,SPI Status Register"
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hexmask.long.byte 0x10 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
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rbitfld.long 0x10 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x10 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x10 25. "RX_FULL,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25].\n" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x10 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x10 20. "TIMEOUT,Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x10 16. "IF,SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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hexmask.long.byte 0x10 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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bitfld.long 0x10 11. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n" "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode."
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rbitfld.long 0x10 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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bitfld.long 0x10 2. "RX_OVERRUN,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself." "0,1"
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rbitfld.long 0x10 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.."
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tree.end
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tree "SPI1"
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base ad:0x40034000
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group.long 0x0++0xB
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line.long 0x0 "SPI_CNTRL,Control and Status Register"
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rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n" "0: Receive FIOF buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x0 23. "VARCLK_EN,Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1 the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)." "0: SPI clock output frequency is fixed and decided..,1: SPI clock output frequency is variable. The.."
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bitfld.long 0x0 22. "TWOB,2-bit Mode Enable\nNote: When 2-bit mode is enabled the serial transmitted 2-bit data are from SPI_TX1/0 and the received 2-bit data input are put in SPI_RX1/0." "0: 2-bit mode Disabled,1: 2-bit mode Enabled"
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bitfld.long 0x0 21. "FIFO,FIFO Mode Enable\nNote:\nBefore enabling FIFO mode the other related settings should be set in advance.\nIn Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer; the.." "0: FIFO mode Disabled,1: FIFO mode Enabled"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits.\nIn Slave mode with level-trigger configuration the slave select pin must be kept at active state during the byte.." "0: Byte reorder function Disabled,1: Byte reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Enable\n" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "IE,Unit Transfer Interrupt Enable\n" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 16. "IF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
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bitfld.long 0x0 11. "CLKP,Clock Polarity\n" "0: SPICLK is idle low,1: SPICLK is idle high"
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bitfld.long 0x0 10. "LSB,Send LSB First\n" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX0/1 register is sent.."
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hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n"
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bitfld.long 0x0 2. "TX_NEG,Transmit on Negative Edge\n" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RX_NEG,Receive on Negative Edge\n" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI is in.." "0: Data transfer stopped,1: In Master mode writing 1 to this bit to start.."
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line.long 0x4 "SPI_DIVIDER,Clock Divider Register"
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hexmask.long.byte 0x4 16.--23. 1. "DIVIDER2,Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit.."
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock fspi_eclk and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of.."
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line.long 0x8 "SPI_SSR,Slave Select Register"
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bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Accomplish Flag\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software the.." "0: Transferred bit length of one transaction does..,1: Transferred bit length meets the specified.."
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bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable (Slave Only)\n" "0: Slave select signal is edge-trigger. This is the..,1: Slave select signal is level-trigger. The SS_LVL.."
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)\n" "0: If this bit is cleared slave select signals will..,1: If this bit is set SPI_SS0/1 signals will be.."
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bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS0/1).\n" "0: The slave select signal SPI_SS0/1 is active on..,1: The slave select signal SPI_SS0/1 is active on.."
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bitfld.long 0x8 0.--1. "SSR,Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set writing 0 to any.." "0,1,2,3"
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rgroup.long 0x10++0x7
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line.long 0x0 "SPI_RX0,Data Receive Register 0"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.."
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line.long 0x4 "SPI_RX1,Data Receive Register 1"
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hexmask.long 0x4 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.."
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wgroup.long 0x20++0x7
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line.long 0x0 "SPI_TX0,Data Transmit Register 0"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example if TX_BIT_LEN is set to.."
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line.long 0x4 "SPI_TX1,Data Transmit Register 1"
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hexmask.long 0x4 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example if TX_BIT_LEN is set to.."
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group.long 0x34++0x13
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line.long 0x0 "SPI_VARCLK,Variable Clock Pattern Register"
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hexmask.long 0x0 0.--31. 1. "VARCLK,Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled this setting is unmeaning. Refer to the 'Variable Clock Function' paragraph for more detail description."
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line.long 0x4 "SPI_DMA,SPI DMA Control Register"
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bitfld.long 0x4 2. "PDMA_RST,PDMA Reset\n" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x4 1. "RX_DMA_GO,Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware.." "0,1"
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bitfld.long 0x4 0. "TX_DMA_GO,Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit.." "0,1"
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line.long 0x8 "SPI_CNTRL2,Control and Status Register 2"
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bitfld.long 0x8 31. "BCn,SPI Peripheral clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details." "0: Backward compatible clock configuration,1: Clock configuration is not backward compatible"
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bitfld.long 0x8 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n" "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
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bitfld.long 0x8 13. "DUAL_IO_EN,Dual I/O Mode Enable\n" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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bitfld.long 0x8 12. "DUAL_IO_DIR,Dual I/O Mode Direction Control\n" "0: Dual Input mode,1: Dual Output mode"
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bitfld.long 0x8 11. "SLV_START_INTSTS,Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n" "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode."
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bitfld.long 0x8 10. "SSTA_INTEN,Slave 3-wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start the user can.." "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled. It will be.."
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bitfld.long 0x8 9. "SLV_ABORT,Slave 3-wire Mode Abort Control\nIn normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock.." "0,1"
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bitfld.long 0x8 8. "NOSLVSEL,Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK SPI_MISO and SPI_MOSI.\nNote: In Slave 3-wire mode the SS_LTRIG SPI_SSR[4] will be.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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line.long 0xC "SPI_FIFO_CTL,SPI FIFO Control Register"
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bitfld.long 0xC 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 24.--26. "RX_THRESHOLD,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable \n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled"
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bitfld.long 0xC 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable\n" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0xC 3. "TX_INTEN,Transmit Threshold Interrupt Enable\n" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled"
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bitfld.long 0xC 2. "RX_INTEN,Receive Threshold Interrupt Enable\n" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled"
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bitfld.long 0xC 1. "TX_CLR,Clear Transmit FIFO Buffer\n" "0: No effect,1: Clear transmit FIFO buffer. The TX_FULL flag.."
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bitfld.long 0xC 0. "RX_CLR,Clear Receive FIFO Buffer\n" "0: No effect,1: Clear receive FIFO buffer. The RX_FULL flag will.."
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line.long 0x10 "SPI_STATUS,SPI Status Register"
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hexmask.long.byte 0x10 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
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rbitfld.long 0x10 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x10 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x10 25. "RX_FULL,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25].\n" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x10 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x10 20. "TIMEOUT,Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x10 16. "IF,SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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hexmask.long.byte 0x10 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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bitfld.long 0x10 11. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n" "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode."
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rbitfld.long 0x10 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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bitfld.long 0x10 2. "RX_OVERRUN,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself." "0,1"
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rbitfld.long 0x10 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.."
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tree.end
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tree "SPI2"
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base ad:0x40130000
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group.long 0x0++0xB
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line.long 0x0 "SPI_CNTRL,Control and Status Register"
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rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n" "0: Receive FIOF buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x0 23. "VARCLK_EN,Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1 the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)." "0: SPI clock output frequency is fixed and decided..,1: SPI clock output frequency is variable. The.."
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bitfld.long 0x0 22. "TWOB,2-bit Mode Enable\nNote: When 2-bit mode is enabled the serial transmitted 2-bit data are from SPI_TX1/0 and the received 2-bit data input are put in SPI_RX1/0." "0: 2-bit mode Disabled,1: 2-bit mode Enabled"
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bitfld.long 0x0 21. "FIFO,FIFO Mode Enable\nNote:\nBefore enabling FIFO mode the other related settings should be set in advance.\nIn Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer; the.." "0: FIFO mode Disabled,1: FIFO mode Enabled"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits.\nIn Slave mode with level-trigger configuration the slave select pin must be kept at active state during the byte.." "0: Byte reorder function Disabled,1: Byte reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Enable\n" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "IE,Unit Transfer Interrupt Enable\n" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 16. "IF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
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bitfld.long 0x0 11. "CLKP,Clock Polarity\n" "0: SPICLK is idle low,1: SPICLK is idle high"
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bitfld.long 0x0 10. "LSB,Send LSB First\n" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX0/1 register is sent.."
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hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n"
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bitfld.long 0x0 2. "TX_NEG,Transmit on Negative Edge\n" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RX_NEG,Receive on Negative Edge\n" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI is in.." "0: Data transfer stopped,1: In Master mode writing 1 to this bit to start.."
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line.long 0x4 "SPI_DIVIDER,Clock Divider Register"
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hexmask.long.byte 0x4 16.--23. 1. "DIVIDER2,Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit.."
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock fspi_eclk and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of.."
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line.long 0x8 "SPI_SSR,Slave Select Register"
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bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Accomplish Flag\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software the.." "0: Transferred bit length of one transaction does..,1: Transferred bit length meets the specified.."
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bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable (Slave Only)\n" "0: Slave select signal is edge-trigger. This is the..,1: Slave select signal is level-trigger. The SS_LVL.."
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)\n" "0: If this bit is cleared slave select signals will..,1: If this bit is set SPI_SS0/1 signals will be.."
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bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS0/1).\n" "0: The slave select signal SPI_SS0/1 is active on..,1: The slave select signal SPI_SS0/1 is active on.."
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bitfld.long 0x8 0.--1. "SSR,Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set writing 0 to any.." "0,1,2,3"
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rgroup.long 0x10++0x7
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line.long 0x0 "SPI_RX0,Data Receive Register 0"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.."
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line.long 0x4 "SPI_RX1,Data Receive Register 1"
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hexmask.long 0x4 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.."
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wgroup.long 0x20++0x7
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line.long 0x0 "SPI_TX0,Data Transmit Register 0"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example if TX_BIT_LEN is set to.."
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line.long 0x4 "SPI_TX1,Data Transmit Register 1"
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hexmask.long 0x4 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example if TX_BIT_LEN is set to.."
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group.long 0x34++0x13
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line.long 0x0 "SPI_VARCLK,Variable Clock Pattern Register"
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hexmask.long 0x0 0.--31. 1. "VARCLK,Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled this setting is unmeaning. Refer to the 'Variable Clock Function' paragraph for more detail description."
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line.long 0x4 "SPI_DMA,SPI DMA Control Register"
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bitfld.long 0x4 2. "PDMA_RST,PDMA Reset\n" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x4 1. "RX_DMA_GO,Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware.." "0,1"
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bitfld.long 0x4 0. "TX_DMA_GO,Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit.." "0,1"
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line.long 0x8 "SPI_CNTRL2,Control and Status Register 2"
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bitfld.long 0x8 31. "BCn,SPI Peripheral clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details." "0: Backward compatible clock configuration,1: Clock configuration is not backward compatible"
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bitfld.long 0x8 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n" "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
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bitfld.long 0x8 13. "DUAL_IO_EN,Dual I/O Mode Enable\n" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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bitfld.long 0x8 12. "DUAL_IO_DIR,Dual I/O Mode Direction Control\n" "0: Dual Input mode,1: Dual Output mode"
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bitfld.long 0x8 11. "SLV_START_INTSTS,Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n" "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode."
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bitfld.long 0x8 10. "SSTA_INTEN,Slave 3-wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start the user can.." "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled. It will be.."
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bitfld.long 0x8 9. "SLV_ABORT,Slave 3-wire Mode Abort Control\nIn normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock.." "0,1"
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bitfld.long 0x8 8. "NOSLVSEL,Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK SPI_MISO and SPI_MOSI.\nNote: In Slave 3-wire mode the SS_LTRIG SPI_SSR[4] will be.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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line.long 0xC "SPI_FIFO_CTL,SPI FIFO Control Register"
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bitfld.long 0xC 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 24.--26. "RX_THRESHOLD,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable \n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled"
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bitfld.long 0xC 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable\n" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0xC 3. "TX_INTEN,Transmit Threshold Interrupt Enable\n" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled"
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bitfld.long 0xC 2. "RX_INTEN,Receive Threshold Interrupt Enable\n" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled"
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bitfld.long 0xC 1. "TX_CLR,Clear Transmit FIFO Buffer\n" "0: No effect,1: Clear transmit FIFO buffer. The TX_FULL flag.."
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bitfld.long 0xC 0. "RX_CLR,Clear Receive FIFO Buffer\n" "0: No effect,1: Clear receive FIFO buffer. The RX_FULL flag will.."
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line.long 0x10 "SPI_STATUS,SPI Status Register"
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hexmask.long.byte 0x10 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
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rbitfld.long 0x10 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x10 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x10 25. "RX_FULL,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25].\n" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x10 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x10 20. "TIMEOUT,Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x10 16. "IF,SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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hexmask.long.byte 0x10 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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bitfld.long 0x10 11. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n" "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode."
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rbitfld.long 0x10 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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bitfld.long 0x10 2. "RX_OVERRUN,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself." "0,1"
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rbitfld.long 0x10 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.."
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tree.end
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tree "SPI3"
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base ad:0x40134000
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group.long 0x0++0xB
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line.long 0x0 "SPI_CNTRL,Control and Status Register"
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rbitfld.long 0x0 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x0 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x0 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n" "0: Receive FIOF buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x0 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x0 23. "VARCLK_EN,Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1 the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)." "0: SPI clock output frequency is fixed and decided..,1: SPI clock output frequency is variable. The.."
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bitfld.long 0x0 22. "TWOB,2-bit Mode Enable\nNote: When 2-bit mode is enabled the serial transmitted 2-bit data are from SPI_TX1/0 and the received 2-bit data input are put in SPI_RX1/0." "0: 2-bit mode Disabled,1: 2-bit mode Enabled"
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bitfld.long 0x0 21. "FIFO,FIFO Mode Enable\nNote:\nBefore enabling FIFO mode the other related settings should be set in advance.\nIn Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer; the.." "0: FIFO mode Disabled,1: FIFO mode Enabled"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits.\nIn Slave mode with level-trigger configuration the slave select pin must be kept at active state during the byte.." "0: Byte reorder function Disabled,1: Byte reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Enable\n" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "IE,Unit Transfer Interrupt Enable\n" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 16. "IF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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hexmask.long.byte 0x0 12.--15. 1. "SP_CYCLE,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
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bitfld.long 0x0 11. "CLKP,Clock Polarity\n" "0: SPICLK is idle low,1: SPICLK is idle high"
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bitfld.long 0x0 10. "LSB,Send LSB First\n" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX0/1 register is sent.."
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hexmask.long.byte 0x0 3.--7. 1. "TX_BIT_LEN,Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n"
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bitfld.long 0x0 2. "TX_NEG,Transmit on Negative Edge\n" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RX_NEG,Receive on Negative Edge\n" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "GO_BUSY,SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit will be cleared automatically. Software can read this bit to check if the SPI is in.." "0: Data transfer stopped,1: In Master mode writing 1 to this bit to start.."
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line.long 0x4 "SPI_DIVIDER,Clock Divider Register"
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hexmask.long.byte 0x4 16.--23. 1. "DIVIDER2,Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit.."
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock fspi_eclk and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of.."
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line.long 0x8 "SPI_SSR,Slave Select Register"
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bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Accomplish Flag\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software the.." "0: Transferred bit length of one transaction does..,1: Transferred bit length meets the specified.."
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bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger Enable (Slave Only)\n" "0: Slave select signal is edge-trigger. This is the..,1: Slave select signal is level-trigger. The SS_LVL.."
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)\n" "0: If this bit is cleared slave select signals will..,1: If this bit is set SPI_SS0/1 signals will be.."
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bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS0/1).\n" "0: The slave select signal SPI_SS0/1 is active on..,1: The slave select signal SPI_SS0/1 is active on.."
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bitfld.long 0x8 0.--1. "SSR,Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set writing 0 to any.." "0,1,2,3"
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rgroup.long 0x10++0x7
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line.long 0x0 "SPI_RX0,Data Receive Register 0"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.."
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line.long 0x4 "SPI_RX1,Data Receive Register 1"
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hexmask.long 0x4 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY.."
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wgroup.long 0x20++0x7
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line.long 0x0 "SPI_TX0,Data Transmit Register 0"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example if TX_BIT_LEN is set to.."
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line.long 0x4 "SPI_TX1,Data Transmit Register 1"
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hexmask.long 0x4 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example if TX_BIT_LEN is set to.."
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group.long 0x34++0x13
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line.long 0x0 "SPI_VARCLK,Variable Clock Pattern Register"
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hexmask.long 0x0 0.--31. 1. "VARCLK,Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled this setting is unmeaning. Refer to the 'Variable Clock Function' paragraph for more detail description."
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line.long 0x4 "SPI_DMA,SPI DMA Control Register"
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bitfld.long 0x4 2. "PDMA_RST,PDMA Reset\n" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x4 1. "RX_DMA_GO,Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware.." "0,1"
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bitfld.long 0x4 0. "TX_DMA_GO,Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit.." "0,1"
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line.long 0x8 "SPI_CNTRL2,Control and Status Register 2"
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bitfld.long 0x8 31. "BCn,SPI Peripheral clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details." "0: Backward compatible clock configuration,1: Clock configuration is not backward compatible"
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bitfld.long 0x8 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n" "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
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bitfld.long 0x8 13. "DUAL_IO_EN,Dual I/O Mode Enable\n" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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bitfld.long 0x8 12. "DUAL_IO_DIR,Dual I/O Mode Direction Control\n" "0: Dual Input mode,1: Dual Output mode"
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bitfld.long 0x8 11. "SLV_START_INTSTS,Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n" "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode."
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bitfld.long 0x8 10. "SSTA_INTEN,Slave 3-wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start the user can.." "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled. It will be.."
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bitfld.long 0x8 9. "SLV_ABORT,Slave 3-wire Mode Abort Control\nIn normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock.." "0,1"
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bitfld.long 0x8 8. "NOSLVSEL,Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK SPI_MISO and SPI_MOSI.\nNote: In Slave 3-wire mode the SS_LTRIG SPI_SSR[4] will be.." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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line.long 0xC "SPI_FIFO_CTL,SPI FIFO Control Register"
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bitfld.long 0xC 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 24.--26. "RX_THRESHOLD,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable \n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled"
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bitfld.long 0xC 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable\n" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0xC 3. "TX_INTEN,Transmit Threshold Interrupt Enable\n" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled"
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bitfld.long 0xC 2. "RX_INTEN,Receive Threshold Interrupt Enable\n" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled"
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bitfld.long 0xC 1. "TX_CLR,Clear Transmit FIFO Buffer\n" "0: No effect,1: Clear transmit FIFO buffer. The TX_FULL flag.."
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bitfld.long 0xC 0. "RX_CLR,Clear Receive FIFO Buffer\n" "0: No effect,1: Clear receive FIFO buffer. The RX_FULL flag will.."
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line.long 0x10 "SPI_STATUS,SPI Status Register"
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hexmask.long.byte 0x10 28.--31. 1. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer."
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rbitfld.long 0x10 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x10 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x10 25. "RX_FULL,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25].\n" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x10 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x10 20. "TIMEOUT,Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x10 16. "IF,SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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hexmask.long.byte 0x10 12.--15. 1. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer."
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bitfld.long 0x10 11. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n" "0: Slave has not detected any SPI clock transition..,1: A transaction has started in Slave 3-wire mode."
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rbitfld.long 0x10 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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bitfld.long 0x10 2. "RX_OVERRUN,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself." "0,1"
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rbitfld.long 0x10 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.."
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tree.end
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tree.end
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tree "SYST (System Control Registers)"
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base ad:0xE000E010
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group.long 0x10++0xB
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line.long 0x0 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x0 16. "COUNTFLAG,Returns 1 If Timer Counted to 0 Since Last Time this Register Was Read\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register." "0,1"
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bitfld.long 0x0 2. "CLKSRC" "0: Clock source is (optional) external reference..,1: Core clock used for SysTick"
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bitfld.long 0x0 1. "TICKINT" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
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bitfld.long 0x0 0. "ENABLE" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
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line.long 0x4 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,Value to load into the Current Value register when the counter reaches 0."
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line.long 0x8 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,Current Counter Value This Is the Value of the Counter at the Time It Is Sampled The Counter Does Not Provide Read-modify-write Protection The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits.."
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tree.end
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tree "TIMER (Timer Controller)"
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base ad:0x0
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tree "TMR01"
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base ad:0x40010000
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group.long 0x0++0xB
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line.long 0x0 "TCSR0,Timer0 Control and Status Register"
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bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protected)\nTIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag (TISR[0] TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
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bitfld.long 0x0 26. "CRST,Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1.\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.."
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rbitfld.long 0x0 25. "CACT,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.7.4.5 for detail description.\n" "0: External counter mode Disabled,1: External counter mode Enabled"
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bitfld.long 0x0 23. "WAKE_EN,Wake-up Enable\nIf this bit is set to 1 while timer interrupt flag (TISR[0] TIF) is generated to 1 and IE (TCSR[29] interrupt enable bit) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer interrupt.."
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bitfld.long 0x0 16. "TDR_EN,Data Load Enable\nWhen this bit is set timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while timer.."
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hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter\n"
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line.long 0x4 "TCMPR0,Timer0 Compare Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field or the core will.."
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line.long 0x8 "TISR0,Timer0 Interrupt Status Register"
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bitfld.long 0x8 1. "TWF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nIt must be cleared by writing 1 to it through software." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by writing 1 to it through software." "0,1"
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rgroup.long 0xC++0x7
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line.long 0x0 "TDR0,Timer0 Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR will be updated continuously to monitor 24-bit timer counter value."
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line.long 0x4 "TCAP0,Timer0 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXEN (TEXCON[3] timer external pin enable) bit is set RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0 and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1] timer.."
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group.long 0x14++0x7
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line.long 0x0 "TEXCON0,Timer0 External Control Register"
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bitfld.long 0x0 7. "TCDB,Timer Counter Pin De-bounce Enable\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
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bitfld.long 0x0 6. "TEXDB,Timer External Capture Pin De-bounce Enable \nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
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bitfld.long 0x0 5. "TEXIEN,Timer External Interrupt Enable\n" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
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bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.."
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bitfld.long 0x0 3. "TEXEN,Timer External Pin Enable \nThis bit enables the RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select ) function on the TMx_EXT pin. \n" "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active"
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bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?"
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bitfld.long 0x0 0. "TX_PHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TEXISR0,Timer0 External Interrupt Status Register"
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bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nWhen TEXEN (TEXCON[3] timer external pin enable) bit is set RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0 and a.." "0,1"
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group.long 0x20++0xB
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line.long 0x0 "TCSR1,Timer1 Control and Status Register"
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bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protected)\nTIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag (TISR[0] TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
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bitfld.long 0x0 26. "CRST,Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1.\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.."
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rbitfld.long 0x0 25. "CACT,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.7.4.5 for detail description.\n" "0: External counter mode Disabled,1: External counter mode Enabled"
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bitfld.long 0x0 23. "WAKE_EN,Wake-up Enable\nIf this bit is set to 1 while timer interrupt flag (TISR[0] TIF) is generated to 1 and IE (TCSR[29] interrupt enable bit) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer interrupt.."
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bitfld.long 0x0 16. "TDR_EN,Data Load Enable\nWhen this bit is set timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while timer.."
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hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter\n"
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line.long 0x4 "TCMPR1,Timer1 Compare Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field or the core will.."
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line.long 0x8 "TISR1,Timer1 Interrupt Status Register"
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bitfld.long 0x8 1. "TWF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nIt must be cleared by writing 1 to it through software." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by writing 1 to it through software." "0,1"
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rgroup.long 0x2C++0x7
|
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line.long 0x0 "TDR1,Timer1 Data Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR will be updated continuously to monitor 24-bit timer counter value."
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line.long 0x4 "TCAP1,Timer1 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXEN (TEXCON[3] timer external pin enable) bit is set RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0 and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1] timer.."
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group.long 0x34++0x7
|
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line.long 0x0 "TEXCON1,Timer1 External Control Register"
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bitfld.long 0x0 7. "TCDB,Timer Counter Pin De-bounce Enable\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
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bitfld.long 0x0 6. "TEXDB,Timer External Capture Pin De-bounce Enable \nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
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bitfld.long 0x0 5. "TEXIEN,Timer External Interrupt Enable\n" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
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bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.."
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bitfld.long 0x0 3. "TEXEN,Timer External Pin Enable \nThis bit enables the RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select ) function on the TMx_EXT pin. \n" "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active"
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bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?"
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bitfld.long 0x0 0. "TX_PHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TEXISR1,Timer1 External Interrupt Status Register"
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bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nWhen TEXEN (TEXCON[3] timer external pin enable) bit is set RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0 and a.." "0,1"
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tree.end
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tree "TMR23"
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base ad:0x40110000
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group.long 0x0++0xB
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line.long 0x0 "TCSR2,Timer2 Control and Status Register"
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bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protected)\nTIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag (TISR[0] TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
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bitfld.long 0x0 26. "CRST,Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1.\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.."
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rbitfld.long 0x0 25. "CACT,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.7.4.5 for detail description.\n" "0: External counter mode Disabled,1: External counter mode Enabled"
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bitfld.long 0x0 23. "WAKE_EN,Wake-up Enable\nIf this bit is set to 1 while timer interrupt flag (TISR[0] TIF) is generated to 1 and IE (TCSR[29] interrupt enable bit) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer interrupt.."
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bitfld.long 0x0 16. "TDR_EN,Data Load Enable\nWhen this bit is set timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while timer.."
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hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter\n"
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line.long 0x4 "TCMPR2,Timer2 Compare Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field or the core will.."
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line.long 0x8 "TISR2,Timer2 Interrupt Status Register"
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bitfld.long 0x8 1. "TWF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nIt must be cleared by writing 1 to it through software." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by writing 1 to it through software." "0,1"
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rgroup.long 0xC++0x7
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line.long 0x0 "TDR2,Timer2 Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR will be updated continuously to monitor 24-bit timer counter value."
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line.long 0x4 "TCAP2,Timer2 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXEN (TEXCON[3] timer external pin enable) bit is set RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0 and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1] timer.."
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group.long 0x14++0x7
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line.long 0x0 "TEXCON2,Timer2 External Control Register"
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bitfld.long 0x0 7. "TCDB,Timer Counter Pin De-bounce Enable\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
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bitfld.long 0x0 6. "TEXDB,Timer External Capture Pin De-bounce Enable \nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
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bitfld.long 0x0 5. "TEXIEN,Timer External Interrupt Enable\n" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
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bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.."
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bitfld.long 0x0 3. "TEXEN,Timer External Pin Enable \nThis bit enables the RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select ) function on the TMx_EXT pin. \n" "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active"
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bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?"
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bitfld.long 0x0 0. "TX_PHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TEXISR2,Timer2 External Interrupt Status Register"
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bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nWhen TEXEN (TEXCON[3] timer external pin enable) bit is set RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0 and a.." "0,1"
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group.long 0x20++0xB
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line.long 0x0 "TCSR3,Timer3 Control and Status Register"
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bitfld.long 0x0 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protected)\nTIMER counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag (TISR[0] TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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bitfld.long 0x0 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
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bitfld.long 0x0 26. "CRST,Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1.\n" "0: No effect,1: Reset 8-bit prescale counter 24-bit up counter.."
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rbitfld.long 0x0 25. "CACT,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.7.4.5 for detail description.\n" "0: External counter mode Disabled,1: External counter mode Enabled"
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bitfld.long 0x0 23. "WAKE_EN,Wake-up Enable\nIf this bit is set to 1 while timer interrupt flag (TISR[0] TIF) is generated to 1 and IE (TCSR[29] interrupt enable bit) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer interrupt.."
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bitfld.long 0x0 16. "TDR_EN,Data Load Enable\nWhen this bit is set timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while timer.."
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hexmask.long.byte 0x0 0.--7. 1. "PRESCALE,Prescale Counter\n"
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line.long 0x4 "TCMPR3,Timer3 Compare Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field or the core will.."
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line.long 0x8 "TISR3,Timer3 Interrupt Status Register"
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bitfld.long 0x8 1. "TWF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nIt must be cleared by writing 1 to it through software." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by writing 1 to it through software." "0,1"
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rgroup.long 0x2C++0x7
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line.long 0x0 "TDR3,Timer3 Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR will be updated continuously to monitor 24-bit timer counter value."
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line.long 0x4 "TCAP3,Timer3 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXEN (TEXCON[3] timer external pin enable) bit is set RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0 and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1] timer.."
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group.long 0x34++0x7
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line.long 0x0 "TEXCON3,Timer3 External Control Register"
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bitfld.long 0x0 7. "TCDB,Timer Counter Pin De-bounce Enable\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
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bitfld.long 0x0 6. "TEXDB,Timer External Capture Pin De-bounce Enable \nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
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bitfld.long 0x0 5. "TEXIEN,Timer External Interrupt Enable\n" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
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bitfld.long 0x0 4. "RSTCAPSEL,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT pin is using to save the..,1: Transition on TMx_EXT pin is using to reset the.."
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bitfld.long 0x0 3. "TEXEN,Timer External Pin Enable \nThis bit enables the RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select ) function on the TMx_EXT pin. \n" "0: RSTCAPSEL function of TMx_EXT pin will be ignored,1: RSTCAPSEL function of TMx_EXT pin is active"
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bitfld.long 0x0 1.--2. "TEX_EDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,?,?"
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bitfld.long 0x0 0. "TX_PHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TEXISR3,Timer3 External Interrupt Status Register"
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bitfld.long 0x4 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nWhen TEXEN (TEXCON[3] timer external pin enable) bit is set RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0 and a.." "0,1"
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tree.end
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tree.end
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tree "UART (Universal Asynchronous Receiver/Transmitter)"
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base ad:0x0
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tree "UART0"
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base ad:0x40050000
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rgroup.long 0x0++0x3
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line.long 0x0 "UA_RBR,UART Receive Buffer Register"
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hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return an 8-bit data received from UART_RXD pin (LSB first)."
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wgroup.long 0x0++0x3
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line.long 0x0 "UA_THR,UART Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the UART will send out an 8-bit data through the UART_TXD pin (LSB first)."
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group.long 0x4++0x13
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line.long 0x0 "UA_IER,UART Interrupt Enable Register"
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bitfld.long 0x0 15. "DMA_RX_EN,RX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable RX DMA service.\n" "0: RX DMA Disabled,1: RX DMA Enabled"
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bitfld.long 0x0 14. "DMA_TX_EN,TX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable TX DMA service.\n" "0: TX DMA Disabled,1: TX DMA Enabled"
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bitfld.long 0x0 13. "AUTO_CTS_EN,NCTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto flow control Disabled,1: nCTS auto flow control Enabled"
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bitfld.long 0x0 12. "AUTO_RTS_EN,NRTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV] the UART will de-assert nRTS signal." "0: nRTS auto flow control Disabled,1: nRTS auto flow control Enabled"
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bitfld.long 0x0 11. "TIME_OUT_EN,Time-out Counter Enable\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable\nNote: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled"
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bitfld.long 0x0 6. "WAKE_EN,UART Wake-up Function Enable (Not Available in UART2 Channel)\n" "0: UART wake-up function Disabled,1: UART wake-up function Enabled when the chip is.."
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bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable\n" "0: INT_BUF_ERR Masked off,1: INT_BUF_ERR Enabled"
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bitfld.long 0x0 4. "TOUT_IEN,RX Time-out Interrupt Enable\n" "0: INT_TOUT Masked off,1: INT_TOUT Enabled"
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bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable (Not Available in UART2 Channel)\n" "0: INT_MODEM Masked off,1: INT_MODEM Enabled"
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bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable \n" "0: INT_RLS Masked off,1: INT_RLS Enabled"
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bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable\n" "0: INT_THRE Masked off,1: INT_THRE Enabled"
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newline
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bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable\n" "0: INT_RDA Masked off,1: INT_RDA Enabled"
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line.long 0x4 "UA_FCR,UART FIFO Control Register"
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hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,NRTS Trigger Level for Auto-flow Control Use (Not Available in UART2 Channel)\n"
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bitfld.long 0x4 8. "RX_DIS,Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level\n"
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bitfld.long 0x4 2. "TFR,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers"
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bitfld.long 0x4 1. "RFR,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers"
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line.long 0x8 "UA_LCR,UART Line Control Register"
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bitfld.long 0x8 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1"
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bitfld.long 0x8 5. "SPE,Stick Parity Enable\n" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.."
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bitfld.long 0x8 4. "EPE,Even Parity Enable\nThis bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x8 3. "PBE,Parity Bit Enable\n" "0: No parity bit,1: Parity bit is generated on each outgoing.."
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bitfld.long 0x8 2. "NSB,Number of 'STOP Bit'\n" "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0x8 0.--1. "WLS,Word Length Selection\n" "0,1,2,3"
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line.long 0xC "UA_MCR,UART Modem Control Register"
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rbitfld.long 0xC 13. "RTS_ST,NRTS Pin State (Read Only) (Not Available in UART2 Channel)\nThis bit is the output pin status of nRTS." "0,1"
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bitfld.long 0xC 9. "LEV_RTS,NRTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the nRTS trigger level.\n" "0: Low level triggered,1: High level triggered"
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bitfld.long 0xC 1. "RTS,NRTS (Request-to-send) Signal (Not Available in UART2 Channel)\n" "0: Drive nRTS pin to logic 1 (If the LEV_RTS set to..,1: Drive nRTS pin to logic 0 (If the LEV_RTS set to.."
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line.long 0x10 "UA_MSR,UART Modem Status Register"
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bitfld.long 0x10 8. "LEV_CTS,NCTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the nCTS trigger level.\n" "0: Low level triggered,1: High level triggered"
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rbitfld.long 0x10 4. "CTS_ST,NCTS Pin Status (Read Only) (Not Available in UART2 Channel)\nThis bit is the pin status of nCTS." "0,1"
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rbitfld.long 0x10 0. "DCTSF,Detect NCTS State Change Flag (Read Only) (Not Available in UART2 Channel)\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nWrite 1 to clear this bit to 0" "0,1"
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rgroup.long 0x18++0x7
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line.long 0x0 "UA_FSR,UART FIFO Status Register"
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bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not.." "0,1"
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bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0,1"
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bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR (TX.." "0,1"
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hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.."
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bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nThis bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0,1"
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bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0,1"
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hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one.\nThe Maximum.."
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bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0,1"
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bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0,1"
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bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 64/16/16 bytes of UART0/UART1/UART2 this bit will be set.\nNote: This bit is read only .." "0,1"
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line.long 0x4 "UA_ISR,UART Interrupt Status Register"
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bitfld.long 0x4 29. "HW_BUF_ERR_INT,In DMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n" "0: No buffer error interrupt is generated in DMA mode,1: Buffer error interrupt is generated in DMA mode"
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bitfld.long 0x4 28. "HW_TOUT_INT,In DMA Mode Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n" "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode"
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bitfld.long 0x4 27. "HW_MODEM_INT,In DMA Mode MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n" "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode"
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bitfld.long 0x4 26. "HW_RLS_INT,In DMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n" "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode"
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bitfld.long 0x4 21. "HW_BUF_ERR_IF,In DMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled the.." "0,1"
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bitfld.long 0x4 20. "HW_TOUT_IF,In DMA Mode Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled the Tout interrupt will be.." "0,1"
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bitfld.long 0x4 19. "HW_MODEM_IF,In DMA Mode MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF is cleared by writing 1 on DCTSF." "0,1"
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bitfld.long 0x4 18. "HW_RLS_IF,In DMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF FEF and PEF is set). If UA_IER [RLS_IEN] is enabled the RLS interrupt will.." "0,1"
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bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN and LIN _IF are both set to 1.\n" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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bitfld.long 0x4 12. "TOUT_INT,Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
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bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only)\nNote: This bit is cleared when LINS_HDET_F LIN_BKDET_F BIT_ERR_F LINS_IDPENR_F and LINS_HERR_F all are cleared" "0,1"
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bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled the buffer error interrupt.." "0,1"
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bitfld.long 0x4 4. "TOUT_IF,Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled the Tout interrupt will be generated. \nNote:.." "0,1"
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bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF." "0,1"
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bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF FEF and PEF is set). If UA_IER [RLS_IEN] is enabled the RLS interrupt will be.." "0,1"
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bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0,1"
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bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled the RDA interrupt will be generated. \nNote: This bit is read only and it will.." "0,1"
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group.long 0x20++0x1B
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line.long 0x0 "UA_TOR,UART Time-out Register"
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hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit."
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hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator\n"
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line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register"
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bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable\nRefer to Table 611 for more information.\nNote: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.."
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bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal to 1\nRefer to Table 611 for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
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hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X\n"
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hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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line.long 0x8 "UA_IRCR,UART IrDA Control Register"
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bitfld.long 0x8 6. "INV_RX,INV_RX\n" "0: No inversion,1: Inverse RX input signal"
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bitfld.long 0x8 5. "INV_TX,INV_TX\n" "0: No inversion,1: Inverse TX output signal"
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bitfld.long 0x8 1. "TX_SELECT,TX_SELECT\n" "0: IrDA receiver Enabled,1: IrDA transmitter Enabled"
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line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register"
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hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable \nThis bit is used to enable RS-485 Address Detection mode. \nNote: This field is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled"
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bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1\n"
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line.long 0x10 "UA_FUN_SEL,UART Function Select Register"
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bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable\n" "0: UART function Enabled,1: LIN function Enabled,?,?"
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line.long 0x14 "UA_LIN_CTL,UART LIN Control Register"
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hexmask.long.byte 0x14 24.--31. 1. "LIN_PID,LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode the frame ID parity can be generated by software or hardware depends on UA_LIN_CTL [LIN_IDPEN]. \n\nNote1: User can fill any 8-bit value to this field and the.."
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bitfld.long 0x14 22.--23. "LIN_HEAD_SEL,LIN Header Select\n" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?"
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bitfld.long 0x14 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1 bit time,?,?,?"
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hexmask.long.byte 0x14 16.--19. 1. "LIN_BKFL,LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of UA_ALT_CSR [LIN_BKFL] User can read/write it by setting UA_ALT_CSR [LIN_BKFL] or UA_LIN_CTL [LIN_BKFL].\nNote2: This.."
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bitfld.long 0x14 12. "BIT_ERR_EN,Bit Error Detect Enable\n" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
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bitfld.long 0x14 11. "LIN_RX_DIS" "0: Error detection function Disabled,1: Bit error detection Enabled"
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bitfld.long 0x14 10. "LIN_BKDET_EN,LIN Break Detection Enable\n" "0: Disable LIN break detection,1: Enable LIN break detection"
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bitfld.long 0x14 9. "LIN_IDPEN,LIN ID Parity Enable\n" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x14 8. "LIN_SHD,LIN TX Send Header Enable \nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL register.\nNote1: These registers are shadow registers of UA_ALT_CSR [LIN_SHD];.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x14 4. "LIN_MUTE_EN,LIN Mute Mode Enable\nNote: The exit from mute mode condition and each control and interactions of this field are explained in character 6.12.5.4 (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x14 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) \nNote3: The control and interactions of this field are.." "0: UA_BAUD is updated as soon as UA_BAUD is writing..,1: UA_BAUD is updated at the next received.."
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bitfld.long 0x14 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (UA_BAUD [DIV_X_EN] and UA_BAUD [DIV_X_ONE] must be 1).\nNote3: The control and interactions of.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x14 1. "LINS_HDET_EN,LIN Slave Header Detection Enable\n" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x14 0. "LINS_EN,LIN Slave Mode Enable\n" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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line.long 0x18 "UA_LIN_SR,UART LIN Status Register"
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rbitfld.long 0x18 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F will be set.\n" "0,1"
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rbitfld.long 0x18 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: This bit is only.." "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x18 3. "LINS_SYNC_F,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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rbitfld.long 0x18 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n" "0: No active,1: Receipted frame ID parity is not correct"
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rbitfld.long 0x18 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short' 'frame error in sync field.." "0: LIN header error not detected,1: LIN header error detected"
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rbitfld.long 0x18 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n" "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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tree.end
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tree "UART1"
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base ad:0x40150000
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rgroup.long 0x0++0x3
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line.long 0x0 "UA_RBR,UART Receive Buffer Register"
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hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return an 8-bit data received from UART_RXD pin (LSB first)."
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wgroup.long 0x0++0x3
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line.long 0x0 "UA_THR,UART Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the UART will send out an 8-bit data through the UART_TXD pin (LSB first)."
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group.long 0x4++0x13
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line.long 0x0 "UA_IER,UART Interrupt Enable Register"
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bitfld.long 0x0 15. "DMA_RX_EN,RX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable RX DMA service.\n" "0: RX DMA Disabled,1: RX DMA Enabled"
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bitfld.long 0x0 14. "DMA_TX_EN,TX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable TX DMA service.\n" "0: TX DMA Disabled,1: TX DMA Enabled"
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bitfld.long 0x0 13. "AUTO_CTS_EN,NCTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto flow control Disabled,1: nCTS auto flow control Enabled"
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bitfld.long 0x0 12. "AUTO_RTS_EN,NRTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV] the UART will de-assert nRTS signal." "0: nRTS auto flow control Disabled,1: nRTS auto flow control Enabled"
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bitfld.long 0x0 11. "TIME_OUT_EN,Time-out Counter Enable\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable\nNote: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled"
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bitfld.long 0x0 6. "WAKE_EN,UART Wake-up Function Enable (Not Available in UART2 Channel)\n" "0: UART wake-up function Disabled,1: UART wake-up function Enabled when the chip is.."
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bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable\n" "0: INT_BUF_ERR Masked off,1: INT_BUF_ERR Enabled"
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bitfld.long 0x0 4. "TOUT_IEN,RX Time-out Interrupt Enable\n" "0: INT_TOUT Masked off,1: INT_TOUT Enabled"
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bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable (Not Available in UART2 Channel)\n" "0: INT_MODEM Masked off,1: INT_MODEM Enabled"
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bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable \n" "0: INT_RLS Masked off,1: INT_RLS Enabled"
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bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable\n" "0: INT_THRE Masked off,1: INT_THRE Enabled"
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bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable\n" "0: INT_RDA Masked off,1: INT_RDA Enabled"
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line.long 0x4 "UA_FCR,UART FIFO Control Register"
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hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,NRTS Trigger Level for Auto-flow Control Use (Not Available in UART2 Channel)\n"
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bitfld.long 0x4 8. "RX_DIS,Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level\n"
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bitfld.long 0x4 2. "TFR,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers"
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bitfld.long 0x4 1. "RFR,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers"
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line.long 0x8 "UA_LCR,UART Line Control Register"
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bitfld.long 0x8 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1"
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bitfld.long 0x8 5. "SPE,Stick Parity Enable\n" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.."
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bitfld.long 0x8 4. "EPE,Even Parity Enable\nThis bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x8 3. "PBE,Parity Bit Enable\n" "0: No parity bit,1: Parity bit is generated on each outgoing.."
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bitfld.long 0x8 2. "NSB,Number of 'STOP Bit'\n" "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0x8 0.--1. "WLS,Word Length Selection\n" "0,1,2,3"
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line.long 0xC "UA_MCR,UART Modem Control Register"
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rbitfld.long 0xC 13. "RTS_ST,NRTS Pin State (Read Only) (Not Available in UART2 Channel)\nThis bit is the output pin status of nRTS." "0,1"
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bitfld.long 0xC 9. "LEV_RTS,NRTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the nRTS trigger level.\n" "0: Low level triggered,1: High level triggered"
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bitfld.long 0xC 1. "RTS,NRTS (Request-to-send) Signal (Not Available in UART2 Channel)\n" "0: Drive nRTS pin to logic 1 (If the LEV_RTS set to..,1: Drive nRTS pin to logic 0 (If the LEV_RTS set to.."
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line.long 0x10 "UA_MSR,UART Modem Status Register"
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bitfld.long 0x10 8. "LEV_CTS,NCTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the nCTS trigger level.\n" "0: Low level triggered,1: High level triggered"
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rbitfld.long 0x10 4. "CTS_ST,NCTS Pin Status (Read Only) (Not Available in UART2 Channel)\nThis bit is the pin status of nCTS." "0,1"
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rbitfld.long 0x10 0. "DCTSF,Detect NCTS State Change Flag (Read Only) (Not Available in UART2 Channel)\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nWrite 1 to clear this bit to 0" "0,1"
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rgroup.long 0x18++0x7
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line.long 0x0 "UA_FSR,UART FIFO Status Register"
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bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not.." "0,1"
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bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0,1"
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bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR (TX.." "0,1"
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hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.."
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bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nThis bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0,1"
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bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0,1"
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hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one.\nThe Maximum.."
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bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0,1"
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bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0,1"
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bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 64/16/16 bytes of UART0/UART1/UART2 this bit will be set.\nNote: This bit is read only .." "0,1"
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line.long 0x4 "UA_ISR,UART Interrupt Status Register"
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bitfld.long 0x4 29. "HW_BUF_ERR_INT,In DMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n" "0: No buffer error interrupt is generated in DMA mode,1: Buffer error interrupt is generated in DMA mode"
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bitfld.long 0x4 28. "HW_TOUT_INT,In DMA Mode Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n" "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode"
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bitfld.long 0x4 27. "HW_MODEM_INT,In DMA Mode MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n" "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode"
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bitfld.long 0x4 26. "HW_RLS_INT,In DMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n" "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode"
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bitfld.long 0x4 21. "HW_BUF_ERR_IF,In DMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled the.." "0,1"
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bitfld.long 0x4 20. "HW_TOUT_IF,In DMA Mode Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled the Tout interrupt will be.." "0,1"
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bitfld.long 0x4 19. "HW_MODEM_IF,In DMA Mode MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF is cleared by writing 1 on DCTSF." "0,1"
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bitfld.long 0x4 18. "HW_RLS_IF,In DMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF FEF and PEF is set). If UA_IER [RLS_IEN] is enabled the RLS interrupt will.." "0,1"
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bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN and LIN _IF are both set to 1.\n" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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bitfld.long 0x4 12. "TOUT_INT,Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
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bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only)\nNote: This bit is cleared when LINS_HDET_F LIN_BKDET_F BIT_ERR_F LINS_IDPENR_F and LINS_HERR_F all are cleared" "0,1"
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bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled the buffer error interrupt.." "0,1"
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bitfld.long 0x4 4. "TOUT_IF,Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled the Tout interrupt will be generated. \nNote:.." "0,1"
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bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF." "0,1"
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bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF FEF and PEF is set). If UA_IER [RLS_IEN] is enabled the RLS interrupt will be.." "0,1"
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bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0,1"
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bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled the RDA interrupt will be generated. \nNote: This bit is read only and it will.." "0,1"
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group.long 0x20++0x1B
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line.long 0x0 "UA_TOR,UART Time-out Register"
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hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit."
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hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator\n"
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line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register"
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bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable\nRefer to Table 611 for more information.\nNote: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.."
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bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal to 1\nRefer to Table 611 for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
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hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X\n"
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hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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line.long 0x8 "UA_IRCR,UART IrDA Control Register"
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bitfld.long 0x8 6. "INV_RX,INV_RX\n" "0: No inversion,1: Inverse RX input signal"
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bitfld.long 0x8 5. "INV_TX,INV_TX\n" "0: No inversion,1: Inverse TX output signal"
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bitfld.long 0x8 1. "TX_SELECT,TX_SELECT\n" "0: IrDA receiver Enabled,1: IrDA transmitter Enabled"
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line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register"
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hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable \nThis bit is used to enable RS-485 Address Detection mode. \nNote: This field is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled"
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bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1\n"
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line.long 0x10 "UA_FUN_SEL,UART Function Select Register"
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bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable\n" "0: UART function Enabled,1: LIN function Enabled,?,?"
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line.long 0x14 "UA_LIN_CTL,UART LIN Control Register"
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hexmask.long.byte 0x14 24.--31. 1. "LIN_PID,LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode the frame ID parity can be generated by software or hardware depends on UA_LIN_CTL [LIN_IDPEN]. \n\nNote1: User can fill any 8-bit value to this field and the.."
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bitfld.long 0x14 22.--23. "LIN_HEAD_SEL,LIN Header Select\n" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?"
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bitfld.long 0x14 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1 bit time,?,?,?"
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hexmask.long.byte 0x14 16.--19. 1. "LIN_BKFL,LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of UA_ALT_CSR [LIN_BKFL] User can read/write it by setting UA_ALT_CSR [LIN_BKFL] or UA_LIN_CTL [LIN_BKFL].\nNote2: This.."
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bitfld.long 0x14 12. "BIT_ERR_EN,Bit Error Detect Enable\n" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
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bitfld.long 0x14 11. "LIN_RX_DIS" "0: Error detection function Disabled,1: Bit error detection Enabled"
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bitfld.long 0x14 10. "LIN_BKDET_EN,LIN Break Detection Enable\n" "0: Disable LIN break detection,1: Enable LIN break detection"
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bitfld.long 0x14 9. "LIN_IDPEN,LIN ID Parity Enable\n" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x14 8. "LIN_SHD,LIN TX Send Header Enable \nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL register.\nNote1: These registers are shadow registers of UA_ALT_CSR [LIN_SHD];.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x14 4. "LIN_MUTE_EN,LIN Mute Mode Enable\nNote: The exit from mute mode condition and each control and interactions of this field are explained in character 6.12.5.4 (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x14 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) \nNote3: The control and interactions of this field are.." "0: UA_BAUD is updated as soon as UA_BAUD is writing..,1: UA_BAUD is updated at the next received.."
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bitfld.long 0x14 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (UA_BAUD [DIV_X_EN] and UA_BAUD [DIV_X_ONE] must be 1).\nNote3: The control and interactions of.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x14 1. "LINS_HDET_EN,LIN Slave Header Detection Enable\n" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x14 0. "LINS_EN,LIN Slave Mode Enable\n" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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line.long 0x18 "UA_LIN_SR,UART LIN Status Register"
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rbitfld.long 0x18 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F will be set.\n" "0,1"
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rbitfld.long 0x18 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: This bit is only.." "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x18 3. "LINS_SYNC_F,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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rbitfld.long 0x18 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n" "0: No active,1: Receipted frame ID parity is not correct"
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rbitfld.long 0x18 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short' 'frame error in sync field.." "0: LIN header error not detected,1: LIN header error detected"
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rbitfld.long 0x18 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n" "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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tree.end
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tree "UART2"
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base ad:0x40154000
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rgroup.long 0x0++0x3
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line.long 0x0 "UA_RBR,UART Receive Buffer Register"
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hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return an 8-bit data received from UART_RXD pin (LSB first)."
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wgroup.long 0x0++0x3
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line.long 0x0 "UA_THR,UART Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the UART will send out an 8-bit data through the UART_TXD pin (LSB first)."
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group.long 0x4++0xB
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line.long 0x0 "UA_IER,UART Interrupt Enable Register"
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bitfld.long 0x0 15. "DMA_RX_EN,RX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable RX DMA service.\n" "0: RX DMA Disabled,1: RX DMA Enabled"
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bitfld.long 0x0 14. "DMA_TX_EN,TX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable TX DMA service.\n" "0: TX DMA Disabled,1: TX DMA Enabled"
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bitfld.long 0x0 13. "AUTO_CTS_EN,NCTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto flow control Disabled,1: nCTS auto flow control Enabled"
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bitfld.long 0x0 12. "AUTO_RTS_EN,NRTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV] the UART will de-assert nRTS signal." "0: nRTS auto flow control Disabled,1: nRTS auto flow control Enabled"
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bitfld.long 0x0 11. "TIME_OUT_EN,Time-out Counter Enable\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x0 8. "LIN_IEN,LIN Bus Interrupt Enable\nNote: This field is used for LIN function mode." "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled"
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bitfld.long 0x0 6. "WAKE_EN,UART Wake-up Function Enable (Not Available in UART2 Channel)\n" "0: UART wake-up function Disabled,1: UART wake-up function Enabled when the chip is.."
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bitfld.long 0x0 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable\n" "0: INT_BUF_ERR Masked off,1: INT_BUF_ERR Enabled"
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bitfld.long 0x0 4. "TOUT_IEN,RX Time-out Interrupt Enable\n" "0: INT_TOUT Masked off,1: INT_TOUT Enabled"
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bitfld.long 0x0 3. "MODEM_IEN,Modem Status Interrupt Enable (Not Available in UART2 Channel)\n" "0: INT_MODEM Masked off,1: INT_MODEM Enabled"
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bitfld.long 0x0 2. "RLS_IEN,Receive Line Status Interrupt Enable \n" "0: INT_RLS Masked off,1: INT_RLS Enabled"
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bitfld.long 0x0 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable\n" "0: INT_THRE Masked off,1: INT_THRE Enabled"
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bitfld.long 0x0 0. "RDA_IEN,Receive Data Available Interrupt Enable\n" "0: INT_RDA Masked off,1: INT_RDA Enabled"
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line.long 0x4 "UA_FCR,UART FIFO Control Register"
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hexmask.long.byte 0x4 16.--19. 1. "RTS_TRI_LEV,NRTS Trigger Level for Auto-flow Control Use (Not Available in UART2 Channel)\n"
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bitfld.long 0x4 8. "RX_DIS,Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level\n"
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bitfld.long 0x4 2. "TFR,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers"
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bitfld.long 0x4 1. "RFR,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers"
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line.long 0x8 "UA_LCR,UART Line Control Register"
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bitfld.long 0x8 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic." "0,1"
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bitfld.long 0x8 5. "SPE,Stick Parity Enable\n" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic.."
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bitfld.long 0x8 4. "EPE,Even Parity Enable\nThis bit has effect only when PBE (UA_LCR[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x8 3. "PBE,Parity Bit Enable\n" "0: No parity bit,1: Parity bit is generated on each outgoing.."
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bitfld.long 0x8 2. "NSB,Number of 'STOP Bit'\n" "0: One ' STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0x8 0.--1. "WLS,Word Length Selection\n" "0,1,2,3"
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rgroup.long 0x18++0x7
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line.long 0x0 "UA_FSR,UART FIFO Status Register"
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bitfld.long 0x0 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not.." "0,1"
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bitfld.long 0x0 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0,1"
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bitfld.long 0x0 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR (TX.." "0,1"
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hexmask.long.byte 0x0 16.--21. 1. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register then TX_POINTER decreases.."
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bitfld.long 0x0 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nThis bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware." "0,1"
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bitfld.long 0x0 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0,1"
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hexmask.long.byte 0x0 8.--13. 1. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device then RX_POINTER increases one. When one byte of RX FIFO is read by CPU then RX_POINTER decreases one.\nThe Maximum.."
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bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0,1"
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bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0,1"
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bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only but can be cleared by writing '1' to it." "0,1"
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bitfld.long 0x0 0. "RX_OVER_IF,RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 64/16/16 bytes of UART0/UART1/UART2 this bit will be set.\nNote: This bit is read only .." "0,1"
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line.long 0x4 "UA_ISR,UART Interrupt Status Register"
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bitfld.long 0x4 29. "HW_BUF_ERR_INT,In DMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n" "0: No buffer error interrupt is generated in DMA mode,1: Buffer error interrupt is generated in DMA mode"
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bitfld.long 0x4 28. "HW_TOUT_INT,In DMA Mode Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n" "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode"
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bitfld.long 0x4 27. "HW_MODEM_INT,In DMA Mode MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n" "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode"
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bitfld.long 0x4 26. "HW_RLS_INT,In DMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n" "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode"
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bitfld.long 0x4 21. "HW_BUF_ERR_IF,In DMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled the.." "0,1"
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bitfld.long 0x4 20. "HW_TOUT_IF,In DMA Mode Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled the Tout interrupt will be.." "0,1"
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bitfld.long 0x4 19. "HW_MODEM_IF,In DMA Mode MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF is cleared by writing 1 on DCTSF." "0,1"
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bitfld.long 0x4 18. "HW_RLS_IF,In DMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF FEF and PEF is set). If UA_IER [RLS_IEN] is enabled the RLS interrupt will.." "0,1"
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bitfld.long 0x4 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN and LIN _IF are both set to 1.\n" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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bitfld.long 0x4 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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bitfld.long 0x4 12. "TOUT_INT,Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
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bitfld.long 0x4 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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bitfld.long 0x4 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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bitfld.long 0x4 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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bitfld.long 0x4 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x4 7. "LIN_IF,LIN Bus Flag (Read Only)\nNote: This bit is cleared when LINS_HDET_F LIN_BKDET_F BIT_ERR_F LINS_IDPENR_F and LINS_HERR_F all are cleared" "0,1"
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bitfld.long 0x4 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled the buffer error interrupt.." "0,1"
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bitfld.long 0x4 4. "TOUT_IF,Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled the Tout interrupt will be generated. \nNote:.." "0,1"
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bitfld.long 0x4 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF." "0,1"
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bitfld.long 0x4 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF FEF and PEF is set). If UA_IER [RLS_IEN] is enabled the RLS interrupt will be.." "0,1"
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bitfld.long 0x4 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled the THRE interrupt will be generated.\nNote: This bit is.." "0,1"
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bitfld.long 0x4 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled the RDA interrupt will be generated. \nNote: This bit is read only and it will.." "0,1"
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group.long 0x20++0x1B
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line.long 0x0 "UA_TOR,UART Time-out Register"
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hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit."
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hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator\n"
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line.long 0x4 "UA_BAUD,UART Baud Rate Divisor Register"
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bitfld.long 0x4 29. "DIV_X_EN,Divider X Enable\nRefer to Table 611 for more information.\nNote: In IrDA mode this bit must disable." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.."
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bitfld.long 0x4 28. "DIV_X_ONE,Divider X Equal to 1\nRefer to Table 611 for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
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hexmask.long.byte 0x4 24.--27. 1. "DIVIDER_X,Divider X\n"
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hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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line.long 0x8 "UA_IRCR,UART IrDA Control Register"
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bitfld.long 0x8 6. "INV_RX,INV_RX\n" "0: No inversion,1: Inverse RX input signal"
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bitfld.long 0x8 5. "INV_TX,INV_TX\n" "0: No inversion,1: Inverse TX output signal"
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bitfld.long 0x8 1. "TX_SELECT,TX_SELECT\n" "0: IrDA receiver Enabled,1: IrDA transmitter Enabled"
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line.long 0xC "UA_ALT_CSR,UART Alternate Control/Status Register"
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hexmask.long.byte 0xC 24.--31. 1. "ADDR_MATCH,Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
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bitfld.long 0xC 15. "RS485_ADD_EN,RS-485 Address Detection Enable \nThis bit is used to enable RS-485 Address Detection mode. \nNote: This field is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO) Enabled"
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bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0xC 7. "LIN_TX_EN,LIN TX Break Mode Enable\nNote: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0xC 6. "LIN_RX_EN,LIN RX Enable\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0xC 0.--3. 1. "LIN_BKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1\n"
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line.long 0x10 "UA_FUN_SEL,UART Function Select Register"
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bitfld.long 0x10 0.--1. "FUN_SEL,Function Select Enable\n" "0: UART function Enabled,1: LIN function Enabled,?,?"
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line.long 0x14 "UA_LIN_CTL,UART LIN Control Register"
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hexmask.long.byte 0x14 24.--31. 1. "LIN_PID,LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode the frame ID parity can be generated by software or hardware depends on UA_LIN_CTL [LIN_IDPEN]. \n\nNote1: User can fill any 8-bit value to this field and the.."
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bitfld.long 0x14 22.--23. "LIN_HEAD_SEL,LIN Header Select\n" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?"
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bitfld.long 0x14 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1 bit time,?,?,?"
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hexmask.long.byte 0x14 16.--19. 1. "LIN_BKFL,LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of UA_ALT_CSR [LIN_BKFL] User can read/write it by setting UA_ALT_CSR [LIN_BKFL] or UA_LIN_CTL [LIN_BKFL].\nNote2: This.."
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bitfld.long 0x14 12. "BIT_ERR_EN,Bit Error Detect Enable\n" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
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bitfld.long 0x14 11. "LIN_RX_DIS" "0: Error detection function Disabled,1: Bit error detection Enabled"
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bitfld.long 0x14 10. "LIN_BKDET_EN,LIN Break Detection Enable\n" "0: Disable LIN break detection,1: Enable LIN break detection"
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bitfld.long 0x14 9. "LIN_IDPEN,LIN ID Parity Enable\n" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x14 8. "LIN_SHD,LIN TX Send Header Enable \nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL register.\nNote1: These registers are shadow registers of UA_ALT_CSR [LIN_SHD];.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x14 4. "LIN_MUTE_EN,LIN Mute Mode Enable\nNote: The exit from mute mode condition and each control and interactions of this field are explained in character 6.12.5.4 (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x14 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) \nNote3: The control and interactions of this field are.." "0: UA_BAUD is updated as soon as UA_BAUD is writing..,1: UA_BAUD is updated at the next received.."
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bitfld.long 0x14 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (UA_BAUD [DIV_X_EN] and UA_BAUD [DIV_X_ONE] must be 1).\nNote3: The control and interactions of.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x14 1. "LINS_HDET_EN,LIN Slave Header Detection Enable\n" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x14 0. "LINS_EN,LIN Slave Mode Enable\n" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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line.long 0x18 "UA_LIN_SR,UART LIN Status Register"
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rbitfld.long 0x18 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F will be set.\n" "0,1"
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rbitfld.long 0x18 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: This bit is only.." "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x18 3. "LINS_SYNC_F,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame header.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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rbitfld.long 0x18 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n" "0: No active,1: Receipted frame ID parity is not correct"
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rbitfld.long 0x18 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short' 'frame error in sync field.." "0: LIN header error not detected,1: LIN header error detected"
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rbitfld.long 0x18 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n" "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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tree.end
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tree.end
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tree "USB (USB Device Controller)"
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base ad:0x40060000
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group.long 0x0++0xB
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line.long 0x0 "USB_INTEN,USB Interrupt Enable Register"
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bitfld.long 0x0 15. "INNAK_EN,Active NAK Function and Its Status in IN Token\n" "0: NAK status is not updated into the endpoint..,1: NAK status is updated into the endpoint status.."
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bitfld.long 0x0 8. "WAKEUP_EN,Wake-up Function Enable\n" "0: USB wake-up function Disabled,1: USB wake-up function Enabled"
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bitfld.long 0x0 3. "WAKEUP_IE,USB Wake-up Interrupt Enable\n" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x0 2. "FLDET_IE,Floating Detected Interrupt Enable\n" "0: Floating detect Interrupt Disabled,1: Floating detect Interrupt Enabled"
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bitfld.long 0x0 1. "USB_IE,USB Event Interrupt Enable\n" "0: USB event interrupt Disabled,1: USB event interrupt Enabled"
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bitfld.long 0x0 0. "BUS_IE,Bus Event Interrupt Enable\n" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled"
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line.long 0x4 "USB_INTSTS,USB Interrupt Event Status Register"
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bitfld.long 0x4 31. "SETUP,Setup Event Status\n" "0: No Setup event,1: Setup event occurred cleared by write 1 to.."
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bitfld.long 0x4 21. "EPEVT5,Endpoint 5's USB Event Status\n" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5 check.."
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bitfld.long 0x4 20. "EPEVT4,Endpoint 4's USB Event Status\n" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4 check.."
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bitfld.long 0x4 19. "EPEVT3,Endpoint 3's USB Event Status\n" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3 check.."
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bitfld.long 0x4 18. "EPEVT2,Endpoint 2's USB Event Status\n" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2 check.."
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bitfld.long 0x4 17. "EPEVT1,Endpoint 1's USB Event Status\n" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1 check.."
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bitfld.long 0x4 16. "EPEVT0,Endpoint 0's USB Event Status\n" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0 check.."
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bitfld.long 0x4 3. "WAKEUP_STS,Wake-up Interrupt Status\n" "0: No Wake-up event occurred,1: Wake-up event occurred cleared by write 1 to.."
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bitfld.long 0x4 2. "FLDET_STS,Floating Detected Interrupt Status\n" "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB bus.."
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bitfld.long 0x4 1. "USB_STS,USB Event Interrupt Status\nThe USB event includes the Setup Token IN Token OUT ACK ISO IN or ISO OUT events in the bus.\n" "0: No USB event occurred,1: USB event occurred check EPSTS0~5[2:0] to know.."
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bitfld.long 0x4 0. "BUS_STS,BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.\n" "0: No BUS event occurred,1: Bus event occurred; check USB_ATTR[3:0] to know.."
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line.long 0x8 "USB_FADDR,USB Device Function Address Register"
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hexmask.long.byte 0x8 0.--6. 1. "FADDR,USB Device Function Address"
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rgroup.long 0xC++0x3
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line.long 0x0 "USB_EPSTS,USB Endpoint Status Register"
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bitfld.long 0x0 23.--25. "EPSTS5,Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint\n" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "EPSTS4,Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint\n" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 17.--19. "EPSTS3,Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint\n" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 14.--16. "EPSTS2,Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint\n" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 11.--13. "EPSTS1,Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint\n" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "EPSTS0,Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint\n" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 7. "OVERRUN,Overrun\nIt indicates that the received data is over the maximum payload number or not.\n" "0: No overrun,1: Out Data is more than the Max Payload in MXPLD.."
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group.long 0x10++0x3
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line.long 0x0 "USB_ATTR,USB Bus Status and Attribution Register"
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bitfld.long 0x0 10. "BYTEM,CPU Access USB SRAM Size Mode Selection\n" "0: Word mode: The size of the transfer from CPU to..,1: Byte mode: The size of the transfer from CPU to.."
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bitfld.long 0x0 9. "PWRDN,Power-down PHY Transceiver Low Active\n" "0: Power-down related circuit of PHY transceiver,1: Turn-on related circuit of PHY transceiver"
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bitfld.long 0x0 8. "DPPU_EN,Pull-up Resistor on USB_DP Enable\n" "0: Pull-up resistor in USB_DP bus Disabled,1: Pull-up resistor in USB_DP bus Active"
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bitfld.long 0x0 7. "USB_EN,USB Controller Enable\n" "0: USB Controller Disabled,1: USB Controller Enabled"
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bitfld.long 0x0 5. "RWAKEUP,Remote Wake-up\n" "0: Release the USB bus from K state,1: Force USB bus to K (USB_DP low USB_DM: high).."
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bitfld.long 0x0 4. "PHY_EN,PHY Transceiver Function Enable\n" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled"
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bitfld.long 0x0 3. "TIMEOUT,Time-out Status\nThis bit is read only." "0: No time-out,1: No Bus response more than 18 bits time"
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bitfld.long 0x0 2. "RESUME,Resume Status\nThis bit is read only." "0: No bus resume,1: Resume from suspend"
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bitfld.long 0x0 1. "SUSPEND,Suspend Status\nThis bit is read only." "0: Bus no suspend,1: Bus idle more than 3ms either cable is plugged.."
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bitfld.long 0x0 0. "USBRST,USB Reset Status\nThis bit is read only." "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) more than.."
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rgroup.long 0x14++0x3
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line.long 0x0 "USB_FLDET,USB Floating Detected Register"
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bitfld.long 0x0 0. "FLDET,Device Floating Detected\n" "0: Controller is not attached into the USB host,1: Controller is attached into the BUS"
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group.long 0x18++0x3
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line.long 0x0 "USB_STBUFSEG,Setup Token Buffer Segmentation Register"
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hexmask.long.byte 0x0 3.--8. 1. "STBUFSEG,It Is Used to Indicate the Offset Address for the Setup Token with the USB SRAM Starting Address The Effective Starting Address Is\nUSB_SRAM address + {STBUFSEG[8:3] 3'b000} \nNote: It is used for Setup token only."
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group.long 0x20++0x5F
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line.long 0x0 "USB_BUFSEG0,Endpoint 0 Buffer Segmentation Register"
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hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,It Is Used to Indicate the Offset Address for Each Endpoint with the USB SRAM Starting Address The Effective Starting Address of the Endpoint Is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7 for the endpoint SRAM.."
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line.long 0x4 "USB_MXPLD0,Endpoint 0 Maximal Payload Register"
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hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x8 "USB_CFG0,Endpoint 0 Configuration Register"
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bitfld.long 0x8 9. "CSTALL,Clear STALL Response\n" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL -handshake in.."
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bitfld.long 0x8 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token based on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x8 5.--6. "STATE,Endpoint STATE\n" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake.\n" "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x8 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint"
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line.long 0xC "USB_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0xC 1. "SSTALL,Set STALL\n" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0xC 0. "CLRRDY,Clear Ready\nWhen the MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start users can set this bit to 1 to turn it off and it is.." "0,1"
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line.long 0x10 "USB_BUFSEG1,Endpoint 1 Buffer Segmentation Register"
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hexmask.long.byte 0x10 3.--8. 1. "BUFSEG,It Is Used to Indicate the Offset Address for Each Endpoint with the USB SRAM Starting Address The Effective Starting Address of the Endpoint Is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7 for the endpoint SRAM.."
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line.long 0x14 "USB_MXPLD1,Endpoint 1 Maximal Payload Register"
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hexmask.long.word 0x14 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x18 "USB_CFG1,Endpoint 1 Configuration Register"
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bitfld.long 0x18 9. "CSTALL,Clear STALL Response\n" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL -handshake in.."
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bitfld.long 0x18 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token based on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x18 5.--6. "STATE,Endpoint STATE\n" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x18 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake.\n" "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x18 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint"
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line.long 0x1C "USB_CFGP1,Endpoint 1 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x1C 1. "SSTALL,Set STALL\n" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x1C 0. "CLRRDY,Clear Ready\nWhen the MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start users can set this bit to 1 to turn it off and it is.." "0,1"
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line.long 0x20 "USB_BUFSEG2,Endpoint 2 Buffer Segmentation Register"
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hexmask.long.byte 0x20 3.--8. 1. "BUFSEG,It Is Used to Indicate the Offset Address for Each Endpoint with the USB SRAM Starting Address The Effective Starting Address of the Endpoint Is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7 for the endpoint SRAM.."
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line.long 0x24 "USB_MXPLD2,Endpoint 2 Maximal Payload Register"
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hexmask.long.word 0x24 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x28 "USB_CFG2,Endpoint 2 Configuration Register"
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bitfld.long 0x28 9. "CSTALL,Clear STALL Response\n" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL -handshake in.."
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bitfld.long 0x28 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token based on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x28 5.--6. "STATE,Endpoint STATE\n" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x28 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake.\n" "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x28 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint"
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line.long 0x2C "USB_CFGP2,Endpoint 2 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x2C 1. "SSTALL,Set STALL\n" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x2C 0. "CLRRDY,Clear Ready\nWhen the MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start users can set this bit to 1 to turn it off and it is.." "0,1"
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line.long 0x30 "USB_BUFSEG3,Endpoint 3 Buffer Segmentation Register"
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hexmask.long.byte 0x30 3.--8. 1. "BUFSEG,It Is Used to Indicate the Offset Address for Each Endpoint with the USB SRAM Starting Address The Effective Starting Address of the Endpoint Is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7 for the endpoint SRAM.."
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line.long 0x34 "USB_MXPLD3,Endpoint 3 Maximal Payload Register"
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hexmask.long.word 0x34 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x38 "USB_CFG3,Endpoint 3 Configuration Register"
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bitfld.long 0x38 9. "CSTALL,Clear STALL Response\n" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL -handshake in.."
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bitfld.long 0x38 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token based on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x38 5.--6. "STATE,Endpoint STATE\n" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x38 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake.\n" "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x38 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint"
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line.long 0x3C "USB_CFGP3,Endpoint 3 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x3C 1. "SSTALL,Set STALL\n" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x3C 0. "CLRRDY,Clear Ready\nWhen the MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start users can set this bit to 1 to turn it off and it is.." "0,1"
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line.long 0x40 "USB_BUFSEG4,Endpoint 4 Buffer Segmentation Register"
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hexmask.long.byte 0x40 3.--8. 1. "BUFSEG,It Is Used to Indicate the Offset Address for Each Endpoint with the USB SRAM Starting Address The Effective Starting Address of the Endpoint Is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7 for the endpoint SRAM.."
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line.long 0x44 "USB_MXPLD4,Endpoint 4 Maximal Payload Register"
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hexmask.long.word 0x44 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x48 "USB_CFG4,Endpoint 4 Configuration Register"
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bitfld.long 0x48 9. "CSTALL,Clear STALL Response\n" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL -handshake in.."
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bitfld.long 0x48 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token based on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x48 5.--6. "STATE,Endpoint STATE\n" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x48 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake.\n" "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x48 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint"
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line.long 0x4C "USB_CFGP4,Endpoint 4 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x4C 1. "SSTALL,Set STALL\n" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x4C 0. "CLRRDY,Clear Ready\nWhen the MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start users can set this bit to 1 to turn it off and it is.." "0,1"
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line.long 0x50 "USB_BUFSEG5,Endpoint 5 Buffer Segmentation Register"
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hexmask.long.byte 0x50 3.--8. 1. "BUFSEG,It Is Used to Indicate the Offset Address for Each Endpoint with the USB SRAM Starting Address The Effective Starting Address of the Endpoint Is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7 for the endpoint SRAM.."
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line.long 0x54 "USB_MXPLD5,Endpoint 5 Maximal Payload Register"
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hexmask.long.word 0x54 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x58 "USB_CFG5,Endpoint 5 Configuration Register"
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bitfld.long 0x58 9. "CSTALL,Clear STALL Response\n" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL -handshake in.."
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bitfld.long 0x58 7. "DSQ_SYNC,Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token based on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x58 5.--6. "STATE,Endpoint STATE\n" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x58 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake.\n" "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x58 0.--3. 1. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint"
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line.long 0x5C "USB_CFGP5,Endpoint 5 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x5C 1. "SSTALL,Set STALL\n" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x5C 0. "CLRRDY,Clear Ready\nWhen the MXPLD register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start users can set this bit to 1 to turn it off and it is.." "0,1"
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group.long 0x90++0x3
|
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line.long 0x0 "USB_DRVSE0,USB Drive SE0 Control Register"
|
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bitfld.long 0x0 0. "DRVSE0,Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_DP and USB_DM) are being pulled low.\n" "0: None,1: Force USB PHY transceiver to drive SE0"
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tree.end
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tree "WDT (Watchdog Timer)"
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base ad:0x40004000
|
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group.long 0x0++0x7
|
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line.long 0x0 "WTCR,Watchdog Timer Control Register"
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bitfld.long 0x0 31. "DBGACK_WDT,ICE Debug Mode Acknowledge Disable (Write Protected)\nWatchdog Timer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement affects Watchdog..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 8.--10. "WTIS,Watchdog Timer Interval Selection (Write-protection Bits)\n" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 7. "WTE,Watchdog Timer Enable (Write Protected)\nNote: If CWDTEN (Config0[31] watchdog enable) bit is set to 0 this bit is forced as 1 and software cannot change this bit to 0." "0: Watchdog Timer Disabled (This action will reset..,1: Watchdog Timer Enabled"
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bitfld.long 0x0 6. "WTIE,Watchdog Timer Interrupt Enable (Write Protected)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU. \n" "0: Watchdog Timer interrupt Disabled,1: Watchdog Timer interrupt Enabled"
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bitfld.long 0x0 5. "WTWKF,Watchdog Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT\nThis bit is cleared by writing 1 to this bit.." "0: Watchdog Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if WDT.."
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bitfld.long 0x0 4. "WTWKE,Watchdog Timer Wake-up Function Enable Bit (Write Protected)\nIf this bit is set to 1 while WDT interrupt flag (WTCR[3] WTIF) is generated to 1 and WTIE (WTCR[6] WDT interrupt enable) is enabled the WDT time-out interrupt signal will generate a.." "0: Wake-up trigger event Disabled if WDT time-out..,1: Wake-up trigger event Enabled if WDT time-out.."
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bitfld.long 0x0 3. "WTIF,Watchdog Timer Interrupt Flag\nThis bit will set to 1 while WDT counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to this bit." "0: Watchdog Timer time-out interrupt did not occur,1: Watchdog Timer time-out interrupt occurred"
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bitfld.long 0x0 2. "WTRF,Watchdog Timer Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to this bit." "0: Watchdog Timer time-out reset did not occur,1: Watchdog Timer time-out reset occurred"
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bitfld.long 0x0 1. "WTRE,Watchdog Timer Reset Enable (Write Protected)\nSetting this bit will enable the Watchdog Timer time-out reset function If the WDT counter value has not been cleared after the specific WDT reset delay period expires..\n" "0: Watchdog Timer time-out reset function Disabled,1: Watchdog Timer time-out reset function Enabled"
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bitfld.long 0x0 0. "WTR,Reset Watchdog Timer Counter (Write Protected)\nNote: This bit will be automatically cleared by hardware." "0: No effect,1: Reset the internal 18-bit WDT counter"
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line.long 0x4 "WTCRALT,Watchdog Timer Alternative Control Register"
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bitfld.long 0x4 0.--1. "WTRDSEL,Watchdog Timer Reset Delay Select (Write-protection Bits)\nWhen WDT time-out happened software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened. Software can select a suitable value of WDT reset.." "0: Watchdog Timer reset delay period is (1024+2) *..,1: Watchdog Timer reset delay period is (128+2) *..,?,?"
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tree.end
|
|
tree "WWDT (Window Watchdog Timer)"
|
|
base ad:0x40004100
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "WWDTRLD,Window Watchdog Timer Reload Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "WWDTRLD,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and.."
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group.long 0x4++0x7
|
|
line.long 0x0 "WWDTCR,Window Watchdog Timer Control Register"
|
|
bitfld.long 0x0 31. "DBGACK_WWDT,ICE Debug Mode Acknowledge Disable\n" "0: WWDT counter stopped if system is in Debug mode,1: WWDT still counted even system is in Debug mode"
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hexmask.long.byte 0x0 16.--21. 1. "WINCMP,WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If Software writes WWDTRLD when current.."
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hexmask.long.byte 0x0 8.--11. 1. "PERIODSEL,WWDT Prescale Period Select\n"
|
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bitfld.long 0x0 1. "WWDTIE,WWDT Interrupt Enable\nSet this bit to enable the Window Watchdog Timer time-out interrupt function.\n" "0: WWDT time-out interrupt function Disabled if..,1: WWDT time-out interrupt function Enabled if.."
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newline
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bitfld.long 0x0 0. "WWDTEN,WWDT Enable\nSet this bit to enable Window Watchdog Timer counter counting.\n" "0: Window Watchdog Timer counter is stopped,1: Window Watchdog Timer counter is starting counting"
|
|
line.long 0x4 "WWDTSR,Window Watchdog Timer Status Register"
|
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bitfld.long 0x4 1. "WWDTRF,WWDT Reset Flag\nWhen WWDT counter counts down to 0 or writes WWDTRLD during current WWDT counter value being larger than WINCMP chip will be reset and this bit is set to 1. This bit will be cleared to 0 by writing 1 to itself." "0,1"
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bitfld.long 0x4 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nWhen current WWDT counter value matches WWCMP this bit is set to 1. This bit will be cleared by writing 1 to itself." "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "WWDTCVR,Window Watchdog Timer Counter Value Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "WWDTCVAL,WWDT Counter Value\nThis register reflects the current WWDT counter value and is read only."
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tree.end
|
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newline
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AUTOINDENT.OFF
|