147 lines
7.0 KiB
Plaintext
147 lines
7.0 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Cortex-M Micro Trace Buffer (MTB)
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; @Props: Released
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; @Author: PEG, NEJ
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; @Manufacturer: ARM
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; @Doc: DDI0486B_coresight_mtb_m0p_r0p1_trm.pdf
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; coresight_mtb_m23_r0p0_technical_reference_manual_DDI0564C_en.pdf
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; arm_coresight_mtb_m33_trm_100231_0002_05_en.pdf
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; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: permtb.per 18278 2024-08-26 15:58:24Z kwisniewski $
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config 16. 8.
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autoindent.on center tree
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base component.base("MTB",0)
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tree "Micro Trace Buffer"
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sif COMP.AVAILABLE("MTB")
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group.long 0x00++0x03
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line.long 0x00 "POSITION,MTB Position Register"
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hexmask.long 0x00 3.--31. 1. "POINTER,Trace Packet Address Pointer[28:0]"
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bitfld.long 0x00 2. "WRAP,Indicates when the POINTER value has wrapped" "Not wrapped,Wrapped"
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sif ((CORENAME()=="CORTEXM33")||(CORENAME()=="CORTEXM35P")||(CORENAME()=="CORTEXM33F")||(CORENAME()=="CORTEXM35PF"))
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group.long 0x04++0x03
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line.long 0x00 "MASTER,MTB Master Register"
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bitfld.long 0x00 31. "EN,Main Trace Enable" "Disabled,Enabled"
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bitfld.long 0x00 30. "NSEN,Non-secure Trace Enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 9. "HALTREQ,Halt Request" "Not requested,Requested"
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bitfld.long 0x00 8. "RAMPRIV,RAM Privilege" "Unprivileged/Privileged,Only privileged"
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newline
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bitfld.long 0x00 6. "TSTOPEN,Trace Stop Input Enable" "Disabled,Enabled"
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bitfld.long 0x00 5. "TSTARTEN,Trace Start Input Enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 0.--4. "MASK,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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else
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group.long 0x04++0x03
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line.long 0x00 "MASTER,MTB Master Register"
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bitfld.long 0x00 31. "EN,Main Trace Enable" "Disabled,Enabled"
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bitfld.long 0x00 9. "HALTREQ,Halt Request" "Not requested,Requested"
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newline
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bitfld.long 0x00 8. "RAMPRIV,RAM Privilege" "Unprivileged/Privileged,Only privileged"
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bitfld.long 0x00 7. "SFRWPRIV,Special Function Register Write Privilege" "0,1"
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newline
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bitfld.long 0x00 6. "TSTOPEN,Trace Stop Input Enable" "Disabled,Enabled"
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bitfld.long 0x00 5. "TSTARTEN,Trace Start Input Enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 0.--4. "MASK,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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endif
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group.long 0x08++0x03
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line.long 0x00 "FLOW,MTB Flow Register"
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hexmask.long 0x00 3.--31. 1. "WATERMARK,WATERMARK[28:0]"
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bitfld.long 0x00 1. "AUTOHALT,Automatic Trace Halt" "Not requested,Requested"
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newline
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bitfld.long 0x00 0. "AUTOSTOP,Watermark auto stop" "Disabled,Enabled"
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sif ((CORENAME()=="CORTEXM33")||(CORENAME()=="CORTEXM35P")||(CORENAME()=="CORTEXM33F")||(CORENAME()=="CORTEXM35PF"))
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rgroup.long 0x0C++0x03
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line.long 0x00 "BASE,MTB Base Register"
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hexmask.long 0x00 5.--31. 0x20 "BASEADDR,Value of the MTBSRAMBASE[31:5] signal"
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else
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rgroup.long 0x0C++0x03
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line.long 0x00 "BASE,MTB Base Register"
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hexmask.long 0x00 0.--31. 1. "BASEADDR,Value of the MTBSRAMBASE signal"
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endif
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if ((CORENAME()=="CORTEXM33")||(CORENAME()=="CORTEXM35P")||(CORENAME()=="CORTEXM33F")||(CORENAME()=="CORTEXM35PF")||(CORENAME()=="CORTEXM23"))
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rgroup.long 0x10++0x03
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line.long 0x00 "TSTART,MTB TSTART Register"
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bitfld.long 0x00 0. "CMPMATCH[0],The behavior of CMPMATCH after receiving the event on Comparator 0" "Ignored,Triggered"
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bitfld.long 0x00 1. "CMPMATCH[1],The behavior of CMPMATCH after receiving the event on Comparator 1" "Ignored,Triggered"
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newline
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bitfld.long 0x00 2. "CMPMATCH[2],The behavior of CMPMATCH after receiving the event on Comparator 2" "Ignored,Triggered"
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bitfld.long 0x00 3. "CMPMATCH[3],The behavior of CMPMATCH after receiving the event on Comparator 3" "Ignored,Triggered"
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rgroup.long 0x14++0x03
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line.long 0x00 "TSTOP,MTB TSTOP Register"
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bitfld.long 0x00 0. "CMPMATCH[0],The behavior of CMPMATCH after receiving the event on Comparator 0" "Ignored,Triggered"
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bitfld.long 0x00 1. "CMPMATCH[1],The behavior of CMPMATCH after receiving the event on Comparator 1" "Ignored,Triggered"
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newline
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bitfld.long 0x00 2. "CMPMATCH[2],The behavior of CMPMATCH after receiving the event on Comparator 2" "Ignored,Triggered"
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bitfld.long 0x00 3. "CMPMATCH[3],The behavior of CMPMATCH after receiving the event on Comparator 3" "Ignored,Triggered"
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endif
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sif ((CORENAME()=="CORTEXM33")||(CORENAME()=="CORTEXM35P")||(CORENAME()=="CORTEXM33F")||(CORENAME()=="CORTEXM35PF"))
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if (((per.l(COMPonent.base("MTB",-1)+0x18))&0x01)==0x00)
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rgroup.long 0x18++0x03
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line.long 0x00 "SECURE,MTB Secure Register"
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hexmask.long 0x00 5.--31. 1. "THRESHOLD,Threshold field"
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bitfld.long 0x00 1. "NS,SRAM Non-secure" "Secure,Non-secure"
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bitfld.long 0x00 0. "THRSEN,Threshold enable" "Disabled,Enabled"
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else
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rgroup.long 0x18++0x03
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line.long 0x00 "SECURE,MTB Secure Register"
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hexmask.long 0x00 5.--31. 1. "THRESHOLD,Threshold field"
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bitfld.long 0x00 1. "NS,SRAM Non-secure (lower addresses/higher addresses)" "Non-secure/Secure,Secure/Non-secure"
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bitfld.long 0x00 0. "THRSEN,Threshold enable" "Disabled,Enabled"
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endif
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endif
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width 15.
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tree "CoreSight Management Registers"
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rgroup.long 0xF00++0x03
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line.long 0x00 "MODECTRL,Integration Mode Control Register"
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hexmask.long 0x00 0.--31. 1. "MODECTRL,MODECTRL"
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rgroup.long 0xFA0++0x03
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line.long 0x00 "TAGSET,Claim TAG Set Register"
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hexmask.long 0x00 0.--31. 1. "TAGSET,TAGSET"
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rgroup.long 0xFA4++0x03
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line.long 0x00 "TAGCLEAR,Claim TAG Clear Register"
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hexmask.long 0x00 0.--31. 1. "TAGCLEAR,TAGCLEAR"
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rgroup.long 0xFB0++0x03
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line.long 0x00 "LOCKACCESS,Lock Access Register"
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hexmask.long 0x00 0.--31. 1. "LOCKACCESS,Hardwired to 0x0000_0000"
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rgroup.long 0xFB4++0x03
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line.long 0x00 "LOCKSTAT,Lock Status Register"
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hexmask.long 0x00 0.--31. 1. "LOCKSTAT,LOCKSTAT"
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rgroup.long 0xFB8++0x03
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line.long 0x00 "AUTHSTAT,Authentication Status Register"
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bitfld.long 0x00 3. "NSNID[1],Non-secure noninvasive debug bit 1" "0,1"
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bitfld.long 0x00 2. "NSNID[0],Non-secure noninvasive debug (NIDEN | DBGEN) bit 0" "FALSE,TRUE"
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newline
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bitfld.long 0x00 1. "NSID[1],Non-secure invasive debug bit 1" "0,1"
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bitfld.long 0x00 0. "NSID[0],Non-secure invasive debug (DBGEN) bit 0" "FALSE,TRUE"
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rgroup.long 0xFBC++0x03
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line.long 0x00 "DEVICEARCH,Device Architecture Register"
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hexmask.long 0x00 0.--31. 1. "DEVICEARCH,DEVICEARCH"
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rgroup.long 0xFC8++0x03
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line.long 0x00 "DEVICECFG,Device Configuration Register"
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hexmask.long 0x00 0.--31. 1. "DEVICECFG,DEVICECFG"
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rgroup.long 0xFCC++0x03
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line.long 0x00 "DEVICETYPID,Device Type Identifier Register"
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hexmask.long 0x00 0.--31. 1. "DEVICETYPID,DEVICETYPID"
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repeat 8. (strings "4" "5" "6" "7" "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C)
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rgroup.long ($2+0xFD0)++0x03
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line.long 0x00 "PERIPHID$1,Peripheral ID Register"
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hexmask.long 0x00 0.--31. 1. "PERIPHID,PERIPHID"
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repeat.end
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repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
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rgroup.long ($2+0xFF0)++0x03
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line.long 0x00 "COMPID$1,Component ID Register"
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hexmask.long 0x00 0.--31. 1. "COMPID,Component ID"
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repeat.end
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tree.end
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else
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newline
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textline "Micro Trace Buffer not available"
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textline "Either MTB component base address is not specified or this core does not support MTB"
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newline
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endif
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tree.end
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textline ""
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