7335 lines
888 KiB
Plaintext
7335 lines
888 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: M2003 On-Chip Peripherals
|
|
; @Props: Released
|
|
; @Author: NEJ
|
|
; @Changelog: 2024-07-26 NEJ
|
|
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
|
|
; @Doc: Generated (TRACE32, build: 171280.), based on:
|
|
; M2003.svd (Ver. 1.0)
|
|
; @Core: Cortex-M23
|
|
; @Chip: M2003FC1AE, M2003XC1AE
|
|
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: perm2003.per 18191 2024-08-02 11:36:27Z kwisniewski $
|
|
|
|
AUTOINDENT.ON CENTER TREE
|
|
ENUMDELIMITER ","
|
|
base ad:0x0
|
|
tree.close "Core Registers (Cortex-M23)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 29. " EXTEXCLALL ,LDREX and STREX instructions use the Global Exclusive Monitor" "Only on Shared regions,Always"
|
|
newline
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
|
|
rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
|
|
bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
|
|
newline
|
|
bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
|
|
line.long 0x04 "SYST_CVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " CURRENT ,Current counter value"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPUID Base Register"
|
|
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/o Main Extension,Reserved,Reserved,Reserved"
|
|
newline
|
|
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xD20=Cortex-M23"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
|
|
group.long 0xD04++0x13
|
|
line.long 0x00 "ICSR,Interrupt Control and State Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
|
|
rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
|
|
newline
|
|
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
|
|
rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
|
|
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
|
|
line.long 0x04 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
|
|
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
|
|
rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
|
|
bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
|
|
newline
|
|
bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
|
|
bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
|
|
line.long 0x0C "SCR,System Control Register"
|
|
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
|
|
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
newline
|
|
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
line.long 0x10 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
|
|
bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
|
|
bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
|
|
group.long 0xD1C++0x0B
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
|
|
line.long 0x04 "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
|
|
line.long 0x08 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x08 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
|
|
bitfld.long 0x08 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
|
|
bitfld.long 0x08 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
|
|
bitfld.long 0x08 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
|
|
bitfld.long 0x08 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x08 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
|
|
bitfld.long 0x08 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
|
|
bitfld.long 0x08 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x08 8. " MONITORACT ,Monitor exception status" "Not active,Active"
|
|
bitfld.long 0x08 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
|
|
bitfld.long 0x08 5. " NMIACT ,NMI exception status" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x08 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
|
|
bitfld.long 0x08 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
|
|
bitfld.long 0x08 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x08 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
|
|
bitfld.long 0x08 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
|
|
tree "Memory System"
|
|
width 10.
|
|
rgroup.long 0xD78++0x0B
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
|
|
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
|
|
line.long 0x04 "CTR,Cache Type Register"
|
|
bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
|
|
bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
|
|
hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
|
|
hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
|
|
group.long 0xD84++0x03
|
|
line.long 0x00 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
|
|
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
|
|
wgroup.long 0xF50++0x03
|
|
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
|
|
wgroup.long 0xF58++0x23
|
|
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
|
|
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
|
|
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
|
|
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
|
|
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
|
|
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
|
|
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
|
|
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
|
|
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
|
|
tree.end
|
|
width 11.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DPIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DPIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DPIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DPIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DCIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DCIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "DCIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,,,,4,,,,8,,,,,,,,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Memory attribute encoding for MPU regions with an AttrIndex of 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Memory attribute encoding for MPU regions with an AttrIndex of 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Memory attribute encoding for MPU regions with an AttrIndex of 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Memory attribute encoding for MPU regions with an AttrIndex of 0"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ATTR7 ,Memory attribute encoding for MPU regions with an AttrIndex of 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " ATTR6 ,Memory attribute encoding for MPU regions with an AttrIndex of 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " ATTR5 ,Memory attribute encoding for MPU regions with an AttrIndex of 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ATTR4 ,Memory attribute encoding for MPU regions with an AttrIndex of 4"
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,,,,4,,,,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hgroup.long 0xDDC++0x03 "Region 8 (not accessible)"
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RBAR8,SAU Region Base Address Register 8"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RLAR8,SAU Region Limit Address Register 8"
|
|
hgroup.long 0xDDC++0x03 "Region 9 (not accessible)"
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RBAR9,SAU Region Base Address Register 9"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RLAR9,SAU Region Limit Address Register 9"
|
|
hgroup.long 0xDDC++0x03 "Region 10 (not accessible)"
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RBAR10,SAU Region Base Address Register 10"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RLAR10,SAU Region Limit Address Register 10"
|
|
hgroup.long 0xDDC++0x03 "Region 11 (not accessible)"
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RBAR11,SAU Region Base Address Register 11"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RLAR11,SAU Region Limit Address Register 11"
|
|
hgroup.long 0xDDC++0x03 "Region 12 (not accessible)"
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RBAR12,SAU Region Base Address Register 12"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RLAR12,SAU Region Limit Address Register 12"
|
|
hgroup.long 0xDDC++0x03 "Region 13 (not accessible)"
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RBAR13,SAU Region Base Address Register 13"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RLAR13,SAU Region Limit Address Register 13"
|
|
hgroup.long 0xDDC++0x03 "Region 14 (not accessible)"
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RBAR14,SAU Region Base Address Register 14"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RLAR14,SAU Region Limit Address Register 14"
|
|
hgroup.long 0xDDC++0x03 "Region 15 (not accessible)"
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RBAR15,SAU Region Base Address Register 15"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RLAR15,SAU Region Limit Address Register 15"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-239,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 24.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 24.
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 11.
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
width 13.
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x0F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x0F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
width 13.
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
textline " "
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
rbitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)==0x1)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x4)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xC)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xF)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
endif
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)==0x1)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x4)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xC)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xF)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
endif
|
|
group.long (0x70+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)==0x1)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x4)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xC)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xF)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)==0x1)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x4)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xC)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xF)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
endif
|
|
group.long (0x90+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)==0x1)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x4)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xC)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xF)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
endif
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION8,DWT Function Register 8"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)==0x1)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x4)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xC)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xF)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
endif
|
|
group.long (0xB0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION9,DWT Function Register 9"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)==0x1)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x4)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xC)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xF)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
endif
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION10,DWT Function Register 10"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)==0x1)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x4)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xC)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xF)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
endif
|
|
group.long (0xD0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION11,DWT Function Register 11"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)==0x1)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x4)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xC)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xF)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
endif
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION12,DWT Function Register 12"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)==0x1)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x4)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xC)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xF)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
endif
|
|
group.long (0xF0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION13,DWT Function Register 13"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x4)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xC)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xF)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
endif
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION14,DWT Function Register 14"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x4)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xC)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xF)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
endif
|
|
group.long (0x110+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION15,DWT Function Register 15"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x40043000
|
|
rgroup.long 0x0++0x17
|
|
line.long 0x0 "ADC_ADDR0,ADC Data Register 0"
|
|
bitfld.long 0x0 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x0 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x4 "ADC_ADDR1,ADC Data Register 1"
|
|
bitfld.long 0x4 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x4 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x8 "ADC_ADDR2,ADC Data Register 2"
|
|
bitfld.long 0x8 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x8 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
|
|
hexmask.long.word 0x8 0.--11. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0xC "ADC_ADDR3,ADC Data Register 3"
|
|
bitfld.long 0xC 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0xC 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
|
|
hexmask.long.word 0xC 0.--11. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x10 "ADC_ADDR4,ADC Data Register 4"
|
|
bitfld.long 0x10 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x10 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
|
|
hexmask.long.word 0x10 0.--11. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x14 "ADC_ADDR5,ADC Data Register 5"
|
|
bitfld.long 0x14 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x14 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "ADC_ADDR11,ADC Data Register 11"
|
|
bitfld.long 0x0 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x0 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
line.long 0x4 "ADC_ADDR12,ADC Data Register 12"
|
|
bitfld.long 0x4 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x4 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
rgroup.long 0x74++0x3
|
|
line.long 0x0 "ADC_ADDR29,ADC Data Register 29"
|
|
bitfld.long 0x0 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x0 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC."
|
|
group.long 0x80++0x13
|
|
line.long 0x0 "ADC_ADCR,ADC Control Register"
|
|
bitfld.long 0x0 12. "RESET,ADC RESET (Write Protect)\nIf user writes this bit the ADC analog macro will reset. but registers in ADC controller will keep.\nNote: This bit is cleared by hardware." "0,1"
|
|
bitfld.long 0x0 11. "ADST,A/D Conversion Start \nADST bit can be set to 1 from four sources: software external pin ADC0_ST PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode and Single-cycle Scan mode. In.." "0: Conversion stops and A/D converter enters idle..,1: When ADST becomes from 1 to 0"
|
|
newline
|
|
bitfld.long 0x0 8. "TRGEN,External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external ADC0_ST pin PWM trigger and Timer trigger. If external trigger is enabled the ADST bit can be set to 1 by the selected hardware trigger source.\nNote: The.." "0: External trigger Disabled,1: External trigger Enabled"
|
|
bitfld.long 0x0 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin ADC0_ST trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger." "0: Low level,1: High level,?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "TRGS,Hardware Trigger Source\nNote: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits." "0: A/D conversion is started by external ADC0_ST pin,1: Timer0 ~ Timer3 overflow pulse trigger,?,?"
|
|
bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode Control\nNote 1: When changing the operation mode software should clear ADST bit first.\nNote 2: In Burst mode the A/D result data is always at ADC Data Register 0." "0: Single conversion,1: When changing the operation mode,2: In Burst mode,?"
|
|
newline
|
|
bitfld.long 0x0 1. "ADIE,A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
|
|
bitfld.long 0x0 0. "ADEN,A/D Converter Enable Bit\nNote: Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption." "0: A/D converter Disabled,1: A/D converter Enabled"
|
|
line.long 0x4 "ADC_ADCHER,ADC Channel Enable Register"
|
|
hexmask.long 0x4 0.--31. 1. "CHEN,Analog Input Channel Enable Control\nSet ADCHER[15:0] bits to enable the corresponding analog input channel 15 ~ 0. \nADCHER[29] ADCHER[12:11] and ADCCHER[5:0] are designed.\nOther bits are reserved.\nBesides setting the ADCHER[29] bit will enable.."
|
|
line.long 0x8 "ADC_ADCMPR0,ADC Compare Register 0"
|
|
hexmask.long.word 0x8 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format)."
|
|
bitfld.long 0x8 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register." "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.."
|
|
hexmask.long.byte 0x8 3.--7. 1. "CMPCH,Compare Channel Selection"
|
|
newline
|
|
bitfld.long 0x8 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
|
|
bitfld.long 0x8 1. "CMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE bit is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x8 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register." "0: Compare function Disabled,1: Compare function Enabled"
|
|
line.long 0xC "ADC_ADCMPR1,ADC Compare Register 1"
|
|
hexmask.long.word 0xC 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format)."
|
|
bitfld.long 0xC 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register." "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1) the.."
|
|
hexmask.long.byte 0xC 3.--7. 1. "CMPCH,Compare Channel Selection"
|
|
newline
|
|
bitfld.long 0xC 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1) the CMPFx bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
|
|
bitfld.long 0xC 1. "CMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE bit is set to 1 a compare interrupt request is generated." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register." "0: Compare function Disabled,1: Compare function Enabled"
|
|
line.long 0x10 "ADC_ADSR0,ADC Status Register0"
|
|
hexmask.long.byte 0x10 27.--31. 1. "CHANNEL,Current Conversion Channel (Read Only)"
|
|
rbitfld.long 0x10 16. "OVERRUNF,Overrun Flag (Read Only)\nIf any one of OVERRUN (ADDRx[16]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and the FIFO is overrun this flag will be set to 1." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 8. "VALIDF,Data Valid Flag (Read Only)\nIf any one of VALID (ADDRx[17]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and any conversion result is valid this flag will be set to 1." "0,1"
|
|
rbitfld.long 0x10 7. "BUSY,BUSY/IDLE (Read Only)\nThis bit is a mirror of ADST bit in ADCR register." "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
|
|
newline
|
|
bitfld.long 0x10 3. "OVF,Over Voltage Flag\nWhen the VDD voltage is over 7V during ADC is enabled this bit is set to 1; it is cleared by writing 1 to it" "0: VDD voltage is normal,1: .VDD voltage has been over 7V during ADC is.."
|
|
bitfld.long 0x10 2. "CMPF1,Compare Flag 1\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register this bit is set to 1; it is cleared by writing 1 to it" "0: Conversion result in ADDR does not meet ADCMPR1..,1: Conversion result in ADDR meets ADCMPR1 setting"
|
|
newline
|
|
bitfld.long 0x10 1. "CMPF0,Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it." "0: Conversion result in ADDR does not meet ADCMPR0..,1: Conversion result in ADDR meets ADCMPR0 setting"
|
|
bitfld.long 0x10 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.\nThe ADF bit is set to 1 at the following three conditions:\nWhen A/D conversion ends in Single mode.\nWhen A/D conversion ends.." "0,1"
|
|
rgroup.long 0x94++0x7
|
|
line.long 0x0 "ADC_ADSR1,ADC Status Register1"
|
|
hexmask.long 0x0 0.--31. 1. "VALID,Data Valid Flag (Read Only)\nVALID[29 12 11 5:0] are the mirror of the VALID bits in ADDR29[17] ADDR12[17] ADDR11[17] ADDR5[17]~ ADDR0[17]. The other bits are reserved.\nNote: When ADC is in burst mode and any conversion result is valid .."
|
|
line.long 0x4 "ADC_ADSR2,ADC Status Register2"
|
|
hexmask.long 0x4 0.--31. 1. "OVERRUN,Overrun Flag (Read Only)\nOVERRUN[29 12 11 5:0] are the mirror of the OVERRUN bit in ADDR29[16] ADDR12[16] ADDR11[16] ADDR5[16] ~ ADDR0[16]. The other bits are reserved. \nNote: When ADC is in burst mode and the FIFO is overrun OVERRUN[29 .."
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "ADC_ESMPCTL,ADC Extend Sample Time Control Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "EXTSMPT,ADC Sampling Time Extend \nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
|
|
tree.end
|
|
tree "CLK (Clock Controller)"
|
|
base ad:0x40000200
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CLK_PWRCTL,System Power-down Control Register"
|
|
bitfld.long 0x0 7. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode this.." "0: Chip operating normally or chip in idle mode..,1: Chip waits CPU sleep command WFI and then enters.."
|
|
bitfld.long 0x0 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' it indicates that resume from Power-down mode' \nThe flag is set if the EINT0~5 GPIO UART0~1 BOD WDT TIMER I2C0 USCI0 and CLKD wake-up occurred.\nNote 1: Write 1.." "?,1: Write 1 to clear the bit to 0"
|
|
newline
|
|
bitfld.long 0x0 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote 1: The interrupt will occur when both PDWKIF and PDWKIEN are high after resume from power-down mode.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up interrupt Disabled,1: The interrupt will occur when both PDWKIF and.."
|
|
bitfld.long 0x0 3. "LIRCEN,LIRC Enable Bit (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: LIRC cannot be disabled and LIRCEN will read as 1 if HCLK clock source is selected from LIRC.\nNote 3: If CWDTEN(CONFIG0[31 4:3]) is.." "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: This bit is write protected"
|
|
newline
|
|
bitfld.long 0x0 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: HIRC cannot be disabled and HIRCEN will read as 1 if HCLK clock source is selected from HIRC (clock source from HIRC)." "0: 24 MHz internal high speed RC oscillator (HIRC)..,1: This bit is write protected"
|
|
line.long 0x4 "CLK_AHBCLK,AHB Devices Clock Enable Register"
|
|
bitfld.long 0x4 21. "GPFCKEN,GPIOF Clock Enable Bit" "0: GPIOF port clock Disabled,1: GPIOF port clock Enabled"
|
|
bitfld.long 0x4 20. "GPECKEN,GPIOE Clock Enable Bit" "0: GPIOE port clock Disabled,1: GPIOE port clock Enabled"
|
|
newline
|
|
bitfld.long 0x4 18. "GPCCKEN,GPIOC Clock Enable Bit" "0: GPIOC port clock Disabled,1: GPIOC port clock Enabled"
|
|
bitfld.long 0x4 17. "GPBCKEN,GPIOB Clock Enable Bit" "0: GPIOB port clock Disabled,1: GPIOB port clock Enabled"
|
|
newline
|
|
bitfld.long 0x4 8. "SRAM0CKEN,SRAM Bank0 Controller Clock Enable Bit" "0: SRAM bank0 clock Disabled,1: SRAM bank0 clock Enabled"
|
|
bitfld.long 0x4 3. "STCKEN,System Tick Clock Enable Bit" "0: External System tick clock Disabled,1: External System tick clock Enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
|
|
bitfld.long 0x4 0. "FMCIDLE,Flash Memory Controller Clock Enable Bit in IDLE Mode" "0: FMC clock Disabled when chip is under IDLE mode,1: FMC clock Enabled when chip is under IDLE mode"
|
|
line.long 0x8 "CLK_APBCLK0,APB Devices Clock Enable Register 0"
|
|
bitfld.long 0x8 28. "ADCCKEN,Analog-digital-converter Clock Enable Bit" "0: ADC clock Disabled,1: ADC clock Enabled"
|
|
bitfld.long 0x8 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
|
|
newline
|
|
bitfld.long 0x8 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
|
|
bitfld.long 0x8 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
|
|
newline
|
|
bitfld.long 0x8 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO clock Disabled,1: CLKO clock Enabled"
|
|
bitfld.long 0x8 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
|
|
bitfld.long 0x8 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
|
|
newline
|
|
bitfld.long 0x8 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
|
|
bitfld.long 0x8 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Watchdog timer and Windows watchdog timer clock..,1: Watchdog timer and Windows watchdog timer clock.."
|
|
line.long 0xC "CLK_APBCLK1,APB Devices Clock Enable Register 1"
|
|
bitfld.long 0xC 26. "ECAP0CKEN,ECAP0 Clock Enable Bit" "0: ECAP0 clock Disabled,1: ECAP0 clock Enabled"
|
|
bitfld.long 0xC 16. "PWM0CKEN,PWM0 Clock Enable Bit" "0: PWM0 clock Disabled,1: PWM0 clock Enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "USCI0CKEN,USCI0 Clock Enable Bit" "0: USCI0 clock Disabled,1: USCI0 clock Enabled"
|
|
line.long 0x10 "CLK_CLKSEL0,Clock Source Select Register 0"
|
|
bitfld.long 0x10 3.--5. "STCLKSEL,SysTick Clock Source Selection (Write Protect)\nNote 2: These bits are write protected. Refer to the SYS_REGLCTL register." "?,?,2: These bits are write protected,?,?,?,?,?"
|
|
bitfld.long 0x10 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CLK_CLKSEL1,Clock Source Select Register 1"
|
|
bitfld.long 0x14 30.--31. "WWDTSEL,Window Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0,1,2,3"
|
|
bitfld.long 0x14 28.--29. "CLKOSEL,Clock Output Clock Source Selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0,1,2,3"
|
|
line.long 0x18 "CLK_CLKSEL2,Clock Source Select Register 2"
|
|
bitfld.long 0x18 24.--25. "ADCSEL,ADC Clock Source Selection" "0,1,2,3"
|
|
bitfld.long 0x18 20.--22. "UART1SEL,UART1 Clock Source Selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 16.--18. "UART0SEL,UART0 Clock Source Selection" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x18 0. "PWM0SEL,PWM0 Clock Source Selection (Read Only)\nThe peripheral clock source of PWM0 is defined by PWM0SEL." "0: Reserved.,1: Clock source from PCLK0"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CLK_CLKDIV0,Clock Divider Number Register 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source"
|
|
hexmask.long.byte 0x0 12.--15. 1. "UART1DIV,UART1 Clock Divide Number From UART1 Clock Source"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "UART0DIV,UART0 Clock Divide Number From UART0 Clock Source"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CLK_PCLKDIV,APB Clock Divider Register"
|
|
bitfld.long 0x0 8.--10. "APB2DIV,APB2 Clock Divider\nAPB2 clock can be divided from HCLK." "0: PCLK2 frequency is HCLK,1: PCLK2 frequency is 1/2 HCLK,?,?,?,?,?,?"
|
|
bitfld.long 0x0 4.--6. "APB1DIV,APB1 Clock Divider\nAPB1 clock can be divided from HCLK." "0: PCLK1 frequency is HCLK,1: PCLK1 frequency is 1/2 HCLK,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "APB0DIV,APB0 Clock Divider\nAPB0 clock can be divided from HCLK." "0: PCLK0 frequency is HCLK,1: PCLK0 frequency is 1/2 HCLK,?,?,?,?,?,?"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "CLK_STATUS,Clock Status Monitor Register"
|
|
bitfld.long 0x0 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1.\nNote: This bit.." "0: Clock switching success,1: Clock switching failure"
|
|
bitfld.long 0x0 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: 24 MHz internal high speed RC oscillator (HIRC)..,1: 24 MHz internal high speed RC oscillator (HIRC).."
|
|
newline
|
|
bitfld.long 0x0 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "CLK_CLKOCTL,Clock Output Control Register"
|
|
bitfld.long 0x0 6. "CLK1HZEN,CLK1HZEN\nNote: This bits has to set to 0." "0,1"
|
|
bitfld.long 0x0 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
|
|
newline
|
|
bitfld.long 0x0 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]."
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "CLK_PMUCTL,Power Manager Control Register"
|
|
bitfld.long 0x0 28.--29. "WKPINEN3," "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "WKPINEN2,Wake-up Pin 3 Enable Bits (Write Protect)\nThis is control register for GPB.12 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Wake-up pin disable at Power-down mode,1: Wake-up pin rising edge enabled at Power-down mode,?,?"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "WKPINEN1,Wake-up Pin 1 Enable Bits (Write Protect)\nThis is control register for GPB.0 to wake-up pin.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Wake-up pin disable at Power-down mode,1: Wake-up pin rising edge enabled at Power-down mode,?,?"
|
|
bitfld.long 0x0 9.--11. "WKTMRIS,Wake-up Timer Time-out Interval Select Bits (Write Protect)\nThese bits control wake-up timer time-out interval when chip under Power-down mode.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Time-out interval is 128 LIRC clocks (12.8ms),1: Time-out interval is 256 LIRC clocks (25.6ms),?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8. "WKTMREN,Wake-up Timer Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Wake-up timer disable at Power-down mode,1: Wake-up timer enabled at Power-down mode"
|
|
rbitfld.long 0x0 7. "WRBUSY,Write Busy Flag (Read Only)\nIf CLK_PMUCTL be written this bit be asserted automatic by hardware and be de-asserted when write procedure finish." "0: CLK_PMUCTL write ready,1: CLK_PMUCTL write ignore"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PDMSEL,Power-down Mode Selection (Write Protect)\nThese bits control chip power-down mode grade selection when CPU executes WFI/WFE instruction.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode is selected (PD),1: Reserved.,?,?,?,?,?,?"
|
|
line.long 0x4 "CLK_PMUSTS,Power Manager Status Register"
|
|
bitfld.long 0x4 31. "CLRWK,Clear Wake-up Flag\nNote: This bit is auto cleared by hardware." "0: No clear,1: Clear all of wake-up flag"
|
|
rbitfld.long 0x4 13. "BODWK,BOD Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Power-down mode was requested with a BOD happened.." "0,1"
|
|
newline
|
|
rbitfld.long 0x4 12. "LVRWK,LVR Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Power-down mode was requested with a LVR happened." "0,1"
|
|
rbitfld.long 0x4 10. "GPCWK,GPC Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Power-down mode was requested by a transition of selected one GPC group pins." "0,1"
|
|
newline
|
|
rbitfld.long 0x4 9. "GPBWK,GPB Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Power-down mode was requested by a transition of selected one GPB group pins." "0,1"
|
|
rbitfld.long 0x4 5. "PINWK3,Pin 3 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Power-down mode was requested by a transition of the Wake-up pin (GPB.12)." "0,1"
|
|
newline
|
|
rbitfld.long 0x4 4. "PINWK2,Pin 2 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Power-down mode was requested by a transition of the Wake-up pin (GPB.2)." "0,1"
|
|
rbitfld.long 0x4 3. "PINWK1,Pin 1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Power-down mode was requested by a transition of the Wake-up pin (GPB.0)." "0,1"
|
|
newline
|
|
rbitfld.long 0x4 1. "TMRWK,Timer Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Power-down mode was requested by wakeup timer time-out." "0,1"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "CLK_SWKDBCTL,Power-down Wake-up De-bounce Control Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SWKDBCLKSEL,Power-down Wake-up De-bounce Sampling Cycle Selection\nNote: De-bounce counter clock source is the 10kHz internal low speed RC oscillator (LIRC)."
|
|
group.long 0xA4++0x7
|
|
line.long 0x0 "CLK_PBSWKCTL,GPB Power-down Wake-up Control Register"
|
|
bitfld.long 0x0 8. "DBEN,GPB Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen.." "0: power-down wake-up pin De-bounce function Disabled,1: power-down wake-up pin De-bounce function Enabled"
|
|
hexmask.long.byte 0x0 4.--7. 1. "WKPSEL,GPB Standby Power-down Wake-up Pin Select\nOthers are reserved."
|
|
newline
|
|
bitfld.long 0x0 2. "PFWKEN,Pin Falling Edge Wake-up Enable Bit" "0: GPB group pin falling edge wake-up function..,1: GPB group pin falling edge wake-up function.."
|
|
bitfld.long 0x0 1. "PRWKEN,Pin Rising Edge Wake-up Enable Bit" "0: GPB group pin rising edge wake-up function..,1: GPB group pin rising edge wake-up function Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "WKEN,Power-down Pin Wake-up Enable Bit" "0: GPB group pin wake-up function Disabled,1: GPB group pin wake-up function Enabled"
|
|
line.long 0x4 "CLK_PCSWKCTL,GPC Power-down Wake-up Control Register"
|
|
bitfld.long 0x4 8. "DBEN,GPC Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen.." "0: power-down wake-up pin De-bounce function Disabled,1: power-down wake-up pin De-bounce function Enabled"
|
|
hexmask.long.byte 0x4 4.--7. 1. "WKPSEL,GPC Power-down Wake-up Pin Select\nOthers are reserved"
|
|
newline
|
|
bitfld.long 0x4 2. "PFWKEN,Pin Falling Edge Wake-up Enable Bit" "0: GPC group pin falling edge wake-up function..,1: GPC group pin falling edge wake-up function.."
|
|
bitfld.long 0x4 1. "PRWKEN,Pin Rising Edge Wake-up Enable Bit" "0: GPC group pin rising edge wake-up function..,1: GPC group pin rising edge wake-up function Enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "WKEN,Standby Power-down Pin Wake-up Enable Bit" "0: GPC group pin wake-up function Disabled,1: GPC group pin wake-up function Enabled"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "CLK_IOPDCTL,GPIO Power-down Control Register"
|
|
bitfld.long 0x0 0. "IOHR,GPIO Hold Release\nWhen GPIO enter power-down mode all I/O status are hold to keep normal operating status. After chip was waked up from power-down mode the I/O are still keep hold status until user set this bit to release I/O hold status.\nNote:.." "0,1"
|
|
tree.end
|
|
tree "ECAP (Enhanced Input Capture Timer)"
|
|
base ad:0x400B4000
|
|
group.long 0x0++0x2B
|
|
line.long 0x0 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider."
|
|
line.long 0x4 "ECAP_HLD0,Input Capture Hold Register 0"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
|
|
line.long 0x8 "ECAP_HLD1,Input Capture Hold Register 1"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
|
|
line.long 0xC "ECAP_HLD2,Input Capture Hold Register 2"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx.."
|
|
line.long 0x10 "ECAP_CNTCMP,Input Capture Compare Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register"
|
|
line.long 0x14 "ECAP_CTL0,Input Capture Control Register 0"
|
|
bitfld.long 0x14 29. "CAPEN,Input Capture Timer/Counter Enable Bit" "0: Input Capture function Disabled,1: Input Capture function Enabled"
|
|
bitfld.long 0x14 28. "CMPEN,Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP if ECAP_CNT value reaches ECAP_CNTCMP the flag CAPCMPF will be set." "0: The compare function Disabled,1: The compare function Enabled"
|
|
newline
|
|
bitfld.long 0x14 25. "CMPCLREN,Input Capture Counter Cleared by Compare-match Control" "0: Compare-match event (CAPCMPF) can clear capture..,1: Compare-match event (CAPCMPF) can clear capture.."
|
|
bitfld.long 0x14 24. "CNTEN,Input Capture Counter Start Counting Control\nSetting this bit to 1 the capture counter (ECAP_CNT) starts up-counting the clock." "0: ECAP_CNT stops counting,1: ECAP_CNT starts up-counting"
|
|
newline
|
|
bitfld.long 0x14 21. "CMPIEN,CAPCMPF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPCMPF can trigger Input Capture..,1: The flag CAPCMPF can trigger Input Capture.."
|
|
bitfld.long 0x14 20. "OVIEN,CAPOVF Trigger Input Capture Interrupt Enable Bit" "0: The flag CAPOVF can trigger Input Capture..,1: The flag CAPOVF can trigger Input Capture.."
|
|
newline
|
|
bitfld.long 0x14 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Control" "0: The flag CAPTF2 can trigger Input Capture..,1: The flag CAPTF2 can trigger Input Capture.."
|
|
bitfld.long 0x14 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Control" "0: The flag CAPTF1 can trigger Input Capture..,1: The flag CAPTF1 can trigger Input Capture.."
|
|
newline
|
|
bitfld.long 0x14 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Control" "0: The flag CAPTF0 can trigger Input Capture..,1: The flag CAPTF0 can trigger Input Capture.."
|
|
bitfld.long 0x14 12.--13. "CAPSEL2,CAP2 Input Source Selection" "0: CAP2 input is from port pin ICAP2,1: Reserved.,?,?"
|
|
newline
|
|
bitfld.long 0x14 10.--11. "CAPSEL1,CAP1 Input Source Selection" "0: CAP1 input is from port pin ICAP1,1: Reserved.,?,?"
|
|
bitfld.long 0x14 8.--9. "CAPSEL0,CAP0 Input Source Selection" "0: CAP0 input is from port pin ICAP0,1: Reserved.,?,?"
|
|
newline
|
|
bitfld.long 0x14 6. "IC2EN,Port Pin IC2 Input to Input Capture Unit Enable Control" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
|
|
bitfld.long 0x14 5. "IC1EN,Port Pin IC1 Input to Input Capture Unit Enable Control" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
|
|
newline
|
|
bitfld.long 0x14 4. "IC0EN,Port Pin IC0 Input to Input Capture Unit Enable Control" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
|
|
bitfld.long 0x14 3. "CAPNFDIS,Input Capture Noise Filter Disable Control" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled (Bypass)"
|
|
newline
|
|
bitfld.long 0x14 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: CAP_CLK,1: CAP_CLK/2,?,?,?,?,?,?"
|
|
line.long 0x18 "ECAP_CTL1,Input Capture Control Register 1"
|
|
bitfld.long 0x18 22. "CAP2CLREN,Capture Counter Cleared by Capture Event2 Control" "0: Event CAPTE2 can clear capture counter..,1: Event CAPTE2 can clear capture counter.."
|
|
bitfld.long 0x18 21. "CAP1CLREN,Capture Counter Cleared by Capture Event1 Control" "0: Event CAPTE1 can clear capture counter..,1: Event CAPTE1 can clear capture counter.."
|
|
newline
|
|
bitfld.long 0x18 20. "CAP0CLREN,Capture Counter Cleared by Capture Event0 Control" "0: Event CAPTE0 can clear capture counter..,1: Event CAPTE0 can clear capture counter.."
|
|
bitfld.long 0x18 16.--17. "CNTSRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source." "0: CAP_CLK (default),1: CAP0,?,?"
|
|
newline
|
|
bitfld.long 0x18 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]." "0: CAP_CLK/1,1: CAP_CLK/4,?,?,?,?,?,?"
|
|
bitfld.long 0x18 11. "OVRLDEN,Capture Counter's Reload Function Triggered by Overflow Enable Bit" "0: The reload triggered by CAPOV Disabled,1: The reload triggered by CAPOV Enabled"
|
|
newline
|
|
bitfld.long 0x18 10. "CAP2RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit" "0: The reload triggered by Event CAPTE2 Disabled,1: The reload triggered by Event CAPTE2 Enabled"
|
|
bitfld.long 0x18 9. "CAP1RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit" "0: The reload triggered by Event CAPTE1 Disabled,1: The reload triggered by Event CAPTE1 Enabled"
|
|
newline
|
|
bitfld.long 0x18 8. "CAP0RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit" "0: The reload triggered by Event CAPTE0 Disabled,1: The reload triggered by Event CAPTE0 Enabled"
|
|
bitfld.long 0x18 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only rising edge change only or both edge changes" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
|
|
newline
|
|
bitfld.long 0x18 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
|
|
bitfld.long 0x18 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?,?"
|
|
line.long 0x1C "ECAP_STATUS,Input Capture Status Register"
|
|
rbitfld.long 0x1C 10. "CAP2,Value of Input Channel 2 CAP2 (Read Only)\nReflecting the value of input channel 2 CAP2.\nNote: The bit is read only and write is ignored." "0,1"
|
|
rbitfld.long 0x1C 9. "CAP1,Value of Input Channel 1 CAP1 (Read Only)\nReflecting the value of input channel 1 CAP1\nNote: The bit is read only and write is ignored." "0,1"
|
|
newline
|
|
rbitfld.long 0x1C 8. "CAP0,Value of Input Channel 0 CAP0 (Read Only)\nReflecting the value of input channel 0 CAP0\nNote: The bit is read only and write is ignored." "0,1"
|
|
bitfld.long 0x1C 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it." "0: No overflow event has occurred since last clear,1: Overflow event(s) has/have occurred since last.."
|
|
newline
|
|
bitfld.long 0x1C 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it." "0: ECAP_CNT has not matched ECAP_CNTCMP value since..,1: ECAP_CNT has matched ECAP_CNTCMP value at least.."
|
|
bitfld.long 0x1C 2. "CAPTF2,Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP2..,1: At least a valid edge change has been detected.."
|
|
newline
|
|
bitfld.long 0x1C 1. "CAPTF1,Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP1..,1: At least a valid edge change has been detected.."
|
|
bitfld.long 0x1C 0. "CAPTF0,Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to it." "0: No valid edge change has been detected at CAP0..,1: At least a valid edge change has been detected.."
|
|
line.long 0x20 "ECAP_WMCTL,Input Capture timer/Counter Window Mode Control Register"
|
|
bitfld.long 0x20 2. "WCAP2EN,Window Mode CAP2 Enable Bit" "0: CAP2 Window Mode is Disabled,1: CAP2 Window Mode is Enabled"
|
|
bitfld.long 0x20 1. "WCAP1EN,Window Mode CAP1 Enable Bit" "0: CAP1 Window Mode is Disabled,1: CAP1 Window Mode is Enabled"
|
|
newline
|
|
bitfld.long 0x20 0. "WCAP0EN,Window Mode CAP0 Enable Bit" "0: CAP0 Window Mode is Disabled,1: CAP0 Window Mode is Enabled"
|
|
line.long 0x24 "ECAP_WMDLY,Window Mode CAP Trigger Delay Control Register"
|
|
hexmask.long.byte 0x24 16.--23. 1. "WMCAP2DLY,Window Mode CAP2 Delay Timer \nSetting this field will delay CAP2 window period after WM CAP2 trigger is coming.\nDelay time is (4 * WMCAP2DLY) * ECAP_CLK"
|
|
hexmask.long.byte 0x24 8.--15. 1. "WMCAP1DLY,Window Mode CAP1 Delay Timer \nSetting this field will delay CAP1 window period after WM CAP1 trigger is coming.\nDelay time is (4 * WMCAP1DLY) * ECAP_CLK"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "WMCAP0DLY,Window Mode CAP0 Delay Timer \nSetting this field will delay CAP0 window period after WM CAP0 trigger is coming.\nDelay time is (4 * WMCAP0DLY) * ECAP_CLK"
|
|
line.long 0x28 "ECAP_TRGHLD,Window Mode Trigger Counter Hold Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. "TRGHOLD,Window Mode Trigger Counter Hold Register\nWhen WM CAP0 trigger is coming the ECAPCNT value is latched into this holding register."
|
|
tree.end
|
|
tree "FMC (Flash Memory Controller)"
|
|
base ad:0x4000C000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "FMC_ISPCTL,ISP Control Register"
|
|
bitfld.long 0x0 24. "INTEN,INT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. Before using INT user needs to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time." "0: ISP INT Disabled,1: ISP INT Enabled"
|
|
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LDROM cannot be updated,1: LDROM can be updated"
|
|
bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CONFIG cannot be updated,1: CONFIG can be updated"
|
|
newline
|
|
bitfld.long 0x0 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in APROM"
|
|
bitfld.long 0x0 2. "SPUEN,SPROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: SPROM cannot be updated,1: SPROM can be updated"
|
|
newline
|
|
bitfld.long 0x0 1. "BS,Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Booting from APROM,1: Booting from LDROM"
|
|
rbitfld.long 0x0 0. "ISPEN,ISP Enable Flag Bit (Read Only)\nNote: This bit is read only to show ISP function enable." "0: ISP function is Disabled status,1: ISP function is Enabled status"
|
|
line.long 0x4 "FMC_ISPADDR,ISP Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address\nThe M2003C series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. I\nFor CRC32 Checksum Calculation command this field is the Flash starting address for checksum calculation 0.5 Kbytes.."
|
|
line.long 0x8 "FMC_ISPDAT,ISP Data Register"
|
|
hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation."
|
|
line.long 0xC "FMC_ISPCMD,ISP Command Register"
|
|
hexmask.long.byte 0xC 0.--6. 1. "CMD,ISP Command\nThe ISP command table is shown below:\nThe other commands are invalid."
|
|
line.long 0x10 "FMC_ISPTRG,ISP Trigger Control Register"
|
|
bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ISP operation is finished,1: ISP is progressed"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "FMC_ISPSTS,ISP Status Register"
|
|
bitfld.long 0x0 31. "SCODE,Security Code Active Flag\nThis bit is set by hardware when detecting SPROM secured code is active at Flash initiation or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation." "0: Secured code is inactive,1: Secured code is active"
|
|
bitfld.long 0x0 24. "INTFLAG,ISP Interrupt Flag\nNote: This function needs to be enabled by FMC_ISPCTRL[24]." "0: ISP Not Finished,1: ISP done or ISPFF set"
|
|
newline
|
|
hexmask.long.word 0x0 9.--23. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory address {VECMAP[14:0] 9'h000} ~ {VECMAP[14:0] 9'h1FF}"
|
|
bitfld.long 0x0 7. "ALLONE,Flash All-one Verification Flag \nThis bit is set by hardware if all of Flash bits are 1 and cleared if Flash bits are not all 1 after 'Run Flash All-One Verification' is complete; this bit also can be cleared by writing 1" "0: Flash bits are not all 1 after 'Run Flash..,1: All of Flash bits are 1 after 'Run Flash All-One.."
|
|
newline
|
|
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\nAPROM.." "0,1"
|
|
rbitfld.long 0x0 5. "PGFF,Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is cleared by performing ISP Flash erase or ISP read CID operation" "0: Flash Program is success,1: Flash Program is failed. Program data is.."
|
|
newline
|
|
rbitfld.long 0x0 2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened." "0: LDROM with IAP mode,1: APROM with IAP mode"
|
|
rbitfld.long 0x0 0. "ISPBUSY,ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0])." "0: ISP operation is finished,1: ISP is progressed"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "FMC_CYCCTL,Flash Access Cycle Control Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CYCLE,Flash Access Cycle Control (Write Protect)\nThis register is updated by software. User needs to check the speed of HCLK and set the cycle 0.\nThe HCLK working frequency range is25 MHz\nThe others are reserved.\nNote: This bit is write protected."
|
|
tree.end
|
|
tree "GPIO (General Purpose I/Os)"
|
|
base ad:0x40004000
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "PB_MODE,PB I/O Mode Control"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 28.--29. "MODE14,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 24.--25. "MODE12,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 20.--21. "MODE10,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 16.--17. "MODE8,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 12.--13. "MODE6,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 8.--9. "MODE4,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 4.--5. "MODE2,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 0.--1. "MODE0,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
line.long 0x4 "PB_DINOFF,PB Digital Input Path Disable Control"
|
|
bitfld.long 0x4 31. "DINOFF15,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 30. "DINOFF14,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 29. "DINOFF13,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 28. "DINOFF12,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 27. "DINOFF11,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 26. "DINOFF10,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 25. "DINOFF9,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 24. "DINOFF8,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 23. "DINOFF7,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 22. "DINOFF6,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 21. "DINOFF5,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 20. "DINOFF4,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 19. "DINOFF3,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 18. "DINOFF2,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 17. "DINOFF1,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 16. "DINOFF0,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
line.long 0x8 "PB_DOUT,PB Data Output Value"
|
|
bitfld.long 0x8 15. "DOUT15,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 14. "DOUT14,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 13. "DOUT13,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 12. "DOUT12,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 11. "DOUT11,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 10. "DOUT10,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 9. "DOUT9,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 8. "DOUT8,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 7. "DOUT7,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 6. "DOUT6,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 5. "DOUT5,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 4. "DOUT4,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 3. "DOUT3,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 2. "DOUT2,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 1. "DOUT1,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 0. "DOUT0,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
line.long 0xC "PB_DATMSK,PB Data Output Write Mask"
|
|
bitfld.long 0xC 15. "DATMSK15,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 14. "DATMSK14,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 13. "DATMSK13,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 12. "DATMSK12,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 11. "DATMSK11,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 10. "DATMSK10,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 9. "DATMSK9,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 8. "DATMSK8,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 7. "DATMSK7,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 6. "DATMSK6,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 5. "DATMSK5,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 4. "DATMSK4,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 3. "DATMSK3,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 2. "DATMSK2,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 1. "DATMSK1,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 0. "DATMSK0,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "PB_PIN,PB Pin Value"
|
|
bitfld.long 0x0 15. "PIN15,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 14. "PIN14,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 13. "PIN13,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 12. "PIN12,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 11. "PIN11,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 10. "PIN10,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 9. "PIN9,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 8. "PIN8,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 7. "PIN7,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 6. "PIN6,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 5. "PIN5,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 4. "PIN4,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 3. "PIN3,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 2. "PIN2,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 1. "PIN1,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 0. "PIN0,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
group.long 0x54++0x17
|
|
line.long 0x0 "PB_DBEN,PB De-bounce Enable Control Register"
|
|
bitfld.long 0x0 15. "DBEN15,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 14. "DBEN14,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "DBEN13,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 12. "DBEN12,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "DBEN11,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 10. "DBEN10,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "DBEN9,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 8. "DBEN8,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "DBEN7,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 6. "DBEN6,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "DBEN5,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 4. "DBEN4,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "DBEN3,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 2. "DBEN2,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "DBEN1,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 0. "DBEN0,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
line.long 0x4 "PB_INTTYPE,PB Interrupt Trigger Type Control"
|
|
bitfld.long 0x4 15. "TYPE15,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 14. "TYPE14,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 13. "TYPE13,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 12. "TYPE12,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 11. "TYPE11,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 10. "TYPE10,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 9. "TYPE9,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 8. "TYPE8,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 7. "TYPE7,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 6. "TYPE6,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 5. "TYPE5,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 4. "TYPE4,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 3. "TYPE3,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 2. "TYPE2,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 1. "TYPE1,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 0. "TYPE0,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
line.long 0x8 "PB_INTEN,PB Interrupt Enable Control Register"
|
|
bitfld.long 0x8 31. "RHIEN15,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 30. "RHIEN14,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 29. "RHIEN13,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 28. "RHIEN12,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 27. "RHIEN11,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 26. "RHIEN10,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 25. "RHIEN9,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 24. "RHIEN8,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 23. "RHIEN7,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 22. "RHIEN6,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 21. "RHIEN5,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 20. "RHIEN4,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 19. "RHIEN3,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 18. "RHIEN2,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 17. "RHIEN1,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 16. "RHIEN0,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 15. "FLIEN15,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 14. "FLIEN14,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 13. "FLIEN13,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 12. "FLIEN12,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 11. "FLIEN11,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 10. "FLIEN10,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 9. "FLIEN9,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 8. "FLIEN8,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 7. "FLIEN7,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 6. "FLIEN6,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 5. "FLIEN5,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 4. "FLIEN4,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 3. "FLIEN3,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 2. "FLIEN2,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 1. "FLIEN1,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 0. "FLIEN0,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
line.long 0xC "PB_INTSRC,PB Interrupt Source Flag"
|
|
bitfld.long 0xC 15. "INTSRC15,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 14. "INTSRC14,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 13. "INTSRC13,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 12. "INTSRC12,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 11. "INTSRC11,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 10. "INTSRC10,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 9. "INTSRC9,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 8. "INTSRC8,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 7. "INTSRC7,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 6. "INTSRC6,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 5. "INTSRC5,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 4. "INTSRC4,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 3. "INTSRC3,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 2. "INTSRC2,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 1. "INTSRC1,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 0. "INTSRC0,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
line.long 0x10 "PB_SMTEN,PB Input Schmitt Trigger Enable Register"
|
|
bitfld.long 0x10 15. "SMTEN15,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 14. "SMTEN14,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. "SMTEN13,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 12. "SMTEN12,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 11. "SMTEN11,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 10. "SMTEN10,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 9. "SMTEN9,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 8. "SMTEN8,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 7. "SMTEN7,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 6. "SMTEN6,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 5. "SMTEN5,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 4. "SMTEN4,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "SMTEN3,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 2. "SMTEN2,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 1. "SMTEN1,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 0. "SMTEN0,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
line.long 0x14 "PB_SLEWCTL,PB High Slew Rate Control Register"
|
|
bitfld.long 0x14 30.--31. "HSREN15,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 28.--29. "HSREN14,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 26.--27. "HSREN13,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 24.--25. "HSREN12,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 22.--23. "HSREN11,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 20.--21. "HSREN10,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 18.--19. "HSREN9,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 16.--17. "HSREN8,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 14.--15. "HSREN7,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 12.--13. "HSREN6,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 10.--11. "HSREN5,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 8.--9. "HSREN4,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 6.--7. "HSREN3,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 4.--5. "HSREN2,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 2.--3. "HSREN1,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 0.--1. "HSREN0,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "PB_PUSEL,PB Pull-up and Pull-down Selection Register"
|
|
bitfld.long 0x0 30.--31. "PUSEL15,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 28.--29. "PUSEL14,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "PUSEL13,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 24.--25. "PUSEL12,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "PUSEL11,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 20.--21. "PUSEL10,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "PUSEL9,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 16.--17. "PUSEL8,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "PUSEL7,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 12.--13. "PUSEL6,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "PUSEL5,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 8.--9. "PUSEL4,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PUSEL3,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 4.--5. "PUSEL2,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PUSEL1,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 0.--1. "PUSEL0,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
line.long 0x4 "PB_DBCTL,PB Interrupt De-bounce Control Register"
|
|
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode - Secure Only\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: This bit is only accessible from the Secure state." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
|
|
bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection - Secure only\nNote: This bit is only accessible from the Secure state." "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection - Secure only\nNote: These bits are only accessible from the Secure state."
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "PC_MODE,PC I/O Mode Control"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 28.--29. "MODE14,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 24.--25. "MODE12,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 20.--21. "MODE10,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 16.--17. "MODE8,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 12.--13. "MODE6,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 8.--9. "MODE4,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 4.--5. "MODE2,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 0.--1. "MODE0,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
line.long 0x4 "PC_DINOFF,PC Digital Input Path Disable Control"
|
|
bitfld.long 0x4 31. "DINOFF15,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 30. "DINOFF14,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 29. "DINOFF13,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 28. "DINOFF12,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 27. "DINOFF11,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 26. "DINOFF10,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 25. "DINOFF9,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 24. "DINOFF8,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 23. "DINOFF7,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 22. "DINOFF6,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 21. "DINOFF5,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 20. "DINOFF4,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 19. "DINOFF3,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 18. "DINOFF2,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 17. "DINOFF1,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 16. "DINOFF0,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
line.long 0x8 "PC_DOUT,PC Data Output Value"
|
|
bitfld.long 0x8 15. "DOUT15,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 14. "DOUT14,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 13. "DOUT13,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 12. "DOUT12,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 11. "DOUT11,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 10. "DOUT10,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 9. "DOUT9,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 8. "DOUT8,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 7. "DOUT7,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 6. "DOUT6,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 5. "DOUT5,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 4. "DOUT4,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 3. "DOUT3,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 2. "DOUT2,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 1. "DOUT1,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 0. "DOUT0,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
line.long 0xC "PC_DATMSK,PC Data Output Write Mask"
|
|
bitfld.long 0xC 15. "DATMSK15,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 14. "DATMSK14,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 13. "DATMSK13,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 12. "DATMSK12,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 11. "DATMSK11,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 10. "DATMSK10,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 9. "DATMSK9,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 8. "DATMSK8,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 7. "DATMSK7,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 6. "DATMSK6,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 5. "DATMSK5,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 4. "DATMSK4,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 3. "DATMSK3,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 2. "DATMSK2,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 1. "DATMSK1,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 0. "DATMSK0,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "PC_PIN,PC Pin Value"
|
|
bitfld.long 0x0 15. "PIN15,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 14. "PIN14,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 13. "PIN13,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 12. "PIN12,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 11. "PIN11,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 10. "PIN10,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 9. "PIN9,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 8. "PIN8,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 7. "PIN7,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 6. "PIN6,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 5. "PIN5,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 4. "PIN4,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 3. "PIN3,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 2. "PIN2,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 1. "PIN1,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 0. "PIN0,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
group.long 0x94++0x17
|
|
line.long 0x0 "PC_DBEN,PC De-bounce Enable Control Register"
|
|
bitfld.long 0x0 15. "DBEN15,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 14. "DBEN14,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "DBEN13,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 12. "DBEN12,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "DBEN11,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 10. "DBEN10,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "DBEN9,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 8. "DBEN8,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "DBEN7,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 6. "DBEN6,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "DBEN5,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 4. "DBEN4,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "DBEN3,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 2. "DBEN2,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "DBEN1,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 0. "DBEN0,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
line.long 0x4 "PC_INTTYPE,PC Interrupt Trigger Type Control"
|
|
bitfld.long 0x4 15. "TYPE15,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 14. "TYPE14,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 13. "TYPE13,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 12. "TYPE12,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 11. "TYPE11,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 10. "TYPE10,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 9. "TYPE9,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 8. "TYPE8,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 7. "TYPE7,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 6. "TYPE6,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 5. "TYPE5,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 4. "TYPE4,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 3. "TYPE3,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 2. "TYPE2,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 1. "TYPE1,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 0. "TYPE0,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
line.long 0x8 "PC_INTEN,PC Interrupt Enable Control Register"
|
|
bitfld.long 0x8 31. "RHIEN15,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 30. "RHIEN14,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 29. "RHIEN13,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 28. "RHIEN12,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 27. "RHIEN11,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 26. "RHIEN10,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 25. "RHIEN9,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 24. "RHIEN8,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 23. "RHIEN7,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 22. "RHIEN6,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 21. "RHIEN5,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 20. "RHIEN4,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 19. "RHIEN3,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 18. "RHIEN2,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 17. "RHIEN1,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 16. "RHIEN0,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 15. "FLIEN15,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 14. "FLIEN14,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 13. "FLIEN13,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 12. "FLIEN12,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 11. "FLIEN11,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 10. "FLIEN10,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 9. "FLIEN9,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 8. "FLIEN8,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 7. "FLIEN7,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 6. "FLIEN6,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 5. "FLIEN5,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 4. "FLIEN4,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 3. "FLIEN3,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 2. "FLIEN2,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 1. "FLIEN1,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 0. "FLIEN0,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
line.long 0xC "PC_INTSRC,PC Interrupt Source Flag"
|
|
bitfld.long 0xC 15. "INTSRC15,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 14. "INTSRC14,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 13. "INTSRC13,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 12. "INTSRC12,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 11. "INTSRC11,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 10. "INTSRC10,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 9. "INTSRC9,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 8. "INTSRC8,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 7. "INTSRC7,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 6. "INTSRC6,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 5. "INTSRC5,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 4. "INTSRC4,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 3. "INTSRC3,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 2. "INTSRC2,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 1. "INTSRC1,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 0. "INTSRC0,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
line.long 0x10 "PC_SMTEN,PC Input Schmitt Trigger Enable Register"
|
|
bitfld.long 0x10 15. "SMTEN15,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 14. "SMTEN14,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. "SMTEN13,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 12. "SMTEN12,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 11. "SMTEN11,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 10. "SMTEN10,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 9. "SMTEN9,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 8. "SMTEN8,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 7. "SMTEN7,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 6. "SMTEN6,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 5. "SMTEN5,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 4. "SMTEN4,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "SMTEN3,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 2. "SMTEN2,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 1. "SMTEN1,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 0. "SMTEN0,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
line.long 0x14 "PC_SLEWCTL,PC High Slew Rate Control Register"
|
|
bitfld.long 0x14 30.--31. "HSREN15,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 28.--29. "HSREN14,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 26.--27. "HSREN13,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 24.--25. "HSREN12,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 22.--23. "HSREN11,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 20.--21. "HSREN10,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 18.--19. "HSREN9,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 16.--17. "HSREN8,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 14.--15. "HSREN7,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 12.--13. "HSREN6,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 10.--11. "HSREN5,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 8.--9. "HSREN4,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 6.--7. "HSREN3,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 4.--5. "HSREN2,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 2.--3. "HSREN1,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 0.--1. "HSREN0,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "PC_PUSEL,PC Pull-up and Pull-down Selection Register"
|
|
bitfld.long 0x0 30.--31. "PUSEL15,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 28.--29. "PUSEL14,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "PUSEL13,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 24.--25. "PUSEL12,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "PUSEL11,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 20.--21. "PUSEL10,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "PUSEL9,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 16.--17. "PUSEL8,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "PUSEL7,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 12.--13. "PUSEL6,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "PUSEL5,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 8.--9. "PUSEL4,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PUSEL3,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 4.--5. "PUSEL2,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PUSEL1,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 0.--1. "PUSEL0,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
line.long 0x4 "PC_DBCTL,PC Interrupt De-bounce Control Register"
|
|
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode - Secure Only\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: This bit is only accessible from the Secure state." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
|
|
bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection - Secure only\nNote: This bit is only accessible from the Secure state." "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection - Secure only\nNote: These bits are only accessible from the Secure state."
|
|
rgroup.long 0x110++0x3
|
|
line.long 0x0 "PE_PIN,PE Pin Value"
|
|
bitfld.long 0x0 15. "PIN15,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 14. "PIN14,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 13. "PIN13,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 12. "PIN12,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 11. "PIN11,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 10. "PIN10,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 9. "PIN9,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 8. "PIN8,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 7. "PIN7,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 6. "PIN6,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 5. "PIN5,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 4. "PIN4,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 3. "PIN3,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 2. "PIN2,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 1. "PIN1,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 0. "PIN0,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
group.long 0x114++0xF
|
|
line.long 0x0 "PE_DBEN,PE De-bounce Enable Control Register"
|
|
bitfld.long 0x0 15. "DBEN15,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 14. "DBEN14,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "DBEN13,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 12. "DBEN12,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "DBEN11,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 10. "DBEN10,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "DBEN9,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 8. "DBEN8,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "DBEN7,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 6. "DBEN6,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "DBEN5,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 4. "DBEN4,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "DBEN3,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 2. "DBEN2,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "DBEN1,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 0. "DBEN0,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
line.long 0x4 "PE_INTTYPE,PE Interrupt Trigger Type Control"
|
|
bitfld.long 0x4 15. "TYPE15,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 14. "TYPE14,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 13. "TYPE13,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 12. "TYPE12,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 11. "TYPE11,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 10. "TYPE10,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 9. "TYPE9,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 8. "TYPE8,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 7. "TYPE7,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 6. "TYPE6,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 5. "TYPE5,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 4. "TYPE4,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 3. "TYPE3,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 2. "TYPE2,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 1. "TYPE1,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 0. "TYPE0,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
line.long 0x8 "PE_INTEN,PE Interrupt Enable Control Register"
|
|
bitfld.long 0x8 31. "RHIEN15,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 30. "RHIEN14,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 29. "RHIEN13,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 28. "RHIEN12,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 27. "RHIEN11,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 26. "RHIEN10,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 25. "RHIEN9,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 24. "RHIEN8,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 23. "RHIEN7,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 22. "RHIEN6,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 21. "RHIEN5,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 20. "RHIEN4,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 19. "RHIEN3,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 18. "RHIEN2,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 17. "RHIEN1,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 16. "RHIEN0,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 15. "FLIEN15,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 14. "FLIEN14,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 13. "FLIEN13,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 12. "FLIEN12,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 11. "FLIEN11,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 10. "FLIEN10,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 9. "FLIEN9,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 8. "FLIEN8,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 7. "FLIEN7,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 6. "FLIEN6,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 5. "FLIEN5,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 4. "FLIEN4,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 3. "FLIEN3,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 2. "FLIEN2,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 1. "FLIEN1,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 0. "FLIEN0,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
line.long 0xC "PE_INTSRC,PE Interrupt Source Flag"
|
|
bitfld.long 0xC 15. "INTSRC15,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 14. "INTSRC14,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 13. "INTSRC13,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 12. "INTSRC12,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 11. "INTSRC11,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 10. "INTSRC10,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 9. "INTSRC9,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 8. "INTSRC8,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 7. "INTSRC7,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 6. "INTSRC6,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 5. "INTSRC5,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 4. "INTSRC4,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 3. "INTSRC3,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 2. "INTSRC2,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 1. "INTSRC1,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 0. "INTSRC0,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
group.long 0x130++0x7
|
|
line.long 0x0 "PE_PUSEL,PE Pull-up Selection Register"
|
|
bitfld.long 0x0 30.--31. "PUSEL15,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 28.--29. "PUSEL14,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "PUSEL13,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 24.--25. "PUSEL12,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "PUSEL11,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 20.--21. "PUSEL10,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "PUSEL9,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 16.--17. "PUSEL8,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "PUSEL7,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 12.--13. "PUSEL6,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "PUSEL5,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 8.--9. "PUSEL4,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PUSEL3,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 4.--5. "PUSEL2,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PUSEL1,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 0.--1. "PUSEL0,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
line.long 0x4 "PE_DBCTL,PE Interrupt De-bounce Control Register"
|
|
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode - Secure Only\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: This bit is only accessible from the Secure state." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
|
|
bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection - Secure only\nNote: This bit is only accessible from the Secure state." "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection - Secure only\nNote: These bits are only accessible from the Secure state."
|
|
group.long 0x140++0xF
|
|
line.long 0x0 "PF_MODE,PF I/O Mode Control"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 28.--29. "MODE14,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 24.--25. "MODE12,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 20.--21. "MODE10,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 16.--17. "MODE8,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 12.--13. "MODE6,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 8.--9. "MODE4,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 4.--5. "MODE2,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
bitfld.long 0x0 0.--1. "MODE0,Port B-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode (tri-state),1: The initial value of this field is defined by..,2: The PB,3: If MFOS is enabled then GPIO mode setting is.."
|
|
line.long 0x4 "PF_DINOFF,PF Digital Input Path Disable Control"
|
|
bitfld.long 0x4 31. "DINOFF15,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 30. "DINOFF14,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 29. "DINOFF13,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 28. "DINOFF12,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 27. "DINOFF11,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 26. "DINOFF10,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 25. "DINOFF9,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 24. "DINOFF8,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 23. "DINOFF7,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 22. "DINOFF6,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 21. "DINOFF5,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 20. "DINOFF4,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 19. "DINOFF3,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 18. "DINOFF2,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
newline
|
|
bitfld.long 0x4 17. "DINOFF1,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
bitfld.long 0x4 16. "DINOFF0,Port B-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
|
|
line.long 0x8 "PF_DOUT,PF Data Output Value"
|
|
bitfld.long 0x8 15. "DOUT15,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 14. "DOUT14,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 13. "DOUT13,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 12. "DOUT12,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 11. "DOUT11,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 10. "DOUT10,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 9. "DOUT9,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 8. "DOUT8,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 7. "DOUT7,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 6. "DOUT6,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 5. "DOUT5,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 4. "DOUT4,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 3. "DOUT3,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 2. "DOUT2,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
newline
|
|
bitfld.long 0x8 1. "DOUT1,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
bitfld.long 0x8 0. "DOUT0,Port B-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
|
|
line.long 0xC "PF_DATMSK,PF Data Output Write Mask"
|
|
bitfld.long 0xC 15. "DATMSK15,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 14. "DATMSK14,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 13. "DATMSK13,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 12. "DATMSK12,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 11. "DATMSK11,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 10. "DATMSK10,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 9. "DATMSK9,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 8. "DATMSK8,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 7. "DATMSK7,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 6. "DATMSK6,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 5. "DATMSK5,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 4. "DATMSK4,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 3. "DATMSK3,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 2. "DATMSK2,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
newline
|
|
bitfld.long 0xC 1. "DATMSK1,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
bitfld.long 0xC 0. "DATMSK0,Port B-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding DOUT"
|
|
rgroup.long 0x150++0x3
|
|
line.long 0x0 "PF_PIN,PF Pin Value"
|
|
bitfld.long 0x0 15. "PIN15,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 14. "PIN14,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 13. "PIN13,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 12. "PIN12,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 11. "PIN11,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 10. "PIN10,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 9. "PIN9,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 8. "PIN8,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 7. "PIN7,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 6. "PIN6,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 5. "PIN5,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 4. "PIN4,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 3. "PIN3,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 2. "PIN2,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
newline
|
|
bitfld.long 0x0 1. "PIN1,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
bitfld.long 0x0 0. "PIN0,Port B-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: The corresponding pin status is low,1: The corresponding pin status is high"
|
|
group.long 0x154++0x17
|
|
line.long 0x0 "PF_DBEN,PF De-bounce Enable Control Register"
|
|
bitfld.long 0x0 15. "DBEN15,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 14. "DBEN14,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "DBEN13,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 12. "DBEN12,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "DBEN11,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 10. "DBEN10,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "DBEN9,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 8. "DBEN8,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "DBEN7,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 6. "DBEN6,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "DBEN5,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 4. "DBEN4,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "DBEN3,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 2. "DBEN2,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "DBEN1,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
bitfld.long 0x0 0. "DBEN0,Port B-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
|
|
line.long 0x4 "PF_INTTYPE,PF Interrupt Trigger Type Control"
|
|
bitfld.long 0x4 15. "TYPE15,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 14. "TYPE14,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 13. "TYPE13,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 12. "TYPE12,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 11. "TYPE11,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 10. "TYPE10,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 9. "TYPE9,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 8. "TYPE8,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 7. "TYPE7,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 6. "TYPE6,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 5. "TYPE5,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 4. "TYPE4,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 3. "TYPE3,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 2. "TYPE2,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x4 1. "TYPE1,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x4 0. "TYPE0,Port B-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
line.long 0x8 "PF_INTEN,PF Interrupt Enable Control Register"
|
|
bitfld.long 0x8 31. "RHIEN15,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 30. "RHIEN14,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 29. "RHIEN13,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 28. "RHIEN12,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 27. "RHIEN11,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 26. "RHIEN10,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 25. "RHIEN9,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 24. "RHIEN8,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 23. "RHIEN7,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 22. "RHIEN6,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 21. "RHIEN5,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 20. "RHIEN4,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 19. "RHIEN3,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 18. "RHIEN2,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 17. "RHIEN1,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 16. "RHIEN0,Port B-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 15. "FLIEN15,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 14. "FLIEN14,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 13. "FLIEN13,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 12. "FLIEN12,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 11. "FLIEN11,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 10. "FLIEN10,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 9. "FLIEN9,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 8. "FLIEN8,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 7. "FLIEN7,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 6. "FLIEN6,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 5. "FLIEN5,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 4. "FLIEN4,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 3. "FLIEN3,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 2. "FLIEN2,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
newline
|
|
bitfld.long 0x8 1. "FLIEN1,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
bitfld.long 0x8 0. "FLIEN0,Port B-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: \nIf the interrupt is level trigger"
|
|
line.long 0xC "PF_INTSRC,PF Interrupt Source Flag"
|
|
bitfld.long 0xC 15. "INTSRC15,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 14. "INTSRC14,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 13. "INTSRC13,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 12. "INTSRC12,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 11. "INTSRC11,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 10. "INTSRC10,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 9. "INTSRC9,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 8. "INTSRC8,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 7. "INTSRC7,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 6. "INTSRC6,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 5. "INTSRC5,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 4. "INTSRC4,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 3. "INTSRC3,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 2. "INTSRC2,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
newline
|
|
bitfld.long 0xC 1. "INTSRC1,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
bitfld.long 0xC 0. "INTSRC0,Port B-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~14/ PF.3~15 pins are ignored." "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
|
|
line.long 0x10 "PF_SMTEN,PF Input Schmitt Trigger Enable Register"
|
|
bitfld.long 0x10 15. "SMTEN15,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 14. "SMTEN14,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. "SMTEN13,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 12. "SMTEN12,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 11. "SMTEN11,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 10. "SMTEN10,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 9. "SMTEN9,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 8. "SMTEN8,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 7. "SMTEN7,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 6. "SMTEN6,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 5. "SMTEN5,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 4. "SMTEN4,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "SMTEN3,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 2. "SMTEN2,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x10 1. "SMTEN1,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
bitfld.long 0x10 0. "SMTEN0,Port B-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
line.long 0x14 "PF_SLEWCTL,PF High Slew Rate Control Register"
|
|
bitfld.long 0x14 30.--31. "HSREN15,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 28.--29. "HSREN14,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 26.--27. "HSREN13,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 24.--25. "HSREN12,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 22.--23. "HSREN11,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 20.--21. "HSREN10,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 18.--19. "HSREN9,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 16.--17. "HSREN8,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 14.--15. "HSREN7,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 12.--13. "HSREN6,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 10.--11. "HSREN5,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 8.--9. "HSREN4,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 6.--7. "HSREN3,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 4.--5. "HSREN2,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
newline
|
|
bitfld.long 0x14 2.--3. "HSREN1,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
bitfld.long 0x14 0.--1. "HSREN0,Port B-F Pin[n] High Slew Rate Control\nNote 1: The PB.6/PB.10/PC.0~13/PC.15/PE.0~15/ PF.3~15 pins are ignored.\nNote 2: Please refer to the Datasheet for detailed pin operation voltage information about VDD VDDIO and VBAT electrical.." "0: Px.n output with normal slew rate mode,1: The PB,2: Please refer to the Datasheet for detailed pin..,?"
|
|
group.long 0x170++0x7
|
|
line.long 0x0 "PF_PUSEL,PF Pull-up and Pull-down Selection Register"
|
|
bitfld.long 0x0 30.--31. "PUSEL15,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 28.--29. "PUSEL14,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "PUSEL13,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 24.--25. "PUSEL12,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "PUSEL11,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 20.--21. "PUSEL10,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "PUSEL9,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 16.--17. "PUSEL8,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "PUSEL7,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 12.--13. "PUSEL6,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "PUSEL5,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 8.--9. "PUSEL4,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PUSEL3,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 4.--5. "PUSEL2,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PUSEL1,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
bitfld.long 0x0 0.--1. "PUSEL0,Port B-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote 1: Basically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register.." "0: Px.n pull-up and pull-down disabled,1: Basically,2: The PB,?"
|
|
line.long 0x4 "PF_DBCTL,PF Interrupt De-bounce Control Register"
|
|
bitfld.long 0x4 5. "ICLKON,Interrupt Clock on Mode - Secure Only\nNote 1: It is recommended to disable this bit to save system power if no special application concern.\nNote 2: This bit is only accessible from the Secure state." "0: Edge detection circuit is active only if I/O pin..,1: It is recommended to disable this bit to save.."
|
|
bitfld.long 0x4 4. "DBCLKSRC,De-bounce Counter Clock Source Selection - Secure only\nNote: This bit is only accessible from the Secure state." "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection - Secure only\nNote: These bits are only accessible from the Secure state."
|
|
group.long 0x840++0x7F
|
|
line.long 0x0 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x4 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x8 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0xC "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x10 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x14 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x18 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x1C "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x20 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x24 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x28 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x2C "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x30 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x34 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x38 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x3C "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x40 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x40 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x44 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x44 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x48 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x48 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x4C "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x4C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x50 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x50 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x54 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x54 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x58 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x58 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x5C "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x5C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x60 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x60 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x64 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x64 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x68 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x68 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x6C "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x6C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x70 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x70 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x74 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x74 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x78 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x78 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x7C "PC15_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x7C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
group.long 0x900++0x7F
|
|
line.long 0x0 "PE0_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x4 "PE1_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x8 "PE2_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0xC "PE3_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x10 "PE4_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x14 "PE5_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x18 "PE6_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x1C "PE7_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x20 "PE8_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x24 "PE9_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x28 "PE10_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x2C "PE11_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x30 "PE12_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x34 "PE13_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x38 "PE14_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x3C "PE15_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x40 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x40 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x44 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x44 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x48 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x48 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x4C "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x4C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x50 "PF4_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x50 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x54 "PF5_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x54 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x58 "PF6_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x58 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x5C "PF7_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x5C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x60 "PF8_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x60 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x64 "PF9_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x64 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x68 "PF10_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x68 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x6C "PF11_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x6C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x70 "PF12_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x70 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x74 "PF13_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x74 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x78 "PF14_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x78 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
line.long 0x7C "PF15_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x7C 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PB0_PDIO will reflect the written value to bit DOUT (PB_DOUT[0]) reading PB0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit Serial Interface Controller)"
|
|
base ad:0x40080000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "I2C_CTL0,I2C Control Register 0"
|
|
bitfld.long 0x0 15. "SARCIF,Slave Address Read Command Interrupt Flag\nThis bit is set by hardware when I2C receive address match read command.\nThis bit is cleared by write 1 to it." "0,1"
|
|
bitfld.long 0x0 14. "DPCIF,Data Phase Count Interrupt Flag\nThis bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting \nThis bit is cleared by write 1 to it." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SRCINTEN,Slave Read Command Interrupt Enable Bit" "0: Slave Read Command Interrupt Disabled,1: Slave Read Command Interrupt Enabled"
|
|
bitfld.long 0x0 12. "DPCINTEN,Data Phase Count Interrupt Enable Bit" "0: Data Phase Count Interrupt Disabled,1: Data Phase Count Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "DPBITSEL,Data Phase Bit Count Select" "0: DPCIF never set by hardware,1: When I2C is transfer data and bit count equal to..,?,?"
|
|
bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
|
|
bitfld.long 0x0 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
|
|
bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
|
|
line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
|
|
hexmask.long.byte 0x4 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
|
|
bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
line.long 0x8 "I2C_DAT,I2C Data Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
|
|
group.long 0x10++0x23
|
|
line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
|
|
hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4."
|
|
line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
|
|
bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit." "0,1"
|
|
line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
|
|
hexmask.long.byte 0x8 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
|
|
bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
|
|
hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
|
|
bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
|
|
hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is.."
|
|
bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
|
|
hexmask.long.byte 0x14 1.--7. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
|
|
line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
|
|
hexmask.long.byte 0x18 1.--7. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
|
|
line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
|
|
hexmask.long.byte 0x1C 1.--7. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
|
|
line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
|
|
hexmask.long.byte 0x20 1.--7. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
|
|
group.long 0x3C++0xB
|
|
line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
|
|
bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
|
|
bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
|
|
line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
|
|
rbitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame (Read Only)\nNote: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
|
|
bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
|
|
newline
|
|
bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
|
|
line.long 0x8 "I2C_CTL1,I2C Control Register 1"
|
|
bitfld.long 0x8 5. "TWOBUFEN,Two-level BUFFER Enable Bit\nSet to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus." "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "I2C_STATUS1,I2C Status Register 1"
|
|
bitfld.long 0x0 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "I2C_TMCTL,I2C Timing Configure Control Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
|
|
hexmask.long.word 0x0 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs."
|
|
tree.end
|
|
tree "NMI (Non-Maskable Interrupt)"
|
|
base ad:0x40000300
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "NMIEN,NMI Source Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "UART1INT,UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART1 NMI source Disabled,1: UART1 NMI source Enabled"
|
|
bitfld.long 0x0 14. "UART0INT,UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "EINT5,External Interrupt From PB.7 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from PB.7 pin NMI source..,1: External interrupt from PB.7 pin NMI source.."
|
|
bitfld.long 0x0 11. "EINT3,External Interrupt From PB.2 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from PB.2 pin NMI source..,1: External interrupt from PB.2 pin NMI source.."
|
|
newline
|
|
bitfld.long 0x0 10. "EINT2,External Interrupt From PB.3 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from PB.3 pin NMI source..,1: External interrupt from PB.3 pin NMI source.."
|
|
bitfld.long 0x0 9. "EINT1,External Interrupt From PB.4 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from PB.4 pin NMI source..,1: External interrupt from PB.4 NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "EINT0,External Interrupt From PB.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from PB.5 pin NMI source..,1: External interrupt from PB.5 pin NMI source.."
|
|
bitfld.long 0x0 2. "PWRWUINT,Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "BODOUT,BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: BOD NMI source Disabled,1: BOD NMI source Enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "NMISTS,NMI Source Interrupt Status Register"
|
|
bitfld.long 0x0 15. "UART1INT,UART1 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
|
|
bitfld.long 0x0 14. "UART0INT,UART0 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x0 13. "EINT5,External Interrupt From PB.7 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.7 interrupt is..,1: External Interrupt from PB.7 interrupt is asserted"
|
|
bitfld.long 0x0 11. "EINT3,External Interrupt From PB.2 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.2 interrupt is..,1: External Interrupt from PB.2 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x0 10. "EINT2,External Interrupt From PB.3 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.3 interrupt is..,1: External Interrupt from PB.3 interrupt is asserted"
|
|
bitfld.long 0x0 9. "EINT1,External Interrupt From PB.4 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.4 interrupt is..,1: External Interrupt from PB.4 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x0 8. "EINT0,External Interrupt From PB.5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.5 interrupt is..,1: External Interrupt from PB.5 interrupt is asserted"
|
|
bitfld.long 0x0 2. "PWRWUINT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x0 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted"
|
|
tree.end
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
base ad:0xE000E100
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "NVIC_ISER0,IRQ00 ~ IRQ31 Set-enable Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER1 registers enable interrupts and show which interrupts are enabled.\nWrite Operation:"
|
|
line.long 0x4 "NVIC_ISER1,IRQ32 ~ IRQ63 Set-enable Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER1 registers enable interrupts and show which interrupts are enabled.\nWrite Operation:"
|
|
line.long 0x8 "NVIC_ISER2,IRQ64 ~ IRQ95 Set-enable Control Register"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "NVIC_ICER0,IRQ00 ~ IRQ31 Clear-enable Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER1 registers disable interrupts and show which interrupts are enabled.\nWrite Operation:"
|
|
line.long 0x4 "NVIC_ICER1,IRQ32 ~ IRQ63 Clear-enable Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER1 registers disable interrupts and show which interrupts are enabled.\nWrite Operation:"
|
|
line.long 0x8 "NVIC_ICER2,IRQ64 ~ IRQ95 Clear-enable Control Register"
|
|
group.long 0x100++0xB
|
|
line.long 0x0 "NVIC_ISPR0,IRQ00 ~ IRQ31 Set-pending Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state and show which interrupts are pending.\nWrite Operation:"
|
|
line.long 0x4 "NVIC_ISPR1,IRQ32 ~ IRQ63 Set-pending Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state and show which interrupts are pending.\nWrite Operation:"
|
|
line.long 0x8 "NVIC_ISPR2,IRQ64 ~ IRQ95 Set-pending Control Register"
|
|
group.long 0x180++0xB
|
|
line.long 0x0 "NVIC_ICPR0,IRQ00 ~ IRQ31 Clear-pending Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts and show which interrupts are pending.\nWrite Operation:"
|
|
line.long 0x4 "NVIC_ICPR1,IRQ32 ~ IRQ63 Clear-pending Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts and show which interrupts are pending.\nWrite Operation:"
|
|
line.long 0x8 "NVIC_ICPR2,IRQ64 ~ IRQ95 Clear-pending Control Register"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "NVIC_IABR0,IRQ00 ~ IRQ31 Active Bit Register"
|
|
hexmask.long 0x0 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active."
|
|
line.long 0x4 "NVIC_IABR1,IRQ32 ~ IRQ63 Active Bit Register"
|
|
hexmask.long 0x4 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active."
|
|
line.long 0x8 "NVIC_IABR2,IRQ64 ~ IRQ95 Active Bit Register"
|
|
group.long 0x280++0x7
|
|
line.long 0x0 "NVIC_ITNS0,IRQ00 ~ IRQ31 Interrupt Target Non-secure Register"
|
|
hexmask.long 0x0 0.--31. 1. "ITNS,Interrupt Target Non-secure Register\nThe NVIC_ITNS0-NVIC_INTS1 registers determines whether each interrupt targets Non-secure or Secure state.\nThis register is RAZ/WI when accessed as Non-secure."
|
|
line.long 0x4 "NVIC_ITNS1,IRQ32 ~ IRQ63 Interrupt Target Non-secure Register"
|
|
hexmask.long 0x4 0.--31. 1. "ITNS,Interrupt Target Non-secure Register\nThe NVIC_ITNS0-NVIC_INTS1 registers determines whether each interrupt targets Non-secure or Secure state.\nNote: This register is RAZ/WI when accessed as Non-secure."
|
|
group.long 0x300++0x3F
|
|
line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x0 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x4 "NVIC_IPR1,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x4 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x8 "NVIC_IPR2,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x8 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0xC "NVIC_IPR3,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0xC 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x10 "NVIC_IPR4,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x10 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x14 "NVIC_IPR5,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x14 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x18 "NVIC_IPR6,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x18 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x1C "NVIC_IPR7,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x1C 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x20 "NVIC_IPR8,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x20 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x20 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x20 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x20 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x24 "NVIC_IPR9,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x24 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x24 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x24 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x24 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x28 "NVIC_IPR10,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x28 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x28 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x28 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x28 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x2C "NVIC_IPR11,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x2C 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x2C 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x2C 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x2C 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x30 "NVIC_IPR12,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x30 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x30 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x30 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x30 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x34 "NVIC_IPR13,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x34 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x34 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x34 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x34 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x38 "NVIC_IPR14,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x38 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x38 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x38 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x38 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x3C "NVIC_IPR15,IRQ0 ~ IRQ63 Priority Control Register"
|
|
bitfld.long 0x3C 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x3C 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x3C 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x3C 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
tree.end
|
|
tree "PWM (PWM Generator and Capture Timer)"
|
|
base ad:0x40058000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "PWM_CTL0,PWM Control Register 0"
|
|
bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
|
|
bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disable,1: ICE debug mode counter halt Enable"
|
|
newline
|
|
bitfld.long 0x0 16. "IMMLDENn,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid." "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
|
|
bitfld.long 0x0 0. "CTRLDn,Center Load Enable Bits\nIn up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period." "0,1"
|
|
line.long 0x4 "PWM_CTL1,PWM Control Register 1"
|
|
bitfld.long 0x4 24.--26. "OUTMODEn,PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode,?,?,?,?,?,?"
|
|
bitfld.long 0x4 8.--9. "CNTTYPE4,PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "CNTTYPE2,PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
|
|
bitfld.long 0x4 0.--1. "CNTTYPE0,PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),?,?"
|
|
group.long 0x10++0x17
|
|
line.long 0x0 "PWM_CLKSRC,PWM Clock Source Register"
|
|
bitfld.long 0x0 16.--18. "ECLKSRC4,PWM_CH45 External Clock Source Select" "0: PWM_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
|
|
bitfld.long 0x0 8.--10. "ECLKSRC2,PWM_CH23 External Clock Source Select" "0: PWM_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "ECLKSRC0,PWM_CH01 External Clock Source Select" "0: PWM_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
|
|
line.long 0x4 "PWM_CLKPSC0_1,PWM Clock Prescale Register 0/1"
|
|
hexmask.long.word 0x4 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
|
|
line.long 0x8 "PWM_CLKPSC2_3,PWM Clock Prescale Register 2/3"
|
|
hexmask.long.word 0x8 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
|
|
line.long 0xC "PWM_CLKPSC4_5,PWM Clock Prescale Register 4/5"
|
|
hexmask.long.word 0xC 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
|
|
line.long 0x10 "PWM_CNTEN,PWM Counter Enable Register"
|
|
bitfld.long 0x10 4. "CNTEN4,PWM Counter Enable Bit 4" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
|
|
bitfld.long 0x10 2. "CNTEN2,PWM Counter Enable Bit 2" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
|
|
newline
|
|
bitfld.long 0x10 0. "CNTEN0,PWM Counter Enable Bit 0" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
|
|
line.long 0x14 "PWM_CNTCLR,PWM Clear Counter Register"
|
|
bitfld.long 0x14 4. "CNTCLR4,Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
|
|
bitfld.long 0x14 2. "CNTCLR2,Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
|
|
newline
|
|
bitfld.long 0x14 0. "CNTCLR0,Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware." "0: No effect,1: Clear 16-bit PWM counter to 0000H"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PWM_PERIOD0,PWM Period Register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PWM_PERIOD2,PWM Period Register 2"
|
|
hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PWM_PERIOD4,PWM Period Register 4"
|
|
hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
|
|
group.long 0x50++0x17
|
|
line.long 0x0 "PWM_CMPDAT0,PWM Comparator Register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
|
|
line.long 0x4 "PWM_CMPDAT1,PWM Comparator Register 1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
|
|
line.long 0x8 "PWM_CMPDAT2,PWM Comparator Register 2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
|
|
line.long 0xC "PWM_CMPDAT3,PWM Comparator Register 3"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
|
|
line.long 0x10 "PWM_CMPDAT4,PWM Comparator Register 4"
|
|
hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
|
|
line.long 0x14 "PWM_CMPDAT5,PWM Comparator Register 5"
|
|
hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as.."
|
|
group.long 0x70++0xB
|
|
line.long 0x0 "PWM_DTCTL0_1,PWM Dead-time Control Register 0/1"
|
|
bitfld.long 0x0 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
|
|
bitfld.long 0x0 16. "DTEN,Enable Dead-time Insertion for PWM Pair(Write Protect)\n(PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive .." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
|
|
line.long 0x4 "PWM_DTCTL2_3,PWM Dead-time Control Register 2/3"
|
|
bitfld.long 0x4 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
|
|
bitfld.long 0x4 16. "DTEN,Enable Dead-time Insertion for PWM Pair(Write Protect)\n(PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive .." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
|
|
line.long 0x8 "PWM_DTCTL4_5,PWM Dead-time Control Register 4/5"
|
|
bitfld.long 0x8 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
|
|
bitfld.long 0x8 16. "DTEN,Enable Dead-time Insertion for PWM Pair(Write Protect)\n(PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive .." "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
|
|
newline
|
|
hexmask.long.word 0x8 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register."
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "PWM_CNT0,PWM Counter Register 0"
|
|
bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter."
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "PWM_CNT2,PWM Counter Register 2"
|
|
bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter."
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x0 "PWM_CNT4,PWM Counter Register 4"
|
|
bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter."
|
|
group.long 0xB0++0x2B
|
|
line.long 0x0 "PWM_WGCTL0,PWM Generation Register 0"
|
|
bitfld.long 0x0 26.--27. "PRDPCTL5,PWM Period Center Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?"
|
|
bitfld.long 0x0 24.--25. "PRDPCTL4,PWM Period Center Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "PRDPCTL3,PWM Period Center Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?"
|
|
bitfld.long 0x0 20.--21. "PRDPCTL2,PWM Period Center Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "PRDPCTL1,PWM Period Center Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?"
|
|
bitfld.long 0x0 16.--17. "PRDPCTL0,PWM Period Center Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type." "0: Do nothing,1: PWM period (center) point output Low,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "ZPCTL5,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
|
|
bitfld.long 0x0 8.--9. "ZPCTL4,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "ZPCTL3,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
|
|
bitfld.long 0x0 4.--5. "ZPCTL2,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "ZPCTL1,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
|
|
bitfld.long 0x0 0.--1. "ZPCTL0,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0." "0: Do nothing,1: PWM zero point output Low,?,?"
|
|
line.long 0x4 "PWM_WGCTL1,PWM Generation Register 1"
|
|
bitfld.long 0x4 26.--27. "CMPDCTL5,PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?"
|
|
bitfld.long 0x4 24.--25. "CMPDCTL4,PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?"
|
|
newline
|
|
bitfld.long 0x4 22.--23. "CMPDCTL3,PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?"
|
|
bitfld.long 0x4 20.--21. "CMPDCTL2,PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?"
|
|
newline
|
|
bitfld.long 0x4 18.--19. "CMPDCTL1,PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?"
|
|
bitfld.long 0x4 16.--17. "CMPDCTL0,PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4." "0: Do nothing,1: PWM compare down point output Low,?,?"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "CMPUCTL5,PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?"
|
|
bitfld.long 0x4 8.--9. "CMPUCTL4,PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "CMPUCTL3,PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?"
|
|
bitfld.long 0x4 4.--5. "CMPUCTL2,PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "CMPUCTL1,PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?"
|
|
bitfld.long 0x4 0.--1. "CMPUCTL0,PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4." "0: Do nothing,1: PWM compare up point output Low,?,?"
|
|
line.long 0x8 "PWM_MSKEN,PWM Mask Enable Register"
|
|
bitfld.long 0x8 5. "MSKEN5,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
|
|
bitfld.long 0x8 4. "MSKEN4,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
|
|
newline
|
|
bitfld.long 0x8 3. "MSKEN3,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
|
|
bitfld.long 0x8 2. "MSKEN2,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
|
|
newline
|
|
bitfld.long 0x8 1. "MSKEN1,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
|
|
bitfld.long 0x8 0. "MSKEN0,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data." "0: PWM output signal is non-masked,1: PWM output signal is masked and output MSKDATn.."
|
|
line.long 0xC "PWM_MSK,PWM Mask Data Register"
|
|
bitfld.long 0xC 5. "MSKDAT5,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
|
|
bitfld.long 0xC 4. "MSKDAT4,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
|
|
newline
|
|
bitfld.long 0xC 3. "MSKDAT3,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
|
|
bitfld.long 0xC 2. "MSKDAT2,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
|
|
newline
|
|
bitfld.long 0xC 1. "MSKDAT1,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
|
|
bitfld.long 0xC 0. "MSKDAT0,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n." "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
|
|
line.long 0x10 "PWM_BNF,PWM Brake Noise Filter Register"
|
|
bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select\nFor PWM0 setting:" "0: Brake 1 pin source come from PWM0_BRAKE1,1: Reserved."
|
|
bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select\nFor PWM0 setting:" "0: Brake 0 pin source come from PWM0_BRAKE0,1: Reserved."
|
|
newline
|
|
bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: The state of pin PWM_BRAKE1 is passed to the..,1: The inversed state of pin PWM_BRAKE1 is passed.."
|
|
bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
|
|
bitfld.long 0x10 8. "BRK1NFEN,PWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled"
|
|
newline
|
|
bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: The state of pin PWM_BRAKE0 is passed to the..,1: The inversed state of pin PWM_BRAKE10 is passed.."
|
|
bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
|
|
bitfld.long 0x10 0. "BRK0NFEN,PWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled"
|
|
line.long 0x14 "PWM_FAILBRK,PWM System Fail Brake Control Register"
|
|
bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
|
|
bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
|
|
line.long 0x18 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0/1"
|
|
bitfld.long 0x18 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?"
|
|
bitfld.long 0x18 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?"
|
|
newline
|
|
bitfld.long 0x18 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
|
|
bitfld.long 0x18 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM_BRAKE1 pin as level-detect brake source..,1: PWM_BRAKE1 pin as level-detect brake source.."
|
|
newline
|
|
bitfld.long 0x18 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM_BRAKE0 pin as level-detect brake source..,1: PWM_BRAKE0 pin as level-detect brake source.."
|
|
bitfld.long 0x18 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
|
|
newline
|
|
bitfld.long 0x18 5. "BRKP1EEN,Enable PWM_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
|
|
bitfld.long 0x18 4. "BRKP0EEN,Enable PWM_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
|
|
line.long 0x1C "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2/3"
|
|
bitfld.long 0x1C 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?"
|
|
bitfld.long 0x1C 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?"
|
|
newline
|
|
bitfld.long 0x1C 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
|
|
bitfld.long 0x1C 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM_BRAKE1 pin as level-detect brake source..,1: PWM_BRAKE1 pin as level-detect brake source.."
|
|
newline
|
|
bitfld.long 0x1C 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM_BRAKE0 pin as level-detect brake source..,1: PWM_BRAKE0 pin as level-detect brake source.."
|
|
bitfld.long 0x1C 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
|
|
newline
|
|
bitfld.long 0x1C 5. "BRKP1EEN,Enable PWM_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
|
|
bitfld.long 0x1C 4. "BRKP0EEN,Enable PWM_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
|
|
line.long 0x20 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4/5"
|
|
bitfld.long 0x20 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?"
|
|
bitfld.long 0x20 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?"
|
|
newline
|
|
bitfld.long 0x20 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
|
|
bitfld.long 0x20 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM_BRAKE1 pin as level-detect brake source..,1: PWM_BRAKE1 pin as level-detect brake source.."
|
|
newline
|
|
bitfld.long 0x20 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM_BRAKE0 pin as level-detect brake source..,1: PWM_BRAKE0 pin as level-detect brake source.."
|
|
bitfld.long 0x20 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
|
|
newline
|
|
bitfld.long 0x20 5. "BRKP1EEN,Enable PWM_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
|
|
bitfld.long 0x20 4. "BRKP0EEN,Enable PWM_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
|
|
line.long 0x24 "PWM_POLCTL,PWM Pin Polar Inverse Register"
|
|
bitfld.long 0x24 5. "PINV5,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
|
|
bitfld.long 0x24 4. "PINV4,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
|
|
newline
|
|
bitfld.long 0x24 3. "PINV3,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
|
|
bitfld.long 0x24 2. "PINV2,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
|
|
newline
|
|
bitfld.long 0x24 1. "PINV1,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
|
|
bitfld.long 0x24 0. "PINV0,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output." "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
|
|
line.long 0x28 "PWM_POEN,PWM Output Enable Register"
|
|
bitfld.long 0x28 5. "POEN5,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
|
|
bitfld.long 0x28 4. "POEN4,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
|
|
newline
|
|
bitfld.long 0x28 3. "POEN3,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
|
|
bitfld.long 0x28 2. "POEN2,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
|
|
newline
|
|
bitfld.long 0x28 1. "POEN1,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
|
|
bitfld.long 0x28 0. "POEN0,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
|
|
wgroup.long 0xDC++0x3
|
|
line.long 0x0 "PWM_SWBRK,PWM Software Brake Control Register"
|
|
bitfld.long 0x0 10. "BRKLTRG4,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
|
|
bitfld.long 0x0 9. "BRKLTRG2,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BRKLTRG0,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
|
|
bitfld.long 0x0 2. "BRKETRG4,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BRKETRG2,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
|
|
bitfld.long 0x0 0. "BRKETRG0,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0,1"
|
|
group.long 0xE0++0xF
|
|
line.long 0x0 "PWM_INTEN0,PWM Interrupt Enable Register 0"
|
|
bitfld.long 0x0 29. "CMPDIEN5,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
|
|
bitfld.long 0x0 28. "CMPDIEN4,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 27. "CMPDIEN3,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
|
|
bitfld.long 0x0 26. "CMPDIEN2,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 25. "CMPDIEN1,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
|
|
bitfld.long 0x0 24. "CMPDIEN0,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 21. "CMPUIEN5,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
|
|
bitfld.long 0x0 20. "CMPUIEN4,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "CMPUIEN3,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
|
|
bitfld.long 0x0 18. "CMPUIEN2,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 17. "CMPUIEN1,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
|
|
bitfld.long 0x0 16. "CMPUIEN0,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "PIEN4,PWM Period Point Interrupt Enable Bit 4\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
|
|
bitfld.long 0x0 10. "PIEN2,PWM Period Point Interrupt Enable Bit 2\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "PIEN0,PWM Period Point Interrupt Enable Bit 0\nNote: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
|
|
bitfld.long 0x0 4. "ZIEN4,PWM Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "ZIEN2,PWM Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
|
|
bitfld.long 0x0 0. "ZIEN0,PWM Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode." "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
|
|
line.long 0x4 "PWM_INTEN1,PWM Interrupt Enable Register 1"
|
|
bitfld.long 0x4 10. "BRKLIEN4_5,PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
|
|
bitfld.long 0x4 9. "BRKLIEN2_3,PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
|
|
newline
|
|
bitfld.long 0x4 8. "BRKLIEN0_1,PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
|
|
bitfld.long 0x4 2. "BRKEIEN4_5,PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "BRKEIEN2_3,PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled"
|
|
bitfld.long 0x4 0. "BRKEIEN0_1,PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled"
|
|
line.long 0x8 "PWM_INTSTS0,PWM Interrupt Flag Register 0"
|
|
bitfld.long 0x8 29. "CMPDIF5,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
|
|
bitfld.long 0x8 28. "CMPDIF4,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "CMPDIF3,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
|
|
bitfld.long 0x8 26. "CMPDIF2,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "CMPDIF1,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
|
|
bitfld.long 0x8 24. "CMPDIF0,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "CMPUIFn,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 .."
|
|
bitfld.long 0x8 12. "PIF4,PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "PIF2,PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
|
|
bitfld.long 0x8 8. "PIF0,PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ZIF4,PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
|
|
bitfld.long 0x8 2. "ZIF2,PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ZIF0,PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
|
|
line.long 0xC "PWM_INTSTS1,PWM Interrupt Flag Register 1"
|
|
rbitfld.long 0xC 29. "BRKLSTS5,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
|
|
rbitfld.long 0xC 28. "BRKLSTS4,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
|
|
newline
|
|
rbitfld.long 0xC 27. "BRKLSTS3,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
|
|
rbitfld.long 0xC 26. "BRKLSTS2,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
|
|
newline
|
|
rbitfld.long 0xC 25. "BRKLSTS1,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
|
|
rbitfld.long 0xC 24. "BRKLSTS0,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel n level-detect brake state is released,1: When PWM channel n level-detect brake detects a.."
|
|
newline
|
|
rbitfld.long 0xC 21. "BRKESTS5,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
|
|
rbitfld.long 0xC 20. "BRKESTS4,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
|
|
newline
|
|
rbitfld.long 0xC 19. "BRKESTS3,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
|
|
rbitfld.long 0xC 18. "BRKESTS2,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
|
|
newline
|
|
rbitfld.long 0xC 17. "BRKESTS1,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
|
|
rbitfld.long 0xC 16. "BRKESTS0,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared EPWM will release brake state until current EPWM period finished. The EPWM waveform.." "0: PWM channel n edge-detect brake state is released,1: When PWM channel n edge-detect brake detects a.."
|
|
newline
|
|
bitfld.long 0xC 13. "BRKLIF5,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
|
|
bitfld.long 0xC 12. "BRKLIF4,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
|
|
newline
|
|
bitfld.long 0xC 11. "BRKLIF3,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
|
|
bitfld.long 0xC 10. "BRKLIF2,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
|
|
newline
|
|
bitfld.long 0xC 9. "BRKLIF1,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
|
|
bitfld.long 0xC 8. "BRKLIF0,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
|
|
newline
|
|
bitfld.long 0xC 5. "BRKEIF5,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
|
|
bitfld.long 0xC 4. "BRKEIF4,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
|
|
newline
|
|
bitfld.long 0xC 3. "BRKEIF3,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
|
|
bitfld.long 0xC 2. "BRKEIF2,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
|
|
newline
|
|
bitfld.long 0xC 1. "BRKEIF1,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
|
|
bitfld.long 0xC 0. "BRKEIF0,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register." "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
|
|
group.long 0xF8++0x7
|
|
line.long 0x0 "PWM_ADCTS0,PWM Trigger ADC Source Select Register 0"
|
|
bitfld.long 0x0 31. "TRGEN3,PWM_CH3 Trigger ADC Enable Bit" "0: PWM_CH3 Trigger ADC function Disabled,1: PWM_CH3 Trigger ADC function Enabled"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,PWM_CH3 Trigger ADC Source Select"
|
|
newline
|
|
bitfld.long 0x0 23. "TRGEN2,PWM_CH2 Trigger ADC Enable Bit" "0: PWM_CH2 Trigger ADC function Disabled,1: PWM_CH2 Trigger ADC function Enabled"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,PWM_CH2 Trigger ADC Source Select"
|
|
newline
|
|
bitfld.long 0x0 15. "TRGEN1,PWM_CH1 Trigger ADC Enable Bit" "0: PWM_CH1 Trigger ADC function Disabled,1: PWM_CH1 Trigger ADC function Enabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,PWM_CH1 Trigger ADC Source Select"
|
|
newline
|
|
bitfld.long 0x0 7. "TRGEN0,PWM_CH0 Trigger ADC Enable Bit" "0: PWM_CH0 Trigger ADC function Disabled,1: PWM_CH0 Trigger ADC function Enabled"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,PWM_CH0 Trigger ADC Source Select"
|
|
line.long 0x4 "PWM_ADCTS1,PWM Trigger ADC Source Select Register 1"
|
|
bitfld.long 0x4 15. "TRGEN5,PWM_CH5 Trigger ADC Enable Bit" "0: PWM_CH5 Trigger ADC function Disabled,1: PWM_CH5 Trigger ADC function Enabled"
|
|
hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,PWM_CH5 Trigger ADC Source Select"
|
|
newline
|
|
bitfld.long 0x4 7. "TRGEN4,PWM_CH4 Trigger ADC Enable Bit" "0: PWM_CH4 Trigger ADC function Disabled,1: PWM_CH4 Trigger ADC function Enabled"
|
|
hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,PWM_CH4 Trigger ADC Source Select"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "PWM_SSCTL,PWM Synchronous Start Control Register"
|
|
bitfld.long 0x0 8.--9. "SSRC,PWM Synchronous Start Source Select Bits" "0: Synchronous start source come from PWM0,1: Reserved.,?,?"
|
|
bitfld.long 0x0 4. "SSEN4,PWM Synchronous Start Function Enable Bit 4\nWhen synchronous start function is enabled the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SSEN2,PWM Synchronous Start Function Enable Bit 2\nWhen synchronous start function is enabled the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
|
|
bitfld.long 0x0 0. "SSEN0,PWM Synchronous Start Function Enable Bit 0\nWhen synchronous start function is enabled the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)." "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
|
|
wgroup.long 0x114++0x3
|
|
line.long 0x0 "PWM_SSTRG,PWM Synchronous Start Trigger Register"
|
|
bitfld.long 0x0 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only)\nPWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit.." "0,1"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "PWM_STATUS,PWM Status Register"
|
|
bitfld.long 0x0 21. "ADCTRG5,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
|
|
bitfld.long 0x0 20. "ADCTRG4,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
|
|
newline
|
|
bitfld.long 0x0 19. "ADCTRG3,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
|
|
bitfld.long 0x0 18. "ADCTRG2,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
|
|
newline
|
|
bitfld.long 0x0 17. "ADCTRG1,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
|
|
bitfld.long 0x0 16. "ADCTRG0,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1." "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
|
|
newline
|
|
bitfld.long 0x0 4. "CNTMAX4,Time-base Counter 4 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value"
|
|
bitfld.long 0x0 2. "CNTMAX2,Time-base Counter 2 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
|
|
newline
|
|
bitfld.long 0x0 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1." "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "PWM_WECAP,PWM Trigger Window Mode ECAP Source Select Register"
|
|
bitfld.long 0x0 23. "TRGWEC2,PWM Trigger Window Mode ECAP2 Enable Bit" "0: PWM Trigger ECAP2 function Disabled,1: PWM Trigger ECAP2 function Enabled"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TRGWECSEL2,PWM Trigger Window Mode ECAP2 Source Select"
|
|
newline
|
|
bitfld.long 0x0 15. "TRGWEC1,PWM Trigger Window Mode ECAP1 Enable Bit" "0: PWM Trigger ECAP1 function Disabled,1: PWM Trigger ECAP1 function Enabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TRGWECSEL1,PWM Trigger Window Mode ECAP1 Source Select"
|
|
newline
|
|
bitfld.long 0x0 7. "TRGWEC0,PWM Trigger Window Mode ECAP0 Enable Bit" "0: PWM Trigger ECAP0 function Disabled,1: PWM Trigger ECAP0 function Enabled"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TRGWECSEL0,PWM Trigger Window Mode ECAP0 Source Select"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "PWM_CAPINEN,PWM Capture Input Enable Register"
|
|
bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
|
|
bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
|
|
newline
|
|
bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
|
|
bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
|
|
newline
|
|
bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
|
|
bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled. The..,1: PWM Channel capture input path Enabled. The.."
|
|
line.long 0x4 "PWM_CAPCTL,PWM Capture Control Register"
|
|
bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
|
|
bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
|
|
newline
|
|
bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
|
|
bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
|
|
newline
|
|
bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
|
|
bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
|
|
newline
|
|
bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
|
|
bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
|
|
bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
|
|
bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
|
|
bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
|
|
newline
|
|
bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
|
|
bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
|
|
newline
|
|
bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
|
|
bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
|
|
newline
|
|
bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
|
|
bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
|
|
newline
|
|
bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
|
|
bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
|
|
newline
|
|
bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
|
|
bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled. RCAPDAT/FCAPDAT..,1: Capture function Enabled. Capture latched the.."
|
|
rgroup.long 0x208++0x33
|
|
line.long 0x0 "PWM_CAPSTS,PWM Capture Status Register"
|
|
bitfld.long 0x0 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
|
|
bitfld.long 0x0 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
|
|
bitfld.long 0x0 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
|
|
bitfld.long 0x0 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
|
|
bitfld.long 0x0 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
|
|
bitfld.long 0x0 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
|
|
bitfld.long 0x0 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF." "0,1"
|
|
line.long 0x4 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0"
|
|
hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x8 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0"
|
|
hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0xC "PWM_RCAPDAT1,PWM Rising Capture Data Register 1"
|
|
hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x10 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1"
|
|
hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x14 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2"
|
|
hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x18 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2"
|
|
hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x1C "PWM_RCAPDAT3,PWM Rising Capture Data Register 3"
|
|
hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x20 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x24 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x28 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4"
|
|
hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x2C "PWM_RCAPDAT5,PWM Rising Capture Data Register 5"
|
|
hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x30 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5"
|
|
hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register."
|
|
group.long 0x250++0x7
|
|
line.long 0x0 "PWM_CAPIEN,PWM Capture Interrupt Enable Register"
|
|
bitfld.long 0x0 13. "CAPFIEN5,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
bitfld.long 0x0 12. "CAPFIEN4,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "CAPFIEN3,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
bitfld.long 0x0 10. "CAPFIEN2,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "CAPFIEN1,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
bitfld.long 0x0 8. "CAPFIEN0,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CAPRIEN5,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
bitfld.long 0x0 4. "CAPRIEN4,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "CAPRIEN3,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
bitfld.long 0x0 2. "CAPRIEN2,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "CAPRIEN1,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
bitfld.long 0x0 0. "CAPRIEN0,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
line.long 0x4 "PWM_CAPIF,PWM Capture Interrupt Flag Register"
|
|
bitfld.long 0x4 13. "CFLIF5,PWM Capture Falling Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
bitfld.long 0x4 12. "CFLIF4,PWM Capture Falling Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
newline
|
|
bitfld.long 0x4 11. "CFLIF3,PWM Capture Falling Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
bitfld.long 0x4 10. "CFLIF2,PWM Capture Falling Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
newline
|
|
bitfld.long 0x4 9. "CFLIF1,PWM Capture Falling Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
bitfld.long 0x4 8. "CFLIF0,PWM Capture Falling Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
|
|
newline
|
|
bitfld.long 0x4 5. "CRLIF5,PWM Capture Rising Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
bitfld.long 0x4 4. "CRLIF4,PWM Capture Rising Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
newline
|
|
bitfld.long 0x4 3. "CRLIF3,PWM Capture Rising Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
bitfld.long 0x4 2. "CRLIF2,PWM Capture Rising Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
newline
|
|
bitfld.long 0x4 1. "CRLIF1,PWM Capture Rising Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
bitfld.long 0x4 0. "CRLIF0,PWM Capture Rising Latch Interrupt Flag\nNote1: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
rgroup.long 0x304++0x3
|
|
line.long 0x0 "PWM_PBUF0,PWM PERIOD0 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
|
|
rgroup.long 0x30C++0x3
|
|
line.long 0x0 "PWM_PBUF2,PWM PERIOD2 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
|
|
rgroup.long 0x314++0x3
|
|
line.long 0x0 "PWM_PBUF4,PWM PERIOD4 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register."
|
|
rgroup.long 0x31C++0x17
|
|
line.long 0x0 "PWM_CMPBUF0,PWM CMPDAT0 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x4 "PWM_CMPBUF1,PWM CMPDAT1 Buffer"
|
|
hexmask.long.word 0x4 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x8 "PWM_CMPBUF2,PWM CMPDAT2 Buffer"
|
|
hexmask.long.word 0x8 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0xC "PWM_CMPBUF3,PWM CMPDAT3 Buffer"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x10 "PWM_CMPBUF4,PWM CMPDAT4 Buffer"
|
|
hexmask.long.word 0x10 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
line.long 0x14 "PWM_CMPBUF5,PWM CMPDAT5 Buffer"
|
|
hexmask.long.word 0x14 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register."
|
|
tree.end
|
|
tree "SCS (System Controller Space)"
|
|
base ad:0xE000E000
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "SYST_CTRL,SysTick Control and Status Register"
|
|
bitfld.long 0x0 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register." "0,1"
|
|
bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
|
|
newline
|
|
bitfld.long 0x0 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
|
|
bitfld.long 0x0 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
|
|
line.long 0x4 "SYST_LOAD,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0."
|
|
line.long 0x8 "SYST_VAL,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the.."
|
|
group.long 0xD04++0x13
|
|
line.long 0x0 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x0 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: If AIRCR.BFHFNMINS is 0 this bit is RAZ/WI from Non-secure state." "0: No effect.\nNMI exception is not pending,1: Changes NMI exception state to pending.\nNMI.."
|
|
bitfld.long 0x0 30. "NMIPENDCLR,NMI Bit-pending Bit\nNote: If AIRCR.BFHFNMINS is 0 this bit is RAZ/WI from Non-secure state." "0: No effect,1: Clear pending status"
|
|
newline
|
|
bitfld.long 0x0 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending." "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
|
|
bitfld.long 0x0 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDSV bit you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time." "0: No effect,1: Removes the pending state from the PendSV.."
|
|
newline
|
|
bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation:" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
|
|
bitfld.long 0x0 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDST bit you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time." "0: No effect,1: Removes the pending state from the SysTick.."
|
|
newline
|
|
rbitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state." "0,1"
|
|
rbitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
hexmask.long.word 0x0 12.--20. 1. "VECTPENDING,Number of the Highest Pended Exception"
|
|
hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Number of the Current Active Exception"
|
|
line.long 0x4 "VTOR,Vector Table Offset Register"
|
|
hexmask.long.tbyte 0x4 9.--31. 1. "TBLOFF,Table Offset Bits\nThe vector table address for the selected Security state."
|
|
line.long 0x8 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register this field should be 0x05FA otherwise the write action will be ignored.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the.."
|
|
bitfld.long 0x8 15. "ENDIANNESS,Data Endianness" "0: Little-endian,1: Big-endian"
|
|
newline
|
|
bitfld.long 0x8 14. "PRIS,Priority Secure Exceptions Bit" "0: Priority ranges of Secure and Non-secure..,?"
|
|
bitfld.long 0x8 13. "BFHFNMINS,BusFault HardFault AndNMI Non-secure Enable Bit" "0: BusFault HardFault and NMI are Secure.1 =..,?"
|
|
newline
|
|
bitfld.long 0x8 3. "SYSRESETREQS,System Reset Request Secure Only Bit" "0: SYSRESETREQ functionality is available to both..,?"
|
|
bitfld.long 0x8 2. "SYSRESETREQ,System Reset Request Bit\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's.." "0,1"
|
|
line.long 0xC "SCR,System Control Register"
|
|
bitfld.long 0xC 4. "SEVONPEND,Send Event on Pending\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE. If the processor is not waiting for an event the event is registered and affects the next WFE.\nThe processor also wakes.." "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
|
|
bitfld.long 0xC 3. "SLEEPDEEPS,SLEEPDEEP Bit Accessible Selection\nControl whether the SLEEPDEEP bit is only accessible from the Secure state." "0: The SLEEPDEEP bit is accessible from both..,1: The SLEEPDEEP bit behaves as RAZ/WI when.."
|
|
newline
|
|
bitfld.long 0xC 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode." "0: Sleep,1: Deep sleep"
|
|
bitfld.long 0xC 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application." "0: Do not sleep when returning to Thread mode,1: Enters sleep or deep sleep on return from an ISR.."
|
|
line.long 0x10 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x10 18. "BP,Branch Prediction Enable Bit\nThis bit is RAZ/WI." "0,1"
|
|
bitfld.long 0x10 17. "IC,Instruction Cache Enable Bit\nThis bit is RAZ/WI." "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "DC,Data Cache Enable Bit\nThis bit is RAZ/WI." "0,1"
|
|
bitfld.long 0x10 10. "STKOFHFNMIGN,Stack Overflow in HardFault and NMI Ignore\nThis bit is RAZ/WI." "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "BFHFNMIGN,BusFault in HardFault or NMI Ignore\nThis bit is RAZ/WI." "0,1"
|
|
bitfld.long 0x10 4. "DIV_0_TRP,Divide by Zero Trap\nThis bit is RAZ/WI." "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "UNALIGN_TRP,Unaligned Trap\nThis bit is RAO/WI." "0,1"
|
|
group.long 0xD1C++0xB
|
|
line.long 0x0 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x0 30.--31. "PRI_11,Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x4 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x4 30.--31. "PRI_15,Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PRI_14,Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
|
|
line.long 0x8 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x8 21. "HARDFAULTPENDED,HardFault Exception Pended State \nThis bit indicates and allows modification of the pending state after HardFault exception corresponding to the selected Security state.\nThis bit is banked between Security states.\nThe possible values.." "0: HardFault exception not pending for the selected..,1: HardFault exception pending for the selected.."
|
|
tree.end
|
|
tree "SYS (System Control Registers)"
|
|
base ad:0x40000000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SYS_PDID,Part Device Identification Number Register"
|
|
hexmask.long 0x0 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used."
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "SYS_RSTSTS,System Reset Status Register"
|
|
bitfld.long 0x0 8. "CPULKRF,CPU Lockup Reset Flag\nThe CPU Lockup reset flag is set by hardware if Cortex-M23 lockup happened.\nNote 1: Write 1 to clear this bit to 0.\nNote 2: When CPU lockup happened under ICE is connected this flag will set to 1 but chip will not reset." "0: No reset from CPU lockup happened,1: Write 1 to clear this bit to 0"
|
|
bitfld.long 0x0 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset the Cortex-M23 core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0." "0: No reset from CPU,1: The Cortex-M23 core and FMC are reset by.."
|
|
newline
|
|
bitfld.long 0x0 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M23 core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from the Cortex-M23,1: The Cortex-M23 had issued the reset signal to.."
|
|
bitfld.long 0x0 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-out Detector to indicate the previous reset source and BOD reset flag is not set in SPD mode when BOD reset occur.\nNote: Write 1 to clear this bit to 0." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.."
|
|
newline
|
|
bitfld.long 0x0 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source and LVR reset flag is not set in SPD mode when LVR reset occur.\nNote: Write 1 to clear this bit to 0." "0: No reset from LVR,1: The LVR controller had issued the reset signal.."
|
|
bitfld.long 0x0 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote 1: Write 1 to clear this bit to 0.\nNote 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit.." "0: No reset from watchdog timer or window watchdog..,1: Write 1 to clear this bit to 0"
|
|
newline
|
|
bitfld.long 0x0 1. "PINRF,nRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.."
|
|
bitfld.long 0x0 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued the.."
|
|
line.long 0x4 "SYS_IPRST0,Peripheral Reset Control Register 0"
|
|
bitfld.long 0x4 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to.." "0: Processor core normal operation,1: Processor core one-shot reset"
|
|
bitfld.long 0x4 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the.." "0: Chip normal operation,1: Chip one-shot reset"
|
|
line.long 0x8 "SYS_IPRST1,Peripheral Reset Control Register 1"
|
|
bitfld.long 0x8 28. "ADCRST,ADC Controller Reset" "0: ADC controller normal operation,1: ADC controller reset"
|
|
bitfld.long 0x8 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
|
|
newline
|
|
bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
|
|
bitfld.long 0x8 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
|
|
newline
|
|
bitfld.long 0x8 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
|
|
bitfld.long 0x8 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
|
|
newline
|
|
bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
|
|
bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
|
|
newline
|
|
bitfld.long 0x8 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
|
|
line.long 0xC "SYS_IPRST2,Peripheral Reset Control Register 2"
|
|
bitfld.long 0xC 26. "ECAP0RST,ECAP0 Controller Reset" "0: ECAP0 controller normal operation,1: ECAP0 controller reset"
|
|
bitfld.long 0xC 16. "PWM0RST,PWM0 Controller Reset" "0: PWM0 controller normal operation,1: PWM0 controller reset"
|
|
newline
|
|
bitfld.long 0xC 8. "USCI0RST,USCI0 Controller Reset" "0: USCI0 controller normal operation,1: USCI0 controller reset"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "SYS_BODCTL,Brown-out Detector Control Register"
|
|
rbitfld.long 0x0 31. "WRBUSY,Write Busy Flag (Read Only)\nIf SYS_BODCTL is written this bit is asserted automatically by hardware and is de-asserted when write procedure is finished." "0: SYS_BODCTL register is ready for write operation..,1: SYS_BODCTL register is busy on the last write.."
|
|
bitfld.long 0x0 16.--18. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [23:21]).\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Brown-out Detector threshold voltage is 2.2V,1: Brown-out Detector threshold voltage is 2.2V,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Without de-glitch function,1: 4 system clock (HCLK),?,?,?,?,?,?"
|
|
bitfld.long 0x0 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register." "0: BOD output is sampled by LIRC clock,1: 4 system clock (HCLK),?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote 1: After enabling the bit the LVR function will be active with.." "0: Low Voltage Reset function Disabled,1: After enabling the bit"
|
|
rbitfld.long 0x0 6. "BODOUT,Brown-out Detector Output Status (Read Only)\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0 BOD function disabled this bit always responds 0." "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
|
|
newline
|
|
bitfld.long 0x0 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\nNote 1: The BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote 2: This bit is write protected. Refer to the.." "0: BOD operate in normal mode (default),1: The BOD consumes about 100uA in normal mode"
|
|
bitfld.long 0x0 4. "BODIF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0." "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the VDD is.."
|
|
newline
|
|
bitfld.long 0x0 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit.\nNote 1: When the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled.." "0: Brown-out 'INTERRUPT' function Enabled,1: When the Brown-out Detector function is enabled"
|
|
bitfld.long 0x0 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBODEN (CONFIG0 [23]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "SYS_PORCTL0,Power-on Reset Controller Register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "PORMASK,Power-on Reset Mask Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can mask internal POR signal to avoid.."
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PB7MFP,PB.7 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x0 20.--23. 1. "PB5MFP,PB.5 Multi-function Pin Selection"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PB4MFP,PB.4 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x0 12.--15. 1. "PB3MFP,PB.3 Multi-function Pin Selection"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "PB2MFP,PB.2 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PB1MFP,PB.1 Multi-function Pin Selection"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PB0MFP,PB.0 Multi-function Pin Selection"
|
|
line.long 0x4 "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "PB15MFP,PB.15 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x4 24.--27. 1. "PB14MFP,PB.14 Multi-function Pin Selection"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "PB13MFP,PB.13 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x4 16.--19. 1. "PB12MFP,PB.12 Multi-function Pin Selection"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "PB11MFP,PB.11 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x4 4.--7. 1. "PB9MFP,PB.9 Multi-function Pin Selection"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "PB8MFP,PB.8 Multi-function Pin Selection"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "SYS_GPC_MFPH,GPIOC High Byte Multiple Function Control Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PC14MFP,PC.14 Multi-function Pin Selection"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "SYS_GPE_MFPH,GPIOE High Byte Multiple Function Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PE15MFP,PE.15 Multi-function Pin Selection"
|
|
line.long 0x4 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "PF1MFP,PF.1 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PF0MFP,PF.0 Multi-function Pin Selection"
|
|
group.long 0x84++0x7
|
|
line.long 0x0 "SYS_GPB_MFOS,GPIOB Multiple Function Output Select Register"
|
|
bitfld.long 0x0 15. "PB15MFOS,PB.15 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.15 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x0 14. "PB14MFOS,PB.14 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.14 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x0 13. "PB13MFOS,PB.13 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.13 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x0 12. "PB12MFOS,PB.12 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.12 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x0 11. "PB11MFOS,PB.11 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.11 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x0 9. "PB9MFOS,PB.9 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.9 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x0 8. "PB8MFOS,PB.8 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.8 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x0 7. "PB7MFOS,PB.7 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.7 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x0 5. "PB5MFOS,PB.5 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.5 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x0 4. "PB4MFOS,PB.4 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.4 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x0 3. "PB3MFOS,PB.3 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.3 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x0 2. "PB2MFOS,PB.2 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.2 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x0 1. "PB1MFOS,PB.1 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.1 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x0 0. "PB0MFOS,PB.0 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PB.0 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
line.long 0x4 "SYS_GPC_MFOS,GPIOC Multiple Function Output Select Register"
|
|
bitfld.long 0x4 14. "PC14MFOS,PC.14 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PC.14 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "SYS_GPF_MFOS,GPIOF Multiple Function Output Select Register"
|
|
bitfld.long 0x0 1. "PF1MFOS,PF.1 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PF.1 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x0 0. "PF0MFOS,PF.0 Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for PF.0 pin." "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "SYS_REGLCTL,Register Lock Control Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "REGLCTL,Register Lock Control Code \nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is completed the.."
|
|
group.long 0x1D8++0x3
|
|
line.long 0x0 "SYS_CPUCFG,CPU General Configuration Register"
|
|
bitfld.long 0x0 0. "INTRTEN,CPU Interrupt Realtime Enable Bit\nWhen this bit is 0 the latency of CPU entering interrupt service routine (ISR) will be various but shorter.\nWhen this bit is 1 the latency of CPU entering ISR will be kept constant." "0: CPU Interrupt Realtime Disabled,1: CPU Interrupt Realtime Enabled"
|
|
group.long 0x1EC++0x3
|
|
line.long 0x0 "SYS_PORCTL1,Power-on Reset Controller Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.."
|
|
tree.end
|
|
tree "TIMER (Timer Controller)"
|
|
base ad:0x0
|
|
tree "TMR0"
|
|
base ad:0x40050000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TIMER0_CTL,Timer0 Control Register"
|
|
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
|
|
newline
|
|
bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
|
|
bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
|
|
newline
|
|
rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
|
|
bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
|
|
bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection\nNote: Set this bit to 0 ." "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Reserved."
|
|
newline
|
|
bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
|
|
bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
|
|
line.long 0x4 "TIMER0_CMP,Timer0 Comparator Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
|
|
line.long 0x8 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
|
|
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
|
|
line.long 0xC "TIMER0_CNT,Timer0 Data Register"
|
|
rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TIMER0_CAP,Timer0 Capture Data Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
|
|
group.long 0x14++0xB
|
|
line.long 0x0 "TIMER0_EXTCTL,Timer0 External Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
|
|
bitfld.long 0x0 20.--21. "CAPLSEL,Capture Trigger Length Selection\nNote: This function is exclusively operational in Timer0 and Timer2." "0: TMx_EXT (x= 0 2) pin input capture length 1..,1: TMx_EXT (x= 0 2) pin input capture length 2..,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,?,?,?,?,?,?,?"
|
|
bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: 000 and 001 are only available when CAPSRC (TIMERx_CTL[22]) is 0." "0: Capture Function source is from TMx_EXT (x=0~3)..,1: Capture Function source is from TMx_EXT (x=0~3)..,?,?,?,?,?,?"
|
|
bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
|
|
bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin internal clock or external..,1: TMx_EXT (x= 0~3) pin internal clock or external.."
|
|
newline
|
|
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
|
|
bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
|
|
line.long 0x4 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
|
|
rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
|
|
bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin internal clock or external..,1: TMx_EXT (x= 0~3) pin internal clock or external.."
|
|
line.long 0x8 "TIMER0_TRGCTL,Timer0 Trigger Control Register"
|
|
bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
|
|
bitfld.long 0x8 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
|
|
newline
|
|
bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIMER0_CAPNF,Timer0 Capture Input Noise Filter Register"
|
|
bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
|
|
rgroup.long 0x78++0xB
|
|
line.long 0x0 "TIMER0_CAP1,Timer0 Capture Data 1 Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDATn,Timer Capture Data n Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and CAPLSEL(TIMERx_EXTCTL[21:20]) not equal to 00b CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting .."
|
|
line.long 0x4 "TIMER0_CAP2,Timer0 Capture Data 2 Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CAPDATn,Timer Capture Data n Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and CAPLSEL(TIMERx_EXTCTL[21:20]) not equal to 00b CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting .."
|
|
line.long 0x8 "TIMER0_CAP3,Timer0 Capture Data 3 Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "CAPDATn,Timer Capture Data n Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and CAPLSEL(TIMERx_EXTCTL[21:20]) not equal to 00b CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting .."
|
|
tree.end
|
|
tree "TMR1"
|
|
base ad:0x40050100
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TIMER1_CTL,Timer1 Control Register"
|
|
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
|
|
newline
|
|
bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
|
|
bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
|
|
newline
|
|
rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
|
|
bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
|
|
bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection\nNote: Set this bit to 0 ." "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Reserved."
|
|
newline
|
|
bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
|
|
bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
|
|
line.long 0x4 "TIMER1_CMP,Timer1 Comparator Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
|
|
line.long 0x8 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
|
|
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
|
|
line.long 0xC "TIMER1_CNT,Timer1 Data Register"
|
|
rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TIMER1_CAP,Timer1 Capture Data Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
|
|
group.long 0x14++0xB
|
|
line.long 0x0 "TIMER1_EXTCTL,Timer1 External Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
|
|
bitfld.long 0x0 20.--21. "CAPLSEL,Capture Trigger Length Selection\nNote: This function is exclusively operational in Timer0 and Timer2." "0: TMx_EXT (x= 0 2) pin input capture length 1..,1: TMx_EXT (x= 0 2) pin input capture length 2..,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,?,?,?,?,?,?,?"
|
|
bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: 000 and 001 are only available when CAPSRC (TIMERx_CTL[22]) is 0." "0: Capture Function source is from TMx_EXT (x=0~3)..,1: Capture Function source is from TMx_EXT (x=0~3)..,?,?,?,?,?,?"
|
|
bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
|
|
bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin internal clock or external..,1: TMx_EXT (x= 0~3) pin internal clock or external.."
|
|
newline
|
|
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
|
|
bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
|
|
line.long 0x4 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
|
|
rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
|
|
bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin internal clock or external..,1: TMx_EXT (x= 0~3) pin internal clock or external.."
|
|
line.long 0x8 "TIMER1_TRGCTL,Timer1 Trigger Control Register"
|
|
bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
|
|
bitfld.long 0x8 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
|
|
newline
|
|
bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIMER1_CAPNF,Timer1 Capture Input Noise Filter Register"
|
|
bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
|
|
tree.end
|
|
tree "TMR2"
|
|
base ad:0x40051000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TIMER2_CTL,Timer2 Control Register"
|
|
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
|
|
newline
|
|
bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
|
|
bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
|
|
newline
|
|
rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
|
|
bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
|
|
bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection\nNote: Set this bit to 0 ." "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Reserved."
|
|
newline
|
|
bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
|
|
bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
|
|
line.long 0x4 "TIMER2_CMP,Timer2 Comparator Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
|
|
line.long 0x8 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
|
|
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
|
|
line.long 0xC "TIMER2_CNT,Timer2 Data Register"
|
|
rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TIMER2_CAP,Timer2 Capture Data Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
|
|
group.long 0x14++0xB
|
|
line.long 0x0 "TIMER2_EXTCTL,Timer2 External Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
|
|
bitfld.long 0x0 20.--21. "CAPLSEL,Capture Trigger Length Selection\nNote: This function is exclusively operational in Timer0 and Timer2." "0: TMx_EXT (x= 0 2) pin input capture length 1..,1: TMx_EXT (x= 0 2) pin input capture length 2..,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,?,?,?,?,?,?,?"
|
|
bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: 000 and 001 are only available when CAPSRC (TIMERx_CTL[22]) is 0." "0: Capture Function source is from TMx_EXT (x=0~3)..,1: Capture Function source is from TMx_EXT (x=0~3)..,?,?,?,?,?,?"
|
|
bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
|
|
bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin internal clock or external..,1: TMx_EXT (x= 0~3) pin internal clock or external.."
|
|
newline
|
|
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
|
|
bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
|
|
line.long 0x4 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
|
|
rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
|
|
bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin internal clock or external..,1: TMx_EXT (x= 0~3) pin internal clock or external.."
|
|
line.long 0x8 "TIMER2_TRGCTL,Timer2 Trigger Control Register"
|
|
bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
|
|
bitfld.long 0x8 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
|
|
newline
|
|
bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIMER2_CAPNF,Timer2 Capture Input Noise Filter Register"
|
|
bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
|
|
rgroup.long 0x78++0xB
|
|
line.long 0x0 "TIMER2_CAP1,Timer2 Capture Data 1 Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDATn,Timer Capture Data n Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and CAPLSEL(TIMERx_EXTCTL[21:20]) not equal to 00b CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting .."
|
|
line.long 0x4 "TIMER2_CAP2,Timer2 Capture Data 2 Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CAPDATn,Timer Capture Data n Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and CAPLSEL(TIMERx_EXTCTL[21:20]) not equal to 00b CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting .."
|
|
line.long 0x8 "TIMER2_CAP3,Timer2 Capture Data 3 Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "CAPDATn,Timer Capture Data n Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and CAPLSEL(TIMERx_EXTCTL[21:20]) not equal to 00b CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting .."
|
|
tree.end
|
|
tree "TMR3"
|
|
base ad:0x40051100
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TIMER3_CTL,Timer3 Control Register"
|
|
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\nNote 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
|
|
newline
|
|
bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
|
|
bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
|
|
newline
|
|
rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
|
|
bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1 and select PCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
|
|
bitfld.long 0x0 22. "CAPSRC,Capture Pin Source Selection\nNote: Set this bit to 0 ." "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Reserved."
|
|
newline
|
|
bitfld.long 0x0 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
|
|
bitfld.long 0x0 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is Enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
|
|
line.long 0x4 "TIMER3_CMP,Timer3 Comparator Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote 1: Never write 0x0 or 0x1 in CMPDAT field .."
|
|
line.long 0x8 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
|
|
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
|
|
line.long 0xC "TIMER3_CNT,Timer3 Data Register"
|
|
rbitfld.long 0xC 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the.." "0: Reset operation is done,1: Reset operation triggered by writing TIMERx_CNT.."
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TIMER3_CAP,Timer3 Capture Data Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the.."
|
|
group.long 0x14++0xB
|
|
line.long 0x0 "TIMER3_EXTCTL,Timer3 External Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Set INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source."
|
|
bitfld.long 0x0 20.--21. "CAPLSEL,Capture Trigger Length Selection\nNote: This function is exclusively operational in Timer0 and Timer2." "0: TMx_EXT (x= 0 2) pin input capture length 1..,1: TMx_EXT (x= 0 2) pin input capture length 2..,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from external TMx..,?,?,?,?,?,?,?"
|
|
bitfld.long 0x0 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling edge..,1: Capture event occurred when detect rising edge..,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: 000 and 001 are only available when CAPSRC (TIMERx_CTL[22]) is 0." "0: Capture Function source is from TMx_EXT (x=0~3)..,1: Capture Function source is from TMx_EXT (x=0~3)..,?,?,?,?,?,?"
|
|
bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
|
|
bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin internal clock or external..,1: TMx_EXT (x= 0~3) pin internal clock or external.."
|
|
newline
|
|
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
|
|
bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source." "0: Capture source Disabled,1: Capture source Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
|
|
line.long 0x4 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
|
|
rbitfld.long 0x4 1. "CAPIFOV,Capture Latch Interrupt Flag Overrun Status (Read Only)\nNote: This bit will be cleared automatically when user clear corresponding CAPIF." "0: Capture latch happened when the corresponding..,1: Capture latch happened when the corresponding.."
|
|
bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer.." "0: TMx_EXT (x= 0~3) pin internal clock or external..,1: TMx_EXT (x= 0~3) pin internal clock or external.."
|
|
line.long 0x8 "TIMER3_TRGCTL,Timer3 Trigger Control Register"
|
|
bitfld.long 0x8 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
|
|
bitfld.long 0x8 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
|
|
newline
|
|
bitfld.long 0x8 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal." "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIMER3_CAPNF,Timer3 Capture Input Noise Filter Register"
|
|
bitfld.long 0x0 8.--10. "CAPNFCNT,Capture Edge Detector Noise Filter Count\nThese bits control the capture filter counter to count from 0 to CAPNFCNT." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "CAPNFSEL,Capture Edge Detector Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0. "CAPNFEN,Capture Noise Filter Enable" "0: Capture Noise Filter function Disabled,1: Capture Noise Filter function Enabled"
|
|
tree.end
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
tree "UART0"
|
|
base ad:0x40070000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "UART0_DAT,UART Receive/Transmit Buffer Register"
|
|
bitfld.long 0x0 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "UART1_DAT,UART Receive/Transmit Buffer Register"
|
|
bitfld.long 0x0 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
|
|
line.long 0x4 "UART0_INTEN,UART Interrupt Enable Register"
|
|
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
|
|
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
|
|
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
|
|
newline
|
|
bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
|
|
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
|
|
newline
|
|
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
|
|
bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
|
|
bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
|
|
bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "UART1_INTEN,UART Interrupt Enable Register"
|
|
bitfld.long 0x0 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
|
|
bitfld.long 0x0 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
|
|
bitfld.long 0x0 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
|
|
bitfld.long 0x0 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
|
|
bitfld.long 0x0 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
|
|
bitfld.long 0x0 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
|
|
bitfld.long 0x0 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
|
|
line.long 0x4 "UART0_FIFO,UART FIFO Control Register"
|
|
hexmask.long.byte 0x4 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
|
|
bitfld.long 0x4 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)."
|
|
bitfld.long 0x4 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
|
|
newline
|
|
bitfld.long 0x4 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "UART1_FIFO,UART FIFO Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
|
|
bitfld.long 0x0 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)."
|
|
bitfld.long 0x0 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
|
|
newline
|
|
bitfld.long 0x0 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
|
|
line.long 0x4 "UART0_LINE,UART Line Control Register"
|
|
bitfld.long 0x4 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
|
|
bitfld.long 0x4 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
|
|
newline
|
|
bitfld.long 0x4 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
|
|
bitfld.long 0x4 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
|
|
bitfld.long 0x4 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
|
|
newline
|
|
bitfld.long 0x4 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data." "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
|
|
bitfld.long 0x4 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
|
|
newline
|
|
bitfld.long 0x4 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "UART1_LINE,UART Line Control Register"
|
|
bitfld.long 0x0 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
|
|
bitfld.long 0x0 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
|
|
newline
|
|
bitfld.long 0x0 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
|
|
bitfld.long 0x0 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
|
|
bitfld.long 0x0 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
|
|
newline
|
|
bitfld.long 0x0 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data." "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
|
|
bitfld.long 0x0 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
|
|
line.long 0x4 "UART0_MODEM,UART Modem Control Register"
|
|
rbitfld.long 0x4 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
|
|
bitfld.long 0x4 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1110 and Figure 6.1111 for UART function mode.\nNote 2: Refer to Figure 6.1114 and Figure 6.1115 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
|
|
newline
|
|
bitfld.long 0x4 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-To-Send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "UART1_MODEM,UART Modem Control Register"
|
|
rbitfld.long 0x0 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
|
|
bitfld.long 0x0 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1110 and Figure 6.1111 for UART function mode.\nNote 2: Refer to Figure 6.1114 and Figure 6.1115 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
|
|
newline
|
|
bitfld.long 0x0 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-To-Send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
|
|
line.long 0x4 "UART0_MODEMSTS,UART Modem Status Register"
|
|
bitfld.long 0x4 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
|
|
rbitfld.long 0x4 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
|
|
newline
|
|
bitfld.long 0x4 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "UART1_MODEMSTS,UART Modem Status Register"
|
|
bitfld.long 0x0 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
|
|
rbitfld.long 0x0 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
|
|
newline
|
|
bitfld.long 0x0 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
|
|
line.long 0x4 "UART0_FIFOSTS,UART FIFO Status Register"
|
|
rbitfld.long 0x4 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
|
|
rbitfld.long 0x4 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
|
|
newline
|
|
rbitfld.long 0x4 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
|
|
bitfld.long 0x4 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
|
|
newline
|
|
rbitfld.long 0x4 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
|
|
rbitfld.long 0x4 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
|
|
rbitfld.long 0x4 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
|
|
newline
|
|
rbitfld.long 0x4 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
hexmask.long.byte 0x4 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
|
|
newline
|
|
bitfld.long 0x4 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
|
|
bitfld.long 0x4 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
|
|
newline
|
|
bitfld.long 0x4 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
|
|
bitfld.long 0x4 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
|
|
newline
|
|
bitfld.long 0x4 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
|
|
bitfld.long 0x4 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
|
|
newline
|
|
bitfld.long 0x4 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "UART1_FIFOSTS,UART FIFO Status Register"
|
|
rbitfld.long 0x0 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
|
|
rbitfld.long 0x0 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
|
|
newline
|
|
rbitfld.long 0x0 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
|
|
bitfld.long 0x0 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
|
|
newline
|
|
rbitfld.long 0x0 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
|
|
rbitfld.long 0x0 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
|
|
rbitfld.long 0x0 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
|
|
newline
|
|
rbitfld.long 0x0 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
hexmask.long.byte 0x0 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
|
|
newline
|
|
bitfld.long 0x0 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
|
|
bitfld.long 0x0 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
|
|
newline
|
|
bitfld.long 0x0 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
|
|
bitfld.long 0x0 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
|
|
newline
|
|
bitfld.long 0x0 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
|
|
bitfld.long 0x0 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
|
|
newline
|
|
bitfld.long 0x0 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
|
|
line.long 0x4 "UART0_INTSTS,UART Interrupt Status Register"
|
|
rbitfld.long 0x4 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
|
|
rbitfld.long 0x4 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x4 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
|
|
bitfld.long 0x4 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x4 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
|
|
rbitfld.long 0x4 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x4 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
|
|
rbitfld.long 0x4 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x4 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated."
|
|
rbitfld.long 0x4 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x4 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
|
|
rbitfld.long 0x4 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x4 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
|
|
rbitfld.long 0x4 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x4 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
|
|
rbitfld.long 0x4 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x4 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
|
|
bitfld.long 0x4 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is read only.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x4 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.\nNote: This bit is read only.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "UART1_INTSTS,UART Interrupt Status Register"
|
|
rbitfld.long 0x0 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
|
|
rbitfld.long 0x0 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x0 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
|
|
bitfld.long 0x0 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x0 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
|
|
rbitfld.long 0x0 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x0 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
|
|
rbitfld.long 0x0 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x0 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated."
|
|
rbitfld.long 0x0 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x0 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
|
|
rbitfld.long 0x0 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x0 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
|
|
rbitfld.long 0x0 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x0 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
|
|
rbitfld.long 0x0 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x0 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
|
|
bitfld.long 0x0 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is read only.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x0 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.\nNote: This bit is read only.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
|
|
line.long 0x4 "UART0_TOUT,UART Time-out Register"
|
|
hexmask.long.byte 0x4 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time."
|
|
hexmask.long.byte 0x4 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "UART1_TOUT,UART Time-out Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time."
|
|
hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
|
|
line.long 0x4 "UART0_BAUD,UART Baud Rate Divider Register"
|
|
bitfld.long 0x4 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
|
|
bitfld.long 0x4 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.114."
|
|
hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.114."
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "UART1_BAUD,UART Baud Rate Divider Register"
|
|
bitfld.long 0x0 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
|
|
bitfld.long 0x0 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.114."
|
|
hexmask.long.word 0x0 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.114."
|
|
line.long 0x4 "UART0_IRDA,UART IrDA Control Register"
|
|
bitfld.long 0x4 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
|
|
bitfld.long 0x4 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
|
|
newline
|
|
bitfld.long 0x4 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "UART1_IRDA,UART IrDA Control Register"
|
|
bitfld.long 0x0 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
|
|
bitfld.long 0x0 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
|
|
line.long 0x4 "UART0_ALTCTL,UART Alternate Control/Status Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
|
|
bitfld.long 0x4 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?"
|
|
newline
|
|
bitfld.long 0x4 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
|
|
rbitfld.long 0x4 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x4 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
|
|
bitfld.long 0x4 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
|
|
newline
|
|
bitfld.long 0x4 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
|
|
bitfld.long 0x4 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode \nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
|
|
group.long 0x2C++0x7
|
|
line.long 0x0 "UART1_ALTCTL,UART Alternate Control/Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
|
|
bitfld.long 0x0 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?"
|
|
newline
|
|
bitfld.long 0x0 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
|
|
rbitfld.long 0x0 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x0 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
|
|
bitfld.long 0x0 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
|
|
newline
|
|
bitfld.long 0x0 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
|
|
bitfld.long 0x0 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode \nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
|
|
line.long 0x4 "UART0_FUNCSEL,UART Function Select Register"
|
|
bitfld.long 0x4 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
|
|
bitfld.long 0x4 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
|
|
newline
|
|
bitfld.long 0x4 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
|
|
bitfld.long 0x4 0.--2. "FUNCSEL,Function Select" "0: UART function,?,?,?,?,?,?,?"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "UART1_FUNCSEL,UART Function Select Register"
|
|
bitfld.long 0x0 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
|
|
bitfld.long 0x0 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
|
|
bitfld.long 0x0 0.--2. "FUNCSEL,Function Select" "0: UART function,?,?,?,?,?,?,?"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "UART0_BRCOMP,UART Baud Rate Compensation Register"
|
|
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
|
|
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "UART1_BRCOMP,UART Baud Rate Compensation Register"
|
|
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
|
|
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
|
|
line.long 0x4 "UART0_WKCTL,UART Wake-up Control Register"
|
|
bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
|
|
bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "UART1_WKCTL,UART Wake-up Control Register"
|
|
bitfld.long 0x0 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
|
|
bitfld.long 0x0 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
|
|
line.long 0x4 "UART0_WKSTS,UART Wake-up Status Register"
|
|
bitfld.long 0x4 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
|
|
bitfld.long 0x4 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "UART1_WKSTS,UART Wake-up Status Register"
|
|
bitfld.long 0x0 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
|
|
bitfld.long 0x0 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
|
|
line.long 0x4 "UART0_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "UART1_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x40071000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "UART0_DAT,UART Receive/Transmit Buffer Register"
|
|
bitfld.long 0x0 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "UART1_DAT,UART Receive/Transmit Buffer Register"
|
|
bitfld.long 0x0 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead.."
|
|
line.long 0x4 "UART0_INTEN,UART Interrupt Enable Register"
|
|
bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
|
|
bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
|
|
bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
|
|
newline
|
|
bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
|
|
bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
|
|
newline
|
|
bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
|
|
bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
|
|
bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
|
|
bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "UART1_INTEN,UART Interrupt Enable Register"
|
|
bitfld.long 0x0 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
|
|
bitfld.long 0x0 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
|
|
bitfld.long 0x0 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
|
|
bitfld.long 0x0 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
|
|
bitfld.long 0x0 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
|
|
bitfld.long 0x0 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
|
|
bitfld.long 0x0 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
|
|
line.long 0x4 "UART0_FIFO,UART FIFO Control Register"
|
|
hexmask.long.byte 0x4 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
|
|
bitfld.long 0x4 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)."
|
|
bitfld.long 0x4 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
|
|
newline
|
|
bitfld.long 0x4 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "UART1_FIFO,UART FIFO Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control."
|
|
bitfld.long 0x0 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)."
|
|
bitfld.long 0x0 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
|
|
newline
|
|
bitfld.long 0x0 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote 1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
|
|
line.long 0x4 "UART0_LINE,UART Line Control Register"
|
|
bitfld.long 0x4 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
|
|
bitfld.long 0x4 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
|
|
newline
|
|
bitfld.long 0x4 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
|
|
bitfld.long 0x4 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
|
|
bitfld.long 0x4 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
|
|
newline
|
|
bitfld.long 0x4 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data." "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
|
|
bitfld.long 0x4 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
|
|
newline
|
|
bitfld.long 0x4 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "UART1_LINE,UART Line Control Register"
|
|
bitfld.long 0x0 9. "RXDINV,RX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Received data signal inverted Disabled,1: Before setting this bit"
|
|
bitfld.long 0x0 8. "TXDINV,TX Data Inverted\nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
|
|
newline
|
|
bitfld.long 0x0 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote 1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote 2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
|
|
bitfld.long 0x0 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
|
|
bitfld.long 0x0 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
|
|
newline
|
|
bitfld.long 0x0 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data." "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
|
|
bitfld.long 0x0 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "WLS,Word Length Selection\nThis field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
|
|
line.long 0x4 "UART0_MODEM,UART Modem Control Register"
|
|
rbitfld.long 0x4 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
|
|
bitfld.long 0x4 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1110 and Figure 6.1111 for UART function mode.\nNote 2: Refer to Figure 6.1114 and Figure 6.1115 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
|
|
newline
|
|
bitfld.long 0x4 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-To-Send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "UART1_MODEM,UART Modem Control Register"
|
|
rbitfld.long 0x0 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
|
|
bitfld.long 0x0 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote 1: Refer to Figure 6.1110 and Figure 6.1111 for UART function mode.\nNote 2: Refer to Figure 6.1114 and Figure 6.1115 for RS-485 function mode.\nNote 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
|
|
newline
|
|
bitfld.long 0x0 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-To-Send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote 1: The nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: The nRTS signal control bit is not effective.."
|
|
line.long 0x4 "UART0_MODEMSTS,UART Modem Status Register"
|
|
bitfld.long 0x4 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
|
|
rbitfld.long 0x4 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
|
|
newline
|
|
bitfld.long 0x4 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "UART1_MODEMSTS,UART Modem Status Register"
|
|
bitfld.long 0x0 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
|
|
rbitfld.long 0x0 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
|
|
newline
|
|
bitfld.long 0x0 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it." "0: nCTS input has not change state,1: nCTS input has change state"
|
|
line.long 0x4 "UART0_FIFOSTS,UART FIFO Status Register"
|
|
rbitfld.long 0x4 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
|
|
rbitfld.long 0x4 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
|
|
newline
|
|
rbitfld.long 0x4 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
|
|
bitfld.long 0x4 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
|
|
newline
|
|
rbitfld.long 0x4 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
|
|
rbitfld.long 0x4 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
|
|
rbitfld.long 0x4 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
|
|
newline
|
|
rbitfld.long 0x4 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
hexmask.long.byte 0x4 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
|
|
newline
|
|
bitfld.long 0x4 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
|
|
bitfld.long 0x4 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
|
|
newline
|
|
bitfld.long 0x4 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
|
|
bitfld.long 0x4 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
|
|
newline
|
|
bitfld.long 0x4 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
|
|
bitfld.long 0x4 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
|
|
newline
|
|
bitfld.long 0x4 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "UART1_FIFOSTS,UART FIFO Status Register"
|
|
rbitfld.long 0x0 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
|
|
rbitfld.long 0x0 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
|
|
newline
|
|
rbitfld.long 0x0 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
|
|
bitfld.long 0x0 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
|
|
newline
|
|
rbitfld.long 0x0 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
|
|
rbitfld.long 0x0 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
|
|
rbitfld.long 0x0 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
|
|
newline
|
|
rbitfld.long 0x0 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
hexmask.long.byte 0x0 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
|
|
newline
|
|
bitfld.long 0x0 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
|
|
bitfld.long 0x0 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
|
|
newline
|
|
bitfld.long 0x0 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
|
|
bitfld.long 0x0 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote 2: This bit can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
|
|
newline
|
|
bitfld.long 0x0 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
|
|
bitfld.long 0x0 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
|
|
newline
|
|
bitfld.long 0x0 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
|
|
line.long 0x4 "UART0_INTSTS,UART Interrupt Status Register"
|
|
rbitfld.long 0x4 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
|
|
rbitfld.long 0x4 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x4 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
|
|
bitfld.long 0x4 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x4 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
|
|
rbitfld.long 0x4 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x4 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
|
|
rbitfld.long 0x4 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x4 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
|
|
rbitfld.long 0x4 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x4 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
|
|
rbitfld.long 0x4 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x4 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
|
|
rbitfld.long 0x4 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x4 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
|
|
rbitfld.long 0x4 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x4 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
|
|
bitfld.long 0x4 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is read only.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x4 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.\nNote: This bit is read only.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "UART1_INTSTS,UART Interrupt Status Register"
|
|
rbitfld.long 0x0 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
|
|
rbitfld.long 0x0 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x0 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1." "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
|
|
bitfld.long 0x0 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x0 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: This bit is active when FUNCSEL"
|
|
rbitfld.long 0x0 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x0 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
|
|
rbitfld.long 0x0 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x0 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
|
|
rbitfld.long 0x0 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x0 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
|
|
rbitfld.long 0x0 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x0 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
|
|
rbitfld.long 0x0 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x0 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
|
|
rbitfld.long 0x0 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x0 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
|
|
bitfld.long 0x0 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.\nNote: This bit is read only.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x0 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.\nNote: This bit is read only.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
|
|
line.long 0x4 "UART0_TOUT,UART Time-out Register"
|
|
hexmask.long.byte 0x4 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time."
|
|
hexmask.long.byte 0x4 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "UART1_TOUT,UART Time-out Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time."
|
|
hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
|
|
line.long 0x4 "UART0_BAUD,UART Baud Rate Divider Register"
|
|
bitfld.long 0x4 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
|
|
bitfld.long 0x4 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.114."
|
|
hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.114."
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "UART1_BAUD,UART Baud Rate Divider Register"
|
|
bitfld.long 0x0 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
|
|
bitfld.long 0x0 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.114."
|
|
hexmask.long.word 0x0 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.114."
|
|
line.long 0x4 "UART0_IRDA,UART IrDA Control Register"
|
|
bitfld.long 0x4 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
|
|
bitfld.long 0x4 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
|
|
newline
|
|
bitfld.long 0x4 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "UART1_IRDA,UART IrDA Control Register"
|
|
bitfld.long 0x0 6. "RXINV,IrDA Inverse Receive Input Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
|
|
bitfld.long 0x0 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
|
|
line.long 0x4 "UART0_ALTCTL,UART Alternate Control/Status Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
|
|
bitfld.long 0x4 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?"
|
|
newline
|
|
bitfld.long 0x4 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
|
|
rbitfld.long 0x4 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x4 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
|
|
bitfld.long 0x4 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
|
|
newline
|
|
bitfld.long 0x4 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
|
|
bitfld.long 0x4 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode \nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
|
|
group.long 0x2C++0x7
|
|
line.long 0x0 "UART1_ALTCTL,UART Alternate Control/Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
|
|
bitfld.long 0x0 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?"
|
|
newline
|
|
bitfld.long 0x0 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
|
|
rbitfld.long 0x0 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
|
|
newline
|
|
bitfld.long 0x0 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
|
|
bitfld.long 0x0 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
|
|
newline
|
|
bitfld.long 0x0 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
|
|
bitfld.long 0x0 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode \nNote: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
|
|
line.long 0x4 "UART0_FUNCSEL,UART Function Select Register"
|
|
bitfld.long 0x4 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
|
|
bitfld.long 0x4 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
|
|
newline
|
|
bitfld.long 0x4 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
|
|
bitfld.long 0x4 0.--2. "FUNCSEL,Function Select" "0: UART function,?,?,?,?,?,?,?"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "UART1_FUNCSEL,UART Function Select Register"
|
|
bitfld.long 0x0 7. "TXRXSWP,TX and RX Swap Enable Bit\nSetting this bit Swaps TX pin and RX pin." "0: TX and RX Swap Disabled,1: TX and RX Swap Enabled"
|
|
bitfld.long 0x0 6. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set. The TX and RX complete current task before TX and RX are disabled. When TX and RX are disabled the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
|
|
bitfld.long 0x0 0.--2. "FUNCSEL,Function Select" "0: UART function,?,?,?,?,?,?,?"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "UART0_BRCOMP,UART Baud Rate Compensation Register"
|
|
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
|
|
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "UART1_BRCOMP,UART Baud Rate Compensation Register"
|
|
bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
|
|
hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
|
|
line.long 0x4 "UART0_WKCTL,UART Wake-up Control Register"
|
|
bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
|
|
bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "UART1_WKCTL,UART Wake-up Control Register"
|
|
bitfld.long 0x0 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
|
|
bitfld.long 0x0 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode." "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
|
|
line.long 0x4 "UART0_WKSTS,UART Wake-up Status Register"
|
|
bitfld.long 0x4 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
|
|
bitfld.long 0x4 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "UART1_WKSTS,UART Wake-up Status Register"
|
|
bitfld.long 0x0 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
|
|
bitfld.long 0x0 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
|
|
line.long 0x4 "UART0_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "UART1_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
|
|
tree.end
|
|
tree.end
|
|
tree "USCI (Universal Serial Control Interface)"
|
|
base ad:0x0
|
|
tree "UI2C (Inter-Integrated Circuit)"
|
|
base ad:0x400D0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "UI2C_CTL,USCI Control Register"
|
|
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "UI2C_BRGEN,USCI Baud Rate Generator Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "NFCNT,Noise Filter Count \nThe register bits control the input filter width.\n0 : filter width 3*PCLK \n1 : filter width 4*PCLK\nN : filter width (3+N)*PCKL\nNote: Filter width Min :3*PCLK Max : 18*PCLK"
|
|
hexmask.long.word 0x0 16.--25. 1. "CLKDIV,Clock Divider"
|
|
newline
|
|
hexmask.long.byte 0x0 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK."
|
|
bitfld.long 0x0 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
|
|
bitfld.long 0x0 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?"
|
|
bitfld.long 0x0 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
|
|
newline
|
|
bitfld.long 0x0 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "UI2C_LINECTL,USCI Line Control Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
|
|
bitfld.long 0x0 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x0 "UI2C_TXDAT,USCI Transmit Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "UI2C_RXDAT,USCI Receive Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions which defined in I2C."
|
|
group.long 0x44++0x23
|
|
line.long 0x0 "UI2C_DEVADDR0,USCI Device Address Register 0"
|
|
hexmask.long.word 0x0 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB the AA bits are compared to the bits DEVADDR[9:8] to check for address match where the X is R/W bit. Then.."
|
|
line.long 0x4 "UI2C_DEVADDR1,USCI Device Address Register 1"
|
|
hexmask.long.word 0x4 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB the AA bits are compared to the bits DEVADDR[9:8] to check for address match where the X is R/W bit. Then.."
|
|
line.long 0x8 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
|
|
hexmask.long.word 0x8 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set to zero .."
|
|
line.long 0xC "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
|
|
hexmask.long.word 0xC 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set to zero .."
|
|
line.long 0x10 "UI2C_WKCTL,USCI Wake-up Control Register"
|
|
bitfld.long 0x10 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according receive 'START'..,1: The chip is woken up according address match"
|
|
bitfld.long 0x10 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
line.long 0x14 "UI2C_WKSTS,USCI Wake-up Status Register"
|
|
bitfld.long 0x14 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
|
|
line.long 0x18 "UI2C_PROTCTL,USCI Protocol Control Register"
|
|
bitfld.long 0x18 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
|
|
hexmask.long.word 0x18 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero.."
|
|
newline
|
|
bitfld.long 0x18 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the.." "0: The monitor mode Disabled,1: The monitor mode Enabled"
|
|
bitfld.long 0x18 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt." "0: SCL output will be forced high due to open drain..,1: I2C module may act as a slave peripheral just.."
|
|
newline
|
|
bitfld.long 0x18 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags.." "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active"
|
|
bitfld.long 0x18 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
|
|
newline
|
|
bitfld.long 0x18 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
|
|
bitfld.long 0x18 2. "STO,I2C STOP Control" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "AA,Assert Acknowledge Control" "0,1"
|
|
bitfld.long 0x18 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
line.long 0x1C "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
|
|
bitfld.long 0x1C 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master." "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
|
|
bitfld.long 0x1C 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12]))." "0: The error interrupt Disabled,1: The error interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x1C 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected." "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
|
|
bitfld.long 0x1C 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master." "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x1C 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected." "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
|
|
bitfld.long 0x1C 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected." "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x1C 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event." "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
|
|
line.long 0x20 "UI2C_PROTSTS,USCI Protocol Status Register"
|
|
bitfld.long 0x20 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This.." "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
|
|
bitfld.long 0x20 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL.." "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
|
|
newline
|
|
bitfld.long 0x20 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
|
|
bitfld.long 0x20 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
|
|
newline
|
|
bitfld.long 0x20 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
|
|
bitfld.long 0x20 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: The device is not selected as slave,1: The device is selected as slave"
|
|
newline
|
|
bitfld.long 0x20 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
|
|
bitfld.long 0x20 12. "ERRIF,Error Interrupt Flag\nNote 1: It is cleared by software writing 1 into this bit\nNote 2: This bit is set for slave mode and user must write 1 into STO register to the defined 'not addressed' slave mode." "0: An I2C error has not been detected,1: It is cleared by software writing 1 into this.."
|
|
newline
|
|
bitfld.long 0x20 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost"
|
|
bitfld.long 0x20 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
|
|
newline
|
|
bitfld.long 0x20 9. "STORIF,Stop Condition Received Interrupt Flag\nNote 1: It is cleared by software writing 1 into this bit" "0: A stop condition has not yet been detected,1: It is cleared by software writing 1 into this bit"
|
|
bitfld.long 0x20 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However this bit also indicates that a repeated start condition has been detected on slave.." "0: A start condition has not yet been detected,1: A start condition has been detected"
|
|
newline
|
|
bitfld.long 0x20 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
|
|
bitfld.long 0x20 5. "TOIF,Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
|
|
group.long 0x88++0x7
|
|
line.long 0x0 "UI2C_ADMAT,I2C Slave Match Address Register"
|
|
bitfld.long 0x0 1. "ADMAT1,USCI Address 1 Match Status Register\nWhen address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
|
|
bitfld.long 0x0 0. "ADMAT0,USCI Address 0 Match Status Register\nWhen address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
|
|
line.long 0x4 "UI2C_TMCTL,I2C Timing Configure Control Register"
|
|
hexmask.long.word 0x4 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.\nNote: Hold time adjust function can only work in master mode when slave mode this field should set as 0"
|
|
hexmask.long.word 0x4 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.."
|
|
tree.end
|
|
tree "USPI (Serial Peripheral Interface)"
|
|
base ad:0x400D0000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "USPI_CTL,USCI Control Register"
|
|
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
|
|
line.long 0x4 "USPI_INTEN,USCI Interrupt Enable Register"
|
|
bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\nNote: The receive finish event happens when hardware receives the last bit of RX data into shift data unit." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
|
|
bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\nNote: For SPI master mode the receive start event happens when SPI master sends slave select active and spi clock to the external.." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\nNote: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
|
|
bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\nNote: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
|
|
line.long 0x8 "USPI_BRGEN,USCI Baud Rate Generator Register"
|
|
hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider"
|
|
bitfld.long 0x8 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
|
|
newline
|
|
bitfld.long 0x8 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
|
|
bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor." "0: fDIV_CLK,1: fPROT_CLK,?,?"
|
|
newline
|
|
bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
|
|
bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
|
|
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
|
|
bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
|
|
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
|
|
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
|
|
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift unit.\nNote: In SPI.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
|
|
line.long 0x4 "USPI_LINECTL,USCI Line Control Register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
|
|
bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol the control.." "0: No effect,1: The control signal will be inverted before its.."
|
|
newline
|
|
bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pins." "0: Data output values of USCIx_DAT0/1 pins are not..,1: Data output values of USCIx_DAT0/1 pins are.."
|
|
bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x0 "USPI_TXDAT,USCI Transmit Data Register"
|
|
bitfld.long 0x0 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field."
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "USPI_RXDAT,USCI Receive Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer."
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
|
|
bitfld.long 0x0 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the receive-related counters state machine.."
|
|
bitfld.long 0x0 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
|
|
newline
|
|
bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared. Should only be.."
|
|
bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared. Should only be.."
|
|
bitfld.long 0x0 6. "TXUDRIEN,Slave Transmit Under Run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
|
|
bitfld.long 0x0 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]) the corresponding interrupt request is activated. It is cleared by software writes 1.." "0: A transmit buffer under-run event has not been..,1: A transmit buffer under-run event has been.."
|
|
bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
|
|
newline
|
|
bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for the.."
|
|
bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software writes 1 to.." "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been detected"
|
|
newline
|
|
bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
|
|
bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
group.long 0x54++0x13
|
|
line.long 0x0 "USPI_WKCTL,USCI Wake-up Control Register"
|
|
bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
|
|
bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
line.long 0x4 "USPI_WKSTS,USCI Wake-up Status Register"
|
|
bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
|
|
line.long 0x8 "USPI_PROTCTL,USCI Protocol Control Register"
|
|
bitfld.long 0x8 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
|
|
bitfld.long 0x8 28. "TXUDRPOL,Transmit Under-run Data Polarity -for Slave\nThis bit defines the transmitting data value of USCIx_DAT1 when no data is available for transferring." "0: The output data value is 0 if TX under run event..,1: The output data value is 1 if TX under run event.."
|
|
newline
|
|
hexmask.long.word 0x8 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period -Slave Only\nIn Slave mode this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC USPI_BRGEN[5]) between the two edges of input SCLK will assert the.."
|
|
bitfld.long 0x8 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "SUSPITV,Suspend Interval -Master Only\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
|
|
bitfld.long 0x8 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable -Master Only" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
|
|
bitfld.long 0x8 2. "SS,Slave Select Control -Master Only\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select back to inactive state.\nNote: In SPI protocol the internal slave.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "SLV3WIRE,Slave 3-wire Mode Selection -Slave Only\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
|
|
bitfld.long 0x8 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
|
|
line.long 0xC "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
|
|
bitfld.long 0xC 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: The Slave mode bit count error interrupt Disabled,1: The Slave mode bit count error interrupt Enabled"
|
|
bitfld.long 0xC 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event." "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled"
|
|
newline
|
|
bitfld.long 0xC 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active." "0: Slave select active interrupt generation Disabled,1: Slave select active interrupt generation Enabled"
|
|
bitfld.long 0xC 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive." "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation Enabled"
|
|
line.long 0x10 "USPI_PROTSTS,USCI Protocol Status Register"
|
|
rbitfld.long 0x10 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1. This bit indicates whether the.." "0: Slave transmit under run event does not occur,1: Slave transmit under run event occurs"
|
|
rbitfld.long 0x10 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
|
|
newline
|
|
rbitfld.long 0x10 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus." "0: The slave select line status is 0,1: The slave select line status is 1"
|
|
bitfld.long 0x10 9. "SSACTIF,Slave Select Active Interrupt Flag -for Slave Only\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to active,1: The slave select signal has changed to active"
|
|
newline
|
|
bitfld.long 0x10 8. "SSINAIF,Slave Select Inactive Interrupt Flag -for Slave Only\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
|
|
bitfld.long 0x10 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag -for Slave Only\nNote: It is cleared by software write 1 to this bit. If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]) bit count error event occurs." "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
|
|
newline
|
|
bitfld.long 0x10 5. "SLVTOIF,Slave Time-out Interrupt Flag -for Slave Only\nNote: It is cleared by software write 1 to this bit" "0: Slave time-out event did not occur,1: Slave time-out event occurred"
|
|
bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The receive end event happens when hardware receives the last bit of RX data into shift data unit." "0: Receive end event did not occur,1: Receive end event occurred"
|
|
newline
|
|
bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. For SPI master mode the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode the.." "0: Receive start event did not occur,1: Receive start event occurred"
|
|
bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit end event happens when hardware sends the last bit of TX data from shift data unit." "0: Transmit end event did not occur,1: Transmit end event occurred"
|
|
newline
|
|
bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit." "0: Transmit start event did not occur,1: Transmit start event occurred"
|
|
tree.end
|
|
tree "UUART (Universal Asynchronous Receiver/Transmitter)"
|
|
base ad:0x400D0000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "UUART_CTL,USCI Control Register"
|
|
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
|
|
line.long 0x4 "UUART_INTEN,USCI Interrupt Enable Register"
|
|
bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event." "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
|
|
bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event." "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
|
|
bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event." "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
|
|
line.long 0x8 "UUART_BRGEN,USCI Baud Rate Generator Register"
|
|
hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.."
|
|
hexmask.long.byte 0x8 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
|
|
newline
|
|
bitfld.long 0x8 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
|
|
bitfld.long 0x8 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
|
|
newline
|
|
bitfld.long 0x8 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter." "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
|
|
bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor." "0: fSAMP_CLK is selected to fDIV_CLK,1: fSAMP_CLK is selected to fPROT_CLK,?,?"
|
|
newline
|
|
bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)." "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
|
|
bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)." "0: Peripheral device clock fPCLK,1: Reserved."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
|
|
bitfld.long 0x0 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 10." "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,?,?"
|
|
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
|
|
newline
|
|
bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
|
|
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
|
|
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
|
|
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
|
|
line.long 0x4 "UUART_LINECTL,USCI Line Control Register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\nNote: In UART.."
|
|
bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal." "0: No effect,1: The control signal will be inverted before its.."
|
|
newline
|
|
bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin." "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of data.."
|
|
bitfld.long 0x4 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x0 "UUART_TXDAT,USCI Transmit Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "UUART_RXDAT,USCI Receive Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])."
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
|
|
bitfld.long 0x0 17. "RXRST,Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1." "0: No effect,1: It is cleared automatically after one PCLK cycle"
|
|
bitfld.long 0x0 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.."
|
|
newline
|
|
bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared (filling level is.."
|
|
bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared (filling level is.."
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
|
|
bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
|
|
bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
newline
|
|
bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software.." "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
|
|
bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
|
|
newline
|
|
bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
group.long 0x54++0x13
|
|
line.long 0x0 "UUART_WKCTL,USCI Wake-up Control Register"
|
|
bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
|
|
bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
line.long 0x4 "UUART_WKSTS,USCI Wake-up Status Register"
|
|
bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
|
|
line.long 0x8 "UUART_PROTCTL,USCI Protocol Control Register"
|
|
bitfld.long 0x8 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
|
|
bitfld.long 0x8 30. "DGE,Deglitch Enable Bit\nNote 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
|
|
newline
|
|
bitfld.long 0x8 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
|
|
bitfld.long 0x8 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information." "0: Stick parity Disabled,1: Stick parity Enabled"
|
|
newline
|
|
hexmask.long.word 0x8 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data.."
|
|
hexmask.long.byte 0x8 11.--14. 1. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode."
|
|
newline
|
|
bitfld.long 0x8 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
|
|
bitfld.long 0x8 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
|
|
newline
|
|
bitfld.long 0x8 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
|
|
bitfld.long 0x8 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART asserted nRTS signal automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2:.." "0: nRTS auto direction control Disabled,1: This bit is used for nRTS auto direction control.."
|
|
newline
|
|
bitfld.long 0x8 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
|
|
bitfld.long 0x8 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
|
|
newline
|
|
bitfld.long 0x8 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
|
|
bitfld.long 0x8 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame." "0: The parity bit Disabled,1: The parity bit Enabled"
|
|
newline
|
|
bitfld.long 0x8 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame." "0: The number of stop bits is 1,1: The number of stop bits is 2"
|
|
line.long 0xC "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
|
|
bitfld.long 0xC 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt." "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
|
|
bitfld.long 0xC 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
|
|
line.long 0x10 "UUART_PROTSTS,USCI Protocol Status Register"
|
|
rbitfld.long 0x10 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
|
|
rbitfld.long 0x10 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal." "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
|
|
newline
|
|
bitfld.long 0x10 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the.." "0: Auto-baud rate detect counter is not overrun,1: This bit is set at the same time of ABRDETIF"
|
|
rbitfld.long 0x10 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver." "0: The receiver is Idle,1: The receiver is BUSY"
|
|
newline
|
|
bitfld.long 0x10 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set the auto-baud rate interrupt will be generated. This bit can be set 4 times.." "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
|
|
bitfld.long 0x10 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
|
|
newline
|
|
bitfld.long 0x10 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
|
|
bitfld.long 0x10 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits." "0: No parity error is generated,1: Parity error is generated"
|
|
newline
|
|
bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive finish interrupt status has not occurred,1: A receive finish interrupt status has occurred"
|
|
bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A receive start interrupt status has not occurred,1: A receive start interrupt status has occurred"
|
|
newline
|
|
bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit." "0: A transmit end interrupt status has not occurred,1: A transmit end interrupt status has occurred"
|
|
bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer." "0: A transmit start interrupt status has not occurred,1: It is cleared by software writing one into this.."
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40040000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "WDT_CTL,WDT Control Register"
|
|
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
|
|
rbitfld.long 0x0 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 2 * WDT_CLK.." "0: Set WDTEN bit is completed,1: Set WDTEN bit is synchronizing and not become.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese four bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register."
|
|
bitfld.long 0x0 7. "WDTEN,WDT Enable Bit (Write Protect)\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111 this bit is forced as 1 and user cannot change.." "0: WDT Disabled (This action will reset the..,1: This bit is write protected"
|
|
newline
|
|
bitfld.long 0x0 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
|
|
bitfld.long 0x0 5. "WKF,WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\nNote 1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote 2: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: This bit is write protected"
|
|
newline
|
|
bitfld.long 0x0 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT time-out..,1: This bit is write protected"
|
|
bitfld.long 0x0 3. "IF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
|
|
bitfld.long 0x0 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected." "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
|
|
line.long 0x4 "WDT_ALTCTL,WDT Alternative Control Register"
|
|
bitfld.long 0x4 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.\nUser can select a.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: This bit is write protected,2: This register will be reset to 0 if WDT time-out..,?"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "WDT_RSTCNT,WDT Reset Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "RSTCNT,WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.\nNote 1: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active."
|
|
tree.end
|
|
tree "WWDT (Window Watchdog Timer)"
|
|
base ad:0x40040100
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "WWDT_RLDCNT,WWDT Reload Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.."
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "WWDT_CTL,WWDT Control Register"
|
|
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nNote: WWDT down counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
|
|
hexmask.long.byte 0x0 16.--21. 1. "CMPDAT,WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "PSCSEL,WWDT Counter Prescale Period Selection"
|
|
bitfld.long 0x0 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU." "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "WWDTEN,WWDT Enable Bit" "0: WWDT counter is stopped,1: WWDT counter starts counting"
|
|
line.long 0x4 "WWDT_STATUS,WWDT Status Register"
|
|
bitfld.long 0x4 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
|
|
bitfld.long 0x4 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: WWDT counter value matches CMPDAT"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "WWDT_CNT,WWDT Counter Value Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value."
|
|
tree.end
|
|
AUTOINDENT.OFF
|