1935 lines
106 KiB
Plaintext
1935 lines
106 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: PY32L020 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2025-01-13 NEJ
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; @Manufacturer: PUYA - Puya Semiconductors Co., Ltd
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; @Doc: Generated (TRACE32, build: 175665.), based on:
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; PY32L020xx.svd (Ver. 1.0.0)
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; @Core: Cortex-M0+
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; @Chip: PY32L020F15U6, PY32L020F15P7, PY32L020L15D6
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; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perpy32l020.per 18850 2025-01-14 10:18:27Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC21=Cortex-M1"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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elif (CORENAME()=="CORTEXM0+")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC60=Cortex-M0+"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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else
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC20=Cortex-M0"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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endif
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
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saveout 0xD98 %l 0x2
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hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x40012400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 7. "AWD,ADC analog watchdog flag" "0,1"
|
|
bitfld.long 0x0 4. "OVR,ADC group regular overrun flag" "0,1"
|
|
bitfld.long 0x0 3. "EOSEQ,ADC group regular end of sequence conversions flag" "0,1"
|
|
bitfld.long 0x0 2. "EOC,ADC group regular end of unitary conversion flag" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling flag" "0,1"
|
|
line.long 0x4 "IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 7. "AWDIE,ADC analog watchdog interrupt" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,ADC group regular overrun interrupt" "0,1"
|
|
bitfld.long 0x4 3. "EOSEQIE,ADC group regular end of sequence conversions interrupt" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary conversion interrupt" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling interrupt" "0,1"
|
|
line.long 0x8 "CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC group regular conversion calibration" "0,1"
|
|
bitfld.long 0x8 6.--7. "VERBUFF_SEL,desc VERBUFF_SEL" "0,1,2,3"
|
|
bitfld.long 0x8 5. "VREF_BUFFERE,desc VREF_BUFFERE" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADC group regular conversion stop" "0,1"
|
|
bitfld.long 0x8 2. "ADSTART,ADC group regular conversion start" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADC enable" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADC enable" "0,1"
|
|
line.long 0xC "CFGR1,ADC configuration register 1"
|
|
hexmask.long.byte 0xC 26.--29. 1. "AWDCH,ADC analog watchdog monitored channel selection"
|
|
bitfld.long 0xC 23. "AWDEN,ADC analog watchdog enable on scope ADC group regular" "0,1"
|
|
bitfld.long 0xC 22. "AWDSGL,ADC analog watchdog monitoring a single channel or all channels" "0,1"
|
|
bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer discontinuous mode" "0,1"
|
|
bitfld.long 0xC 14. "WAIT,Wait conversion mode" "0,1"
|
|
bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion mode" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun configuration" "0,1"
|
|
bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger polarity" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 6.--8. "EXTSEL,ADC group regular external trigger source" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 5. "ALIGN,ADC data alignement" "0,1"
|
|
bitfld.long 0xC 3.--4. "RESSEL,ADC data resolution" "0,1,2,3"
|
|
bitfld.long 0xC 2. "SCANDIR,Scan sequence direction" "0,1"
|
|
line.long 0x10 "CFGR2,ADC configuration register 2"
|
|
hexmask.long.byte 0x10 28.--31. 1. "CKMODE,ADC clock mode"
|
|
line.long 0x14 "SMPR,ADC sampling time register"
|
|
bitfld.long 0x14 0.--2. "SMP,Sampling time selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "TR,ADC analog watchdog 1 threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT,ADC analog watchdog threshold high"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT,ADC analog watchdog threshold low"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CHSELR,ADC group regular sequencer register"
|
|
bitfld.long 0x0 9. "CHSEL9,Channel-9 selection" "0,1"
|
|
bitfld.long 0x0 8. "CHSEL8,Channel-8 selection" "0,1"
|
|
bitfld.long 0x0 7. "CHSEL7,Channel-7 selection" "0,1"
|
|
bitfld.long 0x0 6. "CHSEL6,Channel-6 selection" "0,1"
|
|
bitfld.long 0x0 5. "CHSEL5,Channel-5 selection" "0,1"
|
|
bitfld.long 0x0 4. "CHSEL4,Channel-4 selection" "0,1"
|
|
bitfld.long 0x0 3. "CHSEL3,Channel-3 selection" "0,1"
|
|
bitfld.long 0x0 2. "CHSEL2,Channel-2 selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHSEL1,Channel-1 selection" "0,1"
|
|
bitfld.long 0x0 0. "CHSEL0,Channel-0 selection" "0,1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,ADC group regular data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,ADC group regular conversion data"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "CCSR,ADC calibration configuration and status register"
|
|
rbitfld.long 0x0 31. "CALON,Calibration flag" "0,1"
|
|
bitfld.long 0x0 30. "CALSUC,desc CALSUC" "0,1"
|
|
bitfld.long 0x0 29. "OFFSUC,desc OFFSUC" "0,1"
|
|
bitfld.long 0x0 15. "CALSET,Calibration factor selection" "0,1"
|
|
bitfld.long 0x0 14. "CALBYP,desc CALBYP" "0,1"
|
|
bitfld.long 0x0 12.--13. "CALSMP,Calibration sample time selection" "0,1,2,3"
|
|
bitfld.long 0x0 11. "CALSEL,Calibration contents selection" "0,1"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "CCR,ADC common configuration register"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0,1"
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1"
|
|
tree.end
|
|
tree "COMP (Comparator)"
|
|
base ad:0x0
|
|
tree "COMP1"
|
|
base ad:0x40010200
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CSR,COMP control and status register"
|
|
bitfld.long 0x0 30. "COMP_OUT,Comparator output status" "0,1"
|
|
bitfld.long 0x0 27. "VCSEL,VCSEL" "0,1"
|
|
bitfld.long 0x0 26. "VCDIV_EN,VCDIV_EN" "0,1"
|
|
hexmask.long.byte 0x0 22.--25. 1. "VCDIV,VCDIV"
|
|
bitfld.long 0x0 15. "POLARITY,Comparator polarity selector" "0,1"
|
|
bitfld.long 0x0 11. "WINMODE,Comparator non-inverting input selector for window mode" "0,1"
|
|
bitfld.long 0x0 5. "INNSEL,desc INNSEL" "0,1"
|
|
bitfld.long 0x0 0. "EN,COMP enable bit" "0,1"
|
|
line.long 0x4 "FR,Comparator Filter register"
|
|
hexmask.long.word 0x4 16.--31. 1. "FLTCNT1,Comparator filter and counter"
|
|
bitfld.long 0x4 0. "FLTEN1,Filter enable bit" "0,1"
|
|
tree.end
|
|
tree "COMP2"
|
|
base ad:0x40010210
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CSR,COMP control and status register"
|
|
bitfld.long 0x0 30. "COMP_OUT,Comparator output status" "0,1"
|
|
bitfld.long 0x0 15. "POLARITY,Comparator polarity selector" "0,1"
|
|
bitfld.long 0x0 9. "INPSEL,Comparator signal selector for non-inverting input" "0,1"
|
|
bitfld.long 0x0 5. "INMSEL,Comparator signal selector for inverting input INM" "0,1"
|
|
bitfld.long 0x0 0. "EN,COMP enable bit" "0,1"
|
|
line.long 0x4 "FR,Comparator Filter register"
|
|
hexmask.long.word 0x4 16.--31. 1. "FLTCNT2,Comparator filter and counter"
|
|
bitfld.long 0x4 0. "FLTEN2,Filter enable bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check Calculation Unit)"
|
|
base ad:0x40023000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data Register"
|
|
line.long 0x4 "IDR,Independent Data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "IDR,Independent Data register"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "CR,Control register"
|
|
bitfld.long 0x0 0. "RESET,Reset bit" "0,1"
|
|
tree.end
|
|
tree "DBGMCU (Debug Support)"
|
|
base ad:0x40015800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "IDCODE,MCU Device ID Code Register"
|
|
hexmask.long 0x0 0.--31. 1. "REV_ID,REV_ID"
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "CR,Debug MCU Configuration Register"
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop Mode" "0,1"
|
|
line.long 0x4 "APB_FZ1,APB Freeze Register1"
|
|
bitfld.long 0x4 31. "DBG_LPTIM_STOP,Debug LPTIM stopped when Core ishalted" "0,1"
|
|
line.long 0x8 "APB_FZ2,APB Freeze Register2"
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,Debug TIM 14 stopped whenCore is halted" "0,1"
|
|
bitfld.long 0x8 11. "DBG_TIMER1_STOP,Debug Timer 1 stopped when Core ishalted" "0,1"
|
|
tree.end
|
|
tree "EXTI (Extended Interrupts and Events Controller)"
|
|
base ad:0x40021800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "RTSR,EXTI rising trigger selection register"
|
|
bitfld.long 0x0 18. "RT18,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 17. "RT17,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
line.long 0x4 "FTSR,EXTI falling trigger selection register"
|
|
bitfld.long 0x4 18. "FT18,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 17. "FT17,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
line.long 0x8 "SWIER,EXTI software interrupt event register"
|
|
bitfld.long 0x8 18. "SWI18,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 17. "SWI17,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 7. "SWI7,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 6. "SWI6,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 5. "SWI5,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 4. "SWI4,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 3. "SWI3,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 2. "SWI2,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 1. "SWI1,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 0. "SWI0,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
line.long 0xC "PR,EXTI pending register"
|
|
bitfld.long 0xC 18. "PR18,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 17. "PR17,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 7. "PR7,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 6. "PR6,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 5. "PR5,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 4. "PR4,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 3. "PR3,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 2. "PR2,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 1. "PR1,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 0. "PR0,configurable event inputs x rising edge Pending bit." "0,1"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "EXTICR1,EXTI external interrupt selection register"
|
|
bitfld.long 0x0 24.--25. "EXTI3,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "EXTI2,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EXTI1,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "EXTI0,GPIO port selection" "0,1,2,3"
|
|
line.long 0x4 "EXTICR2,EXTI external interrupt selection register"
|
|
bitfld.long 0x4 24. "EXTI7,GPIO port selection" "0,1"
|
|
bitfld.long 0x4 16. "EXTI6,GPIO port selection" "0,1"
|
|
bitfld.long 0x4 8. "EXTI5,GPIO port selection" "0,1"
|
|
bitfld.long 0x4 0.--1. "EXTI4,GPIO port selection" "0,1,2,3"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "IMR,EXTI CPU wakeup with interrupt mask register"
|
|
bitfld.long 0x0 29. "IM29,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 18. "IM18,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 17. "IM17,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 7. "IM7,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 6. "IM6,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 5. "IM5,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 4. "IM4,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 3. "IM3,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 2. "IM2,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 1. "IM1,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 0. "IM0,CPU wakeup with interrupt mask on event input" "0,1"
|
|
line.long 0x4 "EMR,EXTI CPU wakeup with event mask register"
|
|
bitfld.long 0x4 29. "EM29,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 18. "EM18,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 17. "EM17,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 7. "EM7,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 6. "EM6,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 5. "EM5,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 4. "EM4,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 3. "EM3,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 2. "EM2,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 1. "EM1,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 0. "EM0,CPU wakeup with event mask on event input" "0,1"
|
|
tree.end
|
|
tree "FLASH (Embedded Flash Memory)"
|
|
base ad:0x40022000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ACR,Access control register"
|
|
bitfld.long 0x0 0. "LATENCY,Latency" "0,1"
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "KEYR,Flash key register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Flash key"
|
|
line.long 0x4 "OPTKEYR,Option byte key register"
|
|
hexmask.long 0x4 0.--31. 1. "OPTKEY,Option byte key"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "SR,Status register"
|
|
bitfld.long 0x0 16. "BSY,Busy" "0,1"
|
|
bitfld.long 0x0 15. "OPTVERR,Option and Engineering bits loading validity error" "0,1"
|
|
bitfld.long 0x0 4. "WRPERR,Write protected error" "0,1"
|
|
bitfld.long 0x0 0. "EOP,End of operation" "0,1"
|
|
line.long 0x4 "CR,Flash control register"
|
|
bitfld.long 0x4 31. "LOCK,FLASH_CR Lock" "0,1"
|
|
bitfld.long 0x4 30. "OPTLOCK,Options Lock" "0,1"
|
|
bitfld.long 0x4 27. "OBL_LAUNCH,Force the option byte loading" "0,1"
|
|
bitfld.long 0x4 25. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 24. "EOPIE,End of operation interrupt enable" "0,1"
|
|
bitfld.long 0x4 19. "PGSTRT,Flash main memory program start" "0,1"
|
|
bitfld.long 0x4 17. "OPTSTRT,Option byte program start" "0,1"
|
|
bitfld.long 0x4 11. "SER,Sector erase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MER,Mass erase" "0,1"
|
|
bitfld.long 0x4 1. "PER,Page erase" "0,1"
|
|
bitfld.long 0x4 0. "PG,Programming" "0,1"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "OPTR,Flash option register"
|
|
bitfld.long 0x0 14. "NRST_MODE,NRST_MODE" "0,1"
|
|
bitfld.long 0x0 13. "SWD_MODE,SWD_MODE" "0,1"
|
|
bitfld.long 0x0 12. "IWDG_SW,Independent watchdog selection" "0,1"
|
|
bitfld.long 0x0 9.--11. "BORF_LEV,These bits contain the VDD supply level threshold that activates the reset" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8. "BOREN,BOR reset Level" "0,1"
|
|
line.long 0x4 "SDKR,Flash SDK address register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SDK_END,SDK area end address"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SDK_STRT,SDK area start address"
|
|
line.long 0x8 "BTCR,FLASH boot control register"
|
|
bitfld.long 0x8 15. "NBOOT1,desc NBOOT1" "0,1"
|
|
bitfld.long 0x8 14. "BOOT0,desc BOOT0" "0,1"
|
|
bitfld.long 0x8 0.--2. "BOOT_SIZE,desc BOOT_SIZE" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "WRPR,Flash WRP address register"
|
|
hexmask.long.byte 0xC 0.--5. 1. "WRP,WRP address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "STCR,Flash sleep time config register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SLEEP_TIME,FLash sleep time configuration(counter based on HSI_10M)"
|
|
bitfld.long 0x0 0. "SLEEP_EN,FLash sleep enable" "0,1"
|
|
group.long 0x100++0x23
|
|
line.long 0x0 "TS0,Flash TS0 register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TS0,FLash TS0 register"
|
|
line.long 0x4 "TS1,Flash TS1 register"
|
|
hexmask.long.word 0x4 0.--9. 1. "TS1,FLash TS1 register"
|
|
line.long 0x8 "TS2P,Flash TS2P register"
|
|
hexmask.long.word 0x8 0.--8. 1. "TS2P,FLash TS2P register"
|
|
line.long 0xC "TPS3,Flash TPS3 register"
|
|
hexmask.long.word 0xC 0.--11. 1. "TPS3,FLash TPS3 register"
|
|
line.long 0x10 "TS3,Flash TS3 register"
|
|
hexmask.long.word 0x10 0.--8. 1. "TS3,FLash TS3 register"
|
|
line.long 0x14 "PERTPE,Flash PERTPE register"
|
|
hexmask.long.tbyte 0x14 0.--17. 1. "PERTPE,FLash PERTPE register"
|
|
line.long 0x18 "SMERTPE,Flash SMERTPE register"
|
|
hexmask.long.tbyte 0x18 0.--17. 1. "SMERTPE,FLash SMERTPE register"
|
|
line.long 0x1C "PRGTPE,Flash PRGTPE register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "PRGTPE,FLash PRGTPE register"
|
|
line.long 0x20 "PRETPE,Flash PRETPE register"
|
|
hexmask.long.word 0x20 0.--13. 1. "PRETPE,FLash PRETPE register"
|
|
tree.end
|
|
tree "GPIO (General-Purpose I/Os)"
|
|
base ad:0x0
|
|
tree "GPIOA"
|
|
base ad:0x50000000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 7. "ID7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "ID5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ID3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ID1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 7. "OD7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "OD5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "OD3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "OD1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOB"
|
|
base ad:0x50000400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 7. "ID7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "ID5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ID3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ID1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 7. "OD7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "OD5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "OD3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "OD1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOC"
|
|
base ad:0x50000800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 1. "ID1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 1. "OD1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x40005400
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 15. "SWRST,Software reset" "0,1"
|
|
bitfld.long 0x0 11. "POS,Acknowledge/PEC Position (for datareception)" "0,1"
|
|
bitfld.long 0x0 10. "ACK,Acknowledge enable" "0,1"
|
|
bitfld.long 0x0 9. "STOP,Stop generation" "0,1"
|
|
bitfld.long 0x0 8. "START,Start generation" "0,1"
|
|
bitfld.long 0x0 7. "NOSTRETCH,Clock stretching disable (Slavemode)" "0,1"
|
|
bitfld.long 0x0 6. "ENGC,General call enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 10. "ITBUFEN,Buffer interrupt enable" "0,1"
|
|
bitfld.long 0x4 9. "ITEVTEN,Event interrupt enable" "0,1"
|
|
bitfld.long 0x4 8. "ITERREN,Error interrupt enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "FREQ,Peripheral clock frequency"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
hexmask.long.byte 0x8 1.--7. 1. "ADD,Interface address"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "DR,Data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DR,8-bit data register"
|
|
line.long 0x4 "SR1,Status register 1"
|
|
bitfld.long 0x4 11. "OVR,Overrun/Underrun" "0,1"
|
|
bitfld.long 0x4 10. "AF,Acknowledge failure" "0,1"
|
|
bitfld.long 0x4 9. "ARLO,Arbitration lost (mastermode)" "0,1"
|
|
bitfld.long 0x4 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x4 7. "TxE,Data register empty(transmitters)" "0,1"
|
|
rbitfld.long 0x4 6. "RxNE,Data register not empty(receivers)" "0,1"
|
|
rbitfld.long 0x4 4. "STOPF,Stop detection (slavemode)" "0,1"
|
|
rbitfld.long 0x4 2. "BTF,Byte transfer finished" "0,1"
|
|
rbitfld.long 0x4 1. "ADDR,Address sent (master mode)/matched(slave mode)" "0,1"
|
|
rbitfld.long 0x4 0. "SB,Start bit (Master mode)" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "SR2,Status register 2"
|
|
bitfld.long 0x0 4. "GENCALL,General call address (Slavemode)" "0,1"
|
|
bitfld.long 0x0 2. "TRA,Transmitter/receiver" "0,1"
|
|
bitfld.long 0x0 1. "BUSY,Bus busy" "0,1"
|
|
bitfld.long 0x0 0. "MSL,Master/slave" "0,1"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "CCR,Clock control register"
|
|
bitfld.long 0x0 15. "F_S,I2C master mode selection" "0,1"
|
|
bitfld.long 0x0 14. "DUTY,Fast mode duty cycle" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "CCR,Clock control register in Fast/Standardmode (Master mode)"
|
|
line.long 0x4 "TRISE,TRISE register"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRISE,Maximum rise time in Fast/Standard mode(Master mode)"
|
|
tree.end
|
|
tree "IWDG (Independent Watchdog)"
|
|
base ad:0x40003000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "KR,Key register (IWDG_KR)"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "PR,Prescaler register (IWDG_PR)"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RLR,Reload register (IWDG_RLR)"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status register (IWDG_SR)"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
tree.end
|
|
tree "LPTIM (Low Power Timer)"
|
|
base ad:0x40007C00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload match update OK" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload match update OK Clear Flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear Flag" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload match update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload matchInterrupt Enable" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Reset counter" "0,1"
|
|
bitfld.long 0x8 2. "CNTSTRT,CNTSTRT" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
tree.end
|
|
tree "PWR (Power Management)"
|
|
base ad:0x40007000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,Power control register 1"
|
|
bitfld.long 0x0 19. "HSION_CTRL,HSI open time control" "0,1"
|
|
bitfld.long 0x0 16.--18. "SRAM_RETV,SRAM retention voltage control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 14.--15. "LPR,Low-power run" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "FLS_SLPTIME,Flash wait time after wakeup from the stop mode" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MRRDY_TIME,Time selection wakeup from LP to VR" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "VOS,Voltage scaling range selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "DBP,Disable backup domain write protection" "0,1"
|
|
bitfld.long 0x0 4. "BIAS_CR_SEL,MR Bias current selection" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BIAS_CR,MR Bias current"
|
|
line.long 0x4 "CR2,Power control register 2"
|
|
bitfld.long 0x4 9.--11. "FLT_TIME,Digital filter time configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8. "FLTEN,Digital filter enable" "0,1"
|
|
tree.end
|
|
tree "RCC (Reset/Clock Controller)"
|
|
base ad:0x40021000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Clock control register"
|
|
bitfld.long 0x0 18. "HSEEN" "0,1"
|
|
bitfld.long 0x0 11.--13. "HSIDIV,HSI16 clock division factor" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 10. "HSIRDY,HSI16 clock ready flag" "0,1"
|
|
bitfld.long 0x0 8. "HSION,HSI16 clock enable" "0,1"
|
|
line.long 0x4 "ICSCR,Internal clock sources calibration register"
|
|
bitfld.long 0x4 26.--27. "LSI_STARTUP,LSI startup time" "0,1,2,3"
|
|
hexmask.long.word 0x4 16.--24. 1. "LSI_TRIM,LSI clock trimming"
|
|
bitfld.long 0x4 13.--15. "HSI_FS,HSI frequency selection" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x4 0.--12. 1. "HSI_TRIM,HSI clock trimming"
|
|
line.long 0x8 "CFGR,Clock configuration register"
|
|
bitfld.long 0x8 28.--30. "MCOPRE,Microcontroller clock output prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24.--26. "MCOSEL,Microcontroller clock output" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 12.--14. "PPRE,APB prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 8.--11. 1. "HPRE,AHB prescaler"
|
|
rbitfld.long 0x8 3.--5. "SWS,System clock switch status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "SW,System clock switch" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "ECSCR,External clock source control register"
|
|
bitfld.long 0x0 20.--21. "LSE_STARTUP,desc LSE_STARTUP" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "LSE_DRIVER,desc LSE_DRIVER" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CIER,Clock interrupt enable register"
|
|
bitfld.long 0x0 3. "HSIRDYIE,HSI ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CIFR,Clock interrupt flag register"
|
|
bitfld.long 0x0 9. "LSECSSF,LSE clock secure system interrupt flag" "0,1"
|
|
bitfld.long 0x0 3. "HSIRDYF,HSI ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 2. "LSERDYF,LSE ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "CICR,Clock interrupt clear register"
|
|
bitfld.long 0x0 9. "LSECSSC,LSE clock secure system interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 3. "HSIRDYC,HSI ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0,1"
|
|
group.long 0x24++0x1F
|
|
line.long 0x0 "IOPRSTR,GPIO reset register"
|
|
bitfld.long 0x0 2. "GPIOCRST,I/O port C reset" "0,1"
|
|
bitfld.long 0x0 1. "GPIOBRST,I/O port B reset" "0,1"
|
|
bitfld.long 0x0 0. "GPIOARST,I/O port A reset" "0,1"
|
|
line.long 0x4 "AHBRSTR,AHB peripheral reset register"
|
|
bitfld.long 0x4 12. "CRCRST,CRC reset" "0,1"
|
|
bitfld.long 0x4 8. "FLASHRST,FLASH reset" "0,1"
|
|
line.long 0x8 "APBRSTR1,APB peripheral reset register 1"
|
|
bitfld.long 0x8 31. "LPTIMRST,Low Power Timer reset" "0,1"
|
|
bitfld.long 0x8 28. "PWRRST,Power interface reset" "0,1"
|
|
bitfld.long 0x8 27. "DBGRST,Debug support reset" "0,1"
|
|
bitfld.long 0x8 21. "I2CRST,I2C reset" "0,1"
|
|
line.long 0xC "APBRSTR2,APB peripheral reset register 2"
|
|
bitfld.long 0xC 22. "COMP2RST,COMP2 reset" "0,1"
|
|
bitfld.long 0xC 21. "COMP1RST,COMP1 reset" "0,1"
|
|
bitfld.long 0xC 20. "ADCRST,ADC reset" "0,1"
|
|
bitfld.long 0xC 15. "TIM14RST,TIM14 reset" "0,1"
|
|
bitfld.long 0xC 14. "USART1RST,USART1 reset" "0,1"
|
|
bitfld.long 0xC 12. "SPI1RST,SPI1 reset" "0,1"
|
|
bitfld.long 0xC 11. "TIM1RST,TIM1 timer reset" "0,1"
|
|
bitfld.long 0xC 0. "SYSCFGRST,SYSCFG and COMP reset" "0,1"
|
|
line.long 0x10 "IOPENR,GPIO clock enable register"
|
|
bitfld.long 0x10 2. "GPIOCEN,I/O port C clock enable" "0,1"
|
|
bitfld.long 0x10 1. "GPIOBEN,I/O port B clock enable" "0,1"
|
|
bitfld.long 0x10 0. "GPIOAEN,I/O port A clock enable" "0,1"
|
|
line.long 0x14 "AHBENR,AHB peripheral clock enable register"
|
|
bitfld.long 0x14 12. "CRCEN,CRC clock enable" "0,1"
|
|
bitfld.long 0x14 9. "SRAMEN,SRAM memory interface clock enable" "0,1"
|
|
bitfld.long 0x14 8. "FLASHEN,Flash memory interface clock enable" "0,1"
|
|
line.long 0x18 "APBENR1,APB peripheral clock enable register 1"
|
|
bitfld.long 0x18 31. "LPTIMEN,LPTIM clock enable" "0,1"
|
|
bitfld.long 0x18 28. "PWREN,Power interface clock enable" "0,1"
|
|
bitfld.long 0x18 27. "DBGEN,Debug support clock enable" "0,1"
|
|
bitfld.long 0x18 21. "I2CEN,I2C clock enable" "0,1"
|
|
line.long 0x1C "APBENR2,APB peripheral clock enable register 2"
|
|
bitfld.long 0x1C 22. "COMP2EN,COMP2 clock enable" "0,1"
|
|
bitfld.long 0x1C 21. "COMP1EN,COMP1 clock enable" "0,1"
|
|
bitfld.long 0x1C 20. "ADCEN,ADC clock enable" "0,1"
|
|
bitfld.long 0x1C 15. "TIM14EN,TIM14 clock enable" "0,1"
|
|
bitfld.long 0x1C 14. "USART1EN,USART1 clock enable" "0,1"
|
|
bitfld.long 0x1C 12. "SPI1EN,SPI1 clock enable" "0,1"
|
|
bitfld.long 0x1C 11. "TIM1EN,TIM1 timer clock enable" "0,1"
|
|
bitfld.long 0x1C 0. "SYSCFGEN,SYSCFG COMP and VREFBUF clock enable" "0,1"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "CCIPR,Peripherals independent clock configuration register"
|
|
bitfld.long 0x0 18.--19. "LPTIM1SEL,LPTIM1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x0 11. "COMP2SEL,COMP2 clock source selection" "0,1"
|
|
bitfld.long 0x0 10. "COMP1SEL,COMP1 clock source selection" "0,1"
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "BDCR,RTC domain control register"
|
|
bitfld.long 0x0 25. "LSCOSEL,Low-speed clock output selection" "0,1"
|
|
bitfld.long 0x0 24. "LSCOEN,Low-speed clock output (LSCO) enable" "0,1"
|
|
bitfld.long 0x0 6. "LSECSSD,LSE CSS detect" "0,1"
|
|
bitfld.long 0x0 5. "LSECSSON,LSE CSS enable" "0,1"
|
|
bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0,1"
|
|
bitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
bitfld.long 0x0 0. "LSEON,LSE oscillator enable" "0,1"
|
|
line.long 0x4 "CSR,Control/status register"
|
|
bitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset flag" "0,1"
|
|
bitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
bitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
bitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
bitfld.long 0x4 25. "OBLRSTF,Option byte loader reset flag" "0,1"
|
|
bitfld.long 0x4 23. "RMVF,Remove reset flags" "0,1"
|
|
bitfld.long 0x4 8. "PINRST_FLTDIS,desc PINRST_FLTDIS" "0,1"
|
|
bitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LSION,LSI oscillator enable" "0,1"
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x40013000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 15. "BIDIMODE,desc BIDIMODE" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,desc BIDIOE" "0,1"
|
|
bitfld.long 0x0 11. "DDF,desc DDF" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,desc RXONLY" "0,1"
|
|
bitfld.long 0x0 9. "SSM,desc SSM" "0,1"
|
|
bitfld.long 0x0 8. "SSI,desc SSI" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,desc LSBFIRST" "0,1"
|
|
bitfld.long 0x0 6. "SPE,desc SPE" "0,1"
|
|
bitfld.long 0x0 3.--5. "BR,desc BR" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,desc MSTR" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,desc CPOL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPHA,desc CPHA" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 15. "SLVFM,desc SLVFM" "0,1"
|
|
bitfld.long 0x4 11. "DS,desc DS" "0,1"
|
|
bitfld.long 0x4 7. "TXEIE,desc TXEIE" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,desc RXNEIE" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,desc ERRIE" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,desc SSOE" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,desc SR"
|
|
bitfld.long 0x0 11.--12. "FTLVL,desc FTLVL" "0,1,2,3"
|
|
bitfld.long 0x0 9.--10. "FRLVL,desc FRLVL" "0,1,2,3"
|
|
bitfld.long 0x0 7. "BSY,desc BSY" "0,1"
|
|
bitfld.long 0x0 6. "OVR,desc OVR" "0,1"
|
|
bitfld.long 0x0 5. "MODF,desc MODF" "0,1"
|
|
bitfld.long 0x0 1. "TXE,desc TXE" "0,1"
|
|
bitfld.long 0x0 0. "RXNE,desc RXNE" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "DR,desc DR"
|
|
hexmask.long.word 0x0 0.--15. 1. "DR,desc DR"
|
|
tree.end
|
|
tree "SYSCFG (System Configuration Controller)"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CFGR1,SYSCFG configuration register 1"
|
|
bitfld.long 0x0 19. "I2C_PB6_FMP,desc I2C_PB6_FMP" "0,1"
|
|
bitfld.long 0x0 18. "I2C_PB4_FMP,desc I2C_PB4_FMP" "0,1"
|
|
bitfld.long 0x0 17. "I2C_PB3_FMP,desc I2C_PB3_FMP" "0,1"
|
|
bitfld.long 0x0 16. "I2C_PA2_FMP,desc I2C_PA2_FMP" "0,1"
|
|
bitfld.long 0x0 0.--1. "MEM_MODE,Memory mapping selection bits" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CFGR2,SYSCFG configuration register 2"
|
|
bitfld.long 0x0 9.--10. "ETR_SRC_TIM1,TIM1 ETR source selection" "0,1,2,3"
|
|
bitfld.long 0x0 0. "LOCKUP_LOCK,Cortex-M0+ LOCKUP bit enable bit" "0,1"
|
|
line.long 0x4 "GPIO_ENS,desc GPIO_ENS"
|
|
bitfld.long 0x4 16.--17. "PC_ENS,desc PC_ENS" "0,1,2,3"
|
|
hexmask.long.byte 0x4 8.--15. 1. "PB_ENS,desc PB_ENS"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PA_ENS,desc PA_ENS"
|
|
tree.end
|
|
tree "TIM (Timer)"
|
|
base ad:0x0
|
|
tree "TIM1 (Advanced-Control Timer)"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 8.--9. "CKD,desc CKD" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,desc ARPE" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,desc CMS" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "OPM,desc OPM" "0,1"
|
|
bitfld.long 0x0 2. "URS,desc URS" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,desc UDIS" "0,1"
|
|
bitfld.long 0x0 0. "CEN,desc CEN" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 14. "OIS4,desc OIS4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,desc OIS3N" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,desc OIS3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,desc OIS2N" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,desc OIS2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,desc OIS1N" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,desc OIS1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,desc TI1S" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,desc MMS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 2. "CCUS,desc CCUS" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,desc CCPC" "0,1"
|
|
line.long 0x8 "SMCR,desc SMCR"
|
|
bitfld.long 0x8 15. "ETP,desc ETP" "0,1"
|
|
bitfld.long 0x8 14. "ECE,desc ECE" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,desc ETPS" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,desc ETF"
|
|
bitfld.long 0x8 7. "MSM,desc MSM" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,desc TS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,desc OCCS" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,desc SMS" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,desc DIER"
|
|
bitfld.long 0xC 7. "BIE,desc BIE" "0,1"
|
|
bitfld.long 0xC 6. "TIE,desc TIE" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,desc COMIE" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,desc CC4IE" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,desc CC3IE" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,desc CC2IE" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,desc CC1IE" "0,1"
|
|
bitfld.long 0xC 0. "UIE,desc UIE" "0,1"
|
|
line.long 0x10 "SR,desc SR"
|
|
bitfld.long 0x10 23. "IC4IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x10 22. "IC3IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x10 21. "IC2IF,desc IC2IF" "0,1"
|
|
bitfld.long 0x10 20. "IC1IF,desc IC1IF" "0,1"
|
|
bitfld.long 0x10 19. "IC4IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x10 18. "IC3IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x10 17. "IC2IR,desc IC2IR" "0,1"
|
|
bitfld.long 0x10 16. "IC1IR,desc IC1IR" "0,1"
|
|
bitfld.long 0x10 12. "CC4OF,desc CC4OF" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,desc CC3OF" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,desc CC2OF" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,desc CC1OF" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,desc BIF" "0,1"
|
|
bitfld.long 0x10 6. "TIF,desc TIF" "0,1"
|
|
bitfld.long 0x10 5. "COMIF,desc COMIF" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,desc CC4IF" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,desc CC3IF" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,desc CC2IF" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,desc CC1IF" "0,1"
|
|
bitfld.long 0x10 0. "UIF,desc UIF" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,desc EGR"
|
|
bitfld.long 0x0 7. "BG,desc BG" "0,1"
|
|
bitfld.long 0x0 6. "TG,desc TG" "0,1"
|
|
bitfld.long 0x0 5. "COMG,desc COMG" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,desc CC4G" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,desc CC3G" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,desc CC2G" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 Generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,desc UG" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_OUTPUT,desc CCMR1:OUTPUT"
|
|
bitfld.long 0x0 15. "OC2CE,desc OC2CE" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,desc OC2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,desc OC2PE" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,desc OC2FE" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,desc OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,desc OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,desc OC1PE" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,desc OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_INPUT,desc CCMR1:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,desc IC2F"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,desc IC2PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,desc IC1F"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,desc IC1PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_OUTPUT,desc CCMR2:OUTPUT"
|
|
bitfld.long 0x4 15. "OC4CE,desc OC4CE" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,desc OC4M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,desc OC4PE" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,desc OC4FE" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,desc CC4S" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,desc OC3CE" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,desc OC3M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,desc OC3PE" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,desc OC3FE" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,desc CC3S" "0,1,2,3"
|
|
group.long 0x1C++0x2B
|
|
line.long 0x0 "CCMR2_INPUT,desc CCMR2:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,desc IC4F"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,desc IC4PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,desc CC4S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,desc IC3F"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,desc IC3PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,desc CC3S" "0,1,2,3"
|
|
line.long 0x4 "CCER,desc CCER"
|
|
bitfld.long 0x4 13. "CC4P,desc CC4P" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,desc CC4E" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,desc CC3NP" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,desc CC3NE" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,desc CC3P" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,desc CC3E" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,desc CC2NP" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,desc CC2NE" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,desc CC2P" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,desc CC2E" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,desc CC1NP" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,desc CC1NE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CC1P,desc CC1P" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,desc CC1E" "0,1"
|
|
line.long 0x8 "CNT,desc CNT"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,desc CNT"
|
|
line.long 0xC "PSC,desc PSC"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,desc PSC"
|
|
line.long 0x10 "ARR,desc ARR"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,desc ARR"
|
|
line.long 0x14 "RCR,desc RCR"
|
|
hexmask.long.byte 0x14 0.--7. 1. "REP,desc REP"
|
|
line.long 0x18 "CCR1,desc CCR1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,desc CCR1"
|
|
line.long 0x1C "CCR2,desc CCR2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,desc CCR2"
|
|
line.long 0x20 "CCR3,desc CCR3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,desc CCR3"
|
|
line.long 0x24 "CCR4,desc CCR4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,desc CCR4"
|
|
line.long 0x28 "BDTR,desc BDTR"
|
|
bitfld.long 0x28 15. "MOE,desc MOE" "0,1"
|
|
bitfld.long 0x28 14. "AOE,desc AOE" "0,1"
|
|
bitfld.long 0x28 13. "BKP,desc BKP" "0,1"
|
|
bitfld.long 0x28 12. "BKE,desc BKE" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,desc OSSR" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,desc OSSI" "0,1"
|
|
bitfld.long 0x28 8.--9. "LOCK,desc LOCK" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,desc DTG"
|
|
tree.end
|
|
tree "TIM14 (16-bit General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 8.--9. "CKD,desc CKD" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,desc ARPE" "0,1"
|
|
bitfld.long 0x0 3. "OPM,desc OPM" "0,1"
|
|
bitfld.long 0x0 2. "URS,desc URS" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,desc UDIS" "0,1"
|
|
bitfld.long 0x0 0. "CEN,desc CEN" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,desc DIER"
|
|
bitfld.long 0x0 1. "CC1IE,desc CC1IE" "0,1"
|
|
bitfld.long 0x0 0. "UIE,desc UIE" "0,1"
|
|
line.long 0x4 "SR,desc SR"
|
|
bitfld.long 0x4 20. "IC1IF,desc IC1IF" "0,1"
|
|
bitfld.long 0x4 16. "IC1IR,desc IC1IR" "0,1"
|
|
bitfld.long 0x4 9. "CC1OF,desc CC1OF" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,desc CC1IF" "0,1"
|
|
bitfld.long 0x4 0. "UIF,desc UIF" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,desc EGR"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 Generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,desc UG" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_OUTPUT,desc CCMR1:OUTPUT"
|
|
bitfld.long 0x0 4.--6. "OC1M,desc OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,desc OC1PE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_INPUT,desc CCMR1:INPUT"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,desc IC1F"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,desc IC1PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "CCER,desc CCER"
|
|
bitfld.long 0x0 3. "CC1NP,desc CC1NP" "0,1"
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bitfld.long 0x0 1. "CC1P,desc CC1P" "0,1"
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bitfld.long 0x0 0. "CC1E,desc CC1E" "0,1"
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line.long 0x4 "CNT,desc CNT"
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hexmask.long.word 0x4 0.--15. 1. "CNT,desc CNT"
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line.long 0x8 "PSC,desc PSC"
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hexmask.long.word 0x8 0.--15. 1. "PSC,desc PSC"
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line.long 0xC "ARR,desc ARR"
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hexmask.long.word 0xC 0.--15. 1. "ARR,desc ARR"
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group.long 0x34++0x3
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line.long 0x0 "CCR1,desc CCR1"
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hexmask.long.word 0x0 0.--15. 1. "CCR1,desc CCR1"
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group.long 0x50++0x3
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line.long 0x0 "OR,desc OR"
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bitfld.long 0x0 0.--1. "TI1_RMP,desc TI1_RMP" "0,1,2,3"
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tree.end
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tree.end
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tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
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base ad:0x40013800
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group.long 0x0++0x17
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line.long 0x0 "SR,Status register"
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bitfld.long 0x0 12. "ABRRQ,Automate baudrate detection requeset" "0,1"
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rbitfld.long 0x0 11. "ABRE,Automate baudrate detection error flag" "0,1"
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rbitfld.long 0x0 10. "ABRF,Automate baudrate detection flag" "0,1"
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bitfld.long 0x0 9. "CTS,CTS flag" "0,1"
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rbitfld.long 0x0 7. "TXE,Transmit data register empty" "0,1"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0,1"
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rbitfld.long 0x0 4. "IDLE,IDLE line detected" "0,1"
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newline
|
|
rbitfld.long 0x0 3. "ORE,Overrun error" "0,1"
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rbitfld.long 0x0 2. "NE,Noise error flag" "0,1"
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|
rbitfld.long 0x0 1. "FE,Framing error" "0,1"
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rbitfld.long 0x0 0. "PE,Parity error" "0,1"
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|
line.long 0x4 "DR,Data register"
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hexmask.long.word 0x4 0.--8. 1. "DR,Data value"
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line.long 0x8 "BRR,Baud rate register"
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hexmask.long.word 0x8 4.--15. 1. "DIV_Mantissa,mantissa of USARTDIV"
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hexmask.long.byte 0x8 0.--3. 1. "DIV_Fraction,fraction of USARTDIV"
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line.long 0xC "CR1,Control register 1"
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bitfld.long 0xC 13. "UE,USART enable" "0,1"
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bitfld.long 0xC 12. "M,Word length" "0,1"
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bitfld.long 0xC 11. "WAKE,Wakeup method" "0,1"
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bitfld.long 0xC 10. "PCE,Parity control enable" "0,1"
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bitfld.long 0xC 9. "PS,Parity selection" "0,1"
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|
bitfld.long 0xC 8. "PEIE,PE interrupt enable" "0,1"
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bitfld.long 0xC 7. "TXEIE,TXE interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "IDLEIE,IDLE interrupt enable" "0,1"
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|
bitfld.long 0xC 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0xC 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0xC 1. "RWU,Receiver wakeup" "0,1"
|
|
line.long 0x10 "CR2,Control register 2"
|
|
bitfld.long 0x10 12.--13. "STOP,STOP bits" "0,1,2,3"
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|
bitfld.long 0x10 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x10 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x10 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x10 8. "LBCL,Last bit clock pulse" "0,1"
|
|
hexmask.long.byte 0x10 0.--3. 1. "ADD,Address of the USART node"
|
|
line.long 0x14 "CR3,Control register 3"
|
|
bitfld.long 0x14 13.--14. "ABRMOD,Auto baudrate mode" "0,1,2,3"
|
|
bitfld.long 0x14 12. "ABREN,Auto baudrate enable" "0,1"
|
|
bitfld.long 0x14 11. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x14 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x14 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x14 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x14 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x14 0. "EIE,Error interrupt enable" "0,1"
|
|
tree.end
|
|
newline
|
|
AUTOINDENT.OFF
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