3981 lines
254 KiB
Plaintext
3981 lines
254 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: NETX100 On-Chip Peripherals
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; @Props: Released
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; @Author: BOB
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; @Changelog: 2009-01-21 BOB
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; @Manufacturer: HILSCHER - Hilscher GmbH
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; @Doc: Manual_netX_Program_Reference_Guide_Rev04.pdf (2007-04-20)
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; @Core: ARM926EJ-S
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; @Chip: NETX100
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pernetx100.per 7592 2017-02-18 13:54:14Z askoncej $
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config 16. 8.
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width 0xB
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tree "ARM Core Registers"
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AUTOINDENT.PUSH
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AUTOINDENT.ON CENTER TREE
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width 8.
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tree "ID Registers"
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group c15:0x0000--0x0000
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line.long 0x0 "MIDR,Identity Code"
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hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer"
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hexmask.long.byte 0x0 20.--23. 0x1 "SPEC,Specification Revision"
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hexmask.long.byte 0x0 16.--19. 0x1 "ARCH,Architecture Version"
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hexmask.long.word 0x0 4.--15. 0x1 "PARTNUM,Part Number"
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hexmask.long.byte 0x0 0.--3. 0x01 "REV,Layout Revision"
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group c15:0x0100--0x0100
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line.long 0x0 "CTR,Cache Type"
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bitfld.long 0x0 25.--28. "CLASS,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
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bitfld.long 0x0 24. "H,Cache Havardness" "no,yes"
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newline
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bitfld.long 0x0 18.--21. "DSIZE,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 15.--17. "DASS,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 14. "DM,Data Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 12.--13. "DLENGTH,Data Cache Line Length" "2,4,8,16"
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newline
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bitfld.long 0x0 6.--9. "ISIZE,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 3.--5. "IASS,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 2. "IM,Instruction Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 0.--1. "ILENGTH,Instruction Cache Line Length" "2,4,8,16"
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group c15:0x0200--0x0200
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line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register"
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bitfld.long 0x0 16. "DP,Data TCM Present" "no,yes"
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bitfld.long 0x0 0. "IP,Instruction TCM Present" "no,yes"
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tree.end
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tree "MMU Control and Configuration"
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width 8.
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group c15:0x0001--0x0001
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 15. "L4,Configure Loading TBIT" "Enable,Disable"
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bitfld.long 0x0 14. "RR,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin"
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bitfld.long 0x0 13. "V,Location of Exception Vectors" "0x00000000,0xFFFF0000"
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newline
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bitfld.long 0x0 12. "I,Instruction Cache" "Disable,Enable"
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bitfld.long 0x0 9. "R,ROM Protection" "Disable,Enable"
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bitfld.long 0x0 8. "S,System Protection" "Disable,Enable"
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bitfld.long 0x0 7. "B,Endianism" "Little,Big"
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newline
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bitfld.long 0x0 2. "C,Data Cache" "Disable,Enable"
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bitfld.long 0x0 1. "A,Alignment Fault Checking" "Disable,Enable"
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bitfld.long 0x0 0. "M,MMU" "Disable,Enable"
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newline
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group c15:0x0002--0x0002
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line.long 0x0 "TTBR,Translation Table Base Register"
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hexmask.long 0x0 14.--31. 0x4000 "TTBA,Translation Table Base Address"
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newline
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group c15:0x3--0x3
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line.long 0x0 "DACR,Domain Access Control Register"
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bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
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newline
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bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
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newline
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bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
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newline
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bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
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newline
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group c15:0x0005--0x0005
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line.long 0x0 "DFSR,Data Fault Status Register"
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bitfld.long 0x0 0x4--0x7 "DOMAIN,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 "STATUS,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0105--0x0105
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line.long 0x0 "IFSR,Instruction Fault Status Register"
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bitfld.long 0x0 0x4--0x7 "DOMAIN,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 "STATUS,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0006--0x0006
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line.long 0x0 "DFAR,Data Fault Address Register"
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newline
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group c15:0x000a--0x000a
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line.long 0x0 "TLBR,TLB Lockdown Register"
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bitfld.long 0x0 26.--28. "VICTIM,Victim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. "P,P bit" "0,1"
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newline
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group c15:0x000d--0x000d
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line.long 0x0 "FCSEPID,FCSE Process ID"
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group c15:0x010d--0x010d
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line.long 0x0 "CONTEXT,Context ID"
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tree.end
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tree "Cache Control and Configuration"
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group c15:0x0009--0x0009
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line.long 0x0 "DCACHE,Data Cache Lockdown"
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bitfld.long 0x0 3. "LWAY3,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. "LWAY2,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. "LWAY1,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. "LWAY0,L bit for WAY 0" "0,1"
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group c15:0x0109--0x0109
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line.long 0x0 "ICACHE,Instruction Cache Lockdown"
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bitfld.long 0x0 3. "LWAY3,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. "LWAY2,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. "LWAY1,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. "LWAY0,L bit for WAY 0" "0,1"
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tree.end
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tree "TCM Control and Configuration"
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group c15:0x0019--0x0019
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line.long 0x0 "DTCM,Data TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 "BASE,Base Address"
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bitfld.long 0x0 2.--5. "SIZE,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. "ENABLE,Enable Bit" "disable,enable"
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group c15:0x0119--0x0119
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line.long 0x0 "ITCM,Instruction TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 "BASE,Base Address"
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bitfld.long 0x0 2.--5. "SIZE,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. "ENABLE,Enable Bit" "disable,enable"
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tree.end
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tree "Test and Debug"
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group c15:0x000f--0x000f
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line.long 0x0 "DOVRR,Debug Override Register"
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bitfld.long 0x0 19. "TCALL,Test and clean all" "disable,enable"
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bitfld.long 0x0 18. "DTLBMISS,Abort Data TLB Miss" "no abort,abort"
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bitfld.long 0x0 17. "ITLBMISS,Abort Instruction TLB Miss" "no abort,abort"
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newline
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bitfld.long 0x0 16. "PREFETCH,NC Instruction Prefetching" "enable,disable"
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bitfld.long 0x0 15. "CLOCKGATE,Block Level Clock Gating" "enable,disable"
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bitfld.long 0x0 14. "NCBSTORE,NCB Stores" "disable,enable"
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bitfld.long 0x0 13. "MMU/DC,MMU disable DCache Enabled Behaviour" "NCNB,WT"
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group c15:0x001f--0x001f
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line.long 0x0 "ADDRESS,Debug/Test Address"
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;wgroup c15:0x402f--0x402f
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; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry"
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;wgroup c15:0x403f--0x403f
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; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry"
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;wgroup c15:0x404f--0x404f
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; line.long 0x0 "RMTLBPA,Read PA in main TLB entry"
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;wgroup c15:0x405f--0x405f
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; line.long 0x0 "WMTLBPA,Write PA in main TLB entry"
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;wgroup c15:0x407f--0x407f
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; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM"
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;wgroup c15:0x412f--0x412f
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; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry"
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;wgroup c15:0x413f--0x413f
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; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry"
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;wgroup c15:0x414f--0x414f
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; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry"
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;wgroup c15:0x415f--0x415f
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; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry"
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;wgroup c15:0x417f--0x417f
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; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM"
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group c15:0x101f--0x101f
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line.long 0x0 "TRACE,Trace Control"
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bitfld.long 0x0 2. "FIQ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall"
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bitfld.long 0x0 1. "IRQ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall"
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group c15:0x700f--0x700f
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line.long 0x0 "CACHE,Cache Debug Control"
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bitfld.long 0x0 2. "DWT,Disable Writeback (force WT)" "writeback,write-through"
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bitfld.long 0x0 1. "DIL,Disable ICache Linefill" "enable,disable"
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bitfld.long 0x0 0. "DDL,Disable DCache Linefill" "enable,disable"
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group c15:0x701f--0x701f
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line.long 0x0 "MMU,MMU Debug Control"
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bitfld.long 0x0 7. "TLBMI,Disable Main TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 6. "TLBMD,Disable Main TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 5. "TLBLI,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 4. "TLBLD,Disable Main TLB Load Due to Data Access Miss" "enable,disable"
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newline
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bitfld.long 0x0 3. "TLBMMI,Disable Micro TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 2. "TLBMMD,Disable Micro TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 1. "TLBMLI,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 0. "TLBMLD,Disable Micro TLB Load Due to Data Access Miss" "enable,disable"
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group c15:0x002f--0x002f
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line.long 0x0 "REMAP,Memory Region Remap"
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bitfld.long 0x0 14.--15. "IWB," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 12.--13. "IWT," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 10.--11. "INCB," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 8.--9. "INCNB," "NCNB,NCB,WT,WB"
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newline
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bitfld.long 0x0 6.--7. "DWB," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 4.--5. "DWT," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 2.--3. "DNCB," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 0.--1. "DNCNB," "NCNB,NCB,WT,WB"
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tree.end
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tree "ICEbreaker"
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width 8.
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group ice:0x0--0x5 "Debug Control"
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line.long 0x0 "DBGCTRL,Debug Control Register"
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bitfld.long 0x0 0x5 "ICE,EmbeddedICE Disable" "enabled,disabled"
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bitfld.long 0x0 0x4 "MONITOR,Monitor Mode Enable" "disabled,enabled"
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newline
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bitfld.long 0x0 0x3 "STEP,Single Step" "disabled,enabled"
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bitfld.long 0x0 0x2 "INTDIS,Interrupts Disable" "enabled,disabled"
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bitfld.long 0x0 0x1 "DBGRQ,Debug Request" "no,yes"
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bitfld.long 0x0 0x0 "DBGACK,Debug Acknowledge" "no,yes"
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line.long 0x4 "DBGSTAT,Debug Status Register"
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bitfld.long 0x4 0x6--0x9 "MOE,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res"
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bitfld.long 0x4 0x5 "IJBIT,IJBIT" "0,java"
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bitfld.long 0x4 0x4 "ITBIT,ITBIT" "0,thumb"
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bitfld.long 0x4 0x3 "SYSCOMP,SYSCOMP" "0,1"
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bitfld.long 0x4 0x2 "IFEN,Interrupts Enable" "disabled,enabled"
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bitfld.long 0x4 0x1 "DBGRQ,Debug Request" "no,yes"
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bitfld.long 0x4 0x0 "DBGACK,Debug Acknowledge" "no,yes"
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line.long 0x8 "VECTOR,Vector Catch Register"
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bitfld.long 0x8 0x7 "FIQ,FIQ" "dis,ena"
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bitfld.long 0x8 0x6 "IRQ,IRQ" "dis,ena"
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bitfld.long 0x8 0x4 "D_ABO,D_ABORT" "dis,ena"
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bitfld.long 0x8 0x3 "P_ABO,P_ABORT" "dis,ena"
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bitfld.long 0x8 0x2 "SWI,SWI" "dis,ena"
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bitfld.long 0x8 0x1 "UND,UNDEF" "dis,ena"
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bitfld.long 0x8 0x0 "RES,RESET" "dis,ena"
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line.long 0x10 "COMCTRL,Debug Communication Control Register"
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bitfld.long 0x10 28.--31. "VERSION,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
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bitfld.long 0x10 0x1 "WRITE,Write Register Free" "idle,pend"
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bitfld.long 0x10 0x0 "READ,Read Register Free" "idle,pend"
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line.long 0x14 "COMDATA,Debug Communication Data Register"
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group ice:0x8--0x0d "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 "ENABLE,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 "RANGE,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 "CHAIN,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 "EXTERN,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 "nTRANS,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 "nOPC,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 "MAS,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 "nRW,Read/Write" "R ,W"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 "RANGE,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 "CHAIN,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 "EXTERN,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 "nTRANS,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 "nOPC,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 "MAS,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 "nRW,Read/Write" "ENA,DIS"
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group ice:0x10--0x15 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 "ENABLE,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 "RANGE,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 "CHAIN,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 "EXTERN,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 "nTRANS,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 "nOPC,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 "MAS,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 "nRW,Read/Write" "R ,w"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 "RANGE,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 "CHAIN,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 "EXTERN,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 "nTRANS,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 "nOPC,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 "MAS,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 "nRW,Read/Write" "ENA,DIS"
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tree.end
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AUTOINDENT.POP
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tree.end
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tree "System Functions"
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base ad:0x00100000
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width 20.
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rgroup.long 0x00++0x03 "BOO (Bond Out Option)"
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line.long 0x00 "BOO_STAT,Bond Out Option Status Register"
|
|
bitfld.long 0x00 0.--2. " BOND_OPTION ,Status of the hardwired pins" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70++0x03 "IOC (IO Configuration)"
|
|
line.long 0x00 "IOC_CFG_ACCESS_KEY,IO Configuration Access Key Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IO_CFG_ACCESS_KEY ,Access key for next write access"
|
|
width 13.
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "IOC_CFG,IO Configuration Register"
|
|
bitfld.long 0x00 31. " IF_SELECT_N ,Host interface modes disable" "DPM/EBM/PIO,Disabled"
|
|
bitfld.long 0x00 28. " SEL_E_PWM2_ECLK ,Select outputs for PWM signals clocked by xmac2_eclk_in at PIO pads" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SEL_F1_PWM3_ECLK ,Select outputs for PWM-signals clocked by xmac3_eclk_in at Fieldbus1 pads" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " SEL_F0_PWM3_ECLK ,Select outputs for PWM-signals clocked by xmac3_eclk_in at Fieldbus0 pads" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_WDG ,Select pins for clk watchdoq / system watchdog" "Not selected,Selected"
|
|
bitfld.long 0x00 23. " SEL_ETM ,Select pins for ETM9 of ARM926" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEL_LED_MII3 ,Select inputs for LEDs of mii3" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " SEL_LED_MII2 ,Select inputs for LEDs of mii2" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SEL_MP ,Select outputs for mp" "Not selected,Selected"
|
|
bitfld.long 0x00 19. " SEL_ENC1 ,Select outputs for enc1" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SEL_ENC0 ,Select outputs for enc0" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " SEL_E_RPWM2 ,Select output for PWM-failure at PIO pads" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEL_E_FAILURE2 ,Select output for PWM-failure at PIO pads" "Not selected,Selected"
|
|
bitfld.long 0x00 15. " SEL_E_PWM2 ,Select outputs for PWM-signals at PIO pads" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SEL_F3_PWM3 ,Select outputs for PWM-signals at Fieldbus3 pads" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " SEL_F2_RPWM3 ,Select output for rpwm signal at Fieldbus2 pads" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEL_F2_FAILURE3 ,Select output for PWM-failure at Fieldbus2 pads" "Not selected,Selected"
|
|
bitfld.long 0x00 11. " SEL_F1_PWM3 ,Select outputs for PWM-signals at Fieldbus1 pads" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEL_F1_PWM3 ,Select outputs for PWM-signals at Fieldbus1 pads" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " SEL_F0_FAILURE3 ,Select output for PWM-failure at Fieldbus0 pads" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SEL_F0_PWM3 ,Select outputs for PWM-signals at Fieldbus0 pads" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " SEL_FO1 ,Select outputs for Fiber Optics of Phy1" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEL_FO0 ,Select outputs for Fiber Optics of Phy0" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " SEL_MII3PWM ,Select outputs for PWM output of xMAC3" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEL_MII23 ,Select outputs for MDIO signals" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " SEL_MII3 ,Select outputs for MII interface of xMAC3" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEL_MII2 ,Select outputs for MII interface of xMAC2" "Not selected,Selected"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "IOC_CFG_MSK,IO Configuration Mask Register"
|
|
bitfld.long 0x00 31. " IF_SELECT_N ,Mask of inverted HIF if-select signal" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " SEL_E_PWM2_ECLK ,Mask of select outputs for PWM signals clocked by xmac2_eclk_in at PIO pads" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SEL_F1_PWM3_ECLK ,Mask of select outputs for PWM-signals clocked by xmac3_eclk_in at Fieldbus1 pads" "Not masked,Masked"
|
|
bitfld.long 0x00 25. " SEL_F0_PWM3_ECLK ,Mask of select outputs for PWM-signals clocked by xmac3_eclk_in at Fieldbus0 pads" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_WDG ,Mask of select pins for clk watchdoq / system watchdog" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " SEL_ETM ,Mask of select pins for ETM9 of ARM926" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEL_LED_MII3 ,Mask of select inputs for LEDs of mii3" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " SEL_LED_MII2 ,Mask of select inputs for LEDs of mii2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SEL_MP ,Mask of select outputs for mp" "Not masked,Masked"
|
|
bitfld.long 0x00 19. " SEL_ENC1 ,Mask of select outputs for enc1" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SEL_ENC0 ,Mask of select outputs for enc0" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " SEL_E_RPWM2 ,Mask of select output for rpwm signal at PIO pads" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEL_E_FAILURE2 ,Mask of select output for PWM-failure at PIO pads" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " SEL_E_PWM2 ,Mask of select outputs for PWM-signals at PIO pads" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SEL_F3_PWM3 ,Mask of select outputs for PWM-signals at Fieldbus3 pads" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " SEL_F2_RPWM3 ,Mask of select output for rpwm signal at Fieldbus2 pads" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SEL_F2_FAILURE3 ,Mask of select output for PWM-failure at Fieldbus2 pads" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " SEL_F1_PWM3 ,Mask of select outputs for PWM-signals at Fieldbus1 pads" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEL_F1_PWM3 ,Mask of select output for PWM-signals at Fieldbus1 pads" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SEL_F0_FAILURE3 ,Mask of select output for PWM-failure at Fieldbus0 pads" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SEL_F0_PWM3 ,Mask of select outputs for PWM-signals at Fieldbus0 pads" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " SEL_FO1 ,Mask of select outputs for Fiber Optics of Phy1" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEL_FO0 ,Mask of select outputs for Fiber Optics of Phy0" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " SEL_MII3PWM ,Mask of select outputs for PWM output of xMAC3" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEL_MII23 ,Mask of select outputs for MDIO signals" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " SEL_MII3 ,Mask of select outputs for MII interface of xMAC3" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEL_MII2 ,Mask of select outputs for MII interface of xMAC2" "Not masked,Masked"
|
|
group.long 0x0C++0x03 "RESET (Reset Controller)"
|
|
line.long 0x00 "RESET_CTRL,Reset Control Register"
|
|
bitfld.long 0x00 26. " EN_RSTOUTn ,Enable the output driver of the reset out pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " RSTOUTn ,Programmable reset (control the signal of the RSTOUT pin of the netX)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FIRMW_RES ,System reset activation" "No reset,Reset"
|
|
bitfld.long 0x00 23. " FIRMW_FLG3 ,Firmware Flag 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " FIRMW_FLG2 ,Firmware Flag 2" "0,1"
|
|
bitfld.long 0x00 21. " FIRMW_FLG1 ,Firmware Flag 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIRMW_FLG0 ,Firmware Flag 0" "0,1"
|
|
bitfld.long 0x00 19. " DIS_XPEC3_RES ,XPEC3 module reset disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DIS_XPEC2_RES ,XPEC2 module reset disable" "No,Yes"
|
|
bitfld.long 0x00 17. " DIS_XPEC1_RES ,XPEC1 module reset disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIS_XPEC0_RES ,XPEC0 module reset disable" "No,Yes"
|
|
bitfld.long 0x00 7. " XPEC3_RES ,XPEC3 module reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " XPEC2_RES ,XPEC2 module reset" "No reset,Reset"
|
|
bitfld.long 0x00 5. " XPEC1_RES ,XPEC1 module reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " XPEC0_RES ,XPEC0 module reset" "No reset,Reset"
|
|
eventfld.long 0x00 3. " FIRMW_RES ,Firmware reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HOST_RES ,Host Interface module reset" "No reset,Reset"
|
|
eventfld.long 0x00 1. " WDG_RES ,Watchdog reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSTINn ,External reset" "No reset,Reset"
|
|
rgroup.long 0x34++0x03 "NETX_REV (netX Revision)"
|
|
line.long 0x00 "NETX_REV,netX Revision Register"
|
|
width 19.
|
|
group.long 0x200++0x03 "WDG (Watchdog)"
|
|
line.long 0x00 "WDG_TR,Watchdog Trigger Register"
|
|
bitfld.long 0x00 31. " WR_ENABLE ,Write enable for timeout register" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " WDG_ACT_EN ,Watchdog Active Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WDG_TRIG ,Watchdog trigger" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " IRQ_STATUS ,Interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " WDG_ACCESS_CODE ,Watchdog access code for triggering"
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "WDG_CNTR,Watchdog Counter"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " WDG_COUNTER ,Actual watchdog counter value"
|
|
if (((d.l(ad:(0x00100000+0x200)))&0x80000000)==0x00000000)
|
|
; Write disabled
|
|
rgroup.long 0x208++0x07
|
|
line.long 0x00 "WDG_IRQ_TIMEOUT,Watchdog Interrupt Timeout"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDG_IRQ_TIMEOUT ,Watchdog interrupt request timeout"
|
|
line.long 0x04 "WDG_RESET_TIMEOUT,Watchdog Reset Timeout"
|
|
hexmask.long.word 0x04 0.--15. 1. " WDG_RES_TIMEOUT ,Watchdog reset request timeout"
|
|
else
|
|
group.long 0x208++0x07
|
|
line.long 0x00 "WDG_IRQ_TIMEOUT,Watchdog Interrupt Timeout"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDG_IRQ_TIMEOUT ,Watchdog interrupt request timeout"
|
|
line.long 0x04 "WDG_RESET_TIMEOUT,Watchdog Reset Timeout"
|
|
hexmask.long.word 0x04 0.--15. 1. " WDG_RES_TIMEOUT ,Watchdog reset request timeout"
|
|
endif
|
|
group.long 0x34D8++0x03 "SYS_STA (System Status)"
|
|
line.long 0x00 "SYS_STAT,System Status"
|
|
bitfld.long 0x00 25. " RUN_DRV ,Driver enable for RUN LED" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RDY_DRV ,Driver enable for RDY LED" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RUN_POL ,Output polarity RUN LED" "Low,High"
|
|
bitfld.long 0x00 18. " RDY_POL ,Output polarity RUN LED" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RUN_IN ,Physical input signal level at RUN pin" "Low,High"
|
|
bitfld.long 0x00 16. " RDY_IN ,Physical input signal level at RDY pin" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " NETX_STA_CODE ,netX status code"
|
|
hexmask.long.byte 0x00 4.--7. 1. " HOST_STATE[3:0] ,User defined host status signals"
|
|
textline " "
|
|
hexmask.long.byte 0x00 2.--3. 1. " NETX_STATE[3:2] ,User defined netX status signals"
|
|
bitfld.long 0x00 1. " RUN ,Signal Level of the RUN LED output" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDY ,Signal level of the RDY LED output" "Low,High"
|
|
width 0xB
|
|
tree.end
|
|
tree "Memory Controller"
|
|
base ad:0x00100100
|
|
width 16.
|
|
group.long 0x00++0x0B "MEM SRAM (Memory Controller for SRAM and FLASH)"
|
|
line.long 0x00 "MEM_SRAM0_CTRL,Memory SRAM Control Register for Chip Select Area 0"
|
|
bitfld.long 0x00 24.--25. " WIDTHEXTMEM ,Data path width of ExtMem0 area" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 16.--17. " WSPOSTPAUSEEXTMEM ,Additional wait states after access" "0 cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " WSPREPASEEXTMEM ,Additional wait states for setup time" "0 cycles,1 cycle,2 cycles,3 cycles"
|
|
bitfld.long 0x00 0.--5. " WSEXTMEM ,Wait states 0 - 63 cycles" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
|
|
line.long 0x04 "MEM_SRAM1_CTRL,Memory SRAM Control Register for Chip Select Area 1"
|
|
bitfld.long 0x04 24.--25. " WIDTHEXTMEM ,Data path width of ExtMem0 area" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x04 16.--17. " WSPOSTPAUSEEXTMEM ,Additional wait states after access" "0 cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " WSPREPASEEXTMEM ,Additional wait states for setup time" "0 cycles,1 cycle,2 cycles,3 cycles"
|
|
bitfld.long 0x04 0.--5. " WSEXTMEM ,Wait states 0 - 63 cycles" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
|
|
line.long 0x08 "MEM_SRAM2_CTRL,Memory SRAM Control Register for Chip Select Area 2"
|
|
bitfld.long 0x08 24.--25. " WIDTHEXTMEM ,Data path width of ExtMem0 area" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x08 16.--17. " WSPOSTPAUSEEXTMEM ,Additional wait states after access" "0 cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " WSPREPASEEXTMEM ,Additional wait states for setup time" "0 cycles,1 cycle,2 cycles,3 cycles"
|
|
bitfld.long 0x08 0.--5. " WSEXTMEM ,Wait states 0 - 63 cycles" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
|
|
width 22.
|
|
group.long 0x40++0x0F "MEM SDRAM (Memory Controller for SDRAM)"
|
|
line.long 0x00 "MEM_SDRAM_CFG_CTRL,Memory SDRAM Configuration Control Register"
|
|
bitfld.long 0x00 31. " REFRESH_ERROR ,Refresh command error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 30. " SDRAM_READY ,SDRAM access ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " REFRESH_MODE ,Refresh priortity mode" "Fixed interval,8 refreshes,16 refreshes,2047 refreshes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CTRL_EN ,SDRAM controller enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXTCLK_EN ,External SDRAM clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SDRAM_PWDN ,SDRAM Power Down" "No power down,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DBUS32 ,SDRAM data bus width" "16 bit,32 bit"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " COLUMNS ,Column address coding" "256,512,1k,2k,4k,8k,16k,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " ROWS ,Row adress coding" "2k,4k,8k,16k,32k,64k,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " BANKS ,Bank address coding" "2,4,8,?..."
|
|
line.long 0x04 "MEM_SDRAM_TIMING_CTRL,Memory SDRAM Timing Control Register"
|
|
bitfld.long 0x04 28. " BYPASS_NEG_DELAY ,Bypass phase shift logic for SDRAM data sampling" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x04 24.--26. " DATA_SAMPLE_PHASE ,Adjustable phase-shift for data sampling SDRAM loopback clock" "0,1,2,3,4,5,?..."
|
|
textline " "
|
|
bitfld.long 0x04 23. " MEM_SDCLK_SSNEG ,Edge polarity of clk400 for clk_memsig (must be set)" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x04 20.--22. " MEM_SDCLK_PHASE ,Adjustable phase-shift for external SDRAM clock" "0,1,2,3,4,5,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " T_REFI ,Average Periodic refresh interval" "3.90 us,7.80 us,15.60 us,31.20 us"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " T_RFC ,Refresh to Command time" "4 clks,5 clks,6 clks,7 clks,8 clks,9 clks,10 clks,11 clks,12 clks,13 clks,14 clks,15 clks,16 clks,17 clks,18 clks,19 clks"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " T_RAS ,Active to Precharge command time" "3 clks,4 clks,5 clks,6 clks,7 clks,8 clks,9 clks,10 clks"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " T_RP ,Precharge command period time" "1 clk,2 clks,3 clks,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " T_WR ,Write recovery time" "1 clk,2 clks,3 clks,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " T_RCD ,Active to Read or Write time" "1 clk,2 clks,3 clks,?..."
|
|
line.long 0x08 "MEM_SDRAM_MODE,Memory SDRAM Mode Register"
|
|
bitfld.long 0x08 4.--6. " MR_CAS ,CAS latency" "Reserved,Reserved,CL2,CL3,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " MR_BURST ,Burst Length" "Reserved,Reserved,4 (32-bit data),8 (16-bit data),?..."
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x00 "MEM_SDRAM_EXT_MODE,Memory SDRAM Extended Mode Register"
|
|
width 24.
|
|
group.long 0x80++0x07 "MEM PRIO (Memory Priority Controller)"
|
|
line.long 0x00 "MEM_PRIO_TIMESLOT_CTRL,Memory Priority Timeslot Control Register"
|
|
bitfld.long 0x00 16.--18. " TS_LENGTH_ARMD_MI ,Length of the timeslot of master m4 (ARM data fetch) on external memory interface" "64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8192 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " TS_LENGTH_ARMI_MI ,Length of the timeslot of master m3 (ARM instruction fetch) on external memory interface" "64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8192 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TS_LENGTH_LCD_MI ,Length of the timeslot of master m2 on external memory interface" "64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8192 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TS_LENGTH_XC_MI ,Length of the timeslot of master m1 on external memory interface" "64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8192 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TS_LENGTH_HIF_MI ,Length of the timeslot of master m0 on external memory interface" "64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8192 cycles"
|
|
line.long 0x04 "MEM_PRIO_ACCESS_CTRL,Memory Priority Access Control Register"
|
|
bitfld.long 0x04 24.--29. " TS_ACCESSRATE_ARMD_MI ,Master m4 (ARM data fetch) access rate on external memory" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
|
|
textline " "
|
|
bitfld.long 0x04 18.--23. " TS_ACCESSRATE_ARMI_MI ,Master m3 (ARM instruction fetch) access rate on external memory" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
|
|
textline " "
|
|
bitfld.long 0x04 12.--17. " TS_ACCESSRATE_LCD_MI ,Master m2 access rate on external memory" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
|
|
textline " "
|
|
bitfld.long 0x04 6.--11. " TS_ACCESSRATE_XC_MI ,Master m1 access rate on external memory" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " TS_ACCESSRATE_HIF_MI ,Master m0 access rate on external memory" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
|
|
width 0x0B
|
|
tree.end
|
|
tree "Extension Bus"
|
|
base ad:0x00103610
|
|
width 0x0F
|
|
group.long 0x00++0x0F
|
|
line.long 0x0 "EXT_CONFIG_CS0,Extension Bus Configuration Chip Select 0"
|
|
hexmask.long.byte 0x0 29.--31. 1. " Talewidth ,Delay time from start cycle until ALE inactive"
|
|
hexmask.long.byte 0x0 26.--28. 1. " Tadrhold ,Delay time from start cycle until invalid address at the data bus"
|
|
textline " "
|
|
hexmask.long.byte 0x0 23.--25. 1. " Tcson ,Delay time from start cycle until Chip Select low"
|
|
hexmask.long.byte 0x0 20.--22. 1. " Trdon ,Delay time from start cycle until RD low in system clocks"
|
|
textline " "
|
|
hexmask.long.byte 0x0 17.--19. 1. " Twron ,Delay time from start cycle until WR low in system clocks"
|
|
hexmask.long.byte 0x0 12.--16. 1. " Trdwroff ,Delay time from start cycle until RD and WR inactive"
|
|
textline " "
|
|
hexmask.long.byte 0x0 7.--11. 1. " Trdwrcyc ,Set the end of an access cycle in system clocks"
|
|
bitfld.long 0x0 6. " WAIT_POLARITY ,WAIT input polarity" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x0 5. " WAIT_EN ,External Wait Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " nRD_MODE ,NRD mode" "Normal,Data direction"
|
|
textline " "
|
|
bitfld.long 0x0 3. " DS_MODE ,Data Strobe Mode" "NWR/nWRL/nWRH,NDS/nDSL/nDSH"
|
|
bitfld.long 0x0 2. " nWR_MODE ,NWR mode" "All,Low write"
|
|
textline " "
|
|
bitfld.long 0x0 1. " 8/16BIT ,Interface width selection" "8 bit,16 bit"
|
|
bitfld.long 0x0 0. " CS_EN ,Chip Select Enable" "Disabled,Enabled"
|
|
line.long 0x4 "EXT_CONFIG_CS1,Extension Bus Configuration Chip Select 1"
|
|
hexmask.long.byte 0x4 29.--31. 1. " Talewidth ,Delay time from start cycle until ALE inactive"
|
|
hexmask.long.byte 0x4 26.--28. 1. " Tadrhold ,Delay time from start cycle until invalid address at the data bus"
|
|
textline " "
|
|
hexmask.long.byte 0x4 23.--25. 1. " Tcson ,Delay time from start cycle until Chip Select low"
|
|
hexmask.long.byte 0x4 20.--22. 1. " Trdon ,Delay time from start cycle until RD low in system clocks"
|
|
textline " "
|
|
hexmask.long.byte 0x4 17.--19. 1. " Twron ,Delay time from start cycle until WR low in system clocks"
|
|
hexmask.long.byte 0x4 12.--16. 1. " Trdwroff ,Delay time from start cycle until RD and WR inactive"
|
|
textline " "
|
|
hexmask.long.byte 0x4 7.--11. 1. " Trdwrcyc ,Set the end of an access cycle in system clocks"
|
|
bitfld.long 0x4 6. " WAIT_POLARITY ,WAIT input polarity" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x4 5. " WAIT_EN ,External Wait Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 4. " nRD_MODE ,NRD mode" "Normal,Data direction"
|
|
textline " "
|
|
bitfld.long 0x4 3. " DS_MODE ,Data Strobe Mode" "NWR/nWRL/nWRH,NDS/nDSL/nDSH"
|
|
bitfld.long 0x4 2. " nWR_MODE ,NWR mode" "All,Low write"
|
|
textline " "
|
|
bitfld.long 0x4 1. " 8/16BIT ,Interface width selection" "8 bit,16 bit"
|
|
bitfld.long 0x4 0. " CS_EN ,Chip Select Enable" "Disabled,Enabled"
|
|
line.long 0x8 "EXT_CONFIG_CS2,Extension Bus Configuration Chip Select 2"
|
|
hexmask.long.byte 0x8 29.--31. 1. " Talewidth ,Delay time from start cycle until ALE inactive"
|
|
hexmask.long.byte 0x8 26.--28. 1. " Tadrhold ,Delay time from start cycle until invalid address at the data bus"
|
|
textline " "
|
|
hexmask.long.byte 0x8 23.--25. 1. " Tcson ,Delay time from start cycle until Chip Select low"
|
|
hexmask.long.byte 0x8 20.--22. 1. " Trdon ,Delay time from start cycle until RD low in system clocks"
|
|
textline " "
|
|
hexmask.long.byte 0x8 17.--19. 1. " Twron ,Delay time from start cycle until WR low in system clocks"
|
|
hexmask.long.byte 0x8 12.--16. 1. " Trdwroff ,Delay time from start cycle until RD and WR inactive"
|
|
textline " "
|
|
hexmask.long.byte 0x8 7.--11. 1. " Trdwrcyc ,Set the end of an access cycle in system clocks"
|
|
bitfld.long 0x8 6. " WAIT_POLARITY ,WAIT input polarity" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x8 5. " WAIT_EN ,External Wait Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 4. " nRD_MODE ,NRD mode" "Normal,Data direction"
|
|
textline " "
|
|
bitfld.long 0x8 3. " DS_MODE ,Data Strobe Mode" "NWR/nWRL/nWRH,NDS/nDSL/nDSH"
|
|
bitfld.long 0x8 2. " nWR_MODE ,NWR mode" "All,Low write"
|
|
textline " "
|
|
bitfld.long 0x8 1. " 8/16BIT ,Interface width selection" "8 bit,16 bit"
|
|
bitfld.long 0x8 0. " CS_EN ,Chip Select Enable" "Disabled,Enabled"
|
|
line.long 0xC "EXT_CONFIG_CS3,Extension Bus Configuration Chip Select 3"
|
|
hexmask.long.byte 0xC 29.--31. 1. " Talewidth ,Delay time from start cycle until ALE inactive"
|
|
hexmask.long.byte 0xC 26.--28. 1. " Tadrhold ,Delay time from start cycle until invalid address at the data bus"
|
|
textline " "
|
|
hexmask.long.byte 0xC 23.--25. 1. " Tcson ,Delay time from start cycle until Chip Select low"
|
|
hexmask.long.byte 0xC 20.--22. 1. " Trdon ,Delay time from start cycle until RD low in system clocks"
|
|
textline " "
|
|
hexmask.long.byte 0xC 17.--19. 1. " Twron ,Delay time from start cycle until WR low in system clocks"
|
|
hexmask.long.byte 0xC 12.--16. 1. " Trdwroff ,Delay time from start cycle until RD and WR inactive"
|
|
textline " "
|
|
hexmask.long.byte 0xC 7.--11. 1. " Trdwrcyc ,Set the end of an access cycle in system clocks"
|
|
bitfld.long 0xC 6. " WAIT_POLARITY ,WAIT input polarity" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0xC 5. " WAIT_EN ,External Wait Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 4. " nRD_MODE ,NRD mode" "Normal,Data direction"
|
|
textline " "
|
|
bitfld.long 0xC 3. " DS_MODE ,Data Strobe Mode" "NWR/nWRL/nWRH,NDS/nDSL/nDSH"
|
|
bitfld.long 0xC 2. " nWR_MODE ,NWR mode" "All,Low write"
|
|
textline " "
|
|
bitfld.long 0xC 1. " 8/16BIT ,Interface width selection" "8 bit,16 bit"
|
|
bitfld.long 0xC 0. " CS_EN ,Chip Select Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "Dual-Port Memory"
|
|
tree "DPMHS (Dual-Port Memory Host Side)"
|
|
base ad:0x0000FF00
|
|
width 0x17
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DPMHS_INT_EN0,DPM Host Side Interrupt Enable 0"
|
|
bitfld.long 0x00 31. " INT_EN ,Global interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MEM_LCK ,Memory lock interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " WDG_NETX ,Watchdog timeout of netX supervision interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SYS_STA ,System status change interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TMR ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " HS_EVENT15 ,Handshake event 15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HS_EVENT14 ,Handshake event 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " HS_EVENT13 ,Handshake event 13 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HS_EVENT12 ,Handshake event 12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HS_EVENT11 ,Handshake event 11 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HS_EVENT10 ,Handshake event 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HS_EVENT9 ,Handshake event 9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HS_EVENT8 ,Handshake event 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HS_EVENT7 ,Handshake event 7 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " HS_EVENT6 ,Handshake event 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HS_EVENT5 ,Handshake event 5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HS_EVENT4 ,Handshake event 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HS_EVENT3 ,Handshake event 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HS_EVENT2 ,Handshake event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HS_EVENT1 ,Handshake event 1 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HS_EVENT0 ,Handshake event 0 interrupt enable" "Disabled,Enabled"
|
|
group.long 0xD0++0x13
|
|
line.long 0x10 "DPMHS_INT_STA0,DPM Host Side Interrupt Status 0"
|
|
eventfld.long 0x10 31. " INT_REQ ,Interrupt request" "Not requested,Requested"
|
|
eventfld.long 0x10 30. " MEM_LCK ,Memory lock interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x10 29. " WDG_NETX ,Watchdog timeout netX supervision interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 26. " SYS_STA ,System status change interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x10 25. " TMR ,Timer interrupt" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x10 16.--23. 1. " IRQ_VECTOR[7:0] ,Interrupt Vector according to the status flags"
|
|
textline " "
|
|
eventfld.long 0x10 15. " HS_EVENT15 ,Handshake event 15 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 14. " HS_EVENT14 ,Handshake event 14 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x10 13. " HS_EVENT13 ,Handshake event 13 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 12. " HS_EVENT12 ,Handshake event 12 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x10 11. " HS_EVENT11 ,Handshake event 11 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 10. " HS_EVENT10 ,Handshake event 10 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x10 9. " HS_EVENT9 ,Handshake event 9 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 8. " HS_EVENT8 ,Handshake event 8 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x10 7. " HS_EVENT7 ,Handshake event 7 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 6. " HS_EVENT6 ,Handshake event 6 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x10 5. " HS_EVENT5 ,Handshake event 5 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 4. " HS_EVENT4 ,Handshake event 4 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x10 3. " HS_EVENT3 ,Handshake event 3 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 2. " HS_EVENT2 ,Handshake event 2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x10 1. " HS_EVENT1 ,Handshake event 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 0. " HS_EVENT0 ,Handshake event 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C "DPMHS_RES_REQ,DPM Host Side Reset Request"
|
|
hexmask.long.word 0x0C 8.--16. 1. " DEL_CNT[16:8] ,Delay counter value (not linear counting)"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CONTROL[7:0]/DEL_CNT[7:0] ,Initiation sequence control/Delay counter value (not linear value)"
|
|
line.long 0x08 "DPMHS_SYS_STA,DPM Host Side System Status"
|
|
hexmask.long.byte 0x08 8.--15. 1. " NETX_STA_CODE ,NetX status code"
|
|
hexmask.long.byte 0x08 4.--7. 1. " HOST_STATE[3:0] ,User defined host status signals"
|
|
textline " "
|
|
hexmask.long.byte 0x08 2.--3. 1. " NETX_STATE[1:0] ,User defined netX status signals"
|
|
bitfld.long 0x08 1. " RUN ,Signal Level of the RUN LED output" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " RDY ,Signal level of the RDY LED output" "Low,High"
|
|
line.long 0x04 "DPMHS_TMR_START_VALUE,DPM Host Side Timer Start Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " TMR_START ,Timer start value for count down or cyclic reload"
|
|
line.long 0x00 "DPMHS_TMR_CTRL,DPM Host Side Timer Control"
|
|
bitfld.long 0x00 15. " START ,Start Timer Count" "Not started,Started"
|
|
bitfld.long 0x00 3. " FNCT ,Timer mode function" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CLKDIV ,Timer clock divider" "100 us,10 us,1 us,100 ns,?..."
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "DPMHS_WDG_ARM_TIMEOUT,DPM Host Side Watchdog ARM"
|
|
hexmask.long.word 0x0 0.--15. 1. " TIMEOUT_VAL ,Timeout value"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "DPMHS_WDG_HOST_TRIG,DPM Host Side Watchdog Host Trigger"
|
|
hexmask.long.byte 0x0 0.--7. 1. " WDG_TRIGGER_CODE ,Watchdog trigger code"
|
|
rgroup.long 0xC0++0x0B
|
|
line.long 0x00 "DPMHS_WDG_HOST_TIMEOUT,DPM Host Side Watchdog Host Timeout"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMEOUT_VAL ,Timeout value"
|
|
base ad:0x00000000
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "DPM_HSRP,DPM Host Side Handshake Register Pair"
|
|
button "DPM_HSRP" " data ad:0x00000000++0xFDFF /long"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPMAS (Dual-Port Memory ARM Side)"
|
|
base ad:0x00103000
|
|
width 19.
|
|
tree "DPM ARM Side Handshake Control Registers"
|
|
group.long 0x680++0x03F
|
|
textline " "
|
|
line.long 0x0 "DPM_ARM_HS_CTRL0,DPM ARM Side Handshake Control Register 0"
|
|
bitfld.long 0x0 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x0 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x0 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x4 "DPM_ARM_HS_CTRL1,DPM ARM Side Handshake Control Register 1"
|
|
bitfld.long 0x4 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x4 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x4 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x8 "DPM_ARM_HS_CTRL2,DPM ARM Side Handshake Control Register 2"
|
|
bitfld.long 0x8 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x8 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x8 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0xC "DPM_ARM_HS_CTRL3,DPM ARM Side Handshake Control Register 3"
|
|
bitfld.long 0xC 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0xC 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0xC 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x10 "DPM_ARM_HS_CTRL4,DPM ARM Side Handshake Control Register 4"
|
|
bitfld.long 0x10 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x10 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x10 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x14 "DPM_ARM_HS_CTRL5,DPM ARM Side Handshake Control Register 5"
|
|
bitfld.long 0x14 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x14 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x18 "DPM_ARM_HS_CTRL6,DPM ARM Side Handshake Control Register 6"
|
|
bitfld.long 0x18 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x18 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x18 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x1C "DPM_ARM_HS_CTRL7,DPM ARM Side Handshake Control Register 7"
|
|
bitfld.long 0x1C 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x1C 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x20 "DPM_ARM_HS_CTRL8,DPM ARM Side Handshake Control Register 8"
|
|
bitfld.long 0x20 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x20 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x20 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x24 "DPM_ARM_HS_CTRL9,DPM ARM Side Handshake Control Register 9"
|
|
bitfld.long 0x24 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x24 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x24 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x28 "DPM_ARM_HS_CTRL10,DPM ARM Side Handshake Control Register 10"
|
|
bitfld.long 0x28 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x28 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x28 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x2C "DPM_ARM_HS_CTRL11,DPM ARM Side Handshake Control Register 11"
|
|
bitfld.long 0x2C 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x2C 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x2C 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x30 "DPM_ARM_HS_CTRL12,DPM ARM Side Handshake Control Register 12"
|
|
bitfld.long 0x30 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x30 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x30 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x34 "DPM_ARM_HS_CTRL13,DPM ARM Side Handshake Control Register 13"
|
|
bitfld.long 0x34 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x34 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x34 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x38 "DPM_ARM_HS_CTRL14,DPM ARM Side Handshake Control Register 14"
|
|
bitfld.long 0x38 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x38 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x38 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
line.long 0x3C "DPM_ARM_HS_CTRL15,DPM ARM Side Handshake Control Register 15"
|
|
bitfld.long 0x3C 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x3C 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
|
|
textline " "
|
|
bitfld.long 0x3C 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
|
|
tree.end
|
|
tree "Data Block End And Mapping"
|
|
width 18.
|
|
group.long 0x640++0x03F
|
|
textline ""
|
|
line.long 0x0 "DPM_ARM_DB_END0,DPM ARM Side Data Block 0 End"
|
|
bitfld.long 0x0 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x0 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
|
|
textline ""
|
|
line.long 0x8 "DPM_ARM_DB_END1,DPM ARM Side Data Block 1 End"
|
|
bitfld.long 0x8 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x8 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
|
|
textline ""
|
|
line.long 0x10 "DPM_ARM_DB_END2,DPM ARM Side Data Block 2 End"
|
|
bitfld.long 0x10 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
|
|
textline ""
|
|
line.long 0x18 "DPM_ARM_DB_END3,DPM ARM Side Data Block 3 End"
|
|
bitfld.long 0x18 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x18 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
|
|
textline ""
|
|
line.long 0x20 "DPM_ARM_DB_END4,DPM ARM Side Data Block 4 End"
|
|
bitfld.long 0x20 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x20 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
|
|
textline ""
|
|
line.long 0x28 "DPM_ARM_DB_END5,DPM ARM Side Data Block 5 End"
|
|
bitfld.long 0x28 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x28 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
|
|
textline ""
|
|
line.long 0x30 "DPM_ARM_DB_END6,DPM ARM Side Data Block 6 End"
|
|
bitfld.long 0x30 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x30 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
|
|
textline ""
|
|
line.long 0x38 "DPM_ARM_DB_END7,DPM ARM Side Data Block 7 End"
|
|
bitfld.long 0x38 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x38 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
|
|
textline ""
|
|
line.long 0x4 "DPM_ARM_DB_MAP0,DPM ARM Side Data Block 0 Address Mapping"
|
|
hexmask.long 0x4 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
|
|
line.long 0xC "DPM_ARM_DB_MAP1,DPM ARM Side Data Block 1 Address Mapping"
|
|
hexmask.long 0xC 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
|
|
line.long 0x14 "DPM_ARM_DB_MAP2,DPM ARM Side Data Block 2 Address Mapping"
|
|
hexmask.long 0x14 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
|
|
line.long 0x1C "DPM_ARM_DB_MAP3,DPM ARM Side Data Block 3 Address Mapping"
|
|
hexmask.long 0x1C 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
|
|
line.long 0x24 "DPM_ARM_DB_MAP4,DPM ARM Side Data Block 4 Address Mapping"
|
|
hexmask.long 0x24 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
|
|
line.long 0x2C "DPM_ARM_DB_MAP5,DPM ARM Side Data Block 5 Address Mapping"
|
|
hexmask.long 0x2C 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
|
|
line.long 0x34 "DPM_ARM_DB_MAP6,DPM ARM Side Data Block 6 Address Mapping"
|
|
hexmask.long 0x34 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
|
|
line.long 0x3C "DPM_ARM_DB_MAP7,DPM ARM Side Data Block 7 Address Mapping"
|
|
hexmask.long 0x3C 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
|
|
tree.end
|
|
tree "Input/Output Pins Control"
|
|
textline " "
|
|
group.long 0x630++0x0B
|
|
line.long 0x008 "DPM_ARM_IO_DATA1,DPM ARM Side Input / Output Data 1"
|
|
bitfld.long 0x08 20. " PIO_DATA84 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 19. " PIO_DATA83 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 18. " PIO_DATA82 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 17. " PIO_DATA81 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 16. " PIO_DATA80 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 15. " PIO_DATA79 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 14. " PIO_DATA78 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 13. " PIO_DATA77 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 12. " PIO_DATA76 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " PIO_DATA75 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 10. " PIO_DATA74 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 9. " PIO_DATA73 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 8. " PIO_DATA72 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 7. " PIO_DATA71 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 6. " PIO_DATA70 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " PIO_DATA69 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 4. " PIO_DATA68 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 3. " PIO_DATA67 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PIO_DATA66 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 1. " PIO_DATA65 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 0. " PIO_DATA64 ,Input/output pin level" "0,1"
|
|
line.long 0x004 "DPM_ARM_IO_DRV_EN1,DPM ARM Side Input / Output Driver Enable 1"
|
|
bitfld.long 0x04 20. " PIO_DRV84 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " PIO_DRV83 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " PIO_DRV82 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PIO_DRV81 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PIO_DRV80 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PIO_DRV79 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " PIO_DRV78 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " PIO_DRV77 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PIO_DRV76 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PIO_DRV75 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " PIO_DRV74 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PIO_DRV73 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PIO_DRV72 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PIO_DRV71 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PIO_DRV70 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PIO_DRV69 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PIO_DRV68 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PIO_DRV67 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PIO_DRV66 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PIO_DRV65 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PIO_DRV64 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
line.long 0x000 "DPM_ARM_IO_MODE1,DPM ARM Side Input / Output Mode 1"
|
|
bitfld.long 0x00 30.--31. " IN_CONTROL ,Input data control" "nPOR,100 MHz,PIO[77] low,PIO[77] high"
|
|
bitfld.long 0x00 20. " PIO_MODE84 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PIO_MODE83 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 18. " PIO_MODE82 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PIO_MODE81 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 16. " PIO_MODE80 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PIO_MODE79 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 14. " PIO_MODE78 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PIO_MODE77 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 12. " PIO_MODE76 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PIO_MODE75 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 10. " PIO_MODE74 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PIO_MODE73 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 8. " PIO_MODE72 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PIO_MODE71 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 6. " PIO_MODE70 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIO_MODE69 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 4. " PIO_MODE68 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIO_MODE67 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 2. " PIO_MODE66 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIO_MODE65 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 0. " PIO_MODE64 ,Pin mode selection" "PIO,Host interface"
|
|
group.long 0x620++0x00B
|
|
line.long 0x08 "DPM_ARM_IO_DATA0,DPM ARM Side Input / Output Data 0"
|
|
bitfld.long 0x08 31. " PIO_DATA63 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 30. " PIO_DATA62 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 29. " PIO_DATA61 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 28. " PIO_DATA60 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 27. " PIO_DATA59 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 26. " PIO_DATA58 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 25. " PIO_DATA57 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 24. " PIO_DATA56 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 23. " PIO_DATA55 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 22. " PIO_DATA54 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 21. " PIO_DATA53 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 20. " PIO_DATA52 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PIO_DATA51 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 18. " PIO_DATA50 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 17. " PIO_DATA49 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 16. " PIO_DATA48 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 15. " PIO_DATA47 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 14. " PIO_DATA46 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 13. " PIO_DATA45 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 12. " PIO_DATA44 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 11. " PIO_DATA43 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 10. " PIO_DATA42 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 9. " PIO_DATA41 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 8. " PIO_DATA40 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " PIO_DATA39 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 6. " PIO_DATA38 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 5. " PIO_DATA37 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PIO_DATA36 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 3. " PIO_DATA35 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 2. " PIO_DATA34 ,Input/output pin level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PIO_DATA33 ,Input/output pin level" "0,1"
|
|
bitfld.long 0x08 0. " PIO_DATA32 ,Input/output pin level" "0,1"
|
|
line.long 0x04 "DPM_ARM_IO_DRV_EN0,DPM ARM Side Input / Output Driver Enable 0"
|
|
bitfld.long 0x04 31. " PIO_DRV63 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " PIO_DRV62 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " PIO_DRV61 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " PIO_DRV60 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PIO_DRV59 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " PIO_DRV58 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " PIO_DRV57 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " PIO_DRV56 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PIO_DRV55 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " PIO_DRV54 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " PIO_DRV53 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " PIO_DRV52 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PIO_DRV51 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PIO_DRV50 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PIO_DRV49 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " PIO_DRV48 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PIO_DRV47 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PIO_DRV46 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PIO_DRV45 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " PIO_DRV44 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PIO_DRV43 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PIO_DRV42 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PIO_DRV41 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " PIO_DRV40 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PIO_DRV39 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PIO_DRV38 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PIO_DRV37 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " PIO_DRV36 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PIO_DRV35 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PIO_DRV34 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PIO_DRV33 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PIO_DRV32 ,I/O Pin driver output enable" "Disabled,Enabled"
|
|
line.long 0x00 "DPM_ARM_IO_MODE0,DPM ARM Side Input / Output Mode 0"
|
|
bitfld.long 0x00 31. " PIO_MODE63 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 30. " PIO_MODE62 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PIO_MODE61 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 28. " PIO_MODE60 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PIO_MODE59 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 26. " PIO_MODE58 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PIO_MODE57 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 24. " PIO_MODE56 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PIO_MODE55 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 22. " PIO_MODE54 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PIO_MODE53 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 20. " PIO_MODE52 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PIO_MODE51 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 18. " PIO_MODE50 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PIO_MODE49 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 16. " PIO_MODE48 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PIO_MODE47 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 14. " PIO_MODE46 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PIO_MODE45 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 12. " PIO_MODE44 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PIO_MODE43 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 10. " PIO_MODE42 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PIO_MODE41 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 8. " PIO_MODE40 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PIO_MODE39 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 6. " PIO_MODE38 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIO_MODE37 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 4. " PIO_MODE36 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIO_MODE35 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 2. " PIO_MODE34 ,Pin mode selection" "PIO,Host interface"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIO_MODE33 ,Pin mode selection" "PIO,Host interface"
|
|
bitfld.long 0x00 0. " PIO_MODE32 ,Pin mode selection" "PIO,Host interface"
|
|
tree.end
|
|
tree "Interface and Clockout Configuration"
|
|
width 20.
|
|
group.long 0x604++0x00B
|
|
line.long 0x008 "DPM_ARM_IF_CFG1,DPM ARM Side Interface Configuration Register 1"
|
|
bitfld.long 0x008 31. " WRITE_PROTECT ,Write protection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x008 30. " IRQ_POL_PIO72 ,External interrupt polarity for PIO[72]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x008 29. " IRQ_POL_PIO47 ,External interrupt polarity for PIO[47]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x008 28. " IRQ_POL_PIO40 ,External interrupt polarity for PIO[40]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x008 27. " IRQ_POL_PIO36 ,External interrupt polarity for PIO[36]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x008 26. " IRQ_POL_PIO35 ,External interrupt polarity for PIO[35]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x008 24.--25. " DATAOUT_VALID_TIME ,Sets the valid read data output time in system clocks" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x008 23. " DIS_BUSY_TIMEOUT ,Disable busy timeout" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x008 19. " ADR_IN15 ,Logical level for Dual-Port memory address line 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x008 18. " ADR_IN14 ,Logical level for Dual-Port memory address line 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x008 17. " ADR_IN13 ,Logical level for Dual-Port memory address line 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x008 16. " ADR_IN12 ,Logical level for Dual-Port memory address line 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x008 15. " CS_COMP_SRC19 ,Chip select compare source for address 19" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x008 14. " CS_COMP_SRC18 ,Chip select compare source for address 18" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x008 13. " CS_COMP_SRC17 ,Chip select compare source for address 17" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x008 12. " CS_COMP_SRC16 ,Chip select compare source for address 16" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x008 11. " CS_COMP_SRC15 ,Chip select compare source for address 15" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x008 10. " CS_COMP_SRC14 ,Chip select compare source for address 14" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x008 9. " CS_COMP_SRC13 ,Chip select compare source for address 13" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x008 8. " CS_COMP_SRC12 ,Chip select compare source for address 12" "Internal,External"
|
|
textline " "
|
|
hexmask.long.byte 0x008 0.--7. 1. " CS_COMP_VAL[19:12] ,Chip Select compare value"
|
|
line.long 0x004 "DPM_ARM_IF_CFG0,DPM ARM Side Host Interface Configuration Register 0"
|
|
bitfld.long 0x004 31. " DISABLE_WR ,Write access to the register" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x004 28.--30. " HIF_MODE ,Host interface mode selection" "Disabled,Extension Bus,uP Bus 8 bit,uP Bus 16 bit,I/O Mode,?..."
|
|
textline " "
|
|
bitfld.long 0x004 26.--27. " RD_CTRL ,Configure the control lines for Dual-Port memory read accesses to netX" "RDn;PIO[52],RDn/A0/BHEn;PIO[52/73/43],Disabled,RDn/BHEn;PIO[52/43]"
|
|
textline " "
|
|
bitfld.long 0x004 24.--25. " WR_CTRL ,Configure the control lines for Dual-Port memory write accesses to netX" "WRLn;PIO[45],RDn/A0/BHEn;PIO[52/73/43],WRLn/WRHn;PIO[45/44],RDn/BHEn;PIO[52/43]"
|
|
textline " "
|
|
bitfld.long 0x004 21.--23. " BE1_MODE ,Byte Enable 1 selection" "Low BHEn;PIO[43],High A0;PIO[73],Low RDn/WRLn;PIO[52/45],Low RDn/WRHnPIO[52/44],High internal A0,High BHEn;PIO[43],High activation,High activation"
|
|
textline " "
|
|
bitfld.long 0x004 18.--20. " BE0_MODE ,Byte Enable 0 selection" "Low CS0n;PIO[51],Low A0;PIO[73],Low RDn/WRLn;PIO[52/45],Low internal A0,Low activation,Low activation,Low activation,Low activation"
|
|
textline " "
|
|
bitfld.long 0x004 16.--17. " CIS_MODE ,The CIS memory array select" "Never,Always,Low WRHn,Low PIO[40]"
|
|
textline " "
|
|
bitfld.long 0x004 14.--15. " WAIT_DRV ,Wait mode output drive control; RDY / PIO[46]" "Tri-state,Push/pull,Open drain/source,Sustained tri-state"
|
|
textline " "
|
|
bitfld.long 0x004 13. " WAIT_MODE ,WAIT/BUSY or READY mode function" "Wait,Ready"
|
|
textline " "
|
|
bitfld.long 0x004 12. " WAIT_POLARITY ,Wait polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x004 9.--11. " CS_MODE ,Configure the logic for chip select generation" "Disabled,Internal,Low CS0n/BHEn;PIO[51/43],High CS0n/BHEn;PIO[51/43],Low CS0n PIO[51],Disabled,Low ALE;PIO[35],High ALE;PIO[35]"
|
|
textline " "
|
|
bitfld.long 0x004 7.--8. " IRQ_MODE ,Select the interrupt pin output function of IRQ / INT pin (PIO[47])" "Tri-state,Fixed level,Push/pull,Open drain/source"
|
|
textline " "
|
|
bitfld.long 0x004 6. " IRQ_POLARITY ,Active polarity output" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x004 4.--5. " ALE_MODE ,Selection of address input latching mode (PIO[35] == ALE/AEN)" "Low,High,Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x004 3. " ADDR_MODE ,8/16 bit address mode" "Non multiplexed,Multiplexed"
|
|
textline " "
|
|
bitfld.long 0x004 0.--2. " OE_MODE ,Output driver control of data lines for read accesses" "High RDn low BHe/low A0;PIO[52/43/73],Low RDn BHE/low A0;PIO[52/43/73],Low RDn;PIO[52],Low RDn CS0n/low BHEn;PIO[52/43/51],High RDn BHEn;PIO[52/43],?..."
|
|
line.long 0x000 "DPM_ARM_CLKOUT_CFG,DPM ARM Side Clock out configuration"
|
|
bitfld.long 0x000 31. " CLKOUT_EN ,CLKOUT driver enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x000 0.--29. 1. " CLK_SEL ,Clockout frequency selection"
|
|
tree.end
|
|
tree "DPM ARM View Handshake Registers"
|
|
textline " "
|
|
textline " "
|
|
width 19.
|
|
hgroup.long 0x500++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA0,DPM ARM View Handshake Register 0"
|
|
in
|
|
hgroup.long 0x504++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA1,DPM ARM View Handshake Register 1"
|
|
in
|
|
hgroup.long 0x508++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA2,DPM ARM View Handshake Register 2"
|
|
in
|
|
hgroup.long 0x50C++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA3,DPM ARM View Handshake Register 3"
|
|
in
|
|
hgroup.long 0x510++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA4,DPM ARM View Handshake Register 4"
|
|
in
|
|
hgroup.long 0x514++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA5,DPM ARM View Handshake Register 5"
|
|
in
|
|
hgroup.long 0x518++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA6,DPM ARM View Handshake Register 6"
|
|
in
|
|
hgroup.long 0x51C++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA7,DPM ARM View Handshake Register 7"
|
|
in
|
|
hgroup.long 0x520++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA8,DPM ARM View Handshake Register 8"
|
|
in
|
|
hgroup.long 0x524++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA9,DPM ARM View Handshake Register 9"
|
|
in
|
|
hgroup.long 0x528++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA10,DPM ARM View Handshake Register 10"
|
|
in
|
|
hgroup.long 0x52C++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA11,DPM ARM View Handshake Register 11"
|
|
in
|
|
hgroup.long 0x530++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA12,DPM ARM View Handshake Register 12"
|
|
in
|
|
hgroup.long 0x534++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA13,DPM ARM View Handshake Register 13"
|
|
in
|
|
hgroup.long 0x538++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA14,DPM ARM View Handshake Register 14"
|
|
in
|
|
hgroup.long 0x53C++0x003
|
|
hide.long 0x000 "DPM_ARM_HS_DATA15,DPM ARM View Handshake Register 15"
|
|
in
|
|
wgroup 0x0++0x0
|
|
tree.end
|
|
width 19.
|
|
tree "Interrupt Registers"
|
|
textline " "
|
|
group.long 0x4F0++0x003
|
|
line.long 0x000 "DPM_ARM_INT_EN0,DPM ARM Side Interrupt Enable 1"
|
|
bitfld.long 0x000 31. " GLB_EN ,Global Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x000 30. " MEM_LCK ,Memory Lock Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 29. " WDG ,Watchdog timeout host supervision" "Disabled,Enabled"
|
|
bitfld.long 0x000 28. " INT_PIO72 ,External interrupt enable for pin PIO72" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 27. " INT_PIO47 ,External interrupt enable for pin PIO47" "Disabled,Enabled"
|
|
bitfld.long 0x000 26. " INT_PIO40 ,External interrupt enable for pin PIO40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 25. " INT_PIO36 ,External interrupt enable for pin PIO36" "Disabled,Enabled"
|
|
bitfld.long 0x000 24. " INT_PIO35 ,External interrupt enable for pin PIO35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 15. " HS15 ,Handshake event enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x000 14. " HS14 ,Handshake event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 13. " HS13 ,Handshake event enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x000 12. " HS12 ,Handshake event enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 11. " HS11 ,Handshake event enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x000 10. " HS10 ,Handshake event enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 9. " HS9 ,Handshake event enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x000 8. " HS8 ,Handshake event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 7. " HS7 ,Handshake event enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x000 6. " HS6 ,Handshake event enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 5. " HS5 ,Handshake event enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x000 4. " HS4 ,Handshake event enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 3. " HS3 ,Handshake event enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x000 2. " HS2 ,Handshake event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 1. " HS1 ,Handshake event enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x000 0. " HS0 ,Handshake event enable 0" "Disabled,Enabled"
|
|
group.long 0x4E0++0x003
|
|
line.long 0x0 "DPM_ARM_INT_STAT0,DPM ARM Side Interrupt Status 1"
|
|
eventfld.long 0x000 31. " IRQ_REQ ,Global signaling of interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 30. " MEM_LCK ,Memory Lock Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x000 29. " WDG_IRQ ,Watchdog timeout host supervision" "No supervision,Supervision"
|
|
textline " "
|
|
eventfld.long 0x000 28. " INT_PIO72 ,External interrupt enable for pin PIO72" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 27. " INT_PIO47 ,External interrupt enable for pin PIO47" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 26. " INT_PIO40 ,External interrupt enable for pin PIO40" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 25. " INT_PIO36 ,External interrupt enable for pin PIO36" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 24. " INT_PIO35 ,External interrupt enable for pin PIO35" "No interrupt,Interrupt"
|
|
textline " "
|
|
hexmask.long.byte 0x000 16.--23. 1. " IRQ_VECTOR[7:0] ,Interrupt Vector generated by the interrupt status flags"
|
|
textline " "
|
|
eventfld.long 0x000 15. " HS15 ,Handshake event status 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 14. " HS14 ,Handshake event status 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 13. " HS13 ,Handshake event status 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 12. " HS12 ,Handshake event status 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 11. " HS11 ,Handshake event status 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 10. " HS10 ,Handshake event status 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 9. " HS9 ,Handshake event status 9" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 8. " HS8 ,Handshake event status 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 7. " HS7 ,Handshake event status 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 6. " HS6 ,Handshake event status 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 5. " HS5 ,Handshake event status 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 4. " HS4 ,Handshake event status 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 3. " HS3 ,Handshake event status 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 2. " HS2 ,Handshake event status 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 1. " HS1 ,Handshake event status 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x000 0. " HS0 ,Handshake event status 0" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "WDG, CIS, Extension Bus, Handshake Data AND SYS Status Registers"
|
|
width 25.
|
|
group.long 0x4C8++0x007
|
|
line.long 0x004 "DPM_ARM_WDG_ARM_TRIG,DPM ARM Side Watchdog ARM Supervision Trigger"
|
|
hexmask.long.byte 0x004 0.--7. 1. " WDG_ACCESS_CODE ,Watchdog access code for triggering"
|
|
line.long 0x000 "DPM_ARM_WDG_ARM_TIMEOUT,DPM ARM Side Watchdog ARM Timeout"
|
|
hexmask.long.word 0x000 0.--15. 1. " TIMEOUT_VAL ,Timeout value"
|
|
group.long 0x4BC++0x007
|
|
line.long 0x004 "DPMAS_WDG_HOST_TIMEOUT,DPM ARM Side Watchdog Host Timeout"
|
|
hexmask.long.word 0x004 0.--15. 1. " TIMEOUT_VAL ,Timeout value"
|
|
line.long 0x000 "DPM_ARM_CIS_MAP,DPM ARM Side CIS Mapping Address"
|
|
hexmask.long.tbyte 0x000 8.--31. 1. " CIS_MAPPING ,CIS Mapping Address"
|
|
textline " "
|
|
bitfld.long 0x000 1. " WR_ENABLE ,Write accesses to the CIS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x000 0. " CIS_ENABLE ,Enable CIS MODE" "Disabled,Enabled"
|
|
group.long 0x4D8++0x3
|
|
line.long 0x0 "DPM_ARM_SYS_STAT,System Status Register"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "Peripheral Functions"
|
|
tree "GPIO (General Purpose IOs)"
|
|
base ad:0x00100800
|
|
width 12.
|
|
tree "GPIO Configuration Register"
|
|
if (((d.l(ad:(0x00100800+0x0)))&0x3)==0x0)
|
|
group.long (0x00+0x0)++0x3
|
|
line.long 0x0 "GPIO_CFG0,GPIO 0 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x0)))&0x3)==0x1)
|
|
group.long (0x00+0x0)++0x3
|
|
line.long 0x0 "GPIO_CFG0,GPIO 0 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[0],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x0)++0x3
|
|
line.long 0x0 "GPIO_CFG0,GPIO 0 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x4)))&0x3)==0x0)
|
|
group.long (0x00+0x4)++0x3
|
|
line.long 0x0 "GPIO_CFG1,GPIO 1 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x4)))&0x3)==0x1)
|
|
group.long (0x00+0x4)++0x3
|
|
line.long 0x0 "GPIO_CFG1,GPIO 1 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[1],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x4)++0x3
|
|
line.long 0x0 "GPIO_CFG1,GPIO 1 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x8)))&0x3)==0x0)
|
|
group.long (0x00+0x8)++0x3
|
|
line.long 0x0 "GPIO_CFG2,GPIO 2 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x8)))&0x3)==0x1)
|
|
group.long (0x00+0x8)++0x3
|
|
line.long 0x0 "GPIO_CFG2,GPIO 2 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[2],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x8)++0x3
|
|
line.long 0x0 "GPIO_CFG2,GPIO 2 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0xC)))&0x3)==0x0)
|
|
group.long (0x00+0xC)++0x3
|
|
line.long 0x0 "GPIO_CFG3,GPIO 3 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0xC)))&0x3)==0x1)
|
|
group.long (0x00+0xC)++0x3
|
|
line.long 0x0 "GPIO_CFG3,GPIO 3 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[3],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0xC)++0x3
|
|
line.long 0x0 "GPIO_CFG3,GPIO 3 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x10)))&0x3)==0x0)
|
|
group.long (0x00+0x10)++0x3
|
|
line.long 0x0 "GPIO_CFG4,GPIO 4 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x10)))&0x3)==0x1)
|
|
group.long (0x00+0x10)++0x3
|
|
line.long 0x0 "GPIO_CFG4,GPIO 4 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[4],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x10)++0x3
|
|
line.long 0x0 "GPIO_CFG4,GPIO 4 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x14)))&0x3)==0x0)
|
|
group.long (0x00+0x14)++0x3
|
|
line.long 0x0 "GPIO_CFG5,GPIO 5 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x14)))&0x3)==0x1)
|
|
group.long (0x00+0x14)++0x3
|
|
line.long 0x0 "GPIO_CFG5,GPIO 5 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[5],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x14)++0x3
|
|
line.long 0x0 "GPIO_CFG5,GPIO 5 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x18)))&0x3)==0x0)
|
|
group.long (0x00+0x18)++0x3
|
|
line.long 0x0 "GPIO_CFG6,GPIO 6 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x18)))&0x3)==0x1)
|
|
group.long (0x00+0x18)++0x3
|
|
line.long 0x0 "GPIO_CFG6,GPIO 6 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[6],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x18)++0x3
|
|
line.long 0x0 "GPIO_CFG6,GPIO 6 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x1C)))&0x3)==0x0)
|
|
group.long (0x00+0x1C)++0x3
|
|
line.long 0x0 "GPIO_CFG7,GPIO 7 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x1C)))&0x3)==0x1)
|
|
group.long (0x00+0x1C)++0x3
|
|
line.long 0x0 "GPIO_CFG7,GPIO 7 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[7],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x1C)++0x3
|
|
line.long 0x0 "GPIO_CFG7,GPIO 7 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x20)))&0x3)==0x0)
|
|
group.long (0x00+0x20)++0x3
|
|
line.long 0x0 "GPIO_CFG8,GPIO 8 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x20)))&0x3)==0x1)
|
|
group.long (0x00+0x20)++0x3
|
|
line.long 0x0 "GPIO_CFG8,GPIO 8 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[8],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x20)++0x3
|
|
line.long 0x0 "GPIO_CFG8,GPIO 8 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x24)))&0x3)==0x0)
|
|
group.long (0x00+0x24)++0x3
|
|
line.long 0x0 "GPIO_CFG9,GPIO 9 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x24)))&0x3)==0x1)
|
|
group.long (0x00+0x24)++0x3
|
|
line.long 0x0 "GPIO_CFG9,GPIO 9 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[9],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x24)++0x3
|
|
line.long 0x0 "GPIO_CFG9,GPIO 9 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x28)))&0x3)==0x0)
|
|
group.long (0x00+0x28)++0x3
|
|
line.long 0x0 "GPIO_CFG10,GPIO 10 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x28)))&0x3)==0x1)
|
|
group.long (0x00+0x28)++0x3
|
|
line.long 0x0 "GPIO_CFG10,GPIO 10 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[10],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x28)++0x3
|
|
line.long 0x0 "GPIO_CFG10,GPIO 10 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x2C)))&0x3)==0x0)
|
|
group.long (0x00+0x2C)++0x3
|
|
line.long 0x0 "GPIO_CFG11,GPIO 11 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x2C)))&0x3)==0x1)
|
|
group.long (0x00+0x2C)++0x3
|
|
line.long 0x0 "GPIO_CFG11,GPIO 11 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[11],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x2C)++0x3
|
|
line.long 0x0 "GPIO_CFG11,GPIO 11 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x30)))&0x3)==0x0)
|
|
group.long (0x00+0x30)++0x3
|
|
line.long 0x0 "GPIO_CFG12,GPIO 12 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x30)))&0x3)==0x1)
|
|
group.long (0x00+0x30)++0x3
|
|
line.long 0x0 "GPIO_CFG12,GPIO 12 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[12],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x30)++0x3
|
|
line.long 0x0 "GPIO_CFG12,GPIO 12 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x34)))&0x3)==0x0)
|
|
group.long (0x00+0x34)++0x3
|
|
line.long 0x0 "GPIO_CFG13,GPIO 13 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x34)))&0x3)==0x1)
|
|
group.long (0x00+0x34)++0x3
|
|
line.long 0x0 "GPIO_CFG13,GPIO 13 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[13],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x34)++0x3
|
|
line.long 0x0 "GPIO_CFG13,GPIO 13 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x38)))&0x3)==0x0)
|
|
group.long (0x00+0x38)++0x3
|
|
line.long 0x0 "GPIO_CFG14,GPIO 14 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x38)))&0x3)==0x1)
|
|
group.long (0x00+0x38)++0x3
|
|
line.long 0x0 "GPIO_CFG14,GPIO 14 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[14],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x38)++0x3
|
|
line.long 0x0 "GPIO_CFG14,GPIO 14 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
if (((d.l(ad:(0x00100800+0x3C)))&0x3)==0x0)
|
|
group.long (0x00+0x3C)++0x3
|
|
line.long 0x0 "GPIO_CFG15,GPIO 15 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Read,Capture(continued)at rising edge,Capture(once)at rising edge,Capture (high level)"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
elif (((d.l(ad:(0x00100800+0x3C)))&0x3)==0x1)
|
|
group.long (0x00+0x3C)++0x3
|
|
line.long 0x0 "GPIO_CFG15,GPIO 15 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
bitfld.long 0x0 3.--4. " MODE ,The GPIO mode define" "Set to 0,Set to 1,Set to gpio_out[15],Pwm"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
else
|
|
group.long (0x00+0x3C)++0x3
|
|
line.long 0x0 "GPIO_CFG15,GPIO 15 Configuration Register"
|
|
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INV ,Invert input/output value" "Not inverted,Inverted"
|
|
bitfld.long 0x0 0.--1. " IOCFG ,Defines the input/output configuration mode" "GP input,GP output,UART,?..."
|
|
endif
|
|
tree.end
|
|
width 19.
|
|
tree "GPIO Threshold or Capture Register"
|
|
group.long 0x40++0x3F
|
|
line.long 0x0 "GPIO_THRSH_CAPT0,GPIO 0 Threshold or Capture Register"
|
|
line.long 0x4 "GPIO_THRSH_CAPT1,GPIO 1 Threshold or Capture Register"
|
|
line.long 0x8 "GPIO_THRSH_CAPT2,GPIO 2 Threshold or Capture Register"
|
|
line.long 0xC "GPIO_THRSH_CAPT3,GPIO 3 Threshold or Capture Register"
|
|
line.long 0x10 "GPIO_THRSH_CAPT4,GPIO 4 Threshold or Capture Register"
|
|
line.long 0x14 "GPIO_THRSH_CAPT5,GPIO 5 Threshold or Capture Register"
|
|
line.long 0x18 "GPIO_THRSH_CAPT6,GPIO 6 Threshold or Capture Register"
|
|
line.long 0x1C "GPIO_THRSH_CAPT7,GPIO 7 Threshold or Capture Register"
|
|
line.long 0x20 "GPIO_THRSH_CAPT8,GPIO 8 Threshold or Capture Register"
|
|
line.long 0x24 "GPIO_THRSH_CAPT9,GPIO 9 Threshold or Capture Register"
|
|
line.long 0x28 "GPIO_THRSH_CAPT10,GPIO 10 Threshold or Capture Register"
|
|
line.long 0x2C "GPIO_THRSH_CAPT11,GPIO 11 Threshold or Capture Register"
|
|
line.long 0x30 "GPIO_THRSH_CAPT12,GPIO 12 Threshold or Capture Register"
|
|
line.long 0x34 "GPIO_THRSH_CAPT13,GPIO 13 Threshold or Capture Register"
|
|
line.long 0x38 "GPIO_THRSH_CAPT14,GPIO 14 Threshold or Capture Register"
|
|
line.long 0x3C "GPIO_THRSH_CAPT15,GPIO 15 Threshold or Capture Register"
|
|
tree.end
|
|
textline " "
|
|
width 21.
|
|
group.long 0x80++0x3F
|
|
line.long 0x0 "GPIO_CNTR0_CTRL,GPIO Counter 0 Control"
|
|
bitfld.long 0x0 7.--10. " GPIO_REF ,gpio reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 6. " SEL_EVENT ,Select external event" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RST_EN ,Automatic reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " CNT_EVENT ,Count event" "Clock,External"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IRQ_EN ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " ONCE ,Once or continue count" "Continue,Once"
|
|
textline " "
|
|
bitfld.long 0x0 1. " SYM_NASYM ,Symetric mode" "Asymmetric,Symmetric"
|
|
bitfld.long 0x0 0. " RUN ,Start or stop counter" "Stopped,Started"
|
|
line.long 0x4 "GPIO_CNTR1_CTRL,GPIO Counter 1 Control"
|
|
bitfld.long 0x4 7.--10. " GPIO_REF ,gpio reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 6. " SEL_EVENT ,Select external event" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x4 5. " RST_EN ,Automatic reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 4. " CNT_EVENT ,Count event" "Clock,External"
|
|
textline " "
|
|
bitfld.long 0x4 3. " IRQ_EN ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " ONCE ,Once or continue count" "Continue,Once"
|
|
textline " "
|
|
bitfld.long 0x4 1. " SYM_NASYM ,Symetric mode" "Asymmetric,Symmetric"
|
|
bitfld.long 0x4 0. " RUN ,Start or stop counter" "Stopped,Started"
|
|
line.long 0x8 "GPIO_CNTR2_CTRL,GPIO Counter 2 Control"
|
|
bitfld.long 0x8 7.--10. " GPIO_REF ,gpio reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 6. " SEL_EVENT ,Select external event" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x8 5. " RST_EN ,Automatic reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 4. " CNT_EVENT ,Count event" "Clock,External"
|
|
textline " "
|
|
bitfld.long 0x8 3. " IRQ_EN ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " ONCE ,Once or continue count" "Continue,Once"
|
|
textline " "
|
|
bitfld.long 0x8 1. " SYM_NASYM ,Symetric mode" "Asymmetric,Symmetric"
|
|
bitfld.long 0x8 0. " RUN ,Start or stop counter" "Stopped,Started"
|
|
line.long 0xC "GPIO_CNTR3_CTRL,GPIO Counter 3 Control"
|
|
bitfld.long 0xC 7.--10. " GPIO_REF ,gpio reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 6. " SEL_EVENT ,Select external event" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0xC 5. " RST_EN ,Automatic reset enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 4. " CNT_EVENT ,Count event" "Clock,External"
|
|
textline " "
|
|
bitfld.long 0xC 3. " IRQ_EN ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 2. " ONCE ,Once or continue count" "Continue,Once"
|
|
textline " "
|
|
bitfld.long 0xC 1. " SYM_NASYM ,Symetric mode" "Asymmetric,Symmetric"
|
|
bitfld.long 0xC 0. " RUN ,Start or stop counter" "Stopped,Started"
|
|
line.long 0x10 "GPIO_CNTR4_CTRL,GPIO Counter 4 Control"
|
|
bitfld.long 0x10 7.--10. " GPIO_REF ,gpio reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 6. " SEL_EVENT ,Select external event" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 5. " RST_EN ,Automatic reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " CNT_EVENT ,Count event" "Clock,External"
|
|
textline " "
|
|
bitfld.long 0x10 3. " IRQ_EN ,Interrupt request enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " ONCE ,Once or continue count" "Continue,Once"
|
|
textline " "
|
|
bitfld.long 0x10 1. " SYM_NASYM ,Symetric mode" "Asymmetric,Symmetric"
|
|
bitfld.long 0x10 0. " RUN ,Start or stop counter" "Stopped,Started"
|
|
line.long 0x14 "GPIO_CNTR0_MAX,GPIO Counter 0 Maximum Value"
|
|
line.long 0x18 "GPIO_CNTR1_MAX,GPIO Counter 1 Maximum Value"
|
|
line.long 0x1C "GPIO_CNTR2_MAX,GPIO Counter 2 Maximum Value"
|
|
line.long 0x20 "GPIO_CNTR3_MAX,GPIO Counter 3 Maximum Value"
|
|
line.long 0x24 "GPIO_CNTR4_MAX,GPIO Counter 4 Maximum Value"
|
|
line.long 0x28 "GPIO_CNTR0_CNT,GPIO Counter 0 Current Value"
|
|
line.long 0x2C "GPIO_CNTR1_CNT,GPIO Counter 1 Current Value"
|
|
line.long 0x30 "GPIO_CNTR2_CNT,GPIO Counter 2 Current Value"
|
|
line.long 0x34 "GPIO_CNTR3_CNT,GPIO Counter 3 Current Value"
|
|
line.long 0x38 "GPIO_CNTR4_CNT,GPIO Counter 4 Current Value"
|
|
line.long 0x3C "GPIO_IRQ_MSK_SET,GPIO Interrupt Enable"
|
|
setclrfld.long 0x3C 21. 0x3C 21. 0x40 21. " SYSTIME_set/clr ,Enable interrupt request if sys_time_ns = gpio_systime_ns_cmp" "Disabled,Enabled"
|
|
setclrfld.long 0x3C 20. 0x3C 20. 0x40 20. " CNT4_set/clr ,Enable interrupt request for counter4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x3C 19. 0x3C 19. 0x40 19. " CNT3_set/clr ,Enable interrupt request for counter3" "Disabled,Enabled"
|
|
setclrfld.long 0x3C 18. 0x3C 18. 0x40 18. " CNT2_set/clr ,Enable interrupt request for counter2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x3C 17. 0x3C 17. 0x40 17. " CNT1_set/clr ,Enable interrupt request for counter1" "Disabled,Enabled"
|
|
setclrfld.long 0x3C 16. 0x3C 16. 0x40 16. " CNT0_set/clr ,Enable interrupt request for counter0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x3C 15. 0x3C 15. 0x40 15. " GPIO15_set/clr ,Enable interrupt request for GPIO15" "Disabled,Enabled"
|
|
setclrfld.long 0x3C 14. 0x3C 14. 0x40 14. " GPIO14_set/clr ,Enable interrupt request for GPIO14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x3C 13. 0x3C 13. 0x40 13. " GPIO13_set/clr ,Enable interrupt request for GPIO13" "Disabled,Enabled"
|
|
setclrfld.long 0x3C 12. 0x3C 12. 0x40 12. " GPIO12_set/clr ,Enable interrupt request for GPIO12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x3C 11. 0x3C 11. 0x40 11. " GPIO11_set/clr ,Enable interrupt request for GPIO11" "Disabled,Enabled"
|
|
setclrfld.long 0x3C 10. 0x3C 10. 0x40 10. " GPIO10_set/clr ,Enable interrupt request for GPIO10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x3C 9. 0x3C 9. 0x40 9. " GPIO9_set/clr ,Enable interrupt request for GPIO9" "Disabled,Enabled"
|
|
setclrfld.long 0x3C 8. 0x3C 8. 0x40 8. " GPIO8_set/clr ,Enable interrupt request for GPIO8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x3C 7. 0x3C 7. 0x40 7. " GPIO7_set/clr ,Enable interrupt request for GPIO7" "Disabled,Enabled"
|
|
setclrfld.long 0x3C 6. 0x3C 6. 0x40 6. " GPIO6_set/clr ,Enable interrupt request for GPIO6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x3C 5. 0x3C 5. 0x40 5. " GPIO5_set/clr ,Enable interrupt request for GPIO5" "Disabled,Enabled"
|
|
setclrfld.long 0x3C 4. 0x3C 4. 0x40 4. " GPIO4_set/clr ,Enable interrupt request for GPIO4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x3C 3. 0x3C 3. 0x40 3. " GPIO3_set/clr ,Enable interrupt request for GPIO3" "Disabled,Enabled"
|
|
setclrfld.long 0x3C 2. 0x3C 2. 0x40 2. " GPIO2_set/clr ,Enable interrupt request for GPIO2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x3C 1. 0x3C 1. 0x40 1. " GPIO1_set/clr ,Enable interrupt request for GPIO1" "Disabled,Enabled"
|
|
setclrfld.long 0x3C 0. 0x3C 0. 0x40 0. " GPIO0_set/clr ,Enable interrupt request for GPIO0" "Disabled,Enabled"
|
|
group.long 0xC4++0x0B
|
|
line.long 0x00 "GPIO_SYSTIME_NS_CMP,GPIO System Time NS Compare Value"
|
|
width 10.
|
|
line.long 0x04 "GPIO_OUT,GPIO Output Register"
|
|
bitfld.long 0x04 15. " VAL_OUT15 ,GPIO15 output values" "0,1"
|
|
bitfld.long 0x04 14. " VAL_OUT14 ,GPIO14 output values" "0,1"
|
|
bitfld.long 0x04 13. " VAL_OUT13 ,GPIO13 output values" "0,1"
|
|
bitfld.long 0x04 12. " VAL_OUT12 ,GPIO12 output values" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " VAL_OUT11 ,GPIO11 output values" "0,1"
|
|
bitfld.long 0x04 10. " VAL_OUT10 ,GPIO10 output values" "0,1"
|
|
bitfld.long 0x04 9. " VAL_OUT9 ,GPIO9 output values" "0,1"
|
|
bitfld.long 0x04 8. " VAL_OUT8 ,GPIO8 output values" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " VAL_OUT7 ,GPIO7 output values" "0,1"
|
|
bitfld.long 0x04 6. " VAL_OUT6 ,GPIO6 output values" "0,1"
|
|
bitfld.long 0x04 5. " VAL_OUT5 ,GPIO5 output values" "0,1"
|
|
bitfld.long 0x04 4. " VAL_OUT4 ,GPIO4 output values" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " VAL_OUT3 ,GPIO3 output values" "0,1"
|
|
bitfld.long 0x04 2. " VAL_OUT2 ,GPIO2 output values" "0,1"
|
|
bitfld.long 0x04 1. " VAL_OUT1 ,GPIO1 output values" "0,1"
|
|
bitfld.long 0x04 0. " VAL_OUT0 ,GPIO0 output values" "0,1"
|
|
line.long 0x08 "GPIO_IN,GPIO Input Register"
|
|
bitfld.long 0x08 15. " VAL_IN15 ,GPIO15 input values" "0,1"
|
|
bitfld.long 0x08 14. " VAL_IN14 ,GPIO14 input values" "0,1"
|
|
bitfld.long 0x08 13. " VAL_IN13 ,GPIO13 input values" "0,1"
|
|
bitfld.long 0x08 12. " VAL_IN12 ,GPIO12 input values" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " VAL_IN11 ,GPIO11 input values" "0,1"
|
|
bitfld.long 0x08 10. " VAL_IN10 ,GPIO10 input values" "0,1"
|
|
bitfld.long 0x08 9. " VAL_IN9 ,GPIO9 input values" "0,1"
|
|
bitfld.long 0x08 8. " VAL_IN8 ,GPIO8 input values" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " VAL_IN7 ,GPIO7 input values" "0,1"
|
|
bitfld.long 0x08 6. " VAL_IN6 ,GPIO6 input values" "0,1"
|
|
bitfld.long 0x08 5. " VAL_IN5 ,GPIO5 input values" "0,1"
|
|
bitfld.long 0x08 4. " VAL_IN4 ,GPIO4 input values" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 3. " VAL_IN3 ,GPIO3 input values" "0,1"
|
|
bitfld.long 0x08 2. " VAL_IN2 ,GPIO2 input values" "0,1"
|
|
bitfld.long 0x08 1. " VAL_IN1 ,GPIO1 input values" "0,1"
|
|
bitfld.long 0x08 0. " VAL_IN0 ,GPIO0 input values" "0,1"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_IRQ,GPIO Interrupt Register"
|
|
eventfld.long 0x00 21. " SYS_TIME ,Hold the interrupt for sys_time" "Not hold,Hold"
|
|
eventfld.long 0x00 20. " CNT4 ,Interrupt for counter4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CNT3 ,Interrupt for counter3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " CNT2 ,Interrupt for counter2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CNT1 ,Interrupt for counter1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " CNT0 ,Interrupt for counter0" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " GPIO15 ,GPIO15 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " GPIO14 ,GPIO14 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " GPIO13 ,GPIO13 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " GPIO12 ,GPIO12 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " GPIO11 ,GPIO11 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " GPIO10 ,GPIO10 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " GPIO9 ,GPIO9 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " GPIO8 ,GPIO8 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " GPIO7 ,GPIO7 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " GPIO6 ,GPIO6 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " GPIO5 ,GPIO5 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " GPIO4 ,GPIO4 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " GPIO3 ,GPIO3 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " GPIO2 ,GPIO2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GPIO1 ,GPIO1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " GPIO0 ,GPIO0 interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PIO (Peripheral Inputs Outputs)"
|
|
base ad:0x00100900
|
|
width 0x09
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PIO_IN,PIO Input Register"
|
|
bitfld.long 0x00 30. " VAL30 ,PIO30 input value" "0,1"
|
|
bitfld.long 0x00 29. " VAL29 ,PIO29 input value" "0,1"
|
|
bitfld.long 0x00 28. " VAL28 ,PIO28 input value" "0,1"
|
|
bitfld.long 0x00 27. " VAL27 ,PIO27 input value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 26. " VAL26 ,PIO26 input value" "0,1"
|
|
bitfld.long 0x00 25. " VAL25 ,PIO25 input value" "0,1"
|
|
bitfld.long 0x00 24. " VAL24 ,PIO24 input value" "0,1"
|
|
bitfld.long 0x00 23. " VAL23 ,PIO23 input value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAL22 ,PIO22 input value" "0,1"
|
|
bitfld.long 0x00 21. " VAL21 ,PIO21 input value" "0,1"
|
|
bitfld.long 0x00 20. " VAL20 ,PIO20 input value" "0,1"
|
|
bitfld.long 0x00 19. " VAL19 ,PIO19 input value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VAL18 ,PIO18 input value" "0,1"
|
|
bitfld.long 0x00 17. " VAL17 ,PIO17 input value" "0,1"
|
|
bitfld.long 0x00 16. " VAL16 ,PIO16 input value" "0,1"
|
|
bitfld.long 0x00 15. " VAL15 ,PIO15 input value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " VAL14 ,PIO14 input value" "0,1"
|
|
bitfld.long 0x00 13. " VAL13 ,PIO13 input value" "0,1"
|
|
bitfld.long 0x00 12. " VAL12 ,PIO12 input value" "0,1"
|
|
bitfld.long 0x00 11. " VAL11 ,PIO11 input value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VAL10 ,PIO10 input value" "0,1"
|
|
bitfld.long 0x00 9. " VAL9 ,PIO9 input value" "0,1"
|
|
bitfld.long 0x00 8. " VAL8 ,PIO8 input value" "0,1"
|
|
bitfld.long 0x00 7. " VAL7 ,PIO7 input value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VAL6 ,PIO6 input value" "0,1"
|
|
bitfld.long 0x00 5. " VAL5 ,PIO5 input value" "0,1"
|
|
bitfld.long 0x00 4. " VAL4 ,PIO4 input value" "0,1"
|
|
bitfld.long 0x00 3. " VAL3 ,PIO3 input value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VAL2 ,PIO2 input value" "0,1"
|
|
bitfld.long 0x00 1. " VAL1 ,PIO1 input value" "0,1"
|
|
bitfld.long 0x00 0. " VAL0 ,PIO0 input value" "0,1"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "PIO_OUT,PIO Output Register"
|
|
bitfld.long 0x00 30. " VAL30 ,PIO30 output value" "0,1"
|
|
bitfld.long 0x00 29. " VAL29 ,PIO29 output value" "0,1"
|
|
bitfld.long 0x00 28. " VAL28 ,PIO28 output value" "0,1"
|
|
bitfld.long 0x00 27. " VAL27 ,PIO27 output value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 26. " VAL26 ,PIO26 output value" "0,1"
|
|
bitfld.long 0x00 25. " VAL25 ,PIO25 output value" "0,1"
|
|
bitfld.long 0x00 24. " VAL24 ,PIO24 output value" "0,1"
|
|
bitfld.long 0x00 23. " VAL23 ,PIO23 output value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAL22 ,PIO22 output value" "0,1"
|
|
bitfld.long 0x00 21. " VAL21 ,PIO21 output value" "0,1"
|
|
bitfld.long 0x00 20. " VAL20 ,PIO20 output value" "0,1"
|
|
bitfld.long 0x00 19. " VAL19 ,PIO19 output value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VAL18 ,PIO18 output value" "0,1"
|
|
bitfld.long 0x00 17. " VAL17 ,PIO17 output value" "0,1"
|
|
bitfld.long 0x00 16. " VAL16 ,PIO16 output value" "0,1"
|
|
bitfld.long 0x00 15. " VAL15 ,PIO15 output value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " VAL14 ,PIO14 output value" "0,1"
|
|
bitfld.long 0x00 13. " VAL13 ,PIO13 output value" "0,1"
|
|
bitfld.long 0x00 12. " VAL12 ,PIO12 output value" "0,1"
|
|
bitfld.long 0x00 11. " VAL11 ,PIO11 output value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VAL10 ,PIO10 output value" "0,1"
|
|
bitfld.long 0x00 9. " VAL9 ,PIO9 output value" "0,1"
|
|
bitfld.long 0x00 8. " VAL8 ,PIO8 output value" "0,1"
|
|
bitfld.long 0x00 7. " VAL7 ,PIO7 output value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VAL6 ,PIO6 output value" "0,1"
|
|
bitfld.long 0x00 5. " VAL5 ,PIO5 output value" "0,1"
|
|
bitfld.long 0x00 4. " VAL4 ,PIO4 output value" "0,1"
|
|
bitfld.long 0x00 3. " VAL3 ,PIO3 output value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VAL2 ,PIO2 output value" "0,1"
|
|
bitfld.long 0x00 1. " VAL1 ,PIO1 output value" "0,1"
|
|
bitfld.long 0x00 0. " VAL0 ,PIO0 output value" "0,1"
|
|
line.long 0x04 "PIO_OE,PIO Output Enable Register"
|
|
bitfld.long 0x04 30. " VAL30 ,PIO30 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " VAL29 ,PIO29 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " VAL28 ,PIO28 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " VAL27 ,PIO27 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 26. " VAL26 ,PIO26 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " VAL25 ,PIO25 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " VAL24 ,PIO24 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " VAL23 ,PIO23 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " VAL22 ,PIO22 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " VAL21 ,PIO21 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " VAL20 ,PIO20 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " VAL19 ,PIO19 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " VAL18 ,PIO18 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " VAL17 ,PIO17 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " VAL16 ,PIO16 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " VAL15 ,PIO15 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " VAL14 ,PIO14 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " VAL13 ,PIO13 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " VAL12 ,PIO12 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " VAL11 ,PIO11 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " VAL10 ,PIO10 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " VAL9 ,PIO9 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " VAL8 ,PIO8 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " VAL7 ,PIO7 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " VAL6 ,PIO6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " VAL5 ,PIO5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " VAL4 ,PIO4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " VAL3 ,PIO3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VAL2 ,PIO2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " VAL1 ,PIO1 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " VAL0 ,PIO0 output enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver Transmitter)"
|
|
base ad:0x00100A00
|
|
width 0x17
|
|
tree "UART 0"
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "UART0_DATA,UART 0 Data Register"
|
|
in
|
|
group.long (0x04+0x0)++0x03
|
|
line.long 0x00 "UART0_STAT,UART 0 Status Register"
|
|
bitfld.long 0x00 3. " OE ,Overrun Error" "No error,Error"
|
|
bitfld.long 0x00 2. " BE ,Break Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 0. " FE ,Framing Error" "No error,Error"
|
|
group.long (0x08+0x0)++0x03
|
|
line.long 0x00 "UART0_LINE_CTRL,UART 0 Line Control Register"
|
|
bitfld.long 0x00 5.--6. " WLEN ,Word length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EPS ,Even Parity Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BRK ,Send Break" "Disabled,Enabled"
|
|
group.long (0x0C+0x0)++0x03
|
|
line.long 0x00 "UART0_BAUD_DIV_MSB,UART 0 Baud Rate Divisor MSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BAUDDIV_MSB ,Baud Rate Divisor [15:8]"
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "UART0_BAUD_DIV_LSB,UART 0 Baud Rate Divisor LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BAUDDIV_LSB ,Baud Rate Divisor [7:0]"
|
|
group.long (0x14+0x0)++0x03
|
|
line.long 0x00 "UART0_CTRL,UART 0 Control Register"
|
|
bitfld.long 0x00 7. " LBE ,Loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTIE ,Receive timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIRLP ,IrDA SIR low power mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SIREN ,The IrDA SIR Endec enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled"
|
|
rgroup.long (0x18+0x0)++0x03
|
|
line.long 0x00 "UART0_FLAG,UART 0 Flag Register"
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " RXFF ,Receive FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TXFF ,Transmit FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 4. " RXFE ,Receive FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BUSY ,UART busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTS ,Clear to send" "Low,High"
|
|
group.long (0x1C+0x0)++0x03
|
|
line.long 0x00 "UART0_INT_ID,UART 0 Interrupt Identification Register"
|
|
bitfld.long 0x00 3. " RTIS ,Receive timeout interrupt status" "Not asserted,Asserted"
|
|
bitfld.long 0x00 2. " TIS ,Transmit interrupt status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RIS ,Receive interrupt status" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " MIS ,Modem Interrupt Status" "Not asserted,Asserted"
|
|
width 24.
|
|
group.long (0x20+0x0)++0x03
|
|
line.long 0x00 "UART0_IRDA_LO_PWR_CNTR,UART 0 IrDA Low Power Counter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ILPDVSR ,IrDA Low Power Divisor value [7:0]"
|
|
group.long (0x24+0x0)++0x03
|
|
line.long 0x00 "UART0_RTS_CTRL,UART 0 RTS Control Register"
|
|
bitfld.long 0x00 7. " STICK ,Parity bit works as stick bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CTS_POL ,CTS polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CTS_CTR ,CTS control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RTS_POL ,RTS polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MOD2 ,Machine trail state activated by" "Character sent,Empty FIFO"
|
|
bitfld.long 0x00 2. " COUNT ,RTS counter time base" "Baud,System clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTS ,RTS output" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AUTO ,RTS output controll" "Direct,Automatic"
|
|
group.long (0x28+0x0)++0x03
|
|
line.long 0x00 "UART0_RTS_LEAD_CYC,UART 0 RTS Leading Cycles"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LEAD_CYC ,Number of leading cycles in system clocks or baud rate cycles"
|
|
group.long (0x2C+0x0)++0x03
|
|
line.long 0x00 "UART0_RTS_TRAIL_CYC,UART 0 RTS Trailing cycles"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TRAILCYC ,Number of trail cycles in system clocks or baud rate cycles"
|
|
group.long (0x30+0x0)++0x03
|
|
line.long 0x00 "UART0_OUT_DRV_EN,UART 0 Driver Enable Register"
|
|
bitfld.long 0x00 1. " DRVRTS ,Driver for UARTi_RTS output pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DRVTX ,Driver for UARTi_TXD output pin" "Disabled,Enabled"
|
|
group.long (0x34+0x0)++0x03
|
|
line.long 0x00 "UART0_BAUD_MODE_CTRL,UART 0 Baud Rate Mode Control Register"
|
|
bitfld.long 0x00 0. " BAUD_RATE_MODE ,Sets the generation method of baudrate" "Mode 1,Mode 2"
|
|
group.long (0x38+0x0)++0x03
|
|
line.long 0x00 "UART0_RX_FIFO_IRQ_LVL,UART 0 Receive FIFO Interrupt Trigger Level"
|
|
hexmask.long.byte 0x00 0.--4. 1. " RFIRQLEVEL ,IRQ trigger level of the receive FIFO"
|
|
group.long (0x3C+0x0)++0x03
|
|
line.long 0x00 "UART0_TX_FIFO_IRQ_LVL,UART 0 Transmit FIFO Interrupt Trigger Level"
|
|
hexmask.long.byte 0x00 0.--4. 1. " TFIRQLEVEL ,IRQ trigger level of the transmit FIFO"
|
|
tree.end
|
|
tree "UART 1"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "UART1_DATA,UART 1 Data Register"
|
|
in
|
|
group.long (0x04+0x40)++0x03
|
|
line.long 0x00 "UART1_STAT,UART 1 Status Register"
|
|
bitfld.long 0x00 3. " OE ,Overrun Error" "No error,Error"
|
|
bitfld.long 0x00 2. " BE ,Break Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 0. " FE ,Framing Error" "No error,Error"
|
|
group.long (0x08+0x40)++0x03
|
|
line.long 0x00 "UART1_LINE_CTRL,UART 1 Line Control Register"
|
|
bitfld.long 0x00 5.--6. " WLEN ,Word length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EPS ,Even Parity Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BRK ,Send Break" "Disabled,Enabled"
|
|
group.long (0x0C+0x40)++0x03
|
|
line.long 0x00 "UART1_BAUD_DIV_MSB,UART 1 Baud Rate Divisor MSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BAUDDIV_MSB ,Baud Rate Divisor [15:8]"
|
|
group.long (0x10+0x40)++0x03
|
|
line.long 0x00 "UART1_BAUD_DIV_LSB,UART 1 Baud Rate Divisor LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BAUDDIV_LSB ,Baud Rate Divisor [7:0]"
|
|
group.long (0x14+0x40)++0x03
|
|
line.long 0x00 "UART1_CTRL,UART 1 Control Register"
|
|
bitfld.long 0x00 7. " LBE ,Loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTIE ,Receive timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIRLP ,IrDA SIR low power mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SIREN ,The IrDA SIR Endec enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled"
|
|
rgroup.long (0x18+0x40)++0x03
|
|
line.long 0x00 "UART1_FLAG,UART 1 Flag Register"
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " RXFF ,Receive FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TXFF ,Transmit FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 4. " RXFE ,Receive FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BUSY ,UART busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTS ,Clear to send" "Low,High"
|
|
group.long (0x1C+0x40)++0x03
|
|
line.long 0x00 "UART1_INT_ID,UART 1 Interrupt Identification Register"
|
|
bitfld.long 0x00 3. " RTIS ,Receive timeout interrupt status" "Not asserted,Asserted"
|
|
bitfld.long 0x00 2. " TIS ,Transmit interrupt status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RIS ,Receive interrupt status" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " MIS ,Modem Interrupt Status" "Not asserted,Asserted"
|
|
width 24.
|
|
group.long (0x20+0x40)++0x03
|
|
line.long 0x00 "UART1_IRDA_LO_PWR_CNTR,UART 1 IrDA Low Power Counter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ILPDVSR ,IrDA Low Power Divisor value [7:0]"
|
|
group.long (0x24+0x40)++0x03
|
|
line.long 0x00 "UART1_RTS_CTRL,UART 1 RTS Control Register"
|
|
bitfld.long 0x00 7. " STICK ,Parity bit works as stick bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CTS_POL ,CTS polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CTS_CTR ,CTS control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RTS_POL ,RTS polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MOD2 ,Machine trail state activated by" "Character sent,Empty FIFO"
|
|
bitfld.long 0x00 2. " COUNT ,RTS counter time base" "Baud,System clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTS ,RTS output" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AUTO ,RTS output controll" "Direct,Automatic"
|
|
group.long (0x28+0x40)++0x03
|
|
line.long 0x00 "UART1_RTS_LEAD_CYC,UART 1 RTS Leading Cycles"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LEAD_CYC ,Number of leading cycles in system clocks or baud rate cycles"
|
|
group.long (0x2C+0x40)++0x03
|
|
line.long 0x00 "UART1_RTS_TRAIL_CYC,UART 1 RTS Trailing cycles"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TRAILCYC ,Number of trail cycles in system clocks or baud rate cycles"
|
|
group.long (0x30+0x40)++0x03
|
|
line.long 0x00 "UART1_OUT_DRV_EN,UART 1 Driver Enable Register"
|
|
bitfld.long 0x00 1. " DRVRTS ,Driver for UARTi_RTS output pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DRVTX ,Driver for UARTi_TXD output pin" "Disabled,Enabled"
|
|
group.long (0x34+0x40)++0x03
|
|
line.long 0x00 "UART1_BAUD_MODE_CTRL,UART 1 Baud Rate Mode Control Register"
|
|
bitfld.long 0x00 0. " BAUD_RATE_MODE ,Sets the generation method of baudrate" "Mode 1,Mode 2"
|
|
group.long (0x38+0x40)++0x03
|
|
line.long 0x00 "UART1_RX_FIFO_IRQ_LVL,UART 1 Receive FIFO Interrupt Trigger Level"
|
|
hexmask.long.byte 0x00 0.--4. 1. " RFIRQLEVEL ,IRQ trigger level of the receive FIFO"
|
|
group.long (0x3C+0x40)++0x03
|
|
line.long 0x00 "UART1_TX_FIFO_IRQ_LVL,UART 1 Transmit FIFO Interrupt Trigger Level"
|
|
hexmask.long.byte 0x00 0.--4. 1. " TFIRQLEVEL ,IRQ trigger level of the transmit FIFO"
|
|
tree.end
|
|
tree "UART 2"
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "UART2_DATA,UART 2 Data Register"
|
|
in
|
|
group.long (0x04+0x80)++0x03
|
|
line.long 0x00 "UART2_STAT,UART 2 Status Register"
|
|
bitfld.long 0x00 3. " OE ,Overrun Error" "No error,Error"
|
|
bitfld.long 0x00 2. " BE ,Break Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 0. " FE ,Framing Error" "No error,Error"
|
|
group.long (0x08+0x80)++0x03
|
|
line.long 0x00 "UART2_LINE_CTRL,UART 2 Line Control Register"
|
|
bitfld.long 0x00 5.--6. " WLEN ,Word length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EPS ,Even Parity Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BRK ,Send Break" "Disabled,Enabled"
|
|
group.long (0x0C+0x80)++0x03
|
|
line.long 0x00 "UART2_BAUD_DIV_MSB,UART 2 Baud Rate Divisor MSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BAUDDIV_MSB ,Baud Rate Divisor [15:8]"
|
|
group.long (0x10+0x80)++0x03
|
|
line.long 0x00 "UART2_BAUD_DIV_LSB,UART 2 Baud Rate Divisor LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BAUDDIV_LSB ,Baud Rate Divisor [7:0]"
|
|
group.long (0x14+0x80)++0x03
|
|
line.long 0x00 "UART2_CTRL,UART 2 Control Register"
|
|
bitfld.long 0x00 7. " LBE ,Loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTIE ,Receive timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSIE ,Modem status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIRLP ,IrDA SIR low power mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SIREN ,The IrDA SIR Endec enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART enable" "Disabled,Enabled"
|
|
rgroup.long (0x18+0x80)++0x03
|
|
line.long 0x00 "UART2_FLAG,UART 2 Flag Register"
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " RXFF ,Receive FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TXFF ,Transmit FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 4. " RXFE ,Receive FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BUSY ,UART busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CTS ,Clear to send" "Low,High"
|
|
group.long (0x1C+0x80)++0x03
|
|
line.long 0x00 "UART2_INT_ID,UART 2 Interrupt Identification Register"
|
|
bitfld.long 0x00 3. " RTIS ,Receive timeout interrupt status" "Not asserted,Asserted"
|
|
bitfld.long 0x00 2. " TIS ,Transmit interrupt status" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RIS ,Receive interrupt status" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " MIS ,Modem Interrupt Status" "Not asserted,Asserted"
|
|
width 24.
|
|
group.long (0x20+0x80)++0x03
|
|
line.long 0x00 "UART2_IRDA_LO_PWR_CNTR,UART 2 IrDA Low Power Counter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ILPDVSR ,IrDA Low Power Divisor value [7:0]"
|
|
group.long (0x24+0x80)++0x03
|
|
line.long 0x00 "UART2_RTS_CTRL,UART 2 RTS Control Register"
|
|
bitfld.long 0x00 7. " STICK ,Parity bit works as stick bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CTS_POL ,CTS polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CTS_CTR ,CTS control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RTS_POL ,RTS polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MOD2 ,Machine trail state activated by" "Character sent,Empty FIFO"
|
|
bitfld.long 0x00 2. " COUNT ,RTS counter time base" "Baud,System clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTS ,RTS output" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AUTO ,RTS output controll" "Direct,Automatic"
|
|
group.long (0x28+0x80)++0x03
|
|
line.long 0x00 "UART2_RTS_LEAD_CYC,UART 2 RTS Leading Cycles"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LEAD_CYC ,Number of leading cycles in system clocks or baud rate cycles"
|
|
group.long (0x2C+0x80)++0x03
|
|
line.long 0x00 "UART2_RTS_TRAIL_CYC,UART 2 RTS Trailing cycles"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TRAILCYC ,Number of trail cycles in system clocks or baud rate cycles"
|
|
group.long (0x30+0x80)++0x03
|
|
line.long 0x00 "UART2_OUT_DRV_EN,UART 2 Driver Enable Register"
|
|
bitfld.long 0x00 1. " DRVRTS ,Driver for UARTi_RTS output pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DRVTX ,Driver for UARTi_TXD output pin" "Disabled,Enabled"
|
|
group.long (0x34+0x80)++0x03
|
|
line.long 0x00 "UART2_BAUD_MODE_CTRL,UART 2 Baud Rate Mode Control Register"
|
|
bitfld.long 0x00 0. " BAUD_RATE_MODE ,Sets the generation method of baudrate" "Mode 1,Mode 2"
|
|
group.long (0x38+0x80)++0x03
|
|
line.long 0x00 "UART2_RX_FIFO_IRQ_LVL,UART 2 Receive FIFO Interrupt Trigger Level"
|
|
hexmask.long.byte 0x00 0.--4. 1. " RFIRQLEVEL ,IRQ trigger level of the receive FIFO"
|
|
group.long (0x3C+0x80)++0x03
|
|
line.long 0x00 "UART2_TX_FIFO_IRQ_LVL,UART 2 Transmit FIFO Interrupt Trigger Level"
|
|
hexmask.long.byte 0x00 0.--4. 1. " TFIRQLEVEL ,IRQ trigger level of the transmit FIFO"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x00100C00
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "SPI_DATA,SPI Data Register"
|
|
bitfld.long 0x00 17. " DR_VALID1 ,DATA_BYTE_1 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16. " DR_VALID0 ,DATA_BYTE_0 valid" "Not valid,Valid"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_BYTE_1 ,Data byte 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE_0 ,Data byte 0"
|
|
line.long 0x04 "SPI_STAT,SPI Status Register"
|
|
bitfld.long 0x04 25. " SR_SELECTED ,External master access to spi-interface" "Disabled,Enabled"
|
|
eventfld.long 0x04 24. " SR_OUT_FULL ,Output FIFO is full" "Not full,Full"
|
|
textline " "
|
|
eventfld.long 0x04 23. " SR_OUT_EMPTY ,Output FIFO is empty and interface sending data" "Not empty,Empty"
|
|
eventfld.long 0x04 22. " SR_OUT_FW ,ARM is writing data to fast into output FIFO" "Not to fast,To fast"
|
|
textline " "
|
|
eventfld.long 0x04 21. " SR_OUT_FUEL ,Adjustable fuel value of output FIFO reached" "Not reached,Reached"
|
|
eventfld.long 0x04 20. " SR_IN_FULL ,Input FIFO is full" "Not full,Full"
|
|
textline " "
|
|
eventfld.long 0x04 19. " SR_IN_RECDATA ,Valid data bytes in input FIFO" "Not valid,Valid"
|
|
eventfld.long 0x04 18. " SR_IN_FILL_LEVEL ,Adjustable fill level of input FIFO reached" "Not reached,Reached"
|
|
textline " "
|
|
hexmask.long.word 0x04 9.--17. 1. " SR_OUT_FILL_VAL ,Output FIFO fill value (number of bytes)"
|
|
hexmask.long.word 0x04 0.--8. 1. " SR_IN_FILL_VAL ,Input FIFO fill value (number of bytes)"
|
|
line.long 0x08 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x08 31. " CR_EN ,Enable SPI interface" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " CR_MS ,Mode select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x08 29. " CR_CPOL ,Primary edge of spi_sck" "Rising,Falling"
|
|
bitfld.long 0x08 28. " CR_NCPHA ,spi_sck edge for data change/activ" "Primary/secondary,Secondary/primary"
|
|
textline " "
|
|
bitfld.long 0x08 25.--27. " CR_BURST ,Burst length" "1,2,4,8,16,32,64,128"
|
|
bitfld.long 0x08 22.--24. " CR_BURSTDELAY ,Delay between transmission of 2 data bytes" "0 SCK cycles,1 SCK cycle,2 SCK cycles,3 SCK cycles,4 SCK cycles,5 SCK cycles,6 SCK cycles,7 SCK cycles"
|
|
textline " "
|
|
bitfld.long 0x08 21. " CR_CLR_OUTFIFO ,Clear output FIFO" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " CR_CLR_INFIFO ,Clear input FIFO" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " CS_MODE ,Chip select control" "Software,Internal"
|
|
bitfld.long 0x08 10. " CR_SS2 ,external slave select SPI_CS2" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CR_SS1 ,external slave select SPI_CS1" "Not selected,Selected"
|
|
bitfld.long 0x08 8. " CR_SS0 ,external slave select SPI_CS0" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CR_WRITE ,Spi interface write data enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CR_READ ,Spi interface read data enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1.--4. " CR_SPEED ,SPI Clock Speed" "Reserved,0.05 MHz,0.1 MHz,0.2 MHz,0.5 MHz,1 MHz,1.25 MHz,2 MHz,2.5 MHz,3.33 MHz,5 MHz,10 MHz,12.5 MHz,16.66 MHz,25 MHz,?..."
|
|
width 14.
|
|
line.long 0x0C "SPI_INT_CTRL,SPI Interrupt Control Register"
|
|
bitfld.long 0x0C 24. " IR_OUT_FULL_EN ,IRQ enable for output FIFO is full" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " IR_OUT_EMPTY_EN ,IRQ enable for output FIFO is empty and interface sending data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " IR_OUT_FW_EN ,IRQ enable for ARM is writing data to fast into output FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " IR_OUT_FUEL_EN ,IRQ enable for adjustable fuel value of output FIFO reached" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " IR_IN_FULL_EN ,IRQ enable for input FIFO is full" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " IR_IN_RECDATA_EN ,IRQ enable for valid data bytes in input FIFO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " IR_IN_FUEL_EN ,IRQ enable for adjustable fill level of input FIFO reached" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 9.--17. 1. " IR_OUT_FULL_LEVEL ,Adjustable full level for output FIFO"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--8. 1. " IR_IN_FULL_LEVEL ,Adjustable full level for input FIFO"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x00100D00
|
|
width 0x0A
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
hexmask.long.byte 0x00 4.--10. 1. " ID ,Slave device ID"
|
|
bitfld.long 0x00 1.--3. " SPEED ,Speed select when 100 MHz system clock" "25 kHz,50 kHz,100 kHz,200 kHz,400 kHz,600 kHz,800 kHz,1000 kHz"
|
|
bitfld.long 0x00 0. " ENABLE ,Interface enable" "Disabled,Enabled"
|
|
line.long 0x04 "I2C_DATA,I2C Data Register"
|
|
bitfld.long 0x04 13.--14. " ACK ,Number of acknowledge bits send by slave in actual command" "0,1,2,3"
|
|
bitfld.long 0x04 12. " RDF ,Read Data Finished" "Not finished,Finished"
|
|
bitfld.long 0x04 11. " CMD3 ,Command Bit 3: execute" "No operation,Executed"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CMD2 ,Command Bit 2: send Start Condition" "No effect,Started"
|
|
bitfld.long 0x04 9. " CMD1 ,Command Bit 1: write/read Byte" "Write,Read"
|
|
bitfld.long 0x04 8. " CMD0 ,Command Bit 0: stop" "No effect,Stopped"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA ,Transmit and receive data byte"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SYSTIME (System time with IEEE 1588 functionality)"
|
|
base ad:0x00101100
|
|
width 20.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "SYSTIME_NS,System Time Nanosecond Register"
|
|
line.long 0x04 "SYSTIME_S,System Time Second Register"
|
|
line.long 0x08 "SYS_TIME_NS_BOR,System Time Nanoseconds Border Register"
|
|
line.long 0x0C "SYS_TIME_NS_ADD_UP,System Time Nanoseconds Add Up Register"
|
|
line.long 0x10 "SYS_TIME_S_CMP,System Time Second Compare Register"
|
|
line.long 0x14 "SYS_TIME_S_CMP_EN,System Time Second Compare Enable Register"
|
|
bitfld.long 0x14 0. " ENABLE ,Enable compare with SYSTIME_S (seconds)" "Disabled,Enabled"
|
|
line.long 0x18 "SYS_TIME_S_CMP_INT,System Time Second Compare Interrupt Register"
|
|
eventfld.long 0x18 0. " COMPARE_IRQ ,System time compare interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB (Universal Serial Bus)"
|
|
base ad:0x00120000
|
|
width 17.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "USB_ID,USB ID Register"
|
|
hexmask.long.byte 0x00 8.--12. 1. " CORE_ID ,Core ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV_ID ,Revision ID number of the core"
|
|
group.long 0x04++0x1B
|
|
line.long 0x00 "USB_CTRL,USB Control Register"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASE ,Async Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HRS ,Host Run/Stop" "Stopped,Running"
|
|
bitfld.long 0x00 1. " XSUSP ,XCVR Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSUSP ,Core Suspend" "Not suspended,Suspended"
|
|
line.long 0x04 "USB_FRM_TMR,USB Frame Timer Register"
|
|
bitfld.long 0x04 12. " AGSOF ,Artificially Generated SOF" "Not generated,Generated"
|
|
bitfld.long 0x04 11. " FTLOCK ,Frame Timer Locked" "Not locked,Locked"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--10. 1. " FRAME_NR ,Current Frame Number"
|
|
line.long 0x08 "USB_MAIN_EV,USB Main Event Register"
|
|
eventfld.long 0x08 5. " BWERR_EV ,Bandwidth Error Event" "No error,Error"
|
|
eventfld.long 0x08 4. " HCHA_EV ,Host Controller Halted Event" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " GPIPE_EV ,Global Pipe Transfer Event" "Not occurred,Occurred"
|
|
bitfld.long 0x08 2. " GPORT_EV ,Global Port Status Change Event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x08 1. " FRM32_EV ,Frame 32 Event" "Not occurred,Occurred"
|
|
eventfld.long 0x08 0. " FRM_EV ,Frame Event" "Not occurred,Occurred"
|
|
line.long 0x0C "USB_MAIN_EV_MSK,USB Main Event Mask Register"
|
|
bitfld.long 0x0C 5. " BWERR_EM ,Bandwidth Error Event Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " HCHA_EM ,HC Halted Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " GPIPE_EM ,Global Pipe Event Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " GPORT_EM ,Global Port Status Change Event Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " FRM32_EM ,Frame 32 Event Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " FRM_EM ,Frame Event Mask" "Not masked,Masked"
|
|
line.long 0x10 "USB_PIPE_EV,USB Pipe Event Register"
|
|
eventfld.long 0x10 7. " PI_EV7 ,Pipe Event Flag 7" "Not occurred,Occurred"
|
|
eventfld.long 0x10 6. " PI_EV6 ,Pipe Event Flag 6" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x10 5. " PI_EV5 ,Pipe Event Flag 5" "Not occurred,Occurred"
|
|
eventfld.long 0x10 4. " PI_EV4 ,Pipe Event Flag 4" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x10 3. " PI_EV3 ,Pipe Event Flag 3" "Not occurred,Occurred"
|
|
eventfld.long 0x10 2. " PI_EV2 ,Pipe Event Flag 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x10 1. " PI_EV1 ,Pipe Event Flag 1" "Not occurred,Occurred"
|
|
eventfld.long 0x10 0. " PI_EV0 ,Pipe Event Flag 0" "Not occurred,Occurred"
|
|
line.long 0x14 "USB_PIPE_EV_MSK,USB Pipe Event Mask Register"
|
|
bitfld.long 0x14 7. " PI_EM7 ,Pipe Event Mask 7 Setting" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " PI_EM6 ,Pipe Event Mask 6 Setting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " PI_EM5 ,Pipe Event Mask 5 Setting" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " PI_EM4 ,Pipe Event Mask 4 Setting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PI_EM3 ,Pipe Event Mask 3 Setting" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " PI_EM2 ,Pipe Event Mask 2 Setting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PI_EM1 ,Pipe Event Mask 1 Setting" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PI_EM0 ,Pipe Event Mask 0 Setting" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "USB_PIPE_SEL,USB Pipe Select Register"
|
|
bitfld.long 0x00 0.--2. " PI_SEL ,Pipe Select" "Pipe 0,Pipe 1,Pipe 2,Pipe 3,Pipe 4,Pipe 5,Pipe 6,Pipe 7"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "USB_PORT_STAT,USB Port Status Register"
|
|
bitfld.long 0x00 9. " LINESTATE1 ,USB Line State 1" "Ser_rx_dp,Ser_rx_dm"
|
|
bitfld.long 0x00 8. " LINESTATE0 ,USB Line State 0" "Ser_rx_dp,Ser_rx_dm"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OCURC ,Over Current Condition" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " DLS ,Connected device speed" "Full,Low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PCS ,Port Connect Status" "Not connected,Connected"
|
|
bitfld.long 0x00 4. " CONN_ID ,USB Connector ID Value" "A-Device,B-Device"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VB_SESS_END ,VB Session End" "Not ended,Ended"
|
|
bitfld.long 0x00 2. " VB_SESS_VLD ,VB Session Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VA_SESS_VLD ,VA Session Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " VBUS_VLD ,Vbus Valid" "Not valid,Valid"
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "USB_PORT_CTRL,USB Port Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " P_LEN ,Pulse Length"
|
|
bitfld.long 0x00 12. " ID_PU ,ID-Pullup Output Signal Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VBS_ON ,VBUS Session Request Control" "Not controled,Controled"
|
|
bitfld.long 0x00 9. " DCHRG ,Enable Discharge Circuitry" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TERM_ENA ,Termination Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TERM_SEL ,Termination Select" "Host,Device"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VB_ON ,VBUS Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PSUSP ,Port Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PENA ,Port Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FPRESU ,Force Resume" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 2. " URESET ,USB Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0.--1. " PTESTC ,Port Test Mode" "Disabled,J State,K State,SE0"
|
|
width 26.
|
|
line.long 0x04 "USB_PORT_STAT_CHG_EV,USB Port Status Change Event Register"
|
|
eventfld.long 0x04 8. " P_END_EV ,Pulse End Event" "Not occurred,Occurred"
|
|
eventfld.long 0x04 7. " PWRSC_EV ,Power Status Change Event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 6. " CDC_EV ,Connect/Disconnect Event" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " URES_EV ,USB Reset Event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 4. " SUSP_EV ,Suspend Event" "Not occurred,Occurred"
|
|
eventfld.long 0x04 3. " RSUC_EV ,Resume Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 2. " RSU_EV ,Resume Event" "Not occurred,Occurred"
|
|
eventfld.long 0x04 1. " BERR_EV ,Babble Error Event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 0. " OCU_EV ,Over Current Event" "Not occurred,Occurred"
|
|
line.long 0x08 "USB_PORT_STAT_CHG_EV_MSK,USB Port Status Change Event Mask Register"
|
|
bitfld.long 0x08 8. " P_END_EM ,Pulse End Event Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " PWRSC_EM ,Power Status Change Event Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 6. " CDC_EM ,Connect/Disconnect Event Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " URES_EM ,USB Reset Event Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 4. " SUSP_EM ,Suspend Event Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " RSUC_EM ,Resume Complete Event Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " RSU_EM ,Resume Event Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " BERR_EM ,Babble Error Event Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 0. " OCU_EM ,Over Current Event Mask" "Not masked,Masked"
|
|
width 15.
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "USB_PIPE_CTRL,USB Pipe Control Register"
|
|
bitfld.long 0x00 2. " ACT ,Activate Pipe" "Not activated,Activated"
|
|
bitfld.long 0x00 0.--1. " TPID ,Token PID/Direction" "OUT,IN,SETUP,?..."
|
|
line.long 0x04 "USB_PIPE_CFG,USB Pipe Configuration Register"
|
|
bitfld.long 0x04 30. " IOT ,Interrupt on Transaction" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " HIDBE ,Halt on ISO Data Buffer Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 28. " SKIPISO ,Skip ISO Token" "Not skipped,Skipped"
|
|
bitfld.long 0x04 24.--27. " PI ,Polling Interval" "1 frame,2 frames,4 frames,8 frames,16 frames,32 frames,64 frames,128 frames,256 frames,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " POFF ,Polling Offset"
|
|
bitfld.long 0x04 15. " STALL ,Stall Pipe" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " ACID ,Accept corrupted ISO Data" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " EPS ,Endpoint Speed" "Full,Low"
|
|
textline " "
|
|
bitfld.long 0x04 12. " STRM ,Streaming Mode" "Not activated,Activated"
|
|
bitfld.long 0x04 10.--11. " ET ,Endpoint Transfer Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " MPS ,Maximum Packet Size"
|
|
line.long 0x08 "USB_PIPE_ADDR,USB Pipe Address Register"
|
|
hexmask.long.byte 0x08 4.--10. 1. " EPADDR ,Endpoint Address"
|
|
bitfld.long 0x08 0.--3. " ERNR ,Endpoint Number" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15."
|
|
line.long 0x0C "USB_PIPE_STAT,USB Pipe Status Register"
|
|
bitfld.long 0x0C 8.--9. " CERR ,Error Counter" "0,1,2,3"
|
|
bitfld.long 0x0C 7. " DBERR ,Data Buffer Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " ACTS ,Active Pipe Status" "Not active,Active"
|
|
bitfld.long 0x0C 5. " HALT ,Pipe Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " BBL ,Babble detected" "Not detected,Detected"
|
|
bitfld.long 0x0C 3. " DBSEL ,Selected Data Buffer" "Normal,Alternative"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " DT ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0C 0.--1. " DBOFF ,Data Byte Offset" "0,1,2,3"
|
|
width 23.
|
|
line.long 0x10 "USB_PIPE_DATA_PTR,USB Pipe Data Pointer Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " DPTR ,Data Pointer"
|
|
line.long 0x14 "USB_PIPE_DATA_TOT,USB Pipe Total Bytes Register"
|
|
bitfld.long 0x14 31. " DBV ,Data Buffer Valid" "Not valid,Valid"
|
|
hexmask.long.word 0x14 0.--12. 1. " TBYTES ,Total Bytes To Transfer"
|
|
line.long 0x18 "USB_PIPE_ALT_DATA_PTR,USB Pipe Alternative Data Pointer Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " ALT_DATA_PTR ,Alternative Data Pointer"
|
|
line.long 0x1C "USB_PIPE_ALT_DATA_TOT,USB Pipe Alternative Data Total Bytes Register"
|
|
bitfld.long 0x1C 31. " ADBV ,Alternative Data Buffer Valid" "Not valid,Valid"
|
|
hexmask.long.word 0x1C 0.--10. 1. " ATBYTES ,Alternative Total Bytes To Transfer"
|
|
width 16.
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "USB_DBG_CTRL,USB Debug Control Register"
|
|
bitfld.long 0x00 9. " UDTPID ,Debug Token PID" "Not used,Used"
|
|
bitfld.long 0x00 8. " UDHSPID ,Debug Handshake PID" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 7. " UDDPID ,Use Debug Data PID" "Not used,Used"
|
|
bitfld.long 0x00 6. " FRXCRC16G ,Force Receive Good CRC16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRXCRC5G ,Force Receive Good CRC5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FRXCRCE ,Force Receive CRC Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FTXCRC16E ,Force Transmit CRC16 Error" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FTXCRC5E ,Force Transmit CRC5 Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBSTX ,Disable Bitstuffing Transmit" "No,Yes"
|
|
bitfld.long 0x00 0. " DBSERRDET ,Disable Bitstuff Error Detection" "No,Yes"
|
|
line.long 0x04 "USB_DBG_PID,USB Debug PID Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DHSPID ,Debug Handshake PID"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DTPID ,Debug Token PID"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " DDPID ,Debug Data PID"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "USB_DEBUG_STAT,USB Debug Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DRXPIP ,Debug Receive PID"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "USB_TEST,USB Test Register"
|
|
rgroup.long 0x80++0x07
|
|
line.long 0x00 "USB_MAIN_CFG,USB Main Configuration Register"
|
|
bitfld.long 0x00 24.--29. " RAW_CFG ,RAM Address Width Configuration" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
|
|
bitfld.long 0x00 6.--11. " DW_CFG ,Data Width Configuration" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " NOP_CFG ,Number of Pipes Configuration" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
|
|
line.long 0x04 "USB_MODE_CFG,USB Mode Configuration Register"
|
|
bitfld.long 0x04 17. " XDBG_CFG ,Core Configured For Extended Debug" "Not configured,Configured"
|
|
bitfld.long 0x04 16. " DBG_CFG ,Core Configured For Debug Support" "Not configured,Configured"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " ABUFF_CFG ,Alternative Buffer Configuration"
|
|
hgroup.long 0x00130000++0x03
|
|
hide.long 0x00 "USB_FIFO,FIFO for USB-Interface"
|
|
button "USB_FIFO" "D ad:0x00130000++0xFFFF /long"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "USB_CORE_CTRL,USB Core Control and Status Register"
|
|
bitfld.long 0x00 24. " USB_IRQ ,Reflects usb_irq" "No interrupt,Interrput"
|
|
textline " "
|
|
bitfld.long 0x00 23. " UCIF_RDY ,Reflects ucif_rdy" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DISCHRG_VBUS ,Reflects dischrg_vbus" "Not discharged,Discharged"
|
|
textline " "
|
|
bitfld.long 0x00 21. " VB_ON ,Reflects vb_on" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DLP_ACTIVE ,Reflects dlp_active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CHRG_VBUS ,Reflects chrg_vbus" "Not charged,Charged"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VBUS_VLD ,Reflects vbus_vld" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 17. " VB_SESS_VLD ,Reflects vb_sess_vld" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VB_SESS_END ,Reflects vb_sess_end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VA_SESS_VLD ,Reflects va_sess_vld" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OVER_CURRENT ,Reflects over_current" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCVR_SUSPEND_N ,Reflects xcvr_suspend_n" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CORE_SUSPEND_N ,Reflects core_suspend_n" "Not suspended,Suspended"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--11. 1. " ALT_BUFF_SUPPORT ,Alt Buffer Support"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SOFT_ID_DIG ,Set id_dig Via Software" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " XTD_DBG_SUPPORT ,Extended Debug Support Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBG_SUPPORT ,Debug Support Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESET ,Software Reset" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "VIC (Vector Interrupt Controller)"
|
|
base ad:0x001ff000
|
|
width 18.
|
|
rgroup.long 0x000++0x00B
|
|
line.long 0x00 "VIC_IRQ_STAT,VIC IRQ Status Register"
|
|
bitfld.long 0x00 30. " TIMER4 ,Timer 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " TIMER3 ,Timer 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISO_AREA ,Isolated Area" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " INT_PHY ,Internal PHY" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSYNC3 ,Motion synchronization channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " MSYNC2 ,Motion synchronization channel 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MSYNC1 ,Motion synchronization channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " MSYNC0 ,Motion synchronization channel 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " COM3 ,Communication channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " COM2 ,Communication channel 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " COM1 ,Communication channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " COM0 ,Communication channel 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPIO ,External Interrupts from GPIO 0-14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " HIF ,HIF interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I2C ,I2C" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " SPI ,SPI interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USB ,USB interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " UART2 ,UART 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UART1 ,UART 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " UART0 ,UART 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WATCHDOG ,WATCHDOG" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " GPIO15 ,External interrupt at GPIO 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SYSTIME_S ,System time IRQ from SYSTIME module" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " SYSTIME_NS ,System time ns compare interrupt from GPIO module" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIMER2 ,Timer 2 / Counter 2 from GPIO Module" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " TIMER1 ,Timer 1 / Counter 1 from GPIO Module" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMER0 ,Timer 0 / Counter 0 from GPIO Module" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " SW ,Software Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "VIC_FIQ_STAT,VIC FIQ Status Register"
|
|
bitfld.long 0x04 30. " TIMER4 ,Timer 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " TIMER3 ,Timer 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISO_AREA ,Isolated Area" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " INT_PHY ,Internal PHY" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 24. " MSYNC3 ,Motion synchronization channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 23. " MSYNC2 ,Motion synchronization channel 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 22. " MSYNC1 ,Motion synchronization channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " MSYNC0 ,Motion synchronization channel 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 20. " COM3 ,Communication channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 19. " COM2 ,Communication channel 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 18. " COM1 ,Communication channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " COM0 ,Communication channel 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPIO ,External Interrupts from GPIO 0-14" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 15. " HIF ,HIF interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I2C ,I2C" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " SPI ,SPI interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " USB ,USB interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " UART2 ,UART 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " UART1 ,UART 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " UART0 ,UART 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " WATCHDOG ,WATCHDOG" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " GPIO15 ,External interrupt at GPIO 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SYSTIME_S ,System time IRQ from SYSTIME module" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " SYSTIME_NS ,System time ns compare interrupt from GPIO module" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TIMER2 ,Timer 2 / Counter 2 from GPIO Module" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " TIMER1 ,Timer 1 / Counter 1 from GPIO Module" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TIMER0 ,Timer 0 / Counter 0 from GPIO Module" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " SW ,Software Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "VIC_RAW_INT_STAT,VIC Raw Interrupt Status Register"
|
|
bitfld.long 0x08 30. " TIMER4 ,Timer 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 29. " TIMER3 ,Timer 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISO_AREA ,Isolated Area" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 25. " INT_PHY ,Internal PHY" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 24. " MSYNC3 ,Motion synchronization channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 23. " MSYNC2 ,Motion synchronization channel 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 22. " MSYNC1 ,Motion synchronization channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 21. " MSYNC0 ,Motion synchronization channel 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 20. " COM3 ,Communication channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 19. " COM2 ,Communication channel 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 18. " COM1 ,Communication channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 17. " COM0 ,Communication channel 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 16. " GPIO ,External Interrupts from GPIO 0-14" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 15. " HIF ,HIF interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 13. " I2C ,I2C" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 12. " SPI ,SPI interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 11. " USB ,USB interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 10. " UART2 ,UART 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 9. " UART1 ,UART 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 8. " UART0 ,UART 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 7. " WATCHDOG ,WATCHDOG" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " GPIO15 ,External interrupt at GPIO 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SYSTIME_S ,System time IRQ from SYSTIME module" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " SYSTIME_NS ,System time ns compare interrupt from GPIO module" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TIMER2 ,Timer 2 / Counter 2 from GPIO Module" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " TIMER1 ,Timer 1 / Counter 1 from GPIO Module" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TIMER0 ,Timer 0 / Counter 0 from GPIO Module" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " SW ,Software Interrupt" "No interrupt,Interrupt"
|
|
width 13.
|
|
group.long 0x00C++0x003
|
|
line.long 0x00 "VIC_INT_SEL,VIC Interrupt Select Register"
|
|
bitfld.long 0x00 30. " TIMER4 ,Timer 4" "IRQ,FIQ"
|
|
bitfld.long 0x00 29. " TIMER3 ,Timer 3" "IRQ,FIQ"
|
|
bitfld.long 0x00 26. " ISO_AREA ,Isolated Area" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INT_PHY ,Internal PHY" "IRQ,FIQ"
|
|
bitfld.long 0x00 24. " MSYNC3 ,Motion synchronization channel 3" "IRQ,FIQ"
|
|
bitfld.long 0x00 23. " MSYNC2 ,Motion synchronization channel 2" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MSYNC1 ,Motion synchronization channel 1" "IRQ,FIQ"
|
|
bitfld.long 0x00 21. " MSYNC0 ,Motion synchronization channel 0" "IRQ,FIQ"
|
|
bitfld.long 0x00 20. " COM3 ,Communication channel 3" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 19. " COM2 ,Communication channel 2" "IRQ,FIQ"
|
|
bitfld.long 0x00 18. " COM1 ,Communication channel 1" "IRQ,FIQ"
|
|
bitfld.long 0x00 17. " COM0 ,Communication channel 0" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPIO ,External Interrupts from GPIO 0-14" "IRQ,FIQ"
|
|
bitfld.long 0x00 15. " HIF ,HIF interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 13. " I2C ,I2C" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI ,SPI interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 11. " USB ,USB interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 10. " UART2 ,UART 2" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UART1 ,UART 1" "IRQ,FIQ"
|
|
bitfld.long 0x00 8. " UART0 ,UART 0" "IRQ,FIQ"
|
|
bitfld.long 0x00 7. " WATCHDOG ,WATCHDOG" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 6. " GPIO15 ,External interrupt at GPIO 15" "IRQ,FIQ"
|
|
bitfld.long 0x00 5. " SYSTIME_S ,System time IRQ from SYSTIME module" "IRQ,FIQ"
|
|
bitfld.long 0x00 4. " SYSTIME_NS ,System time ns compare interrupt from GPIO module" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIMER2 ,Timer 2 / Counter 2 from GPIO Module" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " TIMER1 ,Timer 1 / Counter 1 from GPIO Module" "IRQ,FIQ"
|
|
bitfld.long 0x00 1. " TIMER0 ,Timer 0 / Counter 0 from GPIO Module" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SW ,Software Interrupt" "IRQ,FIQ"
|
|
group.long 0x010++0x03
|
|
line.long 0x00 "VIC_INT_EN,VIC Interrupt Enable Register"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " TIMER4_set/clr ,Timer 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " TIMER3_set/clr ,Timer 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " ISO_AREA_set/clr ,Isolated Area" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INT_PHY_set/clr ,Internal PHY" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " MSYNC3_set/clr ,Motion synchronization channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " MSYNC2_set/clr ,Motion synchronization channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " MSYNC1_set/clr ,Motion synchronization channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " MSYNC0_set/clr ,Motion synchronization channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " COM3_set/clr ,Communication channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " COM2_set/clr ,Communication channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " COM1_set/clr ,Communication channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " COM0_set/clr ,Communication channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " GPIO_set/clr ,External Interrupts from GPIO 0-14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " HIF_set/clr ,HIF interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " I2C_set/clr ,I2C" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " SPI_set/clr ,SPI interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " USB_set/clr ,USB interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " UART2_set/clr ,UART 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " UART1_set/clr ,UART 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " UART0_set/clr ,UART 0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " WATCHDOG_set/clr ,WATCHDOG" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " GPIO15_set/clr ,External interrupt at GPIO 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SYSTIME_S_set/clr ,System time IRQ from SYSTIME module" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SYSTIME_NS_set/clr ,System time ns compare interrupt from GPIO module" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TIMER2_set/clr ,Timer 2 / Counter 2 from GPIO Module" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TIMER1_set/clr ,Timer 1 / Counter 1 from GPIO Module" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TIMER0_set/clr ,Timer 0 / Counter 0 from GPIO Module" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SW_set/clr ,Software Interrupt" "Disabled,Enabled"
|
|
group.long 0x018++0x003
|
|
line.long 0x00 "VIC_SWI,VIC Software Interrupt Register"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " TIMER4_set/clr ,Timer 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " TIMER3_set/clr ,Timer 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " ISO_AREA_set/clr ,Isolated Area" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INT_PHY_set/clr ,Internal PHY" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " MSYNC3_set/clr ,Motion synchronization channel 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " MSYNC2_set/clr ,Motion synchronization channel 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " MSYNC1_set/clr ,Motion synchronization channel 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " MSYNC0_set/clr ,Motion synchronization channel 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " COM3_set/clr ,Communication channel 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " COM2_set/clr ,Communication channel 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " COM1_set/clr ,Communication channel 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " COM0_set/clr ,Communication channel 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " GPIO_set/clr ,External Interrupts from GPIO 0-14" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " HIF_set/clr ,HIF interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " I2C_set/clr ,I2C" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " SPI_set/clr ,SPI interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " USB_set/clr ,USB interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " UART2_set/clr ,UART 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " UART1_set/clr ,UART 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " UART0_set/clr ,UART 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " WATCHDOG_set/clr ,WATCHDOG" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " GPIO15_set/clr ,External interrupt at GPIO 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SYSTIME_S_set/clr ,System time IRQ from SYSTIME module" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SYSTIME_NS_set/clr ,System time ns compare interrupt from GPIO module" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TIMER2_set/clr ,Timer 2 / Counter 2 from GPIO Module" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TIMER1_set/clr ,Timer 1 / Counter 1 from GPIO Module" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TIMER0_set/clr ,Timer 0 / Counter 0 from GPIO Module" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SW_set/clr ,Software Interrupt" "No interrupt,Interrupt"
|
|
width 20.
|
|
group.long 0x020++0x003
|
|
line.long 0x00 "VIC_PROT_EN,VIC Protection Enable Register"
|
|
bitfld.long 0x00 0. " VIC_PROT_EN ,VIC Registers Protection Enable" "Disabled,Enabled"
|
|
group.long 0x030++0x007
|
|
line.long 0x000 "VIC_VECT_ADDR,VIC Vector Address Register"
|
|
line.long 0x004 "VIC_DFLT_VECT_ADDR,VIC Default Vector Address Register"
|
|
width 17.
|
|
tree "VIC_VECT_ADDR (VIC Vector Address Registers)"
|
|
group.long 0x100++0x03F
|
|
line.long 0x0 "VIC_VECT_ADDR0,VIC Vector Address Register 0"
|
|
line.long 0x4 "VIC_VECT_ADDR1,VIC Vector Address Register 1"
|
|
line.long 0x8 "VIC_VECT_ADDR2,VIC Vector Address Register 2"
|
|
line.long 0xC "VIC_VECT_ADDR3,VIC Vector Address Register 3"
|
|
line.long 0x10 "VIC_VECT_ADDR4,VIC Vector Address Register 4"
|
|
line.long 0x14 "VIC_VECT_ADDR5,VIC Vector Address Register 5"
|
|
line.long 0x18 "VIC_VECT_ADDR6,VIC Vector Address Register 6"
|
|
line.long 0x1C "VIC_VECT_ADDR7,VIC Vector Address Register 7"
|
|
line.long 0x20 "VIC_VECT_ADDR8,VIC Vector Address Register 8"
|
|
line.long 0x24 "VIC_VECT_ADDR9,VIC Vector Address Register 9"
|
|
line.long 0x28 "VIC_VECT_ADDR10,VIC Vector Address Register 10"
|
|
line.long 0x2C "VIC_VECT_ADDR11,VIC Vector Address Register 11"
|
|
line.long 0x30 "VIC_VECT_ADDR12,VIC Vector Address Register 12"
|
|
line.long 0x34 "VIC_VECT_ADDR13,VIC Vector Address Register 13"
|
|
line.long 0x38 "VIC_VECT_ADDR14,VIC Vector Address Register 14"
|
|
line.long 0x3C "VIC_VECT_ADDR15,VIC Vector Address Register 15"
|
|
tree.end
|
|
tree "VIC_VECT_CNTL (VIC Vector Control Registers)"
|
|
group.long 0x200++0x03F
|
|
line.long 0x0 "VIC_VECT_CTRL0,VIC Vector Control Register 0"
|
|
bitfld.long 0x0 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x4 "VIC_VECT_CTRL1,VIC Vector Control Register 1"
|
|
bitfld.long 0x4 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x8 "VIC_VECT_CTRL2,VIC Vector Control Register 2"
|
|
bitfld.long 0x8 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0xC "VIC_VECT_CTRL3,VIC Vector Control Register 3"
|
|
bitfld.long 0xC 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x10 "VIC_VECT_CTRL4,VIC Vector Control Register 4"
|
|
bitfld.long 0x10 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x14 "VIC_VECT_CTRL5,VIC Vector Control Register 5"
|
|
bitfld.long 0x14 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x18 "VIC_VECT_CTRL6,VIC Vector Control Register 6"
|
|
bitfld.long 0x18 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x1C "VIC_VECT_CTRL7,VIC Vector Control Register 7"
|
|
bitfld.long 0x1C 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x20 "VIC_VECT_CTRL8,VIC Vector Control Register 8"
|
|
bitfld.long 0x20 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x24 "VIC_VECT_CTRL9,VIC Vector Control Register 9"
|
|
bitfld.long 0x24 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x28 "VIC_VECT_CTRL10,VIC Vector Control Register 10"
|
|
bitfld.long 0x28 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x2C "VIC_VECT_CTRL11,VIC Vector Control Register 11"
|
|
bitfld.long 0x2C 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x30 "VIC_VECT_CTRL12,VIC Vector Control Register 12"
|
|
bitfld.long 0x30 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x34 "VIC_VECT_CTRL13,VIC Vector Control Register 13"
|
|
bitfld.long 0x34 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x38 "VIC_VECT_CTRL14,VIC Vector Control Register 14"
|
|
bitfld.long 0x38 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
line.long 0x3C "VIC_VECT_CTRL15,VIC Vector Control Register 15"
|
|
bitfld.long 0x3C 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO15,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,HIF,GPIO,COM0,COM1,COM2,COM3,MSYNC0,MSYNC1,MSYNC2,MSYNC3,INT_PHY,ISO_AREA,Reserved,Reserved,TIMER3,TIMER4,?..."
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "Motion Control Functions"
|
|
tree "PWM (Pulse-width modulation)"
|
|
base ad:0x00162900
|
|
width 0x0F
|
|
group.long 0x5C++0x01B "PWM0"
|
|
line.long 0x00 "PWM0_CFG,PWM 0 Configuration Register"
|
|
bitfld.long 0x00 15. " RUN_RP ,Resolver PWM" "Stopped,Running"
|
|
bitfld.long 0x00 14. " RUN_MP ,Motor PWM" "Stopped,Running"
|
|
textline " "
|
|
bitfld.long 0x00 10. " AUTO_W ,gpio_pin[4/5] set" "VAL_W/VAL_WN,W output/WN output"
|
|
bitfld.long 0x00 9. " AUTO_V ,gpio_pin[2/3] set" "VAL_V/VAL_VN,V output/VN output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AUTO_U ,gpio_pin[0/1] set" "VAL_U/VAL_UN,U output/UN output"
|
|
bitfld.long 0x00 7. " PWM_MODE ,Motor PWM Mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FO_MODE ,Fiber Optic Mode" "Off,On"
|
|
bitfld.long 0x00 5. " VAL_WN ,Value of gpio_pins[5] if serial output date = 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VAL_W ,Value of gpio_pins[4] if serial output date = 1" "0,1"
|
|
bitfld.long 0x00 3. " VAL_VN ,Value of gpio_pins[3] if serial output date = 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VAL_V ,Value of gpio_pins[2] if serial output date = 1" "0,1"
|
|
bitfld.long 0x00 1. " VAL_UN ,Value of gpio_pins[1] if serial output date = 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VAL_U ,Value of gpio_pins[0] if serial output date = 1" "0,1"
|
|
line.long 0x04 "PWM0_STAT,PWM 0 Status Register"
|
|
eventfld.long 0x04 8. " SYSTIME_REQ ,System time captured at RPWM = 0" "0,1"
|
|
eventfld.long 0x04 7. " PWMERR_REQ ,Latched input signal failure" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 6. " PWMERR ,Actual input signal failure" "No error,Error"
|
|
eventfld.long 0x04 0. " SYSTC ,System time captured at beginning of motor PWM" "0,1"
|
|
line.long 0x08 "PWM0_TP,PWM 0 Period"
|
|
hexmask.long.word 0x08 0.--15. 1. " TP ,Length of PWM Period"
|
|
line.long 0x0C "PWM0_TU,PWM 0 Channel U Low Phase Width"
|
|
hexmask.long.word 0x0C 0.--15. 1. " LEVEL_U ,Width of channel U low phase in clock cycles"
|
|
line.long 0x10 "PWM0_TV,PWM 0 Channel V Low Phase Width"
|
|
hexmask.long.word 0x10 0.--15. 1. " LEVEL_V ,Width of channel V low phase in clock cycles"
|
|
line.long 0x14 "PWM0_TW,PWM 0 Channel W Low Phase Width"
|
|
hexmask.long.word 0x14 0.--15. 1. " LEVEL_W ,Width of channel W low phase in clock cycles"
|
|
line.long 0x18 "PWM0_TD,PWM 0 Dead Time Counter Preload"
|
|
hexmask.long.word 0x18 0.--15. 1. " PRELOAD_D ,Counter preload for dead time in clock cycles"
|
|
group.long (0x5C+0x24)++0x03
|
|
line.long 0x00 "PWM0_CNT,Actual Counter Motor PWM 0 Period"
|
|
hexmask.long.word 0x00 0.--15. 1. " PWM_CNT ,Actual counter Motor PWM Period"
|
|
group.long (0x5C+0x2C)++0x03
|
|
line.long 0x00 "PWM0_STRTIME,Captured System Time at Start Point of Motor PWM 0 Period"
|
|
hexmask.long.word 0x00 0.--15. 1. " PWM_STRTIME ,Captured Systime at start point of Motor PWM Period"
|
|
group.long (0x5C+0x1C)++0x07
|
|
line.long 0x00 "RPWM0_TP,Resolver PWM 0 Period"
|
|
hexmask.long.word 0x00 0.--15. 1. " RES_TP ,Resolver PWM Period"
|
|
line.long 0x04 "RPWM0_TR,Resolver PWM 0 Pulse"
|
|
hexmask.long.word 0x04 0.--15. 1. " RES_TR ,Resolver PWM Pulse"
|
|
group.long (0x5C+0x28)++0x03
|
|
line.long 0x00 "RPWM0_CNT,Actual Counter Resolver PWM 0 Period"
|
|
hexmask.long.word 0x00 0.--15. 1. " RPWM_CNT ,Actual counter Resolver PWM Period"
|
|
group.long (0x5C+0x30)++0x03
|
|
line.long 0x00 "RPWM0_STRTIME,Captured System time at Start Point of Resolver PWM 0 Period"
|
|
hexmask.long.word 0x00 0.--15. 1. " RPWM_STRTIME ,Captured System time at start point of Resolver PWM Period"
|
|
group.long 0x15C++0x01B "PWM1"
|
|
line.long 0x00 "PWM1_CFG,PWM 1 Configuration Register"
|
|
bitfld.long 0x00 15. " RUN_RP ,Resolver PWM" "Stopped,Running"
|
|
bitfld.long 0x00 14. " RUN_MP ,Motor PWM" "Stopped,Running"
|
|
textline " "
|
|
bitfld.long 0x00 10. " AUTO_W ,gpio_pin[4/5] set" "VAL_W/VAL_WN,W output/WN output"
|
|
bitfld.long 0x00 9. " AUTO_V ,gpio_pin[2/3] set" "VAL_V/VAL_VN,V output/VN output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AUTO_U ,gpio_pin[0/1] set" "VAL_U/VAL_UN,U output/UN output"
|
|
bitfld.long 0x00 7. " PWM_MODE ,Motor PWM Mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FO_MODE ,Fiber Optic Mode" "Off,On"
|
|
bitfld.long 0x00 5. " VAL_WN ,Value of gpio_pins[5] if serial output date = 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VAL_W ,Value of gpio_pins[4] if serial output date = 1" "0,1"
|
|
bitfld.long 0x00 3. " VAL_VN ,Value of gpio_pins[3] if serial output date = 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VAL_V ,Value of gpio_pins[2] if serial output date = 1" "0,1"
|
|
bitfld.long 0x00 1. " VAL_UN ,Value of gpio_pins[1] if serial output date = 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VAL_U ,Value of gpio_pins[0] if serial output date = 1" "0,1"
|
|
line.long 0x04 "PWM1_STAT,PWM 1 Status Register"
|
|
eventfld.long 0x04 8. " SYSTIME_REQ ,System time captured at RPWM = 0" "0,1"
|
|
eventfld.long 0x04 7. " PWMERR_REQ ,Latched input signal failure" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 6. " PWMERR ,Actual input signal failure" "No error,Error"
|
|
eventfld.long 0x04 0. " SYSTC ,System time captured at beginning of motor PWM" "0,1"
|
|
line.long 0x08 "PWM1_TP,PWM 1 Period"
|
|
hexmask.long.word 0x08 0.--15. 1. " TP ,Length of PWM Period"
|
|
line.long 0x0C "PWM1_TU,PWM 1 Channel U Low Phase Width"
|
|
hexmask.long.word 0x0C 0.--15. 1. " LEVEL_U ,Width of channel U low phase in clock cycles"
|
|
line.long 0x10 "PWM1_TV,PWM 1 Channel V Low Phase Width"
|
|
hexmask.long.word 0x10 0.--15. 1. " LEVEL_V ,Width of channel V low phase in clock cycles"
|
|
line.long 0x14 "PWM1_TW,PWM 1 Channel W Low Phase Width"
|
|
hexmask.long.word 0x14 0.--15. 1. " LEVEL_W ,Width of channel W low phase in clock cycles"
|
|
line.long 0x18 "PWM1_TD,PWM 1 Dead Time Counter Preload"
|
|
hexmask.long.word 0x18 0.--15. 1. " PRELOAD_D ,Counter preload for dead time in clock cycles"
|
|
group.long (0x15C+0x24)++0x03
|
|
line.long 0x00 "PWM1_CNT,Actual Counter Motor PWM 1 Period"
|
|
hexmask.long.word 0x00 0.--15. 1. " PWM_CNT ,Actual counter Motor PWM Period"
|
|
group.long (0x15C+0x2C)++0x03
|
|
line.long 0x00 "PWM1_STRTIME,Captured System Time at Start Point of Motor PWM 1 Period"
|
|
hexmask.long.word 0x00 0.--15. 1. " PWM_STRTIME ,Captured Systime at start point of Motor PWM Period"
|
|
group.long (0x15C+0x1C)++0x07
|
|
line.long 0x00 "RPWM1_TP,Resolver PWM 1 Period"
|
|
hexmask.long.word 0x00 0.--15. 1. " RES_TP ,Resolver PWM Period"
|
|
line.long 0x04 "RPWM1_TR,Resolver PWM 1 Pulse"
|
|
hexmask.long.word 0x04 0.--15. 1. " RES_TR ,Resolver PWM Pulse"
|
|
group.long (0x15C+0x28)++0x03
|
|
line.long 0x00 "RPWM1_CNT,Actual Counter Resolver PWM 1 Period"
|
|
hexmask.long.word 0x00 0.--15. 1. " RPWM_CNT ,Actual counter Resolver PWM Period"
|
|
group.long (0x15C+0x30)++0x03
|
|
line.long 0x00 "RPWM1_STRTIME,Captured System time at Start Point of Resolver PWM 1 Period"
|
|
hexmask.long.word 0x00 0.--15. 1. " RPWM_STRTIME ,Captured System time at start point of Resolver PWM Period"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ENC (Quadrature Encoders)"
|
|
base ad:0x00163000
|
|
width 10.
|
|
group.long 0x99C++0x003
|
|
line.long 0x000 "ENC_STAT,Encoder Position and Capture Status"
|
|
eventfld.long 0x000 15. " MP1 ,Measurement Point 1" "0,1"
|
|
eventfld.long 0x000 14. " MP0 ,Measurement Point 0" "0,1"
|
|
textline " "
|
|
eventfld.long 0x000 13. " ENC1_SIGN ,Encoder 1 signal N" "0,1"
|
|
eventfld.long 0x000 12. " ENC0_SIGN ,Encoder 0 signal N" "0,1"
|
|
textline " "
|
|
eventfld.long 0x000 11. " CAP3 ,Captured register 3" "Not captured,Captured"
|
|
eventfld.long 0x000 10. " CAP2 ,Captured register 2" "Not captured,Captured"
|
|
textline " "
|
|
eventfld.long 0x000 9. " CAP1 ,Captured register 1" "Not captured,Captured"
|
|
eventfld.long 0x000 8. " CAP0 ,Captured register 0" "Not captured,Captured"
|
|
textline " "
|
|
eventfld.long 0x000 7. " ENC1_CAP_ETIME ,Encoder1 captured edge time" "Not captured,Captured"
|
|
eventfld.long 0x000 6. " ENC1_CAP_ZPOS ,Encoder1 captured null position" "Not captured,Captured"
|
|
textline " "
|
|
eventfld.long 0x000 5. " ENC1_OVFL_NEG ,Encoder1 overflow negative" "Not negative,Negative"
|
|
eventfld.long 0x000 4. " ENC1_OVFL_POS ,Encoder1 overflow positive" "Not positive,Positive"
|
|
textline " "
|
|
eventfld.long 0x000 3. " ENC0_CAP_ETIME ,Encoder0 captured edge time" "Not captured,Captured"
|
|
eventfld.long 0x000 2. " ENC0_CAP_ZPOS ,Encoder0 captured null position" "Not captured,Captured"
|
|
textline " "
|
|
eventfld.long 0x000 1. " ENC0_OVFL_NEG ,Encoder0 overflow negative" "Not negative,Negative"
|
|
eventfld.long 0x000 0. " ENC0_OVFL_POS ,Encoder0 overflow positive" "Not positive,Positive"
|
|
group.long 0x990++0x003
|
|
line.long 0x00 "ENC_CFG,Encoder Configuration Register"
|
|
bitfld.long 0x00 12.--13. " ENC1_N_QUALIFIER ,Encoder 1 N-qualifier" "None,N-Signal,MP0=1,MP1=1"
|
|
bitfld.long 0x00 11. " ENC1_COUNT_DIR ,Encoder 1 count direction" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " ENC1_FILTER_SR ,Encoder 1 filter sample rate" "None,10 ns,20 ns,50 ns,100 ns,200 ns,500 ns,1 us"
|
|
bitfld.long 0x00 4.--5. " ENC0_N_QUALIFIER ,Encoder 0 N-qualifier" "None,N-Signal,MP0=1,MP1=1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENC0_COUNT_DIR ,Encoder 0 count direction" "Up,Down"
|
|
bitfld.long 0x00 0.--2. " ENC0_FILTER_SR ,Encoder 0 filter sample rate" "None,10 ns,20 ns,50 ns,100 ns,200 ns,500 ns,1 us"
|
|
group.long 0x998++0x003
|
|
line.long 0x00 "ENC_CMD,Encoder Command Register"
|
|
bitfld.long 0x00 10. " ENC1_RES_ZPOS ,Encoder1 reset null position" "No reset,Reset"
|
|
bitfld.long 0x00 9. " ENC1_RES_POS ,Encoder1 reset position" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENC1_EN ,Encoder1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENC0_RES_ZPOS ,Encoder0 reset null position" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENC0_RES_POS ,Encoder0 reset position" "No reset,Reset"
|
|
bitfld.long 0x00 0. " ENC0_EN ,Encoder0 enable" "Disabled,Enabled"
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "ENC0_POS,Actual Position Encoder 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " POSITION ,Actual position encoder"
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "ENC1_POS,Actual Position Encoder 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " POSITION ,Actual position encoder"
|
|
width 15.
|
|
rgroup.long 0x9A4++0x03
|
|
line.long 0x00 "ENC0_NULL_POS,Sampled Null Position Encoder 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " NULLPOSITION ,Last null position of encoder"
|
|
rgroup.long 0x9AC++0x03
|
|
line.long 0x00 "ENC1_NULL_POS,Sampled Null Position Encoder 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " NULLPOSITION ,Last null position of encoder"
|
|
rgroup.long 0x9B0++0x03
|
|
line.long 0x00 "ENC0_EDGE_TIME,System Time at Last Edge of Encoder 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " EDGETIME ,System time at last edge of encoder"
|
|
rgroup.long 0x9B4++0x03
|
|
line.long 0x00 "ENC1_EDGE_TIME,System Time at Last Edge of Encoder 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " EDGETIME ,System time at last edge of encoder"
|
|
group.long 0x994++0x003
|
|
line.long 0x00 "ENC_CFG_CAPT,Encoder Capture Configuration Register"
|
|
bitfld.long 0x00 14.--15. " CREG3_SRC ,Encoder capture register 3 source" "None,System time ns,Position channel 1,Position channel 2"
|
|
bitfld.long 0x00 12.--13. " CREG3_CW ,Encoder capture register 3 capture with" "mp0 positive edge,mp0 negative edge,mp1 positive edge,mp1 negative edge"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CREG2_SRC ,Encoder capture register 2 source" "None,System time ns,Position channel 1,Position channel 2"
|
|
bitfld.long 0x00 8.--9. " CREG2_CW ,Encoder capture register 2 capture with" "mp0 positive edge,mp0 negative edge,mp1 positive edge,mp1 negative edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CREG1_SRC ,Encoder capture register 1 source" "None,System time ns,Position channel 1,Position channel 2"
|
|
bitfld.long 0x00 4.--5. " CREG1_CW ,Encoder capture register 1 capture with" "mp0 positive edge,mp0 negative edge,mp1 positive edge,mp1 negative edge"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CREG0_SRC ,Encoder capture register 0 source" "None,System time ns,Position channel 1,Position channel 2"
|
|
bitfld.long 0x00 0.--1. " CREG0_CW ,Encoder capture register 0 capture with" "mp0 positive edge,mp0 negative edge,mp1 positive edge,mp1 negative edge"
|
|
rgroup.long 0x9B8++0xF
|
|
line.long 0x0 "ENC_CAPT0,Encoder Capture Register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. " ENC_CAPT0 ,Encoder capture register 0"
|
|
line.long 0x4 "ENC_CAPT1,Encoder Capture Register 1"
|
|
hexmask.long.word 0x4 0.--15. 1. " ENC_CAPT1 ,Encoder capture register 1"
|
|
line.long 0x8 "ENC_CAPT2,Encoder Capture Register 2"
|
|
hexmask.long.word 0x8 0.--15. 1. " ENC_CAPT2 ,Encoder capture register 2"
|
|
line.long 0xC "ENC_CAPT3,Encoder Capture Register 3"
|
|
hexmask.long.word 0xC 0.--15. 1. " ENC_CAPT3 ,Encoder capture register 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC (Analogue Digital Converters)"
|
|
base ad:0x00170000
|
|
width 0x06
|
|
rgroup.long 0x9C++0x03 "Channel 0"
|
|
line.long 0x00 "ADCCH0,Analogue Digital Converter Register Channel 0"
|
|
bitfld.long 0x00 26. " ADC1_BUSY ,ADC1 busy" "Not busy,Busy"
|
|
hexmask.long.word 0x0000 16.--25. 1. " ADC1_D ,Sample value of ADC1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ADC0_BUSY ,ADC0 busy" "Not busy,Busy"
|
|
hexmask.long.word 0x0000 0.--9. 1. " ADC0_D ,Sample value of ADC0"
|
|
wgroup.long 0x9C++0x03
|
|
line.long 0x00 "ADCCH0,Analogue Digital Converter Register Channel 0"
|
|
bitfld.long 0x00 31. " DONT_WRITE_ADC1 ,Dont write ADC1 (must be set to configure ADC0)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--20. " ADC1_SEL[2:0] ,Channel selection of ADC1" "Channel 0,Reserved,Channel 2,Reserved,Channel 4,Reserved,Channel 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 17. " ADC1_START ,Start conversion of ADC1" "Not started,Started"
|
|
bitfld.long 0x00 16. " ADC1_EN ,ADC1 unit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DONT_WRITE_ADC0 ,Dont write ADC0 (must be set to configure ADC1)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " ADC0_SEL[2:0] ,Channel selection of ADC0" "Channel 0,Reserved,Channel 2,Reserved,Channel 4,Reserved,Channel 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADC0_START ,Start conversion of ADC0" "Not started,Started"
|
|
bitfld.long 0x00 0. " ADC0_EN ,ADC0 unit enable" "Disabled,Enabled"
|
|
rgroup.long 0x409C++0x03 "Channel 2"
|
|
line.long 0x00 "ADCCH2,Analogue Digital Converter Register Channel 2"
|
|
bitfld.long 0x00 26. " ADC1_BUSY ,ADC1 busy" "Not busy,Busy"
|
|
hexmask.long.word 0x0000 16.--25. 1. " ADC1_D ,Sample value of ADC1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ADC0_BUSY ,ADC0 busy" "Not busy,Busy"
|
|
hexmask.long.word 0x0000 0.--9. 1. " ADC0_D ,Sample value of ADC0"
|
|
wgroup.long 0x409C++0x03
|
|
line.long 0x00 "ADCCH2,Analogue Digital Converter Register Channel 2"
|
|
bitfld.long 0x00 31. " DONT_WRITE_ADC1 ,Dont write ADC1 (must be set to configure ADC0)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--20. " ADC1_SEL[2:0] ,Channel selection of ADC1" "Channel 0,Reserved,Channel 2,Reserved,Channel 4,Reserved,Channel 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 17. " ADC1_START ,Start conversion of ADC1" "Not started,Started"
|
|
bitfld.long 0x00 16. " ADC1_EN ,ADC1 unit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DONT_WRITE_ADC0 ,Dont write ADC0 (must be set to configure ADC1)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " ADC0_SEL[2:0] ,Channel selection of ADC0" "Channel 0,Reserved,Channel 2,Reserved,Channel 4,Reserved,Channel 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADC0_START ,Start conversion of ADC0" "Not started,Started"
|
|
bitfld.long 0x00 0. " ADC0_EN ,ADC0 unit enable" "Disabled,Enabled"
|
|
rgroup.long 0x809C++0x03 "Channel 4"
|
|
line.long 0x00 "ADCCH4,Analogue Digital Converter Register Channel 4"
|
|
bitfld.long 0x00 26. " ADC1_BUSY ,ADC1 busy" "Not busy,Busy"
|
|
hexmask.long.word 0x0000 16.--25. 1. " ADC1_D ,Sample value of ADC1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ADC0_BUSY ,ADC0 busy" "Not busy,Busy"
|
|
hexmask.long.word 0x0000 0.--9. 1. " ADC0_D ,Sample value of ADC0"
|
|
wgroup.long 0x809C++0x03
|
|
line.long 0x00 "ADCCH4,Analogue Digital Converter Register Channel 4"
|
|
bitfld.long 0x00 31. " DONT_WRITE_ADC1 ,Dont write ADC1 (must be set to configure ADC0)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--20. " ADC1_SEL[2:0] ,Channel selection of ADC1" "Channel 0,Reserved,Channel 2,Reserved,Channel 4,Reserved,Channel 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 17. " ADC1_START ,Start conversion of ADC1" "Not started,Started"
|
|
bitfld.long 0x00 16. " ADC1_EN ,ADC1 unit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DONT_WRITE_ADC0 ,Dont write ADC0 (must be set to configure ADC1)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " ADC0_SEL[2:0] ,Channel selection of ADC0" "Channel 0,Reserved,Channel 2,Reserved,Channel 4,Reserved,Channel 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADC0_START ,Start conversion of ADC0" "Not started,Started"
|
|
bitfld.long 0x00 0. " ADC0_EN ,ADC0 unit enable" "Disabled,Enabled"
|
|
rgroup.long 0xC09C++0x03 "Channel 6"
|
|
line.long 0x00 "ADCCH6,Analogue Digital Converter Register Channel 6"
|
|
bitfld.long 0x00 26. " ADC1_BUSY ,ADC1 busy" "Not busy,Busy"
|
|
hexmask.long.word 0x0000 16.--25. 1. " ADC1_D ,Sample value of ADC1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ADC0_BUSY ,ADC0 busy" "Not busy,Busy"
|
|
hexmask.long.word 0x0000 0.--9. 1. " ADC0_D ,Sample value of ADC0"
|
|
wgroup.long 0xC09C++0x03
|
|
line.long 0x00 "ADCCH6,Analogue Digital Converter Register Channel 6"
|
|
bitfld.long 0x00 31. " DONT_WRITE_ADC1 ,Dont write ADC1 (must be set to configure ADC0)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--20. " ADC1_SEL[2:0] ,Channel selection of ADC1" "Channel 0,Reserved,Channel 2,Reserved,Channel 4,Reserved,Channel 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 17. " ADC1_START ,Start conversion of ADC1" "Not started,Started"
|
|
bitfld.long 0x00 16. " ADC1_EN ,ADC1 unit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DONT_WRITE_ADC0 ,Dont write ADC0 (must be set to configure ADC1)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " ADC0_SEL[2:0] ,Channel selection of ADC0" "Channel 0,Reserved,Channel 2,Reserved,Channel 4,Reserved,Channel 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADC0_START ,Start conversion of ADC0" "Not started,Started"
|
|
bitfld.long 0x00 0. " ADC0_EN ,ADC0 unit enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "Communication Functions"
|
|
tree "PHY (Controller for internal PHYs)"
|
|
base ad:0x00100010
|
|
width 0x08
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PHY_CR,PHY Control Register"
|
|
bitfld.long 0x00 31. " PHY_RESET ,Hardware reset for PHY" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 30. " PHY_SIM_BYP ,PHY Power up Bypass" "Normal,Bypass"
|
|
textline " "
|
|
sif (cpu()!="NETX50")
|
|
bitfld.long 0x00 29. " PHY_CLK_XLATIN ,Source for clock Ethernet PHY" "Phyclk_rate_mul_add,External oscillator"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " PHY1_ENABLE ,PHY1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " PHY1_NP_MSG_CODE ,PHY1 Next Page Message Code" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PHY1_AUTOMDIX ,PHY1 Enable AutoMDIX state machine" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PHY1_FXMODE ,PHY1 100BASE-FX mode" "TX,FX"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " PHY1_MODE ,PHY1 Mode" "10BASE-T Half Duplex,10BASE-T Full Duplex,100BASE-TX/FX Half Duplex,100BASE-TX/FX Full Duplex,100BASE-TX Half Duplex,Repeater mode,Power Down mode,All capable"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PHY0_ENABLE ,PHY0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " PHY0_NP_MSG_CODE ,PHY0 Next Page Message Code" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PHY0_AUTOMDIX ,PHY0 Enable AutoMDIX state machine" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PHY0_FXMODE ,PHY0 100BASE-FX mode" "TX,FX"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PHY0_MODE ,PHY0 Mode" "10BASE-T Half Duplex,10BASE-T Full Duplex,100BASE-TX/FX Half Duplex,100BASE-TX/FX Full Duplex,100BASE-TX Half Duplex,Repeater mode,Power Down mode,All capable"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--3. 1. " PHY_ADDRESS ,Bits 4:1 of phy mdio-address"
|
|
sif (cpu()=="NETX100")
|
|
width 22.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PHY_CLK_RATE_MUL_ADD,PHY Clock Rate Multiplier Add Value"
|
|
hexmask.long 0x00 0.--30. 1. " PHYCLK_RATE_MUL_ADD ,Value added each clk200 cycle to phyclk_rate_mul to generate phyclk"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PFIFO (Pointer FIFO)"
|
|
base ad:0x00164000
|
|
width 21.
|
|
tree "PFIFO_BASE0-31 (Pointer FIFO 0-31 Base Address)"
|
|
hgroup.long 0x000++0x07F
|
|
hide.long 0x0 "PFIFO_BASE0 ,Pointer FIFO 0 Base Address"
|
|
in
|
|
hide.long 0x4 "PFIFO_BASE1 ,Pointer FIFO 1 Base Address"
|
|
in
|
|
hide.long 0x8 "PFIFO_BASE2 ,Pointer FIFO 2 Base Address"
|
|
in
|
|
hide.long 0xC "PFIFO_BASE3 ,Pointer FIFO 3 Base Address"
|
|
in
|
|
hide.long 0x10 "PFIFO_BASE4 ,Pointer FIFO 4 Base Address"
|
|
in
|
|
hide.long 0x14 "PFIFO_BASE5 ,Pointer FIFO 5 Base Address"
|
|
in
|
|
hide.long 0x18 "PFIFO_BASE6 ,Pointer FIFO 6 Base Address"
|
|
in
|
|
hide.long 0x1C "PFIFO_BASE7 ,Pointer FIFO 7 Base Address"
|
|
in
|
|
hide.long 0x20 "PFIFO_BASE8 ,Pointer FIFO 8 Base Address"
|
|
in
|
|
hide.long 0x24 "PFIFO_BASE9 ,Pointer FIFO 9 Base Address"
|
|
in
|
|
hide.long 0x28 "PFIFO_BASE10,Pointer FIFO 10 Base Address"
|
|
in
|
|
hide.long 0x2C "PFIFO_BASE11,Pointer FIFO 11 Base Address"
|
|
in
|
|
hide.long 0x30 "PFIFO_BASE12,Pointer FIFO 12 Base Address"
|
|
in
|
|
hide.long 0x34 "PFIFO_BASE13,Pointer FIFO 13 Base Address"
|
|
in
|
|
hide.long 0x38 "PFIFO_BASE14,Pointer FIFO 14 Base Address"
|
|
in
|
|
hide.long 0x3C "PFIFO_BASE15,Pointer FIFO 15 Base Address"
|
|
in
|
|
hide.long 0x40 "PFIFO_BASE16,Pointer FIFO 16 Base Address"
|
|
in
|
|
hide.long 0x44 "PFIFO_BASE17,Pointer FIFO 17 Base Address"
|
|
in
|
|
hide.long 0x48 "PFIFO_BASE18,Pointer FIFO 18 Base Address"
|
|
in
|
|
hide.long 0x4C "PFIFO_BASE19,Pointer FIFO 19 Base Address"
|
|
in
|
|
hide.long 0x50 "PFIFO_BASE20,Pointer FIFO 20 Base Address"
|
|
in
|
|
hide.long 0x54 "PFIFO_BASE21,Pointer FIFO 21 Base Address"
|
|
in
|
|
hide.long 0x58 "PFIFO_BASE22,Pointer FIFO 22 Base Address"
|
|
in
|
|
hide.long 0x5C "PFIFO_BASE23,Pointer FIFO 23 Base Address"
|
|
in
|
|
hide.long 0x60 "PFIFO_BASE24,Pointer FIFO 24 Base Address"
|
|
in
|
|
hide.long 0x64 "PFIFO_BASE25,Pointer FIFO 25 Base Address"
|
|
in
|
|
hide.long 0x68 "PFIFO_BASE26,Pointer FIFO 26 Base Address"
|
|
in
|
|
hide.long 0x6C "PFIFO_BASE27,Pointer FIFO 27 Base Address"
|
|
in
|
|
hide.long 0x70 "PFIFO_BASE28,Pointer FIFO 28 Base Address"
|
|
in
|
|
hide.long 0x74 "PFIFO_BASE29,Pointer FIFO 29 Base Address"
|
|
in
|
|
hide.long 0x78 "PFIFO_BASE30,Pointer FIFO 30 Base Address"
|
|
in
|
|
hide.long 0x7C "PFIFO_BASE31,Pointer FIFO 31 Base Address"
|
|
in
|
|
tree.end
|
|
tree "PFIFO_BORDER_BASE0-31 (Pointer FIFO 0-31 Upper Border)"
|
|
group.long 0x080++0x7F
|
|
textline " "
|
|
sif (cpu()=="NETX51")
|
|
line.long 0x00 "PTR_FIFO_BOR_BASE0,Pointer FIFO 0 Upper Border"
|
|
hexmask.long.word 0x00 0.--11. 1. " BORDER ,Last address of RAM used by FIFO"
|
|
line.long 0x4 "PTR_FIFO_BOR_BASE1 ,Pointer FIFO 1 Upper Border"
|
|
line.long 0x8 "PTR_FIFO_BOR_BASE2 ,Pointer FIFO 2 Upper Border"
|
|
line.long 0xC "PTR_FIFO_BOR_BASE3 ,Pointer FIFO 3 Upper Border"
|
|
line.long 0x10 "PTR_FIFO_BOR_BASE4 ,Pointer FIFO 4 Upper Border"
|
|
line.long 0x14 "PTR_FIFO_BOR_BASE5 ,Pointer FIFO 5 Upper Border"
|
|
line.long 0x18 "PTR_FIFO_BOR_BASE6 ,Pointer FIFO 6 Upper Border"
|
|
line.long 0x1C "PTR_FIFO_BOR_BASE7 ,Pointer FIFO 7 Upper Border"
|
|
line.long 0x20 "PTR_FIFO_BOR_BASE8 ,Pointer FIFO 8 Upper Border"
|
|
line.long 0x24 "PTR_FIFO_BOR_BASE9 ,Pointer FIFO 9 Upper Border"
|
|
line.long 0x28 "PTR_FIFO_BOR_BASE10,Pointer FIFO 10 Upper Border"
|
|
line.long 0x2C "PTR_FIFO_BOR_BASE11,Pointer FIFO 11 Upper Border"
|
|
line.long 0x30 "PTR_FIFO_BOR_BASE12,Pointer FIFO 12 Upper Border"
|
|
line.long 0x34 "PTR_FIFO_BOR_BASE13,Pointer FIFO 13 Upper Border"
|
|
line.long 0x38 "PTR_FIFO_BOR_BASE14,Pointer FIFO 14 Upper Border"
|
|
line.long 0x3C "PTR_FIFO_BOR_BASE15,Pointer FIFO 15 Upper Border"
|
|
line.long 0x40 "PTR_FIFO_BOR_BASE16,Pointer FIFO 16 Upper Border"
|
|
line.long 0x44 "PTR_FIFO_BOR_BASE17,Pointer FIFO 17 Upper Border"
|
|
line.long 0x48 "PTR_FIFO_BOR_BASE18,Pointer FIFO 18 Upper Border"
|
|
line.long 0x4C "PTR_FIFO_BOR_BASE19,Pointer FIFO 19 Upper Border"
|
|
line.long 0x50 "PTR_FIFO_BOR_BASE20,Pointer FIFO 20 Upper Border"
|
|
line.long 0x54 "PTR_FIFO_BOR_BASE21,Pointer FIFO 21 Upper Border"
|
|
line.long 0x58 "PTR_FIFO_BOR_BASE22,Pointer FIFO 22 Upper Border"
|
|
line.long 0x5C "PTR_FIFO_BOR_BASE23,Pointer FIFO 23 Upper Border"
|
|
line.long 0x60 "PTR_FIFO_BOR_BASE24,Pointer FIFO 24 Upper Border"
|
|
line.long 0x64 "PTR_FIFO_BOR_BASE25,Pointer FIFO 25 Upper Border"
|
|
line.long 0x68 "PTR_FIFO_BOR_BASE26,Pointer FIFO 26 Upper Border"
|
|
line.long 0x6C "PTR_FIFO_BOR_BASE27,Pointer FIFO 27 Upper Border"
|
|
line.long 0x70 "PTR_FIFO_BOR_BASE28,Pointer FIFO 28 Upper Border"
|
|
line.long 0x74 "PTR_FIFO_BOR_BASE29,Pointer FIFO 29 Upper Border"
|
|
line.long 0x78 "PTR_FIFO_BOR_BASE30,Pointer FIFO 30 Upper Border"
|
|
line.long 0x7C "PTR_FIFO_BOR_BASE31,Pointer FIFO 31 Upper Border"
|
|
else
|
|
line.long 0x0 "PTR_FIFO_BOR_BASE0 ,Pointer FIFO 0 Upper Border"
|
|
line.long 0x4 "PTR_FIFO_BOR_BASE1 ,Pointer FIFO 1 Upper Border"
|
|
line.long 0x8 "PTR_FIFO_BOR_BASE2 ,Pointer FIFO 2 Upper Border"
|
|
line.long 0xC "PTR_FIFO_BOR_BASE3 ,Pointer FIFO 3 Upper Border"
|
|
line.long 0x10 "PTR_FIFO_BOR_BASE4 ,Pointer FIFO 4 Upper Border"
|
|
line.long 0x14 "PTR_FIFO_BOR_BASE5 ,Pointer FIFO 5 Upper Border"
|
|
line.long 0x18 "PTR_FIFO_BOR_BASE6 ,Pointer FIFO 6 Upper Border"
|
|
line.long 0x1C "PTR_FIFO_BOR_BASE7 ,Pointer FIFO 7 Upper Border"
|
|
line.long 0x20 "PTR_FIFO_BOR_BASE8 ,Pointer FIFO 8 Upper Border"
|
|
line.long 0x24 "PTR_FIFO_BOR_BASE9 ,Pointer FIFO 9 Upper Border"
|
|
line.long 0x28 "PTR_FIFO_BOR_BASE10,Pointer FIFO 10 Upper Border"
|
|
line.long 0x2C "PTR_FIFO_BOR_BASE11,Pointer FIFO 11 Upper Border"
|
|
line.long 0x30 "PTR_FIFO_BOR_BASE12,Pointer FIFO 12 Upper Border"
|
|
line.long 0x34 "PTR_FIFO_BOR_BASE13,Pointer FIFO 13 Upper Border"
|
|
line.long 0x38 "PTR_FIFO_BOR_BASE14,Pointer FIFO 14 Upper Border"
|
|
line.long 0x3C "PTR_FIFO_BOR_BASE15,Pointer FIFO 15 Upper Border"
|
|
line.long 0x40 "PTR_FIFO_BOR_BASE16,Pointer FIFO 16 Upper Border"
|
|
line.long 0x44 "PTR_FIFO_BOR_BASE17,Pointer FIFO 17 Upper Border"
|
|
line.long 0x48 "PTR_FIFO_BOR_BASE18,Pointer FIFO 18 Upper Border"
|
|
line.long 0x4C "PTR_FIFO_BOR_BASE19,Pointer FIFO 19 Upper Border"
|
|
line.long 0x50 "PTR_FIFO_BOR_BASE20,Pointer FIFO 20 Upper Border"
|
|
line.long 0x54 "PTR_FIFO_BOR_BASE21,Pointer FIFO 21 Upper Border"
|
|
line.long 0x58 "PTR_FIFO_BOR_BASE22,Pointer FIFO 22 Upper Border"
|
|
line.long 0x5C "PTR_FIFO_BOR_BASE23,Pointer FIFO 23 Upper Border"
|
|
line.long 0x60 "PTR_FIFO_BOR_BASE24,Pointer FIFO 24 Upper Border"
|
|
line.long 0x64 "PTR_FIFO_BOR_BASE25,Pointer FIFO 25 Upper Border"
|
|
line.long 0x68 "PTR_FIFO_BOR_BASE26,Pointer FIFO 26 Upper Border"
|
|
line.long 0x6C "PTR_FIFO_BOR_BASE27,Pointer FIFO 27 Upper Border"
|
|
line.long 0x70 "PTR_FIFO_BOR_BASE28,Pointer FIFO 28 Upper Border"
|
|
line.long 0x74 "PTR_FIFO_BOR_BASE29,Pointer FIFO 29 Upper Border"
|
|
line.long 0x78 "PTR_FIFO_BOR_BASE30,Pointer FIFO 30 Upper Border"
|
|
line.long 0x7C "PTR_FIFO_BOR_BASE31,Pointer FIFO 31 Upper Border"
|
|
endif
|
|
tree.end
|
|
width 16.
|
|
tree "PFIFO RESET FULL EMPTY OVERFLOW UNDERRUN"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PTR_FIFO_RESET,Pointer FIFO Reset Vector"
|
|
bitfld.long 0x00 31. " PTR_FIFO_RESET31 ,Reset FIFO 31 " "Normal,Reset"
|
|
bitfld.long 0x00 30. " PTR_FIFO_RESET30 ,Reset FIFO 30 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PTR_FIFO_RESET29 ,Reset FIFO 29 " "Normal,Reset"
|
|
bitfld.long 0x00 28. " PTR_FIFO_RESET28 ,Reset FIFO 28 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PTR_FIFO_RESET27 ,Reset FIFO 27 " "Normal,Reset"
|
|
bitfld.long 0x00 26. " PTR_FIFO_RESET26 ,Reset FIFO 26 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PTR_FIFO_RESET25 ,Reset FIFO 25 " "Normal,Reset"
|
|
bitfld.long 0x00 24. " PTR_FIFO_RESET24 ,Reset FIFO 24 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PTR_FIFO_RESET23 ,Reset FIFO 23 " "Normal,Reset"
|
|
bitfld.long 0x00 22. " PTR_FIFO_RESET22 ,Reset FIFO 22 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PTR_FIFO_RESET21 ,Reset FIFO 21 " "Normal,Reset"
|
|
bitfld.long 0x00 20. " PTR_FIFO_RESET20 ,Reset FIFO 20 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PTR_FIFO_RESET19 ,Reset FIFO 19 " "Normal,Reset"
|
|
bitfld.long 0x00 18. " PTR_FIFO_RESET18 ,Reset FIFO 18 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PTR_FIFO_RESET17 ,Reset FIFO 17 " "Normal,Reset"
|
|
bitfld.long 0x00 16. " PTR_FIFO_RESET16 ,Reset FIFO 16 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PTR_FIFO_RESET15 ,Reset FIFO 15 " "Normal,Reset"
|
|
bitfld.long 0x00 14. " PTR_FIFO_RESET14 ,Reset FIFO 14 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PTR_FIFO_RESET13 ,Reset FIFO 13 " "Normal,Reset"
|
|
bitfld.long 0x00 12. " PTR_FIFO_RESET12 ,Reset FIFO 12 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PTR_FIFO_RESET11 ,Reset FIFO 11 " "Normal,Reset"
|
|
bitfld.long 0x00 10. " PTR_FIFO_RESET10 ,Reset FIFO 10 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PTR_FIFO_RESET9 ,Reset FIFO 9 " "Normal,Reset"
|
|
bitfld.long 0x00 8. " PTR_FIFO_RESET8 ,Reset FIFO 8 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PTR_FIFO_RESET7 ,Reset FIFO 7 " "Normal,Reset"
|
|
bitfld.long 0x00 6. " PTR_FIFO_RESET6 ,Reset FIFO 6 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PTR_FIFO_RESET5 ,Reset FIFO 5 " "Normal,Reset"
|
|
bitfld.long 0x00 4. " PTR_FIFO_RESET4 ,Reset FIFO 4 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTR_FIFO_RESET3 ,Reset FIFO 3 " "Normal,Reset"
|
|
bitfld.long 0x00 2. " PTR_FIFO_RESET2 ,Reset FIFO 2 " "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTR_FIFO_RESET1 ,Reset FIFO 1 " "Normal,Reset"
|
|
bitfld.long 0x00 0. " PTR_FIFO_RESET0 ,Reset FIFO 0 " "Normal,Reset"
|
|
rgroup.long 0x104++0x00F
|
|
line.long 0x00 "PFIFO_FULL,Pointer FIFO Full Vector"
|
|
bitfld.long 0x00 31. " PTR_FIFO_FULL31 ,FIFO 31 full " "Not full,Full"
|
|
bitfld.long 0x00 30. " PTR_FIFO_FULL30 ,FIFO 30 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PTR_FIFO_FULL29 ,FIFO 29 full " "Not full,Full"
|
|
bitfld.long 0x00 28. " PTR_FIFO_FULL28 ,FIFO 28 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PTR_FIFO_FULL27 ,FIFO 27 full " "Not full,Full"
|
|
bitfld.long 0x00 26. " PTR_FIFO_FULL26 ,FIFO 26 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PTR_FIFO_FULL25 ,FIFO 25 full " "Not full,Full"
|
|
bitfld.long 0x00 24. " PTR_FIFO_FULL24 ,FIFO 24 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PTR_FIFO_FULL23 ,FIFO 23 full " "Not full,Full"
|
|
bitfld.long 0x00 22. " PTR_FIFO_FULL22 ,FIFO 22 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PTR_FIFO_FULL21 ,FIFO 21 full " "Not full,Full"
|
|
bitfld.long 0x00 20. " PTR_FIFO_FULL20 ,FIFO 20 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PTR_FIFO_FULL19 ,FIFO 19 full " "Not full,Full"
|
|
bitfld.long 0x00 18. " PTR_FIFO_FULL18 ,FIFO 18 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PTR_FIFO_FULL17 ,FIFO 17 full " "Not full,Full"
|
|
bitfld.long 0x00 16. " PTR_FIFO_FULL16 ,FIFO 16 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PTR_FIFO_FULL15 ,FIFO 15 full " "Not full,Full"
|
|
bitfld.long 0x00 14. " PTR_FIFO_FULL14 ,FIFO 14 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PTR_FIFO_FULL13 ,FIFO 13 full " "Not full,Full"
|
|
bitfld.long 0x00 12. " PTR_FIFO_FULL12 ,FIFO 12 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PTR_FIFO_FULL11 ,FIFO 11 full " "Not full,Full"
|
|
bitfld.long 0x00 10. " PTR_FIFO_FULL10 ,FIFO 10 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PTR_FIFO_FULL9 ,FIFO 9 full " "Not full,Full"
|
|
bitfld.long 0x00 8. " PTR_FIFO_FULL8 ,FIFO 8 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PTR_FIFO_FULL7 ,FIFO 7 full " "Not full,Full"
|
|
bitfld.long 0x00 6. " PTR_FIFO_FULL6 ,FIFO 6 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PTR_FIFO_FULL5 ,FIFO 5 full " "Not full,Full"
|
|
bitfld.long 0x00 4. " PTR_FIFO_FULL4 ,FIFO 4 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTR_FIFO_FULL3 ,FIFO 3 full " "Not full,Full"
|
|
bitfld.long 0x00 2. " PTR_FIFO_FULL2 ,FIFO 2 full " "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTR_FIFO_FULL1 ,FIFO 1 full " "Not full,Full"
|
|
bitfld.long 0x00 0. " PTR_FIFO_FULL0 ,FIFO 0 full " "Not full,Full"
|
|
line.long 0x04 "PFIFO_EMPTY,Pointer FIFO Empty Vector"
|
|
bitfld.long 0x04 31. " PTR_FIFO_EMPTY31 ,FIFO 31 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 30. " PTR_FIFO_EMPTY30 ,FIFO 30 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 29. " PTR_FIFO_EMPTY29 ,FIFO 29 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 28. " PTR_FIFO_EMPTY28 ,FIFO 28 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PTR_FIFO_EMPTY27 ,FIFO 27 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 26. " PTR_FIFO_EMPTY26 ,FIFO 26 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 25. " PTR_FIFO_EMPTY25 ,FIFO 25 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 24. " PTR_FIFO_EMPTY24 ,FIFO 24 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PTR_FIFO_EMPTY23 ,FIFO 23 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 22. " PTR_FIFO_EMPTY22 ,FIFO 22 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 21. " PTR_FIFO_EMPTY21 ,FIFO 21 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 20. " PTR_FIFO_EMPTY20 ,FIFO 20 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PTR_FIFO_EMPTY19 ,FIFO 19 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 18. " PTR_FIFO_EMPTY18 ,FIFO 18 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PTR_FIFO_EMPTY17 ,FIFO 17 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 16. " PTR_FIFO_EMPTY16 ,FIFO 16 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PTR_FIFO_EMPTY15 ,FIFO 15 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 14. " PTR_FIFO_EMPTY14 ,FIFO 14 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PTR_FIFO_EMPTY13 ,FIFO 13 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 12. " PTR_FIFO_EMPTY12 ,FIFO 12 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PTR_FIFO_EMPTY11 ,FIFO 11 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 10. " PTR_FIFO_EMPTY10 ,FIFO 10 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PTR_FIFO_EMPTY9 ,FIFO 9 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 8. " PTR_FIFO_EMPTY8 ,FIFO 8 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PTR_FIFO_EMPTY7 ,FIFO 7 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 6. " PTR_FIFO_EMPTY6 ,FIFO 6 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PTR_FIFO_EMPTY5 ,FIFO 5 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 4. " PTR_FIFO_EMPTY4 ,FIFO 4 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PTR_FIFO_EMPTY3 ,FIFO 3 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 2. " PTR_FIFO_EMPTY2 ,FIFO 2 empty " "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PTR_FIFO_EMPTY1 ,FIFO 1 empty " "Not empty,Empty"
|
|
bitfld.long 0x04 0. " PTR_FIFO_EMPTY0 ,FIFO 0 empty " "Not empty,Empty"
|
|
line.long 0x008 "PFIFO_OVERFLOW,Pointer FIFO Overflow Vector"
|
|
bitfld.long 0x08 31. " PTR_FIFO_OVER31 ,FIFO 31 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 30. " PTR_FIFO_OVER30 ,FIFO 30 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 29. " PTR_FIFO_OVER29 ,FIFO 29 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 28. " PTR_FIFO_OVER28 ,FIFO 28 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 27. " PTR_FIFO_OVER27 ,FIFO 27 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 26. " PTR_FIFO_OVER26 ,FIFO 26 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 25. " PTR_FIFO_OVER25 ,FIFO 25 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 24. " PTR_FIFO_OVER24 ,FIFO 24 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 23. " PTR_FIFO_OVER23 ,FIFO 23 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 22. " PTR_FIFO_OVER22 ,FIFO 22 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 21. " PTR_FIFO_OVER21 ,FIFO 21 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 20. " PTR_FIFO_OVER20 ,FIFO 20 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PTR_FIFO_OVER19 ,FIFO 19 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 18. " PTR_FIFO_OVER18 ,FIFO 18 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 17. " PTR_FIFO_OVER17 ,FIFO 17 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 16. " PTR_FIFO_OVER16 ,FIFO 16 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 15. " PTR_FIFO_OVER15 ,FIFO 15 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 14. " PTR_FIFO_OVER14 ,FIFO 14 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 13. " PTR_FIFO_OVER13 ,FIFO 13 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 12. " PTR_FIFO_OVER12 ,FIFO 12 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 11. " PTR_FIFO_OVER11 ,FIFO 11 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 10. " PTR_FIFO_OVER10 ,FIFO 10 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 9. " PTR_FIFO_OVER9 ,FIFO 9 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 8. " PTR_FIFO_OVER8 ,FIFO 8 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 7. " PTR_FIFO_OVER7 ,FIFO 7 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 6. " PTR_FIFO_OVER6 ,FIFO 6 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 5. " PTR_FIFO_OVER5 ,FIFO 5 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 4. " PTR_FIFO_OVER4 ,FIFO 4 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PTR_FIFO_OVER3 ,FIFO 3 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 2. " PTR_FIFO_OVER2 ,FIFO 2 overflow" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PTR_FIFO_OVER1 ,FIFO 1 overflow" "Not occurred,Occurred"
|
|
bitfld.long 0x08 0. " PTR_FIFO_OVER0 ,FIFO 0 overflow" "Not occurred,Occurred"
|
|
line.long 0x0C "PFIFO_UNDERRUN,Pointer FIFO Under Run Vector"
|
|
bitfld.long 0x0C 31. " PTR_FIFO_UNDER31 ,FIFO 31 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 30. " PTR_FIFO_UNDER30 ,FIFO 30 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " PTR_FIFO_UNDER29 ,FIFO 29 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " PTR_FIFO_UNDER28 ,FIFO 28 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " PTR_FIFO_UNDER27 ,FIFO 27 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " PTR_FIFO_UNDER26 ,FIFO 26 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " PTR_FIFO_UNDER25 ,FIFO 25 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " PTR_FIFO_UNDER24 ,FIFO 24 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " PTR_FIFO_UNDER23 ,FIFO 23 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " PTR_FIFO_UNDER22 ,FIFO 22 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " PTR_FIFO_UNDER21 ,FIFO 21 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " PTR_FIFO_UNDER20 ,FIFO 20 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " PTR_FIFO_UNDER19 ,FIFO 19 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " PTR_FIFO_UNDER18 ,FIFO 18 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " PTR_FIFO_UNDER17 ,FIFO 17 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " PTR_FIFO_UNDER16 ,FIFO 16 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " PTR_FIFO_UNDER15 ,FIFO 15 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " PTR_FIFO_UNDER14 ,FIFO 14 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " PTR_FIFO_UNDER13 ,FIFO 13 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " PTR_FIFO_UNDER12 ,FIFO 12 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " PTR_FIFO_UNDER11 ,FIFO 11 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " PTR_FIFO_UNDER10 ,FIFO 10 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " PTR_FIFO_UNDER9 ,FIFO 9 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " PTR_FIFO_UNDER8 ,FIFO 8 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " PTR_FIFO_UNDER7 ,FIFO 7 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " PTR_FIFO_UNDER6 ,FIFO 6 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " PTR_FIFO_UNDER5 ,FIFO 5 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " PTR_FIFO_UNDER4 ,FIFO 4 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " PTR_FIFO_UNDER3 ,FIFO 3 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " PTR_FIFO_UNDER2 ,FIFO 2 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PTR_FIFO_UNDER1 ,FIFO 1 under run" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " PTR_FIFO_UNDER0 ,FIFO 0 under run" "Not occurred,Occurred"
|
|
tree.end
|
|
tree "PFIFO_FILL_LEVEL_BASE0-31 (Pointer FIFO Fill Level 0-31)"
|
|
width 25.
|
|
rgroup.long 0x180++0x07F
|
|
sif (cpu()=="NETX51")
|
|
line.long 0x00 "PFIFO_FILL_LEVEL_BASE0,Pointer FIFO Fill Level 0"
|
|
hexmask.long.word 0x00 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x4 "PFIFO_FILL_LEVEL_BASE1 ,Pointer FIFO Fill Level 1 "
|
|
line.long 0x8 "PFIFO_FILL_LEVEL_BASE2 ,Pointer FIFO Fill Level 2 "
|
|
line.long 0xC "PFIFO_FILL_LEVEL_BASE3 ,Pointer FIFO Fill Level 3 "
|
|
line.long 0x10 "PFIFO_FILL_LEVEL_BASE4 ,Pointer FIFO Fill Level 4 "
|
|
line.long 0x14 "PFIFO_FILL_LEVEL_BASE5 ,Pointer FIFO Fill Level 5 "
|
|
line.long 0x18 "PFIFO_FILL_LEVEL_BASE6 ,Pointer FIFO Fill Level 6 "
|
|
line.long 0x1C "PFIFO_FILL_LEVEL_BASE7 ,Pointer FIFO Fill Level 7 "
|
|
line.long 0x20 "PFIFO_FILL_LEVEL_BASE8 ,Pointer FIFO Fill Level 8 "
|
|
line.long 0x24 "PFIFO_FILL_LEVEL_BASE9 ,Pointer FIFO Fill Level 9 "
|
|
line.long 0x28 "PFIFO_FILL_LEVEL_BASE10,Pointer FIFO Fill Level 10"
|
|
line.long 0x2C "PFIFO_FILL_LEVEL_BASE11,Pointer FIFO Fill Level 11"
|
|
line.long 0x30 "PFIFO_FILL_LEVEL_BASE12,Pointer FIFO Fill Level 12"
|
|
line.long 0x34 "PFIFO_FILL_LEVEL_BASE13,Pointer FIFO Fill Level 13"
|
|
line.long 0x38 "PFIFO_FILL_LEVEL_BASE14,Pointer FIFO Fill Level 14"
|
|
line.long 0x3C "PFIFO_FILL_LEVEL_BASE15,Pointer FIFO Fill Level 15"
|
|
line.long 0x40 "PFIFO_FILL_LEVEL_BASE16,Pointer FIFO Fill Level 16"
|
|
line.long 0x44 "PFIFO_FILL_LEVEL_BASE17,Pointer FIFO Fill Level 17"
|
|
line.long 0x48 "PFIFO_FILL_LEVEL_BASE18,Pointer FIFO Fill Level 18"
|
|
line.long 0x4C "PFIFO_FILL_LEVEL_BASE19,Pointer FIFO Fill Level 19"
|
|
line.long 0x50 "PFIFO_FILL_LEVEL_BASE20,Pointer FIFO Fill Level 20"
|
|
line.long 0x54 "PFIFO_FILL_LEVEL_BASE21,Pointer FIFO Fill Level 21"
|
|
line.long 0x58 "PFIFO_FILL_LEVEL_BASE22,Pointer FIFO Fill Level 22"
|
|
line.long 0x5C "PFIFO_FILL_LEVEL_BASE23,Pointer FIFO Fill Level 23"
|
|
line.long 0x60 "PFIFO_FILL_LEVEL_BASE24,Pointer FIFO Fill Level 24"
|
|
line.long 0x64 "PFIFO_FILL_LEVEL_BASE25,Pointer FIFO Fill Level 25"
|
|
line.long 0x68 "PFIFO_FILL_LEVEL_BASE26,Pointer FIFO Fill Level 26"
|
|
line.long 0x6C "PFIFO_FILL_LEVEL_BASE27,Pointer FIFO Fill Level 27"
|
|
line.long 0x70 "PFIFO_FILL_LEVEL_BASE28,Pointer FIFO Fill Level 28"
|
|
line.long 0x74 "PFIFO_FILL_LEVEL_BASE29,Pointer FIFO Fill Level 29"
|
|
line.long 0x78 "PFIFO_FILL_LEVEL_BASE30,Pointer FIFO Fill Level 30"
|
|
line.long 0x7C "PFIFO_FILL_LEVEL_BASE31,Pointer FIFO Fill Level 31"
|
|
else
|
|
line.long 0x0 "PFIFO_FILL_LEVEL_BASE0 ,Pointer FIFO Fill Level 0 "
|
|
hexmask.long.word 0x0 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x4 "PFIFO_FILL_LEVEL_BASE1 ,Pointer FIFO Fill Level 1 "
|
|
hexmask.long.word 0x4 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x8 "PFIFO_FILL_LEVEL_BASE2 ,Pointer FIFO Fill Level 2 "
|
|
hexmask.long.word 0x8 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0xC "PFIFO_FILL_LEVEL_BASE3 ,Pointer FIFO Fill Level 3 "
|
|
hexmask.long.word 0xC 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x10 "PFIFO_FILL_LEVEL_BASE4 ,Pointer FIFO Fill Level 4 "
|
|
hexmask.long.word 0x10 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x14 "PFIFO_FILL_LEVEL_BASE5 ,Pointer FIFO Fill Level 5 "
|
|
hexmask.long.word 0x14 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x18 "PFIFO_FILL_LEVEL_BASE6 ,Pointer FIFO Fill Level 6 "
|
|
hexmask.long.word 0x18 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x1C "PFIFO_FILL_LEVEL_BASE7 ,Pointer FIFO Fill Level 7 "
|
|
hexmask.long.word 0x1C 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x20 "PFIFO_FILL_LEVEL_BASE8 ,Pointer FIFO Fill Level 8 "
|
|
hexmask.long.word 0x20 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x24 "PFIFO_FILL_LEVEL_BASE9 ,Pointer FIFO Fill Level 9 "
|
|
hexmask.long.word 0x24 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x28 "PFIFO_FILL_LEVEL_BASE10,Pointer FIFO Fill Level 10"
|
|
hexmask.long.word 0x28 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x2C "PFIFO_FILL_LEVEL_BASE11,Pointer FIFO Fill Level 11"
|
|
hexmask.long.word 0x2C 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x30 "PFIFO_FILL_LEVEL_BASE12,Pointer FIFO Fill Level 12"
|
|
hexmask.long.word 0x30 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x34 "PFIFO_FILL_LEVEL_BASE13,Pointer FIFO Fill Level 13"
|
|
hexmask.long.word 0x34 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x38 "PFIFO_FILL_LEVEL_BASE14,Pointer FIFO Fill Level 14"
|
|
hexmask.long.word 0x38 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x3C "PFIFO_FILL_LEVEL_BASE15,Pointer FIFO Fill Level 15"
|
|
hexmask.long.word 0x3C 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x40 "PFIFO_FILL_LEVEL_BASE16,Pointer FIFO Fill Level 16"
|
|
hexmask.long.word 0x40 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x44 "PFIFO_FILL_LEVEL_BASE17,Pointer FIFO Fill Level 17"
|
|
hexmask.long.word 0x44 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x48 "PFIFO_FILL_LEVEL_BASE18,Pointer FIFO Fill Level 18"
|
|
hexmask.long.word 0x48 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x4C "PFIFO_FILL_LEVEL_BASE19,Pointer FIFO Fill Level 19"
|
|
hexmask.long.word 0x4C 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x50 "PFIFO_FILL_LEVEL_BASE20,Pointer FIFO Fill Level 20"
|
|
hexmask.long.word 0x50 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x54 "PFIFO_FILL_LEVEL_BASE21,Pointer FIFO Fill Level 21"
|
|
hexmask.long.word 0x54 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x58 "PFIFO_FILL_LEVEL_BASE22,Pointer FIFO Fill Level 22"
|
|
hexmask.long.word 0x58 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x5C "PFIFO_FILL_LEVEL_BASE23,Pointer FIFO Fill Level 23"
|
|
hexmask.long.word 0x5C 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x60 "PFIFO_FILL_LEVEL_BASE24,Pointer FIFO Fill Level 24"
|
|
hexmask.long.word 0x60 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x64 "PFIFO_FILL_LEVEL_BASE25,Pointer FIFO Fill Level 25"
|
|
hexmask.long.word 0x64 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x68 "PFIFO_FILL_LEVEL_BASE26,Pointer FIFO Fill Level 26"
|
|
hexmask.long.word 0x68 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x6C "PFIFO_FILL_LEVEL_BASE27,Pointer FIFO Fill Level 27"
|
|
hexmask.long.word 0x6C 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x70 "PFIFO_FILL_LEVEL_BASE28,Pointer FIFO Fill Level 28"
|
|
hexmask.long.word 0x70 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x74 "PFIFO_FILL_LEVEL_BASE29,Pointer FIFO Fill Level 29"
|
|
hexmask.long.word 0x74 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x78 "PFIFO_FILL_LEVEL_BASE30,Pointer FIFO Fill Level 30"
|
|
hexmask.long.word 0x78 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
line.long 0x7C "PFIFO_FILL_LEVEL_BASE31,Pointer FIFO Fill Level 31"
|
|
hexmask.long.word 0x7C 0.--10. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRC (Configurable CRC-Generator)"
|
|
base ad:0x00101000
|
|
width 0x10
|
|
group.long 0x00++0x0F
|
|
sif ((cpu()=="NETX51")||(cpu()=="NETX50")||(cpu()=="NETX100"))
|
|
line.long 0x00 "CRC_VAL,CRC Register"
|
|
line.long 0x04 "CRC_IN_DATA,CRC Input Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CRC_IN_DATA ,CRC input data"
|
|
else
|
|
line.long 0x00 "CRC_CRC,CRC Register"
|
|
line.long 0x04 "CRC_DATA,CRC Input Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CRC_INPUT ,CRC input data"
|
|
endif
|
|
line.long 0x08 "CRC_POLYNOMIAL,CRC Polynomial Register"
|
|
line.long 0x0C "CRC_CONFIG,CRC Configuration Register"
|
|
bitfld.long 0x0C 10. " CRC_IN_MSB_LOW ,Swap crc_data_in" "MSB,LSB"
|
|
bitfld.long 0x0C 8.--9. " CRC_NOF_BITS ,Number of bits to be calculated in parallel" "1 bit,2 bits,4 bits,8 bits"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CRC_DIRECT_DIV ,Calculate direct polynomial division" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " CRC_SHIFT_DIV ,Shift CRC" "Left,Right"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--5. 1. " CRC_LEN ,Length of CRC Polynom - 1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ARM_to_XPEC_IRQ (IRQs between XPEC and ARM Registers)"
|
|
base ad:0x00164400
|
|
width 0x0B
|
|
sif (cpu()=="NETX50")
|
|
group.long 0x00++0x07
|
|
line.long 0x0 "IRQ_XPEC0,IRQs between XPEC0 and ARM Registers"
|
|
hexmask.long.word 0x0 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
|
|
hexmask.long.word 0x0 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
|
|
line.long 0x4 "IRQ_XPEC1,IRQs between XPEC1 and ARM Registers"
|
|
hexmask.long.word 0x4 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
|
|
hexmask.long.word 0x4 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x0 "IRQ_XPEC0,IRQs between XPEC0 and ARM Registers"
|
|
hexmask.long.word 0x0 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
|
|
hexmask.long.word 0x0 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
|
|
line.long 0x4 "IRQ_XPEC1,IRQs between XPEC1 and ARM Registers"
|
|
hexmask.long.word 0x4 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
|
|
hexmask.long.word 0x4 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
|
|
line.long 0x8 "IRQ_XPEC2,IRQs between XPEC2 and ARM Registers"
|
|
hexmask.long.word 0x8 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
|
|
hexmask.long.word 0x8 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
|
|
line.long 0xC "IRQ_XPEC3,IRQs between XPEC3 and ARM Registers"
|
|
hexmask.long.word 0xC 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
|
|
hexmask.long.word 0xC 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
textline ""
|