7680 lines
379 KiB
Plaintext
7680 lines
379 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: BAT32G On-Chip Peripherals
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; @Props: Released
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; @Author: KRZ
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; @Changelog: 2025-01-31 KRZ
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; @Manufacturer: CMSEMICON - China Micro Semicon Co., Ltd.
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; @Doc: Generated (TRACE32, build: 176288.), based on:
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; BAT32G137.svd (Ver. 1.2), BAT32G157.svd (Ver. 1.0),
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; BAT32G139.svd (Ver. 1.0), BAT32G179.svd (Ver. 1.0)
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; @Core: Cortex-M0+
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; @Chip: BAT32G137GH32FP, BAT32G137GH40NB, BAT32G137GH48FA, BAT32G137GH64FB,
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; BAT32G139GK48FA, BAT32G139GK64FB, BAT32G139GK80FA, BAT32G157GK48FA,
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; BAT32G157GK48NB, BAT32G157GK64FB, BAT32G179GM100FA, BAT32G179GM64FB,
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; BAT32G179GM80FA
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; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; ARM Limited (ARM) is supplying this software for use with Cortex-M\n
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; processor based microcontroller, but can be equally used for other\n
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; suitable processor architectures. This file can be freely distributed.\n
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; Modifications to this file shall be clearly marked.\n
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; \n
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; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
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; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
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; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
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; ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
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; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; --------------------------------------------------------------------------------
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; $Id: perbat32g.per 18937 2025-01-31 16:56:20Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC21=Cortex-M1"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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elif (CORENAME()=="CORTEXM0+")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC60=Cortex-M0+"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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else
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC20=Cortex-M0"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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endif
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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|
else
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|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
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group.long 0xD9C++0x03 "Region 2"
|
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (A/D Converter)"
|
|
base ad:0x40045000
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "ADM0,A/D mode register 0"
|
|
bitfld.byte 0x0 7. "ADCS,A/D conversion operation control" "0,1"
|
|
bitfld.byte 0x0 3.--5. "FR,A/D conversion clock (fAD) select" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x0 0. "ADCE,A/D enable" "0,1"
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "ADM1,A/D mode register 1"
|
|
bitfld.byte 0x0 7. "ADMD,A/D conversion channel select mode" "0: Select mode,1: Scan mode"
|
|
bitfld.byte 0x0 3. "ADSCM,A/D conversion mode" "0: Sequential conversion mode,1: One-shot conversion mode"
|
|
bitfld.byte 0x0 0.--1. "ADMODE,A/D mode select" "0,1,2,3"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "ADM2,A/D mode register 2"
|
|
bitfld.byte 0x0 6.--7. "ADREFP,Selection of the + side reference voltage of A/D converter" "0: Supplied from inside AVREF of A/D,?,?,?"
|
|
bitfld.byte 0x0 5. "ADREFM,Selection of the - side reference voltage of A/D converter" "0: Supplied from VSS,1: Supplied from AVREFM"
|
|
bitfld.byte 0x0 3. "ADRCK,the upper limit and lower limit conversion result values" "0,1"
|
|
bitfld.byte 0x0 1. "CHRDE,output CH number in A/D conversion result in Scan mode" "0,1"
|
|
group.byte 0x6++0x0
|
|
line.byte 0x0 "ADTRG,A/D mode register 2"
|
|
bitfld.byte 0x0 6.--7. "ADTMD,A/D conversion trigger mode" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "ADTRS,A/D hard trigger select" "0,1,2,3"
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "ADS,Analog input channel specification register"
|
|
sif (cpuis("BAT32G139*"))
|
|
bitfld.byte 0x0 7. "ADISS,Selection of ADC channel" "0,1"
|
|
bitfld.byte 0x0 6. "ADCHPGA1,Selection of channel n for PGA1" "0,1"
|
|
bitfld.byte 0x0 5. "ADCHPGA0,Selection of channel n for PGA0" "0,1"
|
|
bitfld.byte 0x0 3.--4. "ADSCHn,Select ADC channel n" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
bitfld.byte 0x0 7. "ADISS,Selection of ADC channel" "0,1"
|
|
bitfld.byte 0x0 6. "ADCHPGA1,Selection of channel n for PGA1" "0,1"
|
|
bitfld.byte 0x0 5. "ADCHPGA0,Selection of channel n for PGA0" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "ADSCHn,Select ADC channel n" "0,1,2,3"
|
|
endif
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "ADCR,12-bit A/D conversion result register"
|
|
group.byte 0xF++0x0
|
|
line.byte 0x0 "ADCRH,Higher 8-bit A/D conversion result register"
|
|
group.byte 0xB++0x0
|
|
line.byte 0x0 "ADUL,Conversion result comparison upper limit setting register"
|
|
group.byte 0xA++0x0
|
|
line.byte 0x0 "ADLL,Conversion result comparison lower limit setting register"
|
|
group.byte 0x10++0x0
|
|
line.byte 0x0 "ADTES,A/D test register"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "ADFLG,A/D flag register"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "ADNSMP,A/D sampling time control register"
|
|
group.byte 0x15++0x0
|
|
line.byte 0x0 "ADSMPWAIT,A/D sampling wait control register"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x0 "ADNDIS,A/D charge/discharge control register"
|
|
sif (cpuis("BAT32G157*"))
|
|
group.word 0x1E++0x1
|
|
line.word 0x0 "PGA0SH,PGA 0 sample and hold function register"
|
|
bitfld.word 0x0 15. "PGA0SHEN,Sample and hold function enable control" "0,1"
|
|
hexmask.word 0x0 0.--9. 1. "PGA0SH,Sample and hold time selection"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("BAT32G137*"))
|
|
base ad:0x500660
|
|
elif (cpuis("BAT32G157*"))
|
|
base ad:0x8500C60
|
|
elif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
base ad:0x500C60
|
|
endif
|
|
tree "BGR (Temperature Sensor Calibration Data)"
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "VBG85,The A/D conversion value of VBGR at 85 degrees and 3.0V reference voltage"
|
|
line.long 0x4 "VBG25,The A/D conversion value of VBGR at 25 degrees and 3.0V reference voltage"
|
|
tree.end
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "CAN (CAN Controller)"
|
|
base ad:0x0
|
|
tree "CAN0"
|
|
base ad:0x40045400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CGMCTRL,CAN global module control register"
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "CGMCS,CAN global module clock select register"
|
|
group.word 0x6++0x1
|
|
line.word 0x0 "CGMABT,CAN global automatic block transmission control register"
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "CGMABTD,CAN global automatic block transmission delay setting register"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x40)++0x1
|
|
line.word 0x0 "CMASK1$1,CAN module mask 1 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x44)++0x1
|
|
line.word 0x0 "CMASK2$1,CAN module mask 2 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x48)++0x1
|
|
line.word 0x0 "CMASK3$1,CAN module mask 3 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x4C)++0x1
|
|
line.word 0x0 "CMASK4$1,CAN module mask 4 register"
|
|
repeat.end
|
|
group.word 0x50++0x1
|
|
line.word 0x0 "CCTRL,CAN module control register"
|
|
group.byte 0x52++0x0
|
|
line.byte 0x0 "CLEC,CAN module last error code register"
|
|
rgroup.byte 0x53++0x0
|
|
line.byte 0x0 "CINFO,CAN module information register"
|
|
rgroup.word 0x54++0x1
|
|
line.word 0x0 "CERC,CAN module error counter register"
|
|
group.word 0x56++0x3
|
|
line.word 0x0 "CIE,CAN module interrupt enable register"
|
|
line.word 0x2 "CINTS,CAN module interrupt status register"
|
|
group.byte 0x5A++0x0
|
|
line.byte 0x0 "CBRP,CAN module bit rate prescaler register"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "CBTR,CAN module bit rate register"
|
|
rgroup.byte 0x5E++0x0
|
|
line.byte 0x0 "CLIPT,CAN module last in-pointer register"
|
|
group.word 0x60++0x1
|
|
line.word 0x0 "CRGPT,CAN module receive history list register"
|
|
rgroup.byte 0x62++0x0
|
|
line.byte 0x0 "CLOPT,CAN module last out-pointer register"
|
|
group.word 0x64++0x3
|
|
line.word 0x0 "CTGPT,CAN module transmit history list register"
|
|
line.word 0x2 "CTS,CAN module time stamp register"
|
|
tree.end
|
|
tree "CAN0MSG00"
|
|
base ad:0x40045500
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG01"
|
|
base ad:0x40045510
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG02"
|
|
base ad:0x40045520
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG03"
|
|
base ad:0x40045530
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG04"
|
|
base ad:0x40045540
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG05"
|
|
base ad:0x40045550
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG06"
|
|
base ad:0x40045560
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG07"
|
|
base ad:0x40045570
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG08"
|
|
base ad:0x40045580
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG09"
|
|
base ad:0x40045590
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG10"
|
|
base ad:0x400455A0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG11"
|
|
base ad:0x400455B0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG12"
|
|
base ad:0x400455C0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG13"
|
|
base ad:0x400455D0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG14"
|
|
base ad:0x400455E0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN0MSG15"
|
|
base ad:0x400455F0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
sif (cpuis("BAT32G139*"))
|
|
tree "CAN1"
|
|
base ad:0x40045800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CGMCTRL,CAN global module control register"
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "CGMCS,CAN global module clock select register"
|
|
group.word 0x6++0x1
|
|
line.word 0x0 "CGMABT,CAN global automatic block transmission control register"
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "CGMABTD,CAN global automatic block transmission delay setting register"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x40)++0x1
|
|
line.word 0x0 "CMASK1$1,CAN module mask 1 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x44)++0x1
|
|
line.word 0x0 "CMASK2$1,CAN module mask 2 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x48)++0x1
|
|
line.word 0x0 "CMASK3$1,CAN module mask 3 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x4C)++0x1
|
|
line.word 0x0 "CMASK4$1,CAN module mask 4 register"
|
|
repeat.end
|
|
group.word 0x50++0x1
|
|
line.word 0x0 "CCTRL,CAN module control register"
|
|
group.byte 0x52++0x0
|
|
line.byte 0x0 "CLEC,CAN module last error code register"
|
|
rgroup.byte 0x53++0x0
|
|
line.byte 0x0 "CINFO,CAN module information register"
|
|
rgroup.word 0x54++0x1
|
|
line.word 0x0 "CERC,CAN module error counter register"
|
|
group.word 0x56++0x3
|
|
line.word 0x0 "CIE,CAN module interrupt enable register"
|
|
line.word 0x2 "CINTS,CAN module interrupt status register"
|
|
group.byte 0x5A++0x0
|
|
line.byte 0x0 "CBRP,CAN module bit rate prescaler register"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "CBTR,CAN module bit rate register"
|
|
rgroup.byte 0x5E++0x0
|
|
line.byte 0x0 "CLIPT,CAN module last in-pointer register"
|
|
group.word 0x60++0x1
|
|
line.word 0x0 "CRGPT,CAN module receive history list register"
|
|
rgroup.byte 0x62++0x0
|
|
line.byte 0x0 "CLOPT,CAN module last out-pointer register"
|
|
group.word 0x64++0x3
|
|
line.word 0x0 "CTGPT,CAN module transmit history list register"
|
|
line.word 0x2 "CTS,CAN module time stamp register"
|
|
tree.end
|
|
tree "CAN1MSG00"
|
|
base ad:0x40045900
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG01"
|
|
base ad:0x40045910
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG02"
|
|
base ad:0x40045920
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG03"
|
|
base ad:0x40045930
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG04"
|
|
base ad:0x40045940
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG05"
|
|
base ad:0x40045950
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG06"
|
|
base ad:0x40045960
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG07"
|
|
base ad:0x40045970
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG08"
|
|
base ad:0x40045980
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG09"
|
|
base ad:0x40045990
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG10"
|
|
base ad:0x400459A0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG11"
|
|
base ad:0x400459B0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG12"
|
|
base ad:0x400459C0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG13"
|
|
base ad:0x400459D0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG14"
|
|
base ad:0x400459E0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG15"
|
|
base ad:0x400459F0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
tree "CAN1"
|
|
base ad:0x40045800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CGMCTRL,CAN global module control register"
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "CGMCS,CAN global module clock select register"
|
|
group.word 0x6++0x1
|
|
line.word 0x0 "CGMABT,CAN global automatic block transmission control register"
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "CGMABTD,CAN global automatic block transmission delay setting register"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x40)++0x1
|
|
line.word 0x0 "CMASK1$1,CAN module mask 1 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x44)++0x1
|
|
line.word 0x0 "CMASK2$1,CAN module mask 2 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x48)++0x1
|
|
line.word 0x0 "CMASK3$1,CAN module mask 3 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x4C)++0x1
|
|
line.word 0x0 "CMASK4$1,CAN module mask 4 register"
|
|
repeat.end
|
|
group.word 0x50++0x1
|
|
line.word 0x0 "CCTRL,CAN module control register"
|
|
group.byte 0x52++0x0
|
|
line.byte 0x0 "CLEC,CAN module last error code register"
|
|
rgroup.byte 0x53++0x0
|
|
line.byte 0x0 "CINFO,CAN module information register"
|
|
rgroup.word 0x54++0x1
|
|
line.word 0x0 "CERC,CAN module error counter register"
|
|
group.word 0x56++0x3
|
|
line.word 0x0 "CIE,CAN module interrupt enable register"
|
|
line.word 0x2 "CINTS,CAN module interrupt status register"
|
|
group.byte 0x5A++0x0
|
|
line.byte 0x0 "CBRP,CAN module bit rate prescaler register"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "CBTR,CAN module bit rate register"
|
|
rgroup.byte 0x5E++0x0
|
|
line.byte 0x0 "CLIPT,CAN module last in-pointer register"
|
|
group.word 0x60++0x1
|
|
line.word 0x0 "CRGPT,CAN module receive history list register"
|
|
rgroup.byte 0x62++0x0
|
|
line.byte 0x0 "CLOPT,CAN module last out-pointer register"
|
|
group.word 0x64++0x3
|
|
line.word 0x0 "CTGPT,CAN module transmit history list register"
|
|
line.word 0x2 "CTS,CAN module time stamp register"
|
|
tree.end
|
|
tree "CAN1MSG00"
|
|
base ad:0x40045900
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG01"
|
|
base ad:0x40045910
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG02"
|
|
base ad:0x40045920
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG03"
|
|
base ad:0x40045930
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG04"
|
|
base ad:0x40045940
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG05"
|
|
base ad:0x40045950
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG06"
|
|
base ad:0x40045960
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG07"
|
|
base ad:0x40045970
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG08"
|
|
base ad:0x40045980
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG09"
|
|
base ad:0x40045990
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG10"
|
|
base ad:0x400459A0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG11"
|
|
base ad:0x400459B0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG12"
|
|
base ad:0x400459C0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG13"
|
|
base ad:0x400459D0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG14"
|
|
base ad:0x400459E0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN1MSG15"
|
|
base ad:0x400459F0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2"
|
|
base ad:0x40046400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CGMCTRL,CAN global module control register"
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "CGMCS,CAN global module clock select register"
|
|
group.word 0x6++0x1
|
|
line.word 0x0 "CGMABT,CAN global automatic block transmission control register"
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "CGMABTD,CAN global automatic block transmission delay setting register"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x40)++0x1
|
|
line.word 0x0 "CMASK1$1,CAN module mask 1 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x44)++0x1
|
|
line.word 0x0 "CMASK2$1,CAN module mask 2 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x48)++0x1
|
|
line.word 0x0 "CMASK3$1,CAN module mask 3 register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x4C)++0x1
|
|
line.word 0x0 "CMASK4$1,CAN module mask 4 register"
|
|
repeat.end
|
|
group.word 0x50++0x1
|
|
line.word 0x0 "CCTRL,CAN module control register"
|
|
group.byte 0x52++0x0
|
|
line.byte 0x0 "CLEC,CAN module last error code register"
|
|
rgroup.byte 0x53++0x0
|
|
line.byte 0x0 "CINFO,CAN module information register"
|
|
rgroup.word 0x54++0x1
|
|
line.word 0x0 "CERC,CAN module error counter register"
|
|
group.word 0x56++0x3
|
|
line.word 0x0 "CIE,CAN module interrupt enable register"
|
|
line.word 0x2 "CINTS,CAN module interrupt status register"
|
|
group.byte 0x5A++0x0
|
|
line.byte 0x0 "CBRP,CAN module bit rate prescaler register"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "CBTR,CAN module bit rate register"
|
|
rgroup.byte 0x5E++0x0
|
|
line.byte 0x0 "CLIPT,CAN module last in-pointer register"
|
|
group.word 0x60++0x1
|
|
line.word 0x0 "CRGPT,CAN module receive history list register"
|
|
rgroup.byte 0x62++0x0
|
|
line.byte 0x0 "CLOPT,CAN module last out-pointer register"
|
|
group.word 0x64++0x3
|
|
line.word 0x0 "CTGPT,CAN module transmit history list register"
|
|
line.word 0x2 "CTS,CAN module time stamp register"
|
|
tree.end
|
|
tree "CAN2MSG00"
|
|
base ad:0x40046500
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG01"
|
|
base ad:0x40046510
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG02"
|
|
base ad:0x40046520
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG03"
|
|
base ad:0x40046530
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG04"
|
|
base ad:0x40046540
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG05"
|
|
base ad:0x40046550
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG06"
|
|
base ad:0x40046560
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG07"
|
|
base ad:0x40046570
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG08"
|
|
base ad:0x40046580
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG09"
|
|
base ad:0x40046590
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG10"
|
|
base ad:0x400465A0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG11"
|
|
base ad:0x400465B0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG12"
|
|
base ad:0x400465C0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG13"
|
|
base ad:0x400465D0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG14"
|
|
base ad:0x400465E0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
tree "CAN2MSG15"
|
|
base ad:0x400465F0
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "CMDB$1,CAN message data byte %s register"
|
|
repeat.end
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CMDLC,CAN message data length register"
|
|
line.byte 0x1 "CMCONF,CAN message configuration register"
|
|
group.word 0xA++0x5
|
|
line.word 0x0 "CMIDL,CAN message ID register"
|
|
line.word 0x2 "CMIDH,CAN message ID register"
|
|
line.word 0x4 "CMCTRL,CAN message control register"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "CGC (Clock Generate Control)"
|
|
base ad:0x40020400
|
|
group.byte 0x0++0x1
|
|
line.byte 0x0 "CMC,Clock operaton Mode Control Register"
|
|
bitfld.byte 0x0 7. "EXCLK,External Clock input mode" "0,1"
|
|
bitfld.byte 0x0 6. "OSCSEL,Main OSC Select" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "EXCLKS,External Clock input mode" "0,1"
|
|
bitfld.byte 0x0 4. "OSCSELS,Sub OSC Select" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1.--2. "AMPHS,Control of XT1 clock oscillation frequency" "0,1,2,3"
|
|
bitfld.byte 0x0 0. "AMPH,Control of X1 clock oscillation frequency" "0,1"
|
|
line.byte 0x1 "CSC,Clock operation Status Register"
|
|
bitfld.byte 0x1 7. "MSTOP,High-speed system clock operation control" "0: X1 oscillator operating or External clock from..,1: X1 oscillator stop or External clock from EXCLK.."
|
|
bitfld.byte 0x1 6. "XTSTOP,Subsystem clock operation control" "0: XT1 oscillator operating or External clock from..,1: XT1 oscillator stop or External clock from.."
|
|
newline
|
|
bitfld.byte 0x1 0. "HIOSTOP,High-speed on-chip oscillator clock operation control" "0: High-speed on-chip oscillator operating,1: High-speed on-chip oscillator stopped"
|
|
rgroup.byte 0x2++0x0
|
|
line.byte 0x0 "OSTC,Oscillation stabilization time counter status"
|
|
group.byte 0x3++0x1
|
|
line.byte 0x0 "OSTS,Oscillation stabilization time select register"
|
|
line.byte 0x1 "CKC,System clock control register"
|
|
rbitfld.byte 0x1 7. "CLS,Status of CPU/peripheral hardware clock (fCLK)" "0: Main system clock (fMAIN),1: Subsystem clock (fSUB)"
|
|
bitfld.byte 0x1 6. "CSS,Selection of CPU/peripheral hardware clock (fCLK)" "0: Main system clock (fMAIN),1: Subsystem clock (fSUB)"
|
|
newline
|
|
rbitfld.byte 0x1 5. "MCS,Status of Main system clock (fMAIN)" "0: High-speed on-chip oscillator clock (fIH),1: High-speed system clock (fMX)"
|
|
bitfld.byte 0x1 4. "MCM0,Main system clock (fMAIN) operation control" "0: Select the high-speed on-chip oscillator clock..,1: Select the high-speed system clock (fMX) as the.."
|
|
sif (cpuis("BAT32G137*"))
|
|
group.byte 0x5++0x1
|
|
line.byte 0x0 "LOCKCTL,Lockup Watchdog timer enable register"
|
|
line.byte 0x1 "PRCR,Lockup Watchdog timer enable protect register"
|
|
group.byte 0x8++0x3
|
|
line.byte 0x0 "WDTCFG0,WDT Configeration 0 register"
|
|
line.byte 0x1 "WDTCFG1,WDT Configeration 1 register"
|
|
line.byte 0x2 "WDTCFG2,WDT Configeration 2 register"
|
|
line.byte 0x3 "WDTCFG3,WDT Configeration 3 register"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
group.byte 0x5++0x6
|
|
line.byte 0x0 "LOCKCTL,Lockup Watchdog timer enable register"
|
|
line.byte 0x1 "PRCR,Lockup Watchdog timer enable protect register"
|
|
line.byte 0x2 "SUBCKSEL,Subsystem Clock select register"
|
|
bitfld.byte 0x2 1. "LOCOSEL,SUBOSC speed select" "0: Select 15k for SUBOSC clock,1: Select 30k for SUBOSC clock"
|
|
bitfld.byte 0x2 0. "SELLOSC,Select LOSC or SUBOSC" "0: Select SUBOSC as the SubSystem clock,1: Select LOSC as the SubSystem clock"
|
|
line.byte 0x3 "WDTCFG0,WDT Configeration 0 register"
|
|
line.byte 0x4 "WDTCFG1,WDT Configeration 1 register"
|
|
line.byte 0x5 "WDTCFG2,WDT Configeration 2 register"
|
|
line.byte 0x6 "WDTCFG3,WDT Configeration 3 register"
|
|
group.byte 0x41B++0x0
|
|
line.byte 0x0 "PER2,Peripheral enable register 2"
|
|
bitfld.byte 0x0 4. "OSDCEN,Control of the oscillator stop detection input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 3. "SCI2EN,Control of the SCI2 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 2. "IICA1EN,Control of the IICA1 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 1. "CAN1EN,Control of the CAN1 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 0. "TM81EN,Control of the TM8 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
group.byte 0x800++0x0
|
|
line.byte 0x0 "MCKC,Main system clock control register"
|
|
rbitfld.byte 0x0 7. "CKSTR,Status of Main system clock (fMAIN)" "0: High-speed on-chip oscillator clock (fIH),1: PLL clock (fPLL)"
|
|
bitfld.byte 0x0 1.--2. "PDIV,PLL frequency select register" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x0 0. "CKSELR,Select f(IH) or f(PLL)" "0: Select the high-speed on-chip oscillator clock..,1: Select the PLL clock (fPLL) as the main system.."
|
|
group.byte 0x802++0x0
|
|
line.byte 0x0 "PLLCR,System PLL clock control register"
|
|
rbitfld.byte 0x0 7. "PLLSRSEL,PLL input clock source select" "0: Select the high-speed on-chip oscillator clock..,1: Select external main system clock f(MX) as PLL.."
|
|
bitfld.byte 0x0 2.--3. "PLLD,PLL frequency division ratio select" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x0 1. "PLLM,PLL frequency multiplication factor select" "0: PLL multiplication factor is 12,1: PLL multiplication factor is 16"
|
|
bitfld.byte 0x0 0. "PLLON,PLL operation control" "0: PLL is stopped,1: PLL is operating"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
group.byte 0x5++0x6
|
|
line.byte 0x0 "LOCKCTL,Lockup Watchdog timer enable register"
|
|
line.byte 0x1 "PRCR,Lockup Watchdog timer enable protect register"
|
|
line.byte 0x2 "SUBCKSEL,Subsystem Clock select register"
|
|
bitfld.byte 0x2 1. "LOCOSEL,SUBOSC speed select" "0: Select 15k for SUBOSC clock,1: Select 30k for SUBOSC clock"
|
|
bitfld.byte 0x2 0. "SELLOSC,Select LOSC or SUBOSC" "0: Select SUBOSC as the SubSystem clock,1: Select LOSC as the SubSystem clock"
|
|
line.byte 0x3 "WDTCFG0,WDT Configeration 0 register"
|
|
line.byte 0x4 "WDTCFG1,WDT Configeration 1 register"
|
|
line.byte 0x5 "WDTCFG2,WDT Configeration 2 register"
|
|
line.byte 0x6 "WDTCFG3,WDT Configeration 3 register"
|
|
group.byte 0x41B++0x1
|
|
line.byte 0x0 "PER2,Peripheral enable register 2"
|
|
bitfld.byte 0x0 7. "SPIHS1EN,Control of the SPIHS1 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 6. "SPIHS0EN,Control of the SPIHS0 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 5. "CAN2EN,Control of the CAN2 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 4. "OSDCEN,Control of the oscillator stop detection input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 3. "SCI2EN,Control of the SCI2 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 2. "IICA1EN,Control of the IICA1 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 1. "CAN1EN,Control of the CAN1 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 0. "TM81EN,Control of the TM8 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
line.byte 0x1 "PER3,Peripheral enable register 2"
|
|
bitfld.byte 0x1 0. "LCDBEN,Control of the LCDB input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
group.byte 0x800++0x0
|
|
line.byte 0x0 "MCKC,Main system clock control register"
|
|
rbitfld.byte 0x0 7. "CKSTR,Status of Main system clock (fMAIN)" "0: High-speed on-chip oscillator clock (fIH),1: PLL clock (fPLL)"
|
|
bitfld.byte 0x0 1.--2. "PDIV,PLL frequency select register" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x0 0. "CKSELR,Select f(IH) or f(PLL)" "0: Select the high-speed on-chip oscillator clock..,1: Select the PLL clock (fPLL) as the main system.."
|
|
group.byte 0x802++0x0
|
|
line.byte 0x0 "PLLCR,System PLL clock control register"
|
|
rbitfld.byte 0x0 7. "PLLSRSEL,PLL input clock source select" "0: Select the high-speed on-chip oscillator clock..,1: Select external main system clock f(MX) as PLL.."
|
|
bitfld.byte 0x0 2.--3. "PLLD,PLL frequency division ratio select" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x0 1. "PLLM,PLL frequency multiplication factor select" "0: PLL multiplication factor is 12,1: PLL multiplication factor is 16"
|
|
bitfld.byte 0x0 0. "PLLON,PLL operation control" "0: PLL is stopped,1: PLL is operating"
|
|
group.word 0x1E00++0x3
|
|
line.word 0x0 "SCMCTL,Oscillator stop detection control register"
|
|
bitfld.word 0x0 15. "OSCDEN,Oscillator stop detection control register" "0: Oscillator stop detection stop,1: Oscillator stop detection start"
|
|
hexmask.word 0x0 0.--11. 1. "OSDCCMP,Oscillator stop detected time register"
|
|
line.word 0x2 "SCMMD,Oscillator stop detection mode register"
|
|
bitfld.word 0x2 1. "MDSEL,Oscillator stop detected operation selection register" "0: Interrupt when oscillator stop detection,1: Reset when oscillator stop detection"
|
|
bitfld.word 0x2 0. "CKSEL,Oscillator stop detected object selection register" "0: fMX Oscillator stop detection,1: fSX Oscillator stop detection"
|
|
group.byte 0x1E04++0x0
|
|
line.byte 0x0 "SCMST,Oscillator stop detected status register"
|
|
bitfld.byte 0x0 0. "OSTDF,Oscillator stop detected flag register" "0: Oscillator stop NOT detection,1: Oscillator stop detection"
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
group.byte 0x7++0x0
|
|
line.byte 0x0 "SUBCKSEL,Subsystem Clock select register"
|
|
bitfld.byte 0x0 0. "SELLOSC,Select LOSC or SUBOSC" "0: Select SUBOSC as the SubSystem clock,1: Select LOSC as the SubSystem clock"
|
|
group.byte 0x800++0x0
|
|
line.byte 0x0 "MCKC,Main system clock control register"
|
|
rbitfld.byte 0x0 7. "CKSTR,Status of Main system clock (fMAIN)" "0: High-speed on-chip oscillator clock (fIH),1: PLL clock (fPLL)"
|
|
bitfld.byte 0x0 1.--2. "PDIV,PLL frequency select register" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x0 0. "CKSELR,Select f(IH) or f(PLL)" "0: Select the high-speed on-chip oscillator clock..,1: Select the PLL clock (fPLL) as the main system.."
|
|
group.byte 0x802++0x1
|
|
line.byte 0x0 "PLLCR,System PLL clock control register"
|
|
rbitfld.byte 0x0 7. "PLLSRSEL,PLL input clock source select" "0: Select the high-speed on-chip oscillator clock..,1: Select external main system clock f(MX) as PLL.."
|
|
bitfld.byte 0x0 2.--3. "PLLD,PLL frequency division ratio select" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x0 1. "PLLM,PLL frequency multiplication factor select" "0: PLL multiplication factor is 12,1: PLL multiplication factor is 16"
|
|
bitfld.byte 0x0 0. "PLLON,PLL operation control" "0: PLL is stopped,1: PLL is operating"
|
|
line.byte 0x1 "UPLLCR,USB-dedicated system PLL clock control register"
|
|
rbitfld.byte 0x1 7. "UPLLSRSEL,USB-dedicated PLL input clock source select" "0: Select the high-speed on-chip oscillator clock..,1: Select external main system clock f(MX) as UPLL.."
|
|
bitfld.byte 0x1 2.--3. "UPLLD,USB-dedicated PLL frequency division ratio select" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x1 1. "UPLLM,USB-dedicated PLL frequency multiplication factor select" "0: UPLL multiplication factor is 12,1: UPLL multiplication factor is 16"
|
|
bitfld.byte 0x1 0. "UPLLON,USB-dedicated PLL operation control" "0: UPLL is stopped,1: UPLL is operating"
|
|
endif
|
|
group.byte 0x20++0x0
|
|
line.byte 0x0 "PER0,Peripheral enable register 0"
|
|
bitfld.byte 0x0 7. "RTCEN,Control of the RTC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
sif (cpuis("BAT32G137*"))
|
|
bitfld.byte 0x0 6. "IRDAEN,Control of the IRDA input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 5. "ADCEN,Control of the ADC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 4. "IICA0EN,Control of the IICA0 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 1. "CAN0EN,Control of the CAN input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
bitfld.byte 0x0 6. "IICA1EN,Control of the IICA1 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 5. "IICA0EN,Control of the IICA0 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 4. "SCI2EN,Control of the SCI2 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
bitfld.byte 0x0 6. "IRDAEN,Control of the IRDA input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 5. "ADCEN,Control of the ADC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 4. "IICA0EN,Control of the IICA0 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
bitfld.byte 0x0 5. "ADCEN,Control of the ADC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 4. "IICA0EN,Control of the IICA0 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
endif
|
|
bitfld.byte 0x0 3. "SCI1EN,Control of the SCI1 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 2. "SCI0EN,Control of the SCI0 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
sif (cpuis("BAT32G157*"))
|
|
bitfld.byte 0x0 1. "TM81EN,Control of the TM8 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
bitfld.byte 0x0 1. "CAN0EN,Control of the CAN0 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
bitfld.byte 0x0 1. "CAN0EN,Control of the CAN0 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x0 0. "TM40EN,Control of the TM4 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
group.byte 0x41A++0x0
|
|
line.byte 0x0 "PER1,Peripheral enable register 1"
|
|
sif (cpuis("BAT32G137*"))
|
|
bitfld.byte 0x0 7. "DACEN,Control of the DAC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 6. "TMBEN,Control of the TMB input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 4. "TMMEN,Control of the TMM input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 2. "PWMOPEN,Control of the PWMOP input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 1. "TMCEN,Control of the TMC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 0. "TMAEN,Control of the TMA input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
bitfld.byte 0x0 7. "SPIHS1EN,Control of the SPIHS1 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 6. "SPIHS0EN,Control of the SPIHS0 input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
bitfld.byte 0x0 7. "DACEN,Control of the DAC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 6. "TMBEN,Control of the TMB input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
bitfld.byte 0x0 7. "DACEN,Control of the DAC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 6. "TMBEN,Control of the TMB input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x0 5. "PGACMPEN,Control of the PGACMP input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
sif (cpuis("BAT32G139*"))
|
|
bitfld.byte 0x0 4. "TMMEN,Control of the TMM input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
bitfld.byte 0x0 4. "TMMEN,Control of the TMM input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
endif
|
|
bitfld.byte 0x0 3. "DMAEN,Control of the DMA input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
sif (cpuis("BAT32G157*"))
|
|
bitfld.byte 0x0 2. "EPWMEN,Control of the EPWM input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 1. "LCDBEN,Control of the LCDB input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 0. "ADCEN,Control of the ADC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
bitfld.byte 0x0 2. "PWMOPEN,Control of the PWMOP input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 1. "TMCEN,Control of the TMC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 0. "TMAEN,Control of the TMA input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
bitfld.byte 0x0 2. "PWMOPEN,Control of the PWMOP input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 1. "TMCEN,Control of the TMC input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
newline
|
|
bitfld.byte 0x0 0. "TMAEN,Control of the TMA input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
endif
|
|
group.byte 0x23++0x0
|
|
line.byte 0x0 "OSMC,Subsystem clock supply mode control register"
|
|
bitfld.byte 0x0 7. "RTCLPC,Setting in DEEPSLEEP mode or SLEEP mode while subsystem clock is selected as CPU clock" "0: Enables supply of subsystem clock to peripheral..,1: Stops supply of subsystem clock to peripheral.."
|
|
bitfld.byte 0x0 4. "WUTMMCK0,Selection of operation clock for real-time clock 15-bit interval timer and timer A" "0: The subsystem clock is selected as the..,1: The low-speed on-chip oscillator clock is.."
|
|
sif (cpuis("BAT32G157*"))
|
|
group.byte 0x41B++0x0
|
|
line.byte 0x0 "PER2,Peripheral enable register 2"
|
|
bitfld.byte 0x0 1. "SSIEN,Control of the SSI input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
bitfld.byte 0x0 0. "USBEN,Control of the USB input clock" "0: Disables input clock supply,1: Enables input clock supply"
|
|
endif
|
|
group.byte 0x1820++0x0
|
|
line.byte 0x0 "HOCODIV,High-speed on-chip oscillator frequency select register"
|
|
group.byte 0x1800++0x0
|
|
line.byte 0x0 "HIOTRM,High-speed on-chip oscillator trimming register"
|
|
sif (cpuis("BAT32G139*"))
|
|
group.word 0x1E00++0x3
|
|
line.word 0x0 "SCMCTL,Oscillator stop detection control register"
|
|
bitfld.word 0x0 15. "OSCDEN,Oscillator stop detection control register" "0: Oscillator stop detection stop,1: Oscillator stop detection start"
|
|
hexmask.word 0x0 0.--11. 1. "OSDCCMP,Oscillator stop detected time register"
|
|
line.word 0x2 "SCMMD,Oscillator stop detection mode register"
|
|
bitfld.word 0x2 1. "MDSEL,Oscillator stop detected operation selection register" "0: Interrupt when oscillator stop detection,1: Reset when oscillator stop detection"
|
|
bitfld.word 0x2 0. "CKSEL,Oscillator stop detected object selection register" "0: fMX Oscillator stop detection,1: fSX Oscillator stop detection"
|
|
group.byte 0x1E04++0x0
|
|
line.byte 0x0 "SCMST,Oscillator stop detected status register"
|
|
bitfld.byte 0x0 0. "OSTDF,Oscillator stop detected flag register" "0: Oscillator stop NOT detection,1: Oscillator stop detection"
|
|
group.byte 0x2000++0x0
|
|
line.byte 0x0 "HOCOFC,High-speed on-chip oscillator frequency correction register"
|
|
bitfld.byte 0x0 7. "FCMD,High-speed on-chip oscillator frequency correction operation mode register" "0,1"
|
|
bitfld.byte 0x0 6. "FCIE,Oscillator stop detected operation selection register" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "FCST,Oscillator stop detected object selection register" "0,1"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
group.byte 0x2000++0x0
|
|
line.byte 0x0 "HOCOFC,High-speed on-chip oscillator frequency correction register"
|
|
bitfld.byte 0x0 7. "FCMD,High-speed on-chip oscillator frequency correction operation mode register" "0,1"
|
|
bitfld.byte 0x0 6. "FCIE,Oscillator stop detected operation selection register" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "FCST,Oscillator stop detected object selection register" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "CMP (Comparator)"
|
|
base ad:0x40043840
|
|
group.byte 0x0++0x5
|
|
line.byte 0x0 "COMPMDR,Comparator mode setting register"
|
|
bitfld.byte 0x0 7. "C1MON,Comparator 1 monitor flag" "0,1"
|
|
bitfld.byte 0x0 4. "C1ENB,Comparator 1 operation enable" "0,1"
|
|
bitfld.byte 0x0 3. "C0MON,Comparator 0 monitor flag" "0,1"
|
|
bitfld.byte 0x0 0. "C0ENB,Comparator 0 operation enable" "0,1"
|
|
line.byte 0x1 "COMPFIR,Comparator filter control register"
|
|
bitfld.byte 0x1 7. "C1EDG,Comparator 1 edge detection selection" "0,1"
|
|
bitfld.byte 0x1 6. "C1EPO,Comparator 1 edge polarity switching" "0,1"
|
|
bitfld.byte 0x1 4.--5. "C1FCK,Comparator 1 filter selection" "0,1,2,3"
|
|
bitfld.byte 0x1 3. "C0EDG,Comparator 0 edge detection selection" "0,1"
|
|
bitfld.byte 0x1 2. "C0EPO,Comparator 0 edge polarity switching" "0,1"
|
|
bitfld.byte 0x1 0.--1. "C0FCK,Comparator 0 filter selection" "0,1,2,3"
|
|
line.byte 0x2 "COMPOCR,Comparator output control register"
|
|
bitfld.byte 0x2 7. "C1OTWMD,TIMER WINDOW output mode control bit of comparator 1" "0,1"
|
|
bitfld.byte 0x2 6. "C1OP,VOUT1 output polarity selection" "0,1"
|
|
bitfld.byte 0x2 5. "C1OE,VOUT1 pin output enable" "0,1"
|
|
bitfld.byte 0x2 4. "C1IE,Comparator 1 interrupt request enable" "0,1"
|
|
bitfld.byte 0x2 2. "C0OP,VOUT0 output polarity selection" "0,1"
|
|
bitfld.byte 0x2 1. "C0OE,VOUT0 pin output enable" "0,1"
|
|
bitfld.byte 0x2 0. "C0IE,Comparator 0 interrupt request enable" "0,1"
|
|
line.byte 0x3 "CVRCTL,Comparator internal reference voltage control register"
|
|
bitfld.byte 0x3 5. "CVRE1,Control bit for internal reference voltage 1" "0,1"
|
|
bitfld.byte 0x3 4. "CVRVS1,Ground selection bit for internal reference voltage" "0,1"
|
|
bitfld.byte 0x3 1. "CVRE0,Control bit for internal reference voltage 0" "0,1"
|
|
bitfld.byte 0x3 0. "CVRVS0,Power supply selection bit for internal reference voltage" "0,1"
|
|
line.byte 0x4 "C0RVM,Comparator internal reference voltage select register 0"
|
|
line.byte 0x5 "C1RVM,Comparator internal reference voltage select register 1"
|
|
group.byte 0xA++0x1
|
|
line.byte 0x0 "CMPSEL0,Comparator 0 input signal selection control register"
|
|
bitfld.byte 0x0 7. "CMP0SEL,Selection of the input signal on the positive side of Comparator 0" "0,1"
|
|
bitfld.byte 0x0 0.--1. "C0REFS,Selection of the input signal on the negative side of Comparator 0" "0,1,2,3"
|
|
line.byte 0x1 "CMPSEL1,Comparator 1 input signal selection control register"
|
|
bitfld.byte 0x1 6.--7. "CMP1SEL,Selection of the input signal on the positive side of Comparator 1" "0,1,2,3"
|
|
bitfld.byte 0x1 0.--2. "C1REFS,Selection of the input signal on the negative side of Comparator 1" "0,1,2,3,4,5,6,7"
|
|
sif (cpuis("BAT32G157*"))
|
|
group.byte 0xE++0x1
|
|
line.byte 0x0 "CMP0HY,Comparator 0 input voltage hysteresis control register"
|
|
bitfld.byte 0x0 4.--5. "C0HYSVS,Selection of the input hysteresis voltage of Comparator 0" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "C0HYSLS,Selection of the input hysteresis voltage level of Comparator 0" "0,1,2,3"
|
|
line.byte 0x1 "CMP1HY,Comparator 1 input voltage hysteresis control register"
|
|
bitfld.byte 0x1 4.--5. "C1HYSVS,Selection of the input hysteresis voltage of Comparator 1" "0,1,2,3"
|
|
bitfld.byte 0x1 0.--1. "C1HYSLS,Selection of the input hysteresis voltage level of Comparator 1" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
group.byte 0xE++0x1
|
|
line.byte 0x0 "CMP0HY,Comparator 0 hysteresis control register"
|
|
bitfld.byte 0x0 4.--5. "C0HYSVS,Selection of the hysteresis level of Comparator 0" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "C0HYSLS,Selection of the hysteresis method of Comparator 0" "0,1,2,3"
|
|
line.byte 0x1 "CMP1HY,Comparator 1 hysteresis control register"
|
|
bitfld.byte 0x1 4.--5. "C1HYSVS,Selection of the hysteresis level of Comparator 1" "0,1,2,3"
|
|
bitfld.byte 0x1 0.--1. "C1HYSLS,Selection of the hysteresis method of Comparator 1" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
group.byte 0xE++0x1
|
|
line.byte 0x0 "CMP0HY,Comparator 0 hysteresis control register"
|
|
bitfld.byte 0x0 4.--5. "C0HYSVS,Selection of the hysteresis level of Comparator 0" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "C0HYSLS,Selection of the hysteresis method of Comparator 0" "0,1,2,3"
|
|
line.byte 0x1 "CMP1HY,Comparator 1 hysteresis control register"
|
|
bitfld.byte 0x1 4.--5. "C1HYSVS,Selection of the hysteresis level of Comparator 1" "0,1,2,3"
|
|
bitfld.byte 0x1 0.--1. "C1HYSLS,Selection of the hysteresis method of Comparator 1" "0,1,2,3"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "CRC (General Purpose Cyclic Redundancy Check)"
|
|
base ad:0x400432F0
|
|
group.word 0xA++0x1
|
|
line.word 0x0 "CRCD,CRC data register"
|
|
group.byte 0xBC++0x0
|
|
line.byte 0x0 "CRCIN,CRC input register"
|
|
tree.end
|
|
tree "DAC (D/A Converter)"
|
|
base ad:0x40044700
|
|
group.byte 0x34++0x2
|
|
line.byte 0x0 "DACS0,D/A conversion value setting register 0"
|
|
line.byte 0x1 "DACS1,D/A conversion value setting register 1"
|
|
line.byte 0x2 "DAM,D/A conversion mode register"
|
|
bitfld.byte 0x2 5. "DACE1,D/A converter operation control" "0,1"
|
|
bitfld.byte 0x2 4. "DACE0,D/A converter operation control" "0,1"
|
|
bitfld.byte 0x2 1. "DAMD1,D/A converter operation mode selection" "0,1"
|
|
bitfld.byte 0x2 0. "DAMD0,D/A converter operation mode selection" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "DBG (Debug Support)"
|
|
base ad:0x4001B000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DBGSTR,Debug status register"
|
|
bitfld.long 0x0 29. "CDBGPWRUPACK,DBG Power Up Acknowledgement" "0,1"
|
|
bitfld.long 0x0 28. "CDBGPWRUPREQ,DBG Power Up Request" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "DBGSTOPCR,Debug Stop Control register"
|
|
bitfld.long 0x0 24. "SWDIS,SWD Disable" "0,1"
|
|
bitfld.long 0x0 16. "RPERMSK,Mask RAM parity error in debug mode" "0,1"
|
|
bitfld.long 0x0 2. "RESMSK,Mask internal reset in debug mode" "0,1"
|
|
bitfld.long 0x0 1. "FRZEN1,Stop Communation family macros when cpu halted" "0,1"
|
|
bitfld.long 0x0 0. "FRZEN0,Stop Timer family macros when cpu halted" "0,1"
|
|
tree.end
|
|
sif (cpuis("BAT32G137*"))
|
|
base ad:0x40080000
|
|
elif (cpuis("BAT32G157*"))
|
|
base ad:0x4001C000
|
|
elif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
base ad:0x4001A000
|
|
endif
|
|
tree "DIV (Hardware Divider)"
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DIVIDEND,Dividend register"
|
|
line.long 0x4 "DIVISOR,Divisor register"
|
|
rgroup.long 0x8++0xB
|
|
line.long 0x0 "QUOTIENT,Quotient register"
|
|
line.long 0x4 "REMAINDER,Remainder register"
|
|
line.long 0x8 "STATUS,Status register"
|
|
bitfld.long 0x8 9. "DIVBYZERO,divider zero flag" "0,1"
|
|
bitfld.long 0x8 8. "BUSY,divider busy flag" "0,1"
|
|
tree.end
|
|
tree "DMA (Enhanced DMA Controller)"
|
|
base ad:0x40005000
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "DMAEN$1,DMA activation enable register %s"
|
|
repeat.end
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "DMABAR,DMA base address register"
|
|
line.long 0x4 "IFPRCR,DMA Trigger Protect register"
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x10)++0x0
|
|
line.byte 0x0 "DMAIF$1,DMA Trigger enable register %s"
|
|
repeat.end
|
|
sif (cpuis("BAT32G139*"))
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x18)++0x0
|
|
line.byte 0x0 "DMSET$1,DMA activation enable set register %s"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x20)++0x0
|
|
line.byte 0x0 "DMCLR$1,DMA activation enable clear register %s"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x18)++0x0
|
|
line.byte 0x0 "DMSET$1,DMA activation enable set register %s"
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x20)++0x0
|
|
line.byte 0x0 "DMCLR$1,DMA activation enable clear register %s"
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
tree "DMAVEC (DMA Vector and Control Data Area)"
|
|
base ad:0x20000000
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "VEC[$1],DMA vector area"
|
|
repeat.end
|
|
sif (cpuis("BAT32G137*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x20000040 ad:0x20000050 ad:0x20000060 ad:0x20000070 ad:0x20000080 ad:0x20000090 ad:0x200000A0 ad:0x200000B0 ad:0x200000C0 ad:0x200000D0 ad:0x200000E0 ad:0x200000F0 ad:0x20000100 ad:0x20000110 ad:0x20000120 ad:0x20000130)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x20000040 ad:0x20000050 ad:0x20000060 ad:0x20000070 ad:0x20000080 ad:0x20000090 ad:0x200000A0 ad:0x200000B0 ad:0x200000C0 ad:0x200000D0 ad:0x200000E0 ad:0x200000F0 ad:0x20000100 ad:0x20000110 ad:0x20000120 ad:0x20000130)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 8. "FIFO,FIFO block transfer control" "0: FIFO block transfer disabled,1: FIFO block transfer enabled"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
newline
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
sif (cpuis("BAT32G137*"))
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x20000140 ad:0x20000150 ad:0x20000160 ad:0x20000170 ad:0x20000180 ad:0x20000190 ad:0x200001A0 ad:0x200001B0 ad:0x200001C0 ad:0x200001D0 ad:0x200001E0 ad:0x200001F0 ad:0x20000200 ad:0x20000210 ad:0x20000220 ad:0x20000230)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x20000140 ad:0x20000150 ad:0x20000160 ad:0x20000170 ad:0x20000180 ad:0x20000190 ad:0x200001A0 ad:0x200001B0 ad:0x200001C0 ad:0x200001D0 ad:0x200001E0 ad:0x200001F0 ad:0x20000200 ad:0x20000210 ad:0x20000220 ad:0x20000230)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 8. "FIFO,FIFO block transfer control" "0: FIFO block transfer disabled,1: FIFO block transfer enabled"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
newline
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
sif (cpuis("BAT32G137*"))
|
|
repeat 8. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27)(list ad:0x20000240 ad:0x20000250 ad:0x20000260 ad:0x20000270 ad:0x20000280 ad:0x20000290 ad:0x200002A0 ad:0x200002B0)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
repeat 8. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27)(list ad:0x20000240 ad:0x20000250 ad:0x20000260 ad:0x20000270 ad:0x20000280 ad:0x20000290 ad:0x200002A0 ad:0x200002B0)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 8. "FIFO,FIFO block transfer control" "0: FIFO block transfer disabled,1: FIFO block transfer enabled"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
newline
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x20000040 ad:0x20000050 ad:0x20000060 ad:0x20000070 ad:0x20000080 ad:0x20000090 ad:0x200000A0 ad:0x200000B0 ad:0x200000C0 ad:0x200000D0 ad:0x200000E0 ad:0x200000F0 ad:0x20000100 ad:0x20000110 ad:0x20000120 ad:0x20000130)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x20000140 ad:0x20000150 ad:0x20000160 ad:0x20000170 ad:0x20000180 ad:0x20000190 ad:0x200001A0 ad:0x200001B0 ad:0x200001C0 ad:0x200001D0 ad:0x200001E0 ad:0x200001F0 ad:0x20000200 ad:0x20000210 ad:0x20000220 ad:0x20000230)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
repeat 8. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27)(list ad:0x20000240 ad:0x20000250 ad:0x20000260 ad:0x20000270 ad:0x20000280 ad:0x20000290 ad:0x200002A0 ad:0x200002B0)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x20000040 ad:0x20000050 ad:0x20000060 ad:0x20000070 ad:0x20000080 ad:0x20000090 ad:0x200000A0 ad:0x200000B0 ad:0x200000C0 ad:0x200000D0 ad:0x200000E0 ad:0x200000F0 ad:0x20000100 ad:0x20000110 ad:0x20000120 ad:0x20000130)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x20000140 ad:0x20000150 ad:0x20000160 ad:0x20000170 ad:0x20000180 ad:0x20000190 ad:0x200001A0 ad:0x200001B0 ad:0x200001C0 ad:0x200001D0 ad:0x200001E0 ad:0x200001F0 ad:0x20000200 ad:0x20000210 ad:0x20000220 ad:0x20000230)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
repeat 8. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27)(list ad:0x20000240 ad:0x20000250 ad:0x20000260 ad:0x20000270 ad:0x20000280 ad:0x20000290 ad:0x200002A0 ad:0x200002B0)
|
|
tree "CTRL[$1]"
|
|
base $2
|
|
group.word ($2)++0x7
|
|
line.word 0x0 "DMACR,DMA Control register"
|
|
bitfld.word 0x0 6.--7. "SZ,Transfer Data size selection" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.word 0x0 5. "RPTINT,Enabling/disabling repeat mode interrupts" "0: Interrupt generation disabled,1: Interrupt generation enabled"
|
|
bitfld.word 0x0 4. "CHNE,Enabling/disabling chain transfers" "0: Chain transfers disabled,1: Chain transfers enabled"
|
|
bitfld.word 0x0 3. "DAMOD,Destination address control" "0: Fixed,1: Incremented"
|
|
newline
|
|
bitfld.word 0x0 2. "SAMOD,Source address control" "0: Fixed,1: Incremented"
|
|
bitfld.word 0x0 1. "RPTSEL,Repeat area selection" "0: Transfer destination is the repeat area,1: Transfer source is the repeat area"
|
|
bitfld.word 0x0 0. "MODE,Transfer mode selection" "0: Normal mode,1: Repeat mode"
|
|
line.word 0x2 "DMBLS,DMA Block Size register"
|
|
line.word 0x4 "DMACT,DMA Transfer Count register"
|
|
line.word 0x6 "DMRLD,DMA Transfer Count Reload register"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DMSAR,DMA Source Address register"
|
|
line.long 0x4 "DMDAR,DMA Destination Address register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x20000000
|
|
endif
|
|
tree.end
|
|
tree "ELC (Event Link Controller)"
|
|
base ad:0x40043400
|
|
group.byte 0x0++0xE
|
|
line.byte 0x0 "ELSELR00,Event output destination select register 00"
|
|
line.byte 0x1 "ELSELR01,Event output destination select register 01"
|
|
line.byte 0x2 "ELSELR02,Event output destination select register 02"
|
|
line.byte 0x3 "ELSELR03,Event output destination select register 03"
|
|
line.byte 0x4 "ELSELR04,Event output destination select register 04"
|
|
line.byte 0x5 "ELSELR05,Event output destination select register 05"
|
|
line.byte 0x6 "ELSELR06,Event output destination select register 06"
|
|
line.byte 0x7 "ELSELR07,Event output destination select register 07"
|
|
line.byte 0x8 "ELSELR08,Event output destination select register 08"
|
|
line.byte 0x9 "ELSELR09,Event output destination select register 09"
|
|
line.byte 0xA "ELSELR10,Event output destination select register 10"
|
|
line.byte 0xB "ELSELR11,Event output destination select register 11"
|
|
line.byte 0xC "ELSELR12,Event output destination select register 12"
|
|
line.byte 0xD "ELSELR13,Event output destination select register 13"
|
|
line.byte 0xE "ELSELR14,Event output destination select register 14"
|
|
sif (cpuis("BAT32G137*"))
|
|
group.byte 0xF++0x6
|
|
line.byte 0x0 "ELSELR15,Event output destination select register 15"
|
|
line.byte 0x1 "ELSELR16,Event output destination select register 16"
|
|
line.byte 0x2 "ELSELR17,Event output destination select register 17"
|
|
line.byte 0x3 "ELSELR18,Event output destination select register 18"
|
|
line.byte 0x4 "ELSELR19,Event output destination select register 19"
|
|
line.byte 0x5 "ELSELR20,Event output destination select register 20"
|
|
line.byte 0x6 "ELSELR21,Event output destination select register 21"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
group.byte 0xF++0x7
|
|
line.byte 0x0 "ELSELR15,Event output destination select register 15"
|
|
line.byte 0x1 "ELSELR16,Event output destination select register 16"
|
|
line.byte 0x2 "ELSELR17,Event output destination select register 17"
|
|
line.byte 0x3 "ELSELR18,Event output destination select register 18"
|
|
line.byte 0x4 "ELSELR19,Event output destination select register 19"
|
|
line.byte 0x5 "ELSELR20,Event output destination select register 20"
|
|
line.byte 0x6 "ELSELR21,Event output destination select register 21"
|
|
line.byte 0x7 "ELSELR22,Event output destination select register 21"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
group.byte 0xF++0x7
|
|
line.byte 0x0 "ELSELR15,Event output destination select register 15"
|
|
line.byte 0x1 "ELSELR16,Event output destination select register 16"
|
|
line.byte 0x2 "ELSELR17,Event output destination select register 17"
|
|
line.byte 0x3 "ELSELR18,Event output destination select register 18"
|
|
line.byte 0x4 "ELSELR19,Event output destination select register 19"
|
|
line.byte 0x5 "ELSELR20,Event output destination select register 20"
|
|
line.byte 0x6 "ELSELR21,Event output destination select register 21"
|
|
line.byte 0x7 "ELSELR22,Event output destination select register 21"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "EPWM (Enhanced PWM Controller)"
|
|
base ad:0x40044400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "EPWMSRC,Input source select register"
|
|
bitfld.word 0x0 0. "SRC0%s,Selsect the source clock of EPWM0%s" "0,1"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "EPWMCTL,EPWMO0n output control register"
|
|
bitfld.word 0x0 8. "IE0%s,EPWM0%s output inverted enable register" "0,1"
|
|
bitfld.word 0x0 0. "OE0%s,EPWM0%s output enable register" "0,1"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "EPWMSTL,EPWMO0n cutoff output level register"
|
|
bitfld.word 0x0 14. "IO7%s,EPWM07 output enable register" "0,1"
|
|
bitfld.word 0x0 12. "IO6%s,EPWM06 output enable register" "0,1"
|
|
bitfld.word 0x0 10. "IO5%s,EPWM05 output enable register" "0,1"
|
|
bitfld.word 0x0 8. "IO4%s,EPWM04 output enable register" "0,1"
|
|
bitfld.word 0x0 6. "IO3%s,EPWM03 output enable register" "0,1"
|
|
bitfld.word 0x0 4. "IO2%s,EPWM02 output enable register" "0,1"
|
|
bitfld.word 0x0 2. "IO1%s,EPWM01 output enable register" "0,1"
|
|
bitfld.word 0x0 0. "IO0%s,EPWM00 output enable register" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "EPWMSTC,EPWMO0n cutoff control register"
|
|
bitfld.word 0x0 4. "REL_SEL,Cutoff release timing select register" "0,1"
|
|
bitfld.word 0x0 3. "HS_SEL,Output forced cutoff release mode selection" "0,1"
|
|
bitfld.word 0x0 2. "IN_EG,Output forced cutoff source edge/output forced cutoff release edge selection" "0,1"
|
|
bitfld.word 0x0 0. "SC_SEL%s,Cutoff source selection" "0,1"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "EPWMSTR,Status register"
|
|
bitfld.word 0x0 1. "SHTFLG,cutoff status register" "0,1"
|
|
bitfld.word 0x0 0. "HZCLR,software release cutoff register" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "FMC (Flash Memory Controller)"
|
|
base ad:0x40020000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "FLSTS,Flash status register"
|
|
bitfld.long 0x0 2. "EVF,Flash hardware verification error flag" "0,1"
|
|
bitfld.long 0x0 0. "OVF,Flash erase or write operaiton finish" "0,1"
|
|
line.long 0x4 "FLOPMD1,Flash operation mode register 1"
|
|
line.long 0x8 "FLOPMD2,Flash operation mode register 2"
|
|
line.long 0xC "FLERMD,Flash erase mode register"
|
|
line.long 0x10 "FLCERCNT,Flash chip erase control register"
|
|
line.long 0x14 "FLSERCNT,Flash sector erase control register"
|
|
sif (cpuis("BAT32G157*"))
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "FLNVSCNT,Flash address setup time (Tnvs) control register"
|
|
endif
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "FLPROCNT,Flash program (write) control register"
|
|
line.long 0x4 "FLPROT,Flash protect control register"
|
|
sif (cpuis("BAT32G157*"))
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "FLPRVCNT,Flash program recovery time (Trcv) control register"
|
|
line.long 0x4 "FLERVCNT,Flash erase recovery time (Trcv) control register"
|
|
endif
|
|
tree.end
|
|
tree "IICA (Serial Interface)"
|
|
base ad:0x0
|
|
sif (cpuis("BAT32G137*"))
|
|
tree "IICA"
|
|
base ad:0x40041A30
|
|
group.byte 0x0++0x4
|
|
line.byte 0x0 "IICCTL00,IICA control register 0"
|
|
bitfld.byte 0x0 7. "IICE,I2C operation enable" "0,1"
|
|
bitfld.byte 0x0 6. "LREL,Exit from communications" "0,1"
|
|
bitfld.byte 0x0 5. "WREL,Wait cancellation" "0,1"
|
|
bitfld.byte 0x0 4. "SPIE,Enable generation of interrupt request when stop condition is detected" "0,1"
|
|
bitfld.byte 0x0 3. "WTIM,Control of wait and interrupt request generation" "0,1"
|
|
bitfld.byte 0x0 2. "ACKE,Acknowledgment control" "0,1"
|
|
bitfld.byte 0x0 1. "STT,Start condition trigger" "0,1"
|
|
bitfld.byte 0x0 0. "SPT,Stop condition trigger" "0,1"
|
|
line.byte 0x1 "IICCTL01,IICA control register 0"
|
|
bitfld.byte 0x1 7. "WUP,Control of address match wakeup" "0,1"
|
|
rbitfld.byte 0x1 5. "CLD,Detection of SCLAn pin level (valid only when IICEn = 1)" "0,1"
|
|
rbitfld.byte 0x1 4. "DAD,Detection of SDAAn pin level (valid only when IICEn = 1)" "0,1"
|
|
bitfld.byte 0x1 3. "SMC,Operation mode switching" "0,1"
|
|
bitfld.byte 0x1 2. "DFC,Digital filter operation control" "0,1"
|
|
bitfld.byte 0x1 0. "PRS,Operation clock (fMCK) contro" "0,1"
|
|
line.byte 0x2 "IICWL0,IICA low-level width setting register 0"
|
|
line.byte 0x3 "IICWH0,IICA high-level width setting register 0"
|
|
line.byte 0x4 "SVA0,Slave address register 0"
|
|
group.byte 0x120++0x0
|
|
line.byte 0x0 "IICA0,IICA shift register 0"
|
|
rgroup.byte 0x121++0x0
|
|
line.byte 0x0 "IICS0,IICA status register 0"
|
|
bitfld.byte 0x0 7. "MSTS,Master status check flag" "0,1"
|
|
bitfld.byte 0x0 6. "ALD,Detection of arbitration loss" "0,1"
|
|
bitfld.byte 0x0 5. "EXC,Detection of extension code reception" "0,1"
|
|
bitfld.byte 0x0 4. "COI,Detection of matching addresses" "0,1"
|
|
bitfld.byte 0x0 3. "TRC,Detection of transmit/receive status" "0,1"
|
|
bitfld.byte 0x0 2. "ACKD,Detection of acknowledge (ACK)" "0,1"
|
|
bitfld.byte 0x0 1. "STD,Detection of start condition" "0,1"
|
|
bitfld.byte 0x0 0. "SPD,Detection of stop condition" "0,1"
|
|
group.byte 0x122++0x0
|
|
line.byte 0x0 "IICF0,IICA flag register 0"
|
|
rbitfld.byte 0x0 7. "STCF,STT clear flag" "0,1"
|
|
rbitfld.byte 0x0 6. "IICBSY,I2C bus status flag" "0,1"
|
|
bitfld.byte 0x0 1. "STCEN,Initial start enable trigger" "0,1"
|
|
bitfld.byte 0x0 0. "IICRSV,Communication reservation function disable bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "IICA0"
|
|
base ad:0x40041A30
|
|
group.byte 0x0++0x4
|
|
line.byte 0x0 "IICCTL00,IICA0 control register 0"
|
|
bitfld.byte 0x0 7. "IICE,I2C operation enable" "0,1"
|
|
bitfld.byte 0x0 6. "LREL,Exit from communications" "0,1"
|
|
bitfld.byte 0x0 5. "WREL,Wait cancellation" "0,1"
|
|
bitfld.byte 0x0 4. "SPIE,Enable generation of interrupt request when stop condition is detected" "0,1"
|
|
bitfld.byte 0x0 3. "WTIM,Control of wait and interrupt request generation" "0,1"
|
|
bitfld.byte 0x0 2. "ACKE,Acknowledgment control" "0,1"
|
|
bitfld.byte 0x0 1. "STT,Start condition trigger" "0,1"
|
|
bitfld.byte 0x0 0. "SPT,Stop condition trigger" "0,1"
|
|
line.byte 0x1 "IICCTL01,IICA0 control register 1"
|
|
bitfld.byte 0x1 7. "WUP,Control of address match wakeup" "0,1"
|
|
rbitfld.byte 0x1 5. "CLD,Detection of SCLAn pin level (valid only when IICEn = 1)" "0,1"
|
|
rbitfld.byte 0x1 4. "DAD,Detection of SDAAn pin level (valid only when IICEn = 1)" "0,1"
|
|
bitfld.byte 0x1 3. "SMC,Operation mode switching" "0,1"
|
|
bitfld.byte 0x1 2. "DFC,Digital filter operation control" "0,1"
|
|
bitfld.byte 0x1 0. "PRS,Operation clock (fMCK) contro" "0,1"
|
|
line.byte 0x2 "IICWL0,IICA0 low-level width setting register"
|
|
line.byte 0x3 "IICWH0,IICA0 high-level width setting register"
|
|
line.byte 0x4 "SVA0,Slave address register"
|
|
group.byte 0x120++0x0
|
|
line.byte 0x0 "IICA0,IICA0 shift register"
|
|
rgroup.byte 0x121++0x0
|
|
line.byte 0x0 "IICS0,IICA0 status register"
|
|
bitfld.byte 0x0 7. "MSTS,Master status check flag" "0,1"
|
|
bitfld.byte 0x0 6. "ALD,Detection of arbitration loss" "0,1"
|
|
bitfld.byte 0x0 5. "EXC,Detection of extension code reception" "0,1"
|
|
bitfld.byte 0x0 4. "COI,Detection of matching addresses" "0,1"
|
|
bitfld.byte 0x0 3. "TRC,Detection of transmit/receive status" "0,1"
|
|
bitfld.byte 0x0 2. "ACKD,Detection of acknowledge (ACK)" "0,1"
|
|
bitfld.byte 0x0 1. "STD,Detection of start condition" "0,1"
|
|
bitfld.byte 0x0 0. "SPD,Detection of stop condition" "0,1"
|
|
group.byte 0x122++0x0
|
|
line.byte 0x0 "IICF0,IICA0 flag register"
|
|
rbitfld.byte 0x0 7. "STCF,STT clear flag" "0,1"
|
|
rbitfld.byte 0x0 6. "IICBSY,I2C bus status flag" "0,1"
|
|
bitfld.byte 0x0 1. "STCEN,Initial start enable trigger" "0,1"
|
|
bitfld.byte 0x0 0. "IICRSV,Communication reservation function disable bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "IICA1"
|
|
base ad:0x40042E30
|
|
group.byte 0x0++0x4
|
|
line.byte 0x0 "IICCTL10,IICA1 control register 0"
|
|
bitfld.byte 0x0 7. "IICE,I2C operation enable" "0,1"
|
|
bitfld.byte 0x0 6. "LREL,Exit from communications" "0,1"
|
|
bitfld.byte 0x0 5. "WREL,Wait cancellation" "0,1"
|
|
bitfld.byte 0x0 4. "SPIE,Enable generation of interrupt request when stop condition is detected" "0,1"
|
|
bitfld.byte 0x0 3. "WTIM,Control of wait and interrupt request generation" "0,1"
|
|
bitfld.byte 0x0 2. "ACKE,Acknowledgment control" "0,1"
|
|
bitfld.byte 0x0 1. "STT,Start condition trigger" "0,1"
|
|
bitfld.byte 0x0 0. "SPT,Stop condition trigger" "0,1"
|
|
line.byte 0x1 "IICCTL11,IICA1 control register 1"
|
|
bitfld.byte 0x1 7. "WUP,Control of address match wakeup" "0,1"
|
|
rbitfld.byte 0x1 5. "CLD,Detection of SCLAn pin level (valid only when IICEn = 1)" "0,1"
|
|
rbitfld.byte 0x1 4. "DAD,Detection of SDAAn pin level (valid only when IICEn = 1)" "0,1"
|
|
bitfld.byte 0x1 3. "SMC,Operation mode switching" "0,1"
|
|
bitfld.byte 0x1 2. "DFC,Digital filter operation control" "0,1"
|
|
bitfld.byte 0x1 0. "PRS,Operation clock (fMCK) contro" "0,1"
|
|
line.byte 0x2 "IICWL1,IICA1 low-level width setting register"
|
|
line.byte 0x3 "IICWH1,IICA1 high-level width setting register"
|
|
line.byte 0x4 "SVA1,Slave address register"
|
|
group.byte 0x120++0x0
|
|
line.byte 0x0 "IICA1,IICA1 shift register"
|
|
rgroup.byte 0x121++0x0
|
|
line.byte 0x0 "IICS1,IICA1 status register"
|
|
bitfld.byte 0x0 7. "MSTS,Master status check flag" "0,1"
|
|
bitfld.byte 0x0 6. "ALD,Detection of arbitration loss" "0,1"
|
|
bitfld.byte 0x0 5. "EXC,Detection of extension code reception" "0,1"
|
|
bitfld.byte 0x0 4. "COI,Detection of matching addresses" "0,1"
|
|
bitfld.byte 0x0 3. "TRC,Detection of transmit/receive status" "0,1"
|
|
bitfld.byte 0x0 2. "ACKD,Detection of acknowledge (ACK)" "0,1"
|
|
bitfld.byte 0x0 1. "STD,Detection of start condition" "0,1"
|
|
bitfld.byte 0x0 0. "SPD,Detection of stop condition" "0,1"
|
|
group.byte 0x122++0x0
|
|
line.byte 0x0 "IICF1,IICA1 flag register"
|
|
rbitfld.byte 0x0 7. "STCF,STT clear flag" "0,1"
|
|
rbitfld.byte 0x0 6. "IICBSY,I2C bus status flag" "0,1"
|
|
bitfld.byte 0x0 1. "STCEN,Initial start enable trigger" "0,1"
|
|
bitfld.byte 0x0 0. "IICRSV,Communication reservation function disable bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "IICA0"
|
|
base ad:0x40041A30
|
|
group.byte 0x0++0x4
|
|
line.byte 0x0 "IICCTL00,IICA control register 0"
|
|
bitfld.byte 0x0 7. "IICE,I2C operation enable" "0,1"
|
|
bitfld.byte 0x0 6. "LREL,Exit from communications" "0,1"
|
|
bitfld.byte 0x0 5. "WREL,Wait cancellation" "0,1"
|
|
bitfld.byte 0x0 4. "SPIE,Enable generation of interrupt request when stop condition is detected" "0,1"
|
|
bitfld.byte 0x0 3. "WTIM,Control of wait and interrupt request generation" "0,1"
|
|
bitfld.byte 0x0 2. "ACKE,Acknowledgment control" "0,1"
|
|
bitfld.byte 0x0 1. "STT,Start condition trigger" "0,1"
|
|
bitfld.byte 0x0 0. "SPT,Stop condition trigger" "0,1"
|
|
line.byte 0x1 "IICCTL01,IICA control register 1"
|
|
bitfld.byte 0x1 7. "WUP,Control of address match wakeup" "0,1"
|
|
rbitfld.byte 0x1 5. "CLD,Detection of SCLAn pin level (valid only when IICEn = 1)" "0,1"
|
|
rbitfld.byte 0x1 4. "DAD,Detection of SDAAn pin level (valid only when IICEn = 1)" "0,1"
|
|
bitfld.byte 0x1 3. "SMC,Operation mode switching" "0,1"
|
|
bitfld.byte 0x1 2. "DFC,Digital filter operation control" "0,1"
|
|
bitfld.byte 0x1 0. "PRS,Operation clock (fMCK) contro" "0,1"
|
|
line.byte 0x2 "IICWL0,IICA low-level width setting register 0"
|
|
line.byte 0x3 "IICWH0,IICA high-level width setting register 0"
|
|
line.byte 0x4 "SVA0,Slave address register 0"
|
|
group.byte 0x120++0x0
|
|
line.byte 0x0 "IICA00,IICA shift register 00"
|
|
rgroup.byte 0x121++0x0
|
|
line.byte 0x0 "IICS0,IICA status register 0"
|
|
bitfld.byte 0x0 7. "MSTS,Master status check flag" "0,1"
|
|
bitfld.byte 0x0 6. "ALD,Detection of arbitration loss" "0,1"
|
|
bitfld.byte 0x0 5. "EXC,Detection of extension code reception" "0,1"
|
|
bitfld.byte 0x0 4. "COI,Detection of matching addresses" "0,1"
|
|
bitfld.byte 0x0 3. "TRC,Detection of transmit/receive status" "0,1"
|
|
bitfld.byte 0x0 2. "ACKD,Detection of acknowledge (ACK)" "0,1"
|
|
bitfld.byte 0x0 1. "STD,Detection of start condition" "0,1"
|
|
bitfld.byte 0x0 0. "SPD,Detection of stop condition" "0,1"
|
|
group.byte 0x122++0x0
|
|
line.byte 0x0 "IICF0,IICA flag register 0"
|
|
rbitfld.byte 0x0 7. "STCF,STT clear flag" "0,1"
|
|
rbitfld.byte 0x0 6. "IICBSY,I2C bus status flag" "0,1"
|
|
bitfld.byte 0x0 1. "STCEN,Initial start enable trigger" "0,1"
|
|
bitfld.byte 0x0 0. "IICRSV,Communication reservation function disable bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "IICA1"
|
|
base ad:0x40046230
|
|
group.byte 0x0++0x4
|
|
line.byte 0x0 "IICCTL10,IICA control register 0"
|
|
bitfld.byte 0x0 7. "IICE,I2C operation enable" "0,1"
|
|
bitfld.byte 0x0 6. "LREL,Exit from communications" "0,1"
|
|
bitfld.byte 0x0 5. "WREL,Wait cancellation" "0,1"
|
|
bitfld.byte 0x0 4. "SPIE,Enable generation of interrupt request when stop condition is detected" "0,1"
|
|
bitfld.byte 0x0 3. "WTIM,Control of wait and interrupt request generation" "0,1"
|
|
bitfld.byte 0x0 2. "ACKE,Acknowledgment control" "0,1"
|
|
bitfld.byte 0x0 1. "STT,Start condition trigger" "0,1"
|
|
bitfld.byte 0x0 0. "SPT,Stop condition trigger" "0,1"
|
|
line.byte 0x1 "IICCTL11,IICA control register 1"
|
|
bitfld.byte 0x1 7. "WUP,Control of address match wakeup" "0,1"
|
|
rbitfld.byte 0x1 5. "CLD,Detection of SCLAn pin level (valid only when IICEn = 1)" "0,1"
|
|
rbitfld.byte 0x1 4. "DAD,Detection of SDAAn pin level (valid only when IICEn = 1)" "0,1"
|
|
bitfld.byte 0x1 3. "SMC,Operation mode switching" "0,1"
|
|
bitfld.byte 0x1 2. "DFC,Digital filter operation control" "0,1"
|
|
bitfld.byte 0x1 0. "PRS,Operation clock (fMCK) contro" "0,1"
|
|
line.byte 0x2 "IICWL1,IICA low-level width setting register 1"
|
|
line.byte 0x3 "IICWH1,IICA high-level width setting register 1"
|
|
line.byte 0x4 "SVA1,Slave address register 1"
|
|
group.byte 0x120++0x0
|
|
line.byte 0x0 "IICA10,IICA shift register 10"
|
|
rgroup.byte 0x121++0x0
|
|
line.byte 0x0 "IICS1,IICA status register 1"
|
|
bitfld.byte 0x0 7. "MSTS,Master status check flag" "0,1"
|
|
bitfld.byte 0x0 6. "ALD,Detection of arbitration loss" "0,1"
|
|
bitfld.byte 0x0 5. "EXC,Detection of extension code reception" "0,1"
|
|
bitfld.byte 0x0 4. "COI,Detection of matching addresses" "0,1"
|
|
bitfld.byte 0x0 3. "TRC,Detection of transmit/receive status" "0,1"
|
|
bitfld.byte 0x0 2. "ACKD,Detection of acknowledge (ACK)" "0,1"
|
|
bitfld.byte 0x0 1. "STD,Detection of start condition" "0,1"
|
|
bitfld.byte 0x0 0. "SPD,Detection of stop condition" "0,1"
|
|
group.byte 0x122++0x0
|
|
line.byte 0x0 "IICF1,IICA flag register 1"
|
|
rbitfld.byte 0x0 7. "STCF,STT clear flag" "0,1"
|
|
rbitfld.byte 0x0 6. "IICBSY,I2C bus status flag" "0,1"
|
|
bitfld.byte 0x0 1. "STCEN,Initial start enable trigger" "0,1"
|
|
bitfld.byte 0x0 0. "IICRSV,Communication reservation function disable bit" "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "INT (Interrupt Controller)"
|
|
base ad:0x40006000
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G157*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40006000 ad:0x40006004 ad:0x40006008 ad:0x4000600C ad:0x40006010 ad:0x40006014 ad:0x40006018 ad:0x4000601C ad:0x40006020 ad:0x40006024 ad:0x40006028 ad:0x4000602C ad:0x40006030 ad:0x40006034 ad:0x40006038 ad:0x4000603C)
|
|
tree "IF[$1]"
|
|
base $2
|
|
group.byte ($2)++0x1
|
|
line.byte 0x0 "IFL,Interrupt flag register"
|
|
line.byte 0x1 "IFH,Interrupt flag register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40006000 ad:0x40006004 ad:0x40006008 ad:0x4000600C ad:0x40006010 ad:0x40006014 ad:0x40006018 ad:0x4000601C ad:0x40006020 ad:0x40006024 ad:0x40006028 ad:0x4000602C ad:0x40006030 ad:0x40006034 ad:0x40006038 ad:0x4000603C)
|
|
tree "IF[$1]"
|
|
base $2
|
|
group.byte ($2)++0x2
|
|
line.byte 0x0 "IFL,Interrupt flag register"
|
|
line.byte 0x1 "IFH,Interrupt flag register"
|
|
line.byte 0x2 "IFT,Interrupt flag register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G157*"))
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40006040 ad:0x40006044 ad:0x40006048 ad:0x4000604C ad:0x40006050 ad:0x40006054 ad:0x40006058 ad:0x4000605C ad:0x40006060 ad:0x40006064 ad:0x40006068 ad:0x4000606C ad:0x40006070 ad:0x40006074 ad:0x40006078 ad:0x4000607C)
|
|
tree "IF[$1]"
|
|
base $2
|
|
group.byte ($2)++0x1
|
|
line.byte 0x0 "IFL,Interrupt flag register"
|
|
line.byte 0x1 "IFH,Interrupt flag register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40006040 ad:0x40006044 ad:0x40006048 ad:0x4000604C ad:0x40006050 ad:0x40006054 ad:0x40006058 ad:0x4000605C ad:0x40006060 ad:0x40006064 ad:0x40006068 ad:0x4000606C ad:0x40006070 ad:0x40006074 ad:0x40006078 ad:0x4000607C)
|
|
tree "IF[$1]"
|
|
base $2
|
|
group.byte ($2)++0x2
|
|
line.byte 0x0 "IFL,Interrupt flag register"
|
|
line.byte 0x1 "IFH,Interrupt flag register"
|
|
line.byte 0x2 "IFT,Interrupt flag register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G157*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40006100 ad:0x40006104 ad:0x40006108 ad:0x4000610C ad:0x40006110 ad:0x40006114 ad:0x40006118 ad:0x4000611C ad:0x40006120 ad:0x40006124 ad:0x40006128 ad:0x4000612C ad:0x40006130 ad:0x40006134 ad:0x40006138 ad:0x4000613C)
|
|
tree "MK[$1]"
|
|
base $2
|
|
group.byte ($2)++0x1
|
|
line.byte 0x0 "MKL,Interrupt mask register"
|
|
line.byte 0x1 "MKH,Interrupt mask register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40006100 ad:0x40006104 ad:0x40006108 ad:0x4000610C ad:0x40006110 ad:0x40006114 ad:0x40006118 ad:0x4000611C ad:0x40006120 ad:0x40006124 ad:0x40006128 ad:0x4000612C ad:0x40006130 ad:0x40006134 ad:0x40006138 ad:0x4000613C)
|
|
tree "MK[$1]"
|
|
base $2
|
|
group.byte ($2)++0x2
|
|
line.byte 0x0 "MKL,Interrupt mask register"
|
|
line.byte 0x1 "MKH,Interrupt mask register"
|
|
line.byte 0x2 "MKT,Interrupt mask register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G157*"))
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40006140 ad:0x40006144 ad:0x40006148 ad:0x4000614C ad:0x40006150 ad:0x40006154 ad:0x40006158 ad:0x4000615C ad:0x40006160 ad:0x40006164 ad:0x40006168 ad:0x4000616C ad:0x40006170 ad:0x40006174 ad:0x40006178 ad:0x4000617C)
|
|
tree "MK[$1]"
|
|
base $2
|
|
group.byte ($2)++0x1
|
|
line.byte 0x0 "MKL,Interrupt mask register"
|
|
line.byte 0x1 "MKH,Interrupt mask register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40006140 ad:0x40006144 ad:0x40006148 ad:0x4000614C ad:0x40006150 ad:0x40006154 ad:0x40006158 ad:0x4000615C ad:0x40006160 ad:0x40006164 ad:0x40006168 ad:0x4000616C ad:0x40006170 ad:0x40006174 ad:0x40006178 ad:0x4000617C)
|
|
tree "MK[$1]"
|
|
base $2
|
|
group.byte ($2)++0x2
|
|
line.byte 0x0 "MKL,Interrupt mask register"
|
|
line.byte 0x1 "MKH,Interrupt mask register"
|
|
line.byte 0x2 "MKT,Interrupt mask register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40006000 ad:0x40006004 ad:0x40006008 ad:0x4000600C ad:0x40006010 ad:0x40006014 ad:0x40006018 ad:0x4000601C ad:0x40006020 ad:0x40006024 ad:0x40006028 ad:0x4000602C ad:0x40006030 ad:0x40006034 ad:0x40006038 ad:0x4000603C)
|
|
tree "IF[$1]"
|
|
base $2
|
|
group.byte ($2)++0x2
|
|
line.byte 0x0 "IFL,Interrupt flag register"
|
|
line.byte 0x1 "IFH,Interrupt flag register"
|
|
line.byte 0x2 "IFT,Interrupt flag register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40006040 ad:0x40006044 ad:0x40006048 ad:0x4000604C ad:0x40006050 ad:0x40006054 ad:0x40006058 ad:0x4000605C ad:0x40006060 ad:0x40006064 ad:0x40006068 ad:0x4000606C ad:0x40006070 ad:0x40006074 ad:0x40006078 ad:0x4000607C)
|
|
tree "IF[$1]"
|
|
base $2
|
|
group.byte ($2)++0x2
|
|
line.byte 0x0 "IFL,Interrupt flag register"
|
|
line.byte 0x1 "IFH,Interrupt flag register"
|
|
line.byte 0x2 "IFT,Interrupt flag register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40006100 ad:0x40006104 ad:0x40006108 ad:0x4000610C ad:0x40006110 ad:0x40006114 ad:0x40006118 ad:0x4000611C ad:0x40006120 ad:0x40006124 ad:0x40006128 ad:0x4000612C ad:0x40006130 ad:0x40006134 ad:0x40006138 ad:0x4000613C)
|
|
tree "MK[$1]"
|
|
base $2
|
|
group.byte ($2)++0x2
|
|
line.byte 0x0 "MKL,Interrupt mask register"
|
|
line.byte 0x1 "MKH,Interrupt mask register"
|
|
line.byte 0x2 "MKT,Interrupt mask register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40006140 ad:0x40006144 ad:0x40006148 ad:0x4000614C ad:0x40006150 ad:0x40006154 ad:0x40006158 ad:0x4000615C ad:0x40006160 ad:0x40006164 ad:0x40006168 ad:0x4000616C ad:0x40006170 ad:0x40006174 ad:0x40006178 ad:0x4000617C)
|
|
tree "MK[$1]"
|
|
base $2
|
|
group.byte ($2)++0x2
|
|
line.byte 0x0 "MKL,Interrupt mask register"
|
|
line.byte 0x1 "MKH,Interrupt mask register"
|
|
line.byte 0x2 "MKT,Interrupt mask register"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40006000
|
|
endif
|
|
tree.end
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G157*"))
|
|
base ad:0x40045B38
|
|
elif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
base ad:0x40046B38
|
|
endif
|
|
tree "INTM (Pin Input Edge Detection)"
|
|
group.byte 0x0++0x1
|
|
line.byte 0x0 "EGP0,External interrupt rising edge enable register"
|
|
bitfld.byte 0x0 7. "EGP7" "0,1"
|
|
bitfld.byte 0x0 6. "EGP6" "0,1"
|
|
bitfld.byte 0x0 5. "EGP5" "0,1"
|
|
bitfld.byte 0x0 4. "EGP4" "0,1"
|
|
bitfld.byte 0x0 3. "EGP3" "0,1"
|
|
bitfld.byte 0x0 2. "EGP2" "0,1"
|
|
bitfld.byte 0x0 1. "EGP1" "0,1"
|
|
bitfld.byte 0x0 0. "EGP0" "0,1"
|
|
line.byte 0x1 "EGN0,External interrupt falling edge enable register"
|
|
bitfld.byte 0x1 7. "EGN7" "0,1"
|
|
bitfld.byte 0x1 6. "EGN6" "0,1"
|
|
bitfld.byte 0x1 5. "EGN5" "0,1"
|
|
bitfld.byte 0x1 4. "EGN4" "0,1"
|
|
bitfld.byte 0x1 3. "EGN3" "0,1"
|
|
bitfld.byte 0x1 2. "EGN2" "0,1"
|
|
bitfld.byte 0x1 1. "EGN1" "0,1"
|
|
bitfld.byte 0x1 0. "EGN0" "0,1"
|
|
sif (cpuis("BAT32G137*"))
|
|
group.byte 0x2++0x1
|
|
line.byte 0x0 "EGP1,External interrupt rising edge enable register"
|
|
bitfld.byte 0x0 3. "EGP11" "0,1"
|
|
bitfld.byte 0x0 2. "EGP10" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "EGP9" "0,1"
|
|
bitfld.byte 0x0 0. "EGP8" "0,1"
|
|
line.byte 0x1 "EGN1,External interrupt falling edge enable register"
|
|
bitfld.byte 0x1 3. "EGN11" "0,1"
|
|
bitfld.byte 0x1 2. "EGN10" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "EGN9" "0,1"
|
|
bitfld.byte 0x1 0. "EGN8" "0,1"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
group.byte 0x2++0x1
|
|
line.byte 0x0 "EGP1,External interrupt rising edge enable register"
|
|
bitfld.byte 0x0 3. "EGP11" "0,1"
|
|
bitfld.byte 0x0 2. "EGP10" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "EGP9" "0,1"
|
|
bitfld.byte 0x0 0. "EGP8" "0,1"
|
|
line.byte 0x1 "EGN1,External interrupt falling edge enable register"
|
|
bitfld.byte 0x1 3. "EGN11" "0,1"
|
|
bitfld.byte 0x1 2. "EGN10" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "EGN9" "0,1"
|
|
bitfld.byte 0x1 0. "EGN8" "0,1"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "EGP0,External interrupt rising edge enable register"
|
|
bitfld.long 0x0 7. "EGP7" "0,1"
|
|
bitfld.long 0x0 6. "EGP6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EGP5" "0,1"
|
|
bitfld.long 0x0 4. "EGP4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EGP3" "0,1"
|
|
bitfld.long 0x0 2. "EGP2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EGP1" "0,1"
|
|
bitfld.long 0x0 0. "EGP0" "0,1"
|
|
group.byte 0x2++0x1
|
|
line.byte 0x0 "EGP1,External interrupt rising edge enable register"
|
|
bitfld.byte 0x0 3. "EGP11" "0,1"
|
|
bitfld.byte 0x0 2. "EGP10" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "EGP9" "0,1"
|
|
bitfld.byte 0x0 0. "EGP8" "0,1"
|
|
line.byte 0x1 "EGN1,External interrupt falling edge enable register"
|
|
bitfld.byte 0x1 3. "EGN11" "0,1"
|
|
bitfld.byte 0x1 2. "EGN10" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "EGN9" "0,1"
|
|
bitfld.byte 0x1 0. "EGN8" "0,1"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("BAT32G137*"))
|
|
tree "IRDA (Infrared Data Association)"
|
|
base ad:0x400440A0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "IRCR,IrDA control register"
|
|
bitfld.long 0x0 7. "IRE,IrRxD enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "IRCKS,IrRxD clock selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "IRTXINV,IrRxD data polarity switching" "0,1"
|
|
bitfld.long 0x0 2. "IRRXINV,IrRxD data polarity switching" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "KEY (Key Interrupt)"
|
|
base ad:0x40044B30
|
|
group.byte 0x7++0x0
|
|
line.byte 0x0 "KRM,Key return mode register"
|
|
tree.end
|
|
sif (cpuis("BAT32G157*"))
|
|
base ad:0x40045400
|
|
elif (cpuis("BAT32G179*"))
|
|
base ad:0x40047400
|
|
endif
|
|
sif (cpuis("BAT32G157*")||cpuis("BAT32G179*"))
|
|
tree "LCDB (LCD Bus Interface)"
|
|
group.byte 0x0++0x2
|
|
line.byte 0x0 "LBCTL,LCD Bus Interface mode register"
|
|
bitfld.byte 0x0 7. "EL,Control the level of signal 'E' in mod68 mode" "0,1"
|
|
bitfld.byte 0x0 6. "IMD,Mode of external bus interface access selection" "0,1"
|
|
bitfld.byte 0x0 4.--5. "LBC,Internal clock (SPCLK) selection" "0,1,2,3"
|
|
bitfld.byte 0x0 3. "TCIS,INTLCDB (DMA trigger) generation control bit" "0,1"
|
|
bitfld.byte 0x0 1. "TPF,Flag of transfer in progress on external bus interface" "0,1"
|
|
bitfld.byte 0x0 0. "BYF,Data register busy flag" "0,1"
|
|
line.byte 0x1 "LBCYC,LCB Bus Interface cycle control register"
|
|
line.byte 0x2 "LBWST,LCB Bus Interface wait control register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "LBDATA,LCD Bus Interface data register"
|
|
group.byte 0x10++0x0
|
|
line.byte 0x0 "LBDATAL,SPI data register"
|
|
group.word 0x12++0x1
|
|
line.word 0x0 "LBDATAR,LCD Bus Interface read data register"
|
|
group.byte 0x12++0x0
|
|
line.byte 0x0 "LBDATARL,LCD Bus Interface read data register"
|
|
tree.end
|
|
endif
|
|
tree "LVD (Low Voltage Detector)"
|
|
base ad:0x40020440
|
|
rgroup.byte 0x1++0x0
|
|
line.byte 0x0 "LVIM,Voltage detection register"
|
|
bitfld.byte 0x0 7. "LVISEN,Enable rewritting LVIS register" "0: Disabling of rewriting the LVIS register,1: Enabling of rewriting the LVIS register"
|
|
bitfld.byte 0x0 1. "LVIOMSK,Mask status flag of LVD output" "0: Mask of LVD output is invalid,1: Mask of LVD output is valid"
|
|
newline
|
|
bitfld.byte 0x0 0. "LVIF,Voltage detection flag" "0: Supply voltage (VDD) greater or equal to..,1: Supply voltage (VDD) less than detection voltage.."
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "LVIS,Voltage detection level register"
|
|
bitfld.byte 0x0 7. "LVIMD,Operation mode of voltage detection" "0: interrupt mode,1: reset mode"
|
|
bitfld.byte 0x0 0. "LVILV,LVD detection level" "0: High-voltage detection level (VLVDH),1: Low-voltage detection level (VLVDL or VLVD)"
|
|
tree.end
|
|
tree "MISC (Miscellaneous Functions)"
|
|
base ad:0x40040470
|
|
group.byte 0x0++0x1
|
|
line.byte 0x0 "NFEN0,Noise filter enable register 0"
|
|
bitfld.byte 0x0 4. "SNFEN20,Enable noise filter of RxD2" "0,1"
|
|
bitfld.byte 0x0 2. "SNFEN10,Enable noise filter of RxD1" "0,1"
|
|
bitfld.byte 0x0 0. "SNFEN00,Enable noise filter of RxD0" "0,1"
|
|
line.byte 0x1 "NFEN1,Noise filter enable register 1"
|
|
bitfld.byte 0x1 3. "TNFEN03,Enable noise filter of TI03" "0,1"
|
|
bitfld.byte 0x1 2. "TNFEN02,Enable noise filter of TI02" "0,1"
|
|
bitfld.byte 0x1 1. "TNFEN01,Enable noise filter of TI01" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "TNFEN00,Enable noise filter of TI00" "0,1"
|
|
sif (cpuis("BAT32G157*"))
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "NFEN2,Noise filter enable register 2"
|
|
bitfld.byte 0x0 7. "TNFEN17,Enable noise filter of TI17" "0,1"
|
|
bitfld.byte 0x0 6. "TNFEN16,Enable noise filter of TI16" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "TNFEN15,Enable noise filter of TI15" "0,1"
|
|
bitfld.byte 0x0 4. "TNFEN14,Enable noise filter of TI14" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TNFEN13,Enable noise filter of TI13" "0,1"
|
|
bitfld.byte 0x0 2. "TNFEN12,Enable noise filter of TI12" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "TNFEN11,Enable noise filter of TI11" "0,1"
|
|
bitfld.byte 0x0 0. "TNFEN10,Enable noise filter of TI10" "0,1"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "NFEN2,Noise filter enable register 2"
|
|
bitfld.byte 0x0 7. "TNFEN17,Enable noise filter of TI17" "0,1"
|
|
bitfld.byte 0x0 6. "TNFEN16,Enable noise filter of TI16" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "TNFEN15,Enable noise filter of TI15" "0,1"
|
|
bitfld.byte 0x0 4. "TNFEN14,Enable noise filter of TI14" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TNFEN13,Enable noise filter of TI13" "0,1"
|
|
bitfld.byte 0x0 2. "TNFEN12,Enable noise filter of TI12" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "TNFEN11,Enable noise filter of TI11" "0,1"
|
|
bitfld.byte 0x0 0. "TNFEN10,Enable noise filter of TI10" "0,1"
|
|
group.byte 0x5++0x0
|
|
line.byte 0x0 "TIOS1,Timer I/O select register 1"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "NFEN2,Noise filter enable register 2"
|
|
bitfld.byte 0x0 7. "TNFEN17,Enable noise filter of TI17" "0,1"
|
|
bitfld.byte 0x0 6. "TNFEN16,Enable noise filter of TI16" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "TNFEN15,Enable noise filter of TI15" "0,1"
|
|
bitfld.byte 0x0 4. "TNFEN14,Enable noise filter of TI14" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TNFEN13,Enable noise filter of TI13" "0,1"
|
|
bitfld.byte 0x0 2. "TNFEN12,Enable noise filter of TI12" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "TNFEN11,Enable noise filter of TI11" "0,1"
|
|
bitfld.byte 0x0 0. "TNFEN10,Enable noise filter of TI10" "0,1"
|
|
group.byte 0x5++0x0
|
|
line.byte 0x0 "TIOS1,Timer I/O select register 1"
|
|
endif
|
|
group.byte 0x3++0x1
|
|
line.byte 0x0 "ISC,Input switch control register"
|
|
bitfld.byte 0x0 7. "SSIE00,The slave select input (SS00) of SPI00 is valid" "0: The slave select input (SS00) pin is invalid,1: The slave select input (SS00) pin is valid"
|
|
bitfld.byte 0x0 1. "ISC1,Switching TI03 input" "0: Uses TI03 pin as an timer input,1: Uses RXD0 pin as an timer input"
|
|
bitfld.byte 0x0 0. "ISC0,Switching external interrupt (INTP0) input" "0: Uses INTP0 pin as an external interrupt,1: Uses RXD0 pin as an external interrupt"
|
|
line.byte 0x1 "TIOS0,Timer I/O select register 0"
|
|
sif (cpuis("BAT32G137*"))
|
|
group.byte 0x5++0x0
|
|
line.byte 0x0 "TIOS1,Timer I/O select register 1"
|
|
endif
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "RTCCL,Real-time clock select register"
|
|
tree.end
|
|
sif (cpuis("BAT32G137*"))
|
|
tree "MTB (Micro Trace Buffer)"
|
|
base ad:0x40019000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "POSITION,MTB Position Register"
|
|
hexmask.long 0x0 3.--31. 1. "POINTER"
|
|
bitfld.long 0x0 2. "WRAP" "0,1"
|
|
line.long 0x4 "MASTER,MTB Master Register"
|
|
bitfld.long 0x4 31. "EN" "0,1"
|
|
bitfld.long 0x4 9. "HALTREQ" "0,1"
|
|
bitfld.long 0x4 8. "RAMPRIV" "0,1"
|
|
bitfld.long 0x4 7. "SFRWPRIV" "0,1"
|
|
bitfld.long 0x4 6. "TSTOPEN" "0,1"
|
|
bitfld.long 0x4 5. "TSTARTEN" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "MASK"
|
|
line.long 0x8 "FLOW,MTB Flow Register"
|
|
hexmask.long 0x8 3.--31. 1. "WATERMARK"
|
|
bitfld.long 0x8 1. "AUTOHALT" "0,1"
|
|
bitfld.long 0x8 0. "AUTOSTOP" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "BASE,MTB Base Register"
|
|
group.long 0xFB0++0x3
|
|
line.long 0x0 "LOCKACCESS,MTB Lock Access Register"
|
|
rgroup.long 0xFB4++0xB
|
|
line.long 0x0 "LOCKSTATUS,MTB Lock Status Register"
|
|
line.long 0x4 "AUTHSTATUS,MTB Authentication Status Register"
|
|
line.long 0x8 "DEVARCH,MTB Device Architecture Register"
|
|
rgroup.long 0xFC8++0x7
|
|
line.long 0x0 "DEVID,MTB Device Configuration Register"
|
|
line.long 0x4 "DEVTYPE,MTB Device Type Register"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xFD0)++0x3
|
|
line.long 0x0 "PID$1,CoreSight Register"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xFE0)++0x3
|
|
line.long 0x0 "PID$1,CoreSight Register"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xFF0)++0x3
|
|
line.long 0x0 "CID$1,CoreSight Register"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "PCBZ (Clock/Buzzer Output Controller)"
|
|
base ad:0x40040FA0
|
|
group.byte 0x5++0x1
|
|
line.byte 0x0 "CKS0,Clock output select registers 0"
|
|
bitfld.byte 0x0 7. "PCLOE,PCLBUZn pin output enable" "0,1"
|
|
bitfld.byte 0x0 3. "CSEL,PCLBUZn output clock select" "0,1"
|
|
bitfld.byte 0x0 0.--2. "CCS,PCLBUZn output clock select" "0,1,2,3,4,5,6,7"
|
|
line.byte 0x1 "CKS1,Clock output select registers 1"
|
|
bitfld.byte 0x1 7. "PCLOE,PCLBUZn pin output enable" "0,1"
|
|
bitfld.byte 0x1 3. "CSEL,PCLBUZn output clock select" "0,1"
|
|
bitfld.byte 0x1 0.--2. "CCS,PCLBUZn output clock select" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "PGA (Programmable Gain Aplifier)"
|
|
base ad:0x40043840
|
|
group.byte 0x6++0x0
|
|
line.byte 0x0 "PGA0CTL,PGA 0 control register"
|
|
bitfld.byte 0x0 7. "PGAEN,Programmable gain amplifier operation control" "0,1"
|
|
sif (cpuis("BAT32G157*"))
|
|
bitfld.byte 0x0 4. "PGA0INHL,PGA0IN and PGA0GNA input selection of the programmable gain amplifier" "0,1"
|
|
bitfld.byte 0x0 3. "PGA0R1_N,Differential or single-ended input selection of the programmable gain amplifier" "0,1"
|
|
endif
|
|
sif (cpuis("BAT32G137*"))
|
|
bitfld.byte 0x0 3. "PVRVS,GND selection of feedback resistance of the programmable gain amplifier" "0,1"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
bitfld.byte 0x0 3. "PVRVS,GND selection of feedback resistance of the programmable gain amplifier" "0: PGA0GND selected,1: VSS pin selected"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
bitfld.byte 0x0 3. "PVRVS,GND selection of feedback resistance of the programmable gain amplifier" "0: PGA0GND selected,1: VSS pin selected"
|
|
endif
|
|
bitfld.byte 0x0 0.--2. "PGAVG,Programmable gain amplifier amplification factor selection" "0,1,2,3,4,5,6,7"
|
|
sif (cpuis("BAT32G137*"))
|
|
group.byte 0x7++0x0
|
|
line.byte 0x0 "PGA1CTL,PGA 1 control register"
|
|
bitfld.byte 0x0 7. "PGAEN,Programmable gain amplifier operation control" "0,1"
|
|
bitfld.byte 0x0 3. "PVRVS,GND selection of feedback resistance of the programmable gain amplifier" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0.--2. "PGAVG,Programmable gain amplifier amplification factor selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
group.byte 0x7++0x0
|
|
line.byte 0x0 "PGA1CTL,PGA 1 control register"
|
|
bitfld.byte 0x0 7. "PGAEN,Programmable gain amplifier operation control" "0,1"
|
|
bitfld.byte 0x0 3. "PVRVS,GND selection of feedback resistance of the programmable gain amplifier" "0: VSS pin selected,1: PGA0GND selected"
|
|
newline
|
|
bitfld.byte 0x0 0.--2. "PGAVG,Programmable gain amplifier amplification factor selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
group.byte 0x7++0x0
|
|
line.byte 0x0 "PGA1CTL,PGA 1 control register"
|
|
bitfld.byte 0x0 7. "PGAEN,Programmable gain amplifier operation control" "0,1"
|
|
bitfld.byte 0x0 3. "PVRVS,GND selection of feedback resistance of the programmable gain amplifier" "0: VSS pin selected,1: PGA0GND selected"
|
|
newline
|
|
bitfld.byte 0x0 0.--2. "PGAVG,Programmable gain amplifier amplification factor selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
tree.end
|
|
tree "PORT (Port Functions)"
|
|
base ad:0x40040000
|
|
sif (cpuis("BAT32G157*"))
|
|
group.word 0x0++0x7
|
|
line.word 0x0 "PA,Port register A"
|
|
line.word 0x2 "PB,Port register B"
|
|
line.word 0x4 "PC,Port register C"
|
|
line.word 0x6 "PD,Port register D"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "PH,Port register H"
|
|
group.word 0x60++0x7
|
|
line.word 0x0 "PSETA,Port set register A"
|
|
line.word 0x2 "PSETB,Port set register B"
|
|
line.word 0x4 "PSETC,Port set register C"
|
|
line.word 0x6 "PSETD,Port set register D"
|
|
group.word 0x6E++0x9
|
|
line.word 0x0 "PSETH,Port set register H"
|
|
line.word 0x2 "PCLRA,Port clear register A"
|
|
line.word 0x4 "PCLRB,Port clear register B"
|
|
line.word 0x6 "PCLRC,Port clear register C"
|
|
line.word 0x8 "PCLRD,Port clear register D"
|
|
group.word 0x7E++0x9
|
|
line.word 0x0 "PCLRH,Port clear register H"
|
|
line.word 0x2 "PREADA,Port read register A"
|
|
line.word 0x4 "PREADB,Port read register B"
|
|
line.word 0x6 "PREADC,Port read register C"
|
|
line.word 0x8 "PREADD,Port read register D"
|
|
group.word 0x8E++0x1
|
|
line.word 0x0 "PREADH,Port read register H"
|
|
group.byte 0x47D++0x1
|
|
line.byte 0x0 "USBPMR,USB port configuration register"
|
|
bitfld.byte 0x0 0.--1. "DMPMR,USB_DP and USB_DM pin function select" "0: PA07 and PA08 did not use as USB pins,?,?,3: PA07 used as USB_DP and PA08 used as USB_DM"
|
|
line.byte 0x1 "USBPRCR,USB port configuration protect register"
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
group.word 0x10++0x7
|
|
line.word 0x0 "PMA,Port mode register A"
|
|
line.word 0x2 "PMB,Port mode register B"
|
|
line.word 0x4 "PMC,Port mode register C"
|
|
line.word 0x6 "PMD,Port mode register D"
|
|
group.word 0x1E++0x9
|
|
line.word 0x0 "PMH,Port mode register H"
|
|
line.word 0x2 "PUA,Pull-up resistor option register A"
|
|
line.word 0x4 "PUB,Pull-up resistor option register B"
|
|
line.word 0x6 "PUC,Pull-up resistor option register C"
|
|
line.word 0x8 "PUD,Pull-up resistor option register D"
|
|
group.word 0x2E++0x9
|
|
line.word 0x0 "PUH,Pull-up resistor option register H"
|
|
line.word 0x2 "PDA,Pull-down resistor option register A"
|
|
line.word 0x4 "PDB,Pull-down resistor option register B"
|
|
line.word 0x6 "PDC,Pull-down resistor option register C"
|
|
line.word 0x8 "PDD,Pull-down resistor option register D"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "POMA,Port output mode register A"
|
|
line.word 0x2 "POMB,Port output mode register B"
|
|
line.word 0x4 "POMC,Port output mode register C"
|
|
line.word 0x6 "POMD,Port output mode register D"
|
|
group.word 0x4E++0x9
|
|
line.word 0x0 "POMH,Port output mode register H"
|
|
line.word 0x2 "PMCA,Port mode control register A"
|
|
line.word 0x4 "PMCB,Port mode control register B"
|
|
line.word 0x6 "PMCC,Port mode control register C"
|
|
line.word 0x8 "PMCD,Port mode control register D"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
group.byte 0x30++0x1
|
|
line.byte 0x0 "PU0,Pull-up resistor option register 0"
|
|
line.byte 0x1 "PU1,Pull-up resistor option register 1"
|
|
group.byte 0x33++0x4
|
|
line.byte 0x0 "PU3,Pull-up resistor option register 3"
|
|
line.byte 0x1 "PU4,Pull-up resistor option register 4"
|
|
line.byte 0x2 "PU5,Pull-up resistor option register 5"
|
|
line.byte 0x3 "PU6,Pull-up resistor option register 6"
|
|
line.byte 0x4 "PU7,Pull-up resistor option register 7"
|
|
group.byte 0x3A++0x4
|
|
line.byte 0x0 "PU10,Pull-up resistor option register 10"
|
|
line.byte 0x1 "PU11,Pull-up resistor option register 11"
|
|
line.byte 0x2 "PU12,Pull-up resistor option register 12"
|
|
line.byte 0x3 "PU13,Pull-up resistor option register 13"
|
|
line.byte 0x4 "PU14,Pull-up resistor option register 14"
|
|
group.byte 0x40++0x1
|
|
line.byte 0x0 "PIM0,Port input mode register 0"
|
|
line.byte 0x1 "PIM1,Port input mode register 1"
|
|
group.byte 0x43++0x2
|
|
line.byte 0x0 "PIM3,Port input mode register 3"
|
|
line.byte 0x1 "PIM4,Port input mode register 4"
|
|
line.byte 0x2 "PIM5,Port input mode register 5"
|
|
group.byte 0x47++0x0
|
|
line.byte 0x0 "PIM7,Port input mode register 7"
|
|
group.byte 0x4E++0x0
|
|
line.byte 0x0 "PIM14,Port input mode register 14"
|
|
group.byte 0x50++0x1
|
|
line.byte 0x0 "POM0,Port output mode register 0"
|
|
line.byte 0x1 "POM1,Port output mode register 1"
|
|
group.byte 0x53++0x2
|
|
line.byte 0x0 "POM3,Port output mode register 3"
|
|
line.byte 0x1 "POM4,Port output mode register 4"
|
|
line.byte 0x2 "POM5,Port output mode register 5"
|
|
group.byte 0x57++0x0
|
|
line.byte 0x0 "POM7,Port output mode register 7"
|
|
group.byte 0x5E++0x0
|
|
line.byte 0x0 "POM14,Port output mode register 14"
|
|
group.byte 0x60++0x2
|
|
line.byte 0x0 "PMC0,Port mode control register 0"
|
|
line.byte 0x1 "PMC1,Port mode control register 1"
|
|
line.byte 0x2 "PMC2,Port mode control register 2"
|
|
group.byte 0x6A++0x0
|
|
line.byte 0x0 "PMC10,Port mode control register 10"
|
|
group.byte 0x6C++0x3
|
|
line.byte 0x0 "PMC12,Port mode control register 12"
|
|
line.byte 0x1 "PMC13,Port mode control register 13"
|
|
line.byte 0x2 "PMC14,Port mode control register 14"
|
|
line.byte 0x3 "PMC15,Port mode control register 15"
|
|
group.byte 0x80++0x7
|
|
line.byte 0x0 "PSET0,Port set register 0"
|
|
line.byte 0x1 "PSET1,Port set register 1"
|
|
line.byte 0x2 "PSET2,Port set register 2"
|
|
line.byte 0x3 "PSET3,Port set register 3"
|
|
line.byte 0x4 "PSET4,Port set register 4"
|
|
line.byte 0x5 "PSET5,Port set register 5"
|
|
line.byte 0x6 "PSET6,Port set register 6"
|
|
line.byte 0x7 "PSET7,Port set register 7"
|
|
group.byte 0x8A++0xD
|
|
line.byte 0x0 "PSET10,Port set register 10"
|
|
line.byte 0x1 "PSET11,Port set register 11"
|
|
line.byte 0x2 "PSET12,Port set register 12"
|
|
line.byte 0x3 "PSET13,Port set register 13"
|
|
line.byte 0x4 "PSET14,Port set register 14"
|
|
line.byte 0x5 "PSET15,Port set register 15"
|
|
line.byte 0x6 "PCLR0,Port clear register 0"
|
|
line.byte 0x7 "PCLR1,Port clear register 1"
|
|
line.byte 0x8 "PCLR2,Port clear register 2"
|
|
line.byte 0x9 "PCLR3,Port clear register 3"
|
|
line.byte 0xA "PCLR4,Port clear register 4"
|
|
line.byte 0xB "PCLR5,Port clear register 5"
|
|
line.byte 0xC "PCLR6,Port clear register 6"
|
|
line.byte 0xD "PCLR7,Port clear register 7"
|
|
group.byte 0x9A++0xD
|
|
line.byte 0x0 "PCLR10,Port clear register 10"
|
|
line.byte 0x1 "PCLR11,Port clear register 11"
|
|
line.byte 0x2 "PCLR12,Port clear register 12"
|
|
line.byte 0x3 "PCLR13,Port clear register 13"
|
|
line.byte 0x4 "PCLR14,Port clear register 14"
|
|
line.byte 0x5 "PCLR15,Port clear register 15"
|
|
line.byte 0x6 "PREAD0,Port read register 0"
|
|
line.byte 0x7 "PREAD1,Port read register 1"
|
|
line.byte 0x8 "PREAD2,Port read register 2"
|
|
line.byte 0x9 "PREAD3,Port read register 3"
|
|
line.byte 0xA "PREAD4,Port read register 4"
|
|
line.byte 0xB "PREAD5,Port read register 5"
|
|
line.byte 0xC "PREAD6,Port read register 6"
|
|
line.byte 0xD "PREAD7,Port read register 7"
|
|
group.byte 0xAA++0x5
|
|
line.byte 0x0 "PREAD10,Port read register 10"
|
|
line.byte 0x1 "PREAD11,Port read register 11"
|
|
line.byte 0x2 "PREAD12,Port read register 12"
|
|
line.byte 0x3 "PREAD13,Port read register 13"
|
|
line.byte 0x4 "PREAD14,Port read register 14"
|
|
line.byte 0x5 "PREAD15,Port read register 15"
|
|
group.byte 0x877++0x0
|
|
line.byte 0x0 "PIOR0,Peripheral I/O redirection register 0"
|
|
group.byte 0x879++0x0
|
|
line.byte 0x0 "PIOR1,Peripheral I/O redirection register 1"
|
|
group.byte 0x87C++0x1
|
|
line.byte 0x0 "PIOR3,Peripheral I/O redirection register 3"
|
|
line.byte 0x1 "GDIDIS,Global digital input disable register"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
group.byte 0x30++0x1
|
|
line.byte 0x0 "PU0,Pull-up resistor option register 0"
|
|
line.byte 0x1 "PU1,Pull-up resistor option register 1"
|
|
group.byte 0x33++0x5
|
|
line.byte 0x0 "PU3,Pull-up resistor option register 3"
|
|
line.byte 0x1 "PU4,Pull-up resistor option register 4"
|
|
line.byte 0x2 "PU5,Pull-up resistor option register 5"
|
|
line.byte 0x3 "PU6,Pull-up resistor option register 6"
|
|
line.byte 0x4 "PU7,Pull-up resistor option register 7"
|
|
line.byte 0x5 "PU8,Pull-up resistor option register 8"
|
|
group.byte 0x3A++0x4
|
|
line.byte 0x0 "PU10,Pull-up resistor option register 10"
|
|
line.byte 0x1 "PU11,Pull-up resistor option register 11"
|
|
line.byte 0x2 "PU12,Pull-up resistor option register 12"
|
|
line.byte 0x3 "PU13,Pull-up resistor option register 13"
|
|
line.byte 0x4 "PU14,Pull-up resistor option register 14"
|
|
group.byte 0x40++0x1
|
|
line.byte 0x0 "PIM0,Port input mode register 0"
|
|
line.byte 0x1 "PIM1,Port input mode register 1"
|
|
group.byte 0x43++0x2
|
|
line.byte 0x0 "PIM3,Port input mode register 3"
|
|
line.byte 0x1 "PIM4,Port input mode register 4"
|
|
line.byte 0x2 "PIM5,Port input mode register 5"
|
|
group.byte 0x47++0x1
|
|
line.byte 0x0 "PIM7,Port input mode register 7"
|
|
line.byte 0x1 "PIM8,Port input mode register 8"
|
|
group.byte 0x4E++0x0
|
|
line.byte 0x0 "PIM14,Port input mode register 14"
|
|
group.byte 0x50++0x1
|
|
line.byte 0x0 "POM0,Port output mode register 0"
|
|
line.byte 0x1 "POM1,Port output mode register 1"
|
|
group.byte 0x53++0x2
|
|
line.byte 0x0 "POM3,Port output mode register 3"
|
|
line.byte 0x1 "POM4,Port output mode register 4"
|
|
line.byte 0x2 "POM5,Port output mode register 5"
|
|
group.byte 0x57++0x1
|
|
line.byte 0x0 "POM7,Port output mode register 7"
|
|
line.byte 0x1 "POM8,Port output mode register 8"
|
|
group.byte 0x5E++0x0
|
|
line.byte 0x0 "POM14,Port output mode register 14"
|
|
group.byte 0x60++0x2
|
|
line.byte 0x0 "PMC0,Port mode control register 0"
|
|
line.byte 0x1 "PMC1,Port mode control register 1"
|
|
line.byte 0x2 "PMC2,Port mode control register 2"
|
|
group.byte 0x6A++0x0
|
|
line.byte 0x0 "PMC10,Port mode control register 10"
|
|
group.byte 0x6C++0x3
|
|
line.byte 0x0 "PMC12,Port mode control register 12"
|
|
line.byte 0x1 "PMC13,Port mode control register 13"
|
|
line.byte 0x2 "PMC14,Port mode control register 14"
|
|
line.byte 0x3 "PMC15,Port mode control register 15"
|
|
group.byte 0x80++0x8
|
|
line.byte 0x0 "PSET0,Port set register 0"
|
|
line.byte 0x1 "PSET1,Port set register 1"
|
|
line.byte 0x2 "PSET2,Port set register 2"
|
|
line.byte 0x3 "PSET3,Port set register 3"
|
|
line.byte 0x4 "PSET4,Port set register 4"
|
|
line.byte 0x5 "PSET5,Port set register 5"
|
|
line.byte 0x6 "PSET6,Port set register 6"
|
|
line.byte 0x7 "PSET7,Port set register 7"
|
|
line.byte 0x8 "PSET8,Port set register 8"
|
|
group.byte 0x8A++0xE
|
|
line.byte 0x0 "PSET10,Port set register 10"
|
|
line.byte 0x1 "PSET11,Port set register 11"
|
|
line.byte 0x2 "PSET12,Port set register 12"
|
|
line.byte 0x3 "PSET13,Port set register 13"
|
|
line.byte 0x4 "PSET14,Port set register 14"
|
|
line.byte 0x5 "PSET15,Port set register 15"
|
|
line.byte 0x6 "PCLR0,Port clear register 0"
|
|
line.byte 0x7 "PCLR1,Port clear register 1"
|
|
line.byte 0x8 "PCLR2,Port clear register 2"
|
|
line.byte 0x9 "PCLR3,Port clear register 3"
|
|
line.byte 0xA "PCLR4,Port clear register 4"
|
|
line.byte 0xB "PCLR5,Port clear register 5"
|
|
line.byte 0xC "PCLR6,Port clear register 6"
|
|
line.byte 0xD "PCLR7,Port clear register 7"
|
|
line.byte 0xE "PCLR8,Port clear register 8"
|
|
group.byte 0x9A++0xE
|
|
line.byte 0x0 "PCLR10,Port clear register 10"
|
|
line.byte 0x1 "PCLR11,Port clear register 11"
|
|
line.byte 0x2 "PCLR12,Port clear register 12"
|
|
line.byte 0x3 "PCLR13,Port clear register 13"
|
|
line.byte 0x4 "PCLR14,Port clear register 14"
|
|
line.byte 0x5 "PCLR15,Port clear register 15"
|
|
line.byte 0x6 "PREAD0,Port read register 0"
|
|
line.byte 0x7 "PREAD1,Port read register 1"
|
|
line.byte 0x8 "PREAD2,Port read register 2"
|
|
line.byte 0x9 "PREAD3,Port read register 3"
|
|
line.byte 0xA "PREAD4,Port read register 4"
|
|
line.byte 0xB "PREAD5,Port read register 5"
|
|
line.byte 0xC "PREAD6,Port read register 6"
|
|
line.byte 0xD "PREAD7,Port read register 7"
|
|
line.byte 0xE "PREAD8,Port read register 8"
|
|
group.byte 0xAA++0x5
|
|
line.byte 0x0 "PREAD10,Port read register 10"
|
|
line.byte 0x1 "PREAD11,Port read register 11"
|
|
line.byte 0x2 "PREAD12,Port read register 12"
|
|
line.byte 0x3 "PREAD13,Port read register 13"
|
|
line.byte 0x4 "PREAD14,Port read register 14"
|
|
line.byte 0x5 "PREAD15,Port read register 15"
|
|
group.byte 0x877++0x0
|
|
line.byte 0x0 "PIOR0,Peripheral I/O redirection register 0"
|
|
group.byte 0x879++0x0
|
|
line.byte 0x0 "PIOR1,Peripheral I/O redirection register 1"
|
|
group.byte 0x87C++0x1
|
|
line.byte 0x0 "PIOR3,Peripheral I/O redirection register 3"
|
|
line.byte 0x1 "GDIDIS,Global digital input disable register"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
group.byte 0x300++0x7
|
|
line.byte 0x0 "P0,Port register 0"
|
|
line.byte 0x1 "P1,Port register 1"
|
|
line.byte 0x2 "P2,Port register 2"
|
|
line.byte 0x3 "P3,Port register 3"
|
|
line.byte 0x4 "P4,Port register 4"
|
|
line.byte 0x5 "P5,Port register 5"
|
|
line.byte 0x6 "P6,Port register 6"
|
|
line.byte 0x7 "P7,Port register 7"
|
|
group.byte 0x30A++0x5
|
|
line.byte 0x0 "P10,Port register 10"
|
|
line.byte 0x1 "P11,Port register 11"
|
|
line.byte 0x2 "P12,Port register 12"
|
|
line.byte 0x3 "P13,Port register 13"
|
|
line.byte 0x4 "P14,Port register 14"
|
|
line.byte 0x5 "P15,Port register 15"
|
|
group.byte 0x875++0x0
|
|
line.byte 0x0 "PIOR2,Peripheral I/O redirection register 2"
|
|
group.byte 0x87B++0x0
|
|
line.byte 0x0 "PMS,Port mode select register"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
group.byte 0x300++0x8
|
|
line.byte 0x0 "P0,Port register 0"
|
|
line.byte 0x1 "P1,Port register 1"
|
|
line.byte 0x2 "P2,Port register 2"
|
|
line.byte 0x3 "P3,Port register 3"
|
|
line.byte 0x4 "P4,Port register 4"
|
|
line.byte 0x5 "P5,Port register 5"
|
|
line.byte 0x6 "P6,Port register 6"
|
|
line.byte 0x7 "P7,Port register 7"
|
|
line.byte 0x8 "P8,Port register 8"
|
|
group.byte 0x30A++0x5
|
|
line.byte 0x0 "P10,Port register 10"
|
|
line.byte 0x1 "P11,Port register 11"
|
|
line.byte 0x2 "P12,Port register 12"
|
|
line.byte 0x3 "P13,Port register 13"
|
|
line.byte 0x4 "P14,Port register 14"
|
|
line.byte 0x5 "P15,Port register 15"
|
|
group.byte 0x875++0x0
|
|
line.byte 0x0 "PIOR2,Peripheral I/O redirection register 2"
|
|
group.byte 0x87B++0x0
|
|
line.byte 0x0 "PMS,Port mode select register"
|
|
endif
|
|
sif (cpuis("BAT32G137*"))
|
|
group.byte 0x320++0x7
|
|
line.byte 0x0 "PM0,Port mode register 0"
|
|
line.byte 0x1 "PM1,Port mode register 1"
|
|
line.byte 0x2 "PM2,Port mode register 2"
|
|
line.byte 0x3 "PM3,Port mode register 3"
|
|
line.byte 0x4 "PM4,Port mode register 4"
|
|
line.byte 0x5 "PM5,Port mode register 5"
|
|
line.byte 0x6 "PM6,Port mode register 6"
|
|
line.byte 0x7 "PM7,Port mode register 7"
|
|
group.byte 0x32C++0x2
|
|
line.byte 0x0 "PM12,Port mode register 12"
|
|
line.byte 0x1 "PM13,Port mode register 13"
|
|
line.byte 0x2 "PM14,Port mode register 14"
|
|
group.byte 0x300++0x7
|
|
line.byte 0x0 "P0,Port register 0"
|
|
line.byte 0x1 "P1,Port register 1"
|
|
line.byte 0x2 "P2,Port register 2"
|
|
line.byte 0x3 "P3,Port register 3"
|
|
line.byte 0x4 "P4,Port register 4"
|
|
line.byte 0x5 "P5,Port register 5"
|
|
line.byte 0x6 "P6,Port register 6"
|
|
line.byte 0x7 "P7,Port register 7"
|
|
group.byte 0x30C++0x2
|
|
line.byte 0x0 "P12,Port register 12"
|
|
line.byte 0x1 "P13,Port register 13"
|
|
line.byte 0x2 "P14,Port register 14"
|
|
group.byte 0x30++0x1
|
|
line.byte 0x0 "PU0,Pull-up resistor option register 0"
|
|
line.byte 0x1 "PU1,Pull-up resistor option register 1"
|
|
group.byte 0x33++0x2
|
|
line.byte 0x0 "PU3,Pull-up resistor option register 3"
|
|
line.byte 0x1 "PU4,Pull-up resistor option register 4"
|
|
line.byte 0x2 "PU5,Pull-up resistor option register 5"
|
|
group.byte 0x37++0x0
|
|
line.byte 0x0 "PU7,Pull-up resistor option register 7"
|
|
group.byte 0x3C++0x2
|
|
line.byte 0x0 "PU12,Pull-up resistor option register 12"
|
|
line.byte 0x1 "PU13,Pull-up resistor option register 13"
|
|
line.byte 0x2 "PU14,Pull-up resistor option register 14"
|
|
group.byte 0x40++0x1
|
|
line.byte 0x0 "PIM0,Port input mode register 0"
|
|
line.byte 0x1 "PIM1,Port input mode register 1"
|
|
group.byte 0x43++0x0
|
|
line.byte 0x0 "PIM3,Port input mode register 3"
|
|
group.byte 0x45++0x0
|
|
line.byte 0x0 "PIM5,Port input mode register 5"
|
|
group.byte 0x47++0x0
|
|
line.byte 0x0 "PIM7,Port input mode register 7"
|
|
group.byte 0x50++0x1
|
|
line.byte 0x0 "POM0,Port output mode register 0"
|
|
line.byte 0x1 "POM1,Port output mode register 1"
|
|
group.byte 0x53++0x0
|
|
line.byte 0x0 "POM3,Port output mode register 3"
|
|
group.byte 0x55++0x0
|
|
line.byte 0x0 "POM5,Port output mode register 5"
|
|
group.byte 0x57++0x0
|
|
line.byte 0x0 "POM7,Port output mode register 7"
|
|
group.byte 0x60++0x2
|
|
line.byte 0x0 "PMC0,Port mode control register 0"
|
|
line.byte 0x1 "PMC1,Port mode control register 1"
|
|
line.byte 0x2 "PMC2,Port mode control register 2"
|
|
group.byte 0x6C++0x0
|
|
line.byte 0x0 "PMC12,Port mode control register 12"
|
|
group.byte 0x6E++0x0
|
|
line.byte 0x0 "PMC14,Port mode control register 14"
|
|
group.byte 0x877++0x0
|
|
line.byte 0x0 "PIOR0,Peripheral I/O redirection register 0"
|
|
group.byte 0x879++0x0
|
|
line.byte 0x0 "PIOR1,Peripheral I/O redirection register 1"
|
|
group.byte 0x875++0x0
|
|
line.byte 0x0 "PIOR2,Peripheral I/O redirection register 2"
|
|
group.byte 0x87C++0x0
|
|
line.byte 0x0 "PIOR3,Peripheral I/O redirection register 3"
|
|
group.byte 0x87B++0x0
|
|
line.byte 0x0 "PMS,Port mode select register"
|
|
group.byte 0x87D++0x0
|
|
line.byte 0x0 "GDIDIS,Global digital input disable register"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
group.byte 0x320++0x7
|
|
line.byte 0x0 "PM0,Port mode register 0"
|
|
line.byte 0x1 "PM1,Port mode register 1"
|
|
line.byte 0x2 "PM2,Port mode register 2"
|
|
line.byte 0x3 "PM3,Port mode register 3"
|
|
line.byte 0x4 "PM4,Port mode register 4"
|
|
line.byte 0x5 "PM5,Port mode register 5"
|
|
line.byte 0x6 "PM6,Port mode register 6"
|
|
line.byte 0x7 "PM7,Port mode register 7"
|
|
group.byte 0x32A++0x5
|
|
line.byte 0x0 "PM10,Port mode register 10"
|
|
line.byte 0x1 "PM11,Port mode register 11"
|
|
line.byte 0x2 "PM12,Port mode register 12"
|
|
line.byte 0x3 "PM13,Port mode register 13"
|
|
line.byte 0x4 "PM14,Port mode register 14"
|
|
line.byte 0x5 "PM15,Port mode register 15"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
group.byte 0x320++0x8
|
|
line.byte 0x0 "PM0,Port mode register 0"
|
|
line.byte 0x1 "PM1,Port mode register 1"
|
|
line.byte 0x2 "PM2,Port mode register 2"
|
|
line.byte 0x3 "PM3,Port mode register 3"
|
|
line.byte 0x4 "PM4,Port mode register 4"
|
|
line.byte 0x5 "PM5,Port mode register 5"
|
|
line.byte 0x6 "PM6,Port mode register 6"
|
|
line.byte 0x7 "PM7,Port mode register 7"
|
|
line.byte 0x8 "PM8,Port mode register 8"
|
|
group.byte 0x32A++0x5
|
|
line.byte 0x0 "PM10,Port mode register 10"
|
|
line.byte 0x1 "PM11,Port mode register 11"
|
|
line.byte 0x2 "PM12,Port mode register 12"
|
|
line.byte 0x3 "PM13,Port mode register 13"
|
|
line.byte 0x4 "PM14,Port mode register 14"
|
|
line.byte 0x5 "PM15,Port mode register 15"
|
|
group.byte 0x874++0x0
|
|
line.byte 0x0 "PIOR4,Peripheral I/O redirection register 3"
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
group.byte 0x900++0x13
|
|
line.byte 0x0 "PB00CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "PH04CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x2 "PH03CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x2 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x3 "PH02CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x3 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x4 "PH01CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x4 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x5 "PC14CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x5 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x6 "PC15CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x6 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x7 "PC08CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x7 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x8 "PC09CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x8 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x9 "PC10CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x9 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xA "PC11CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xA 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xB "PA00CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xB 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xC "PA01CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xC 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xD "PA02CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xD 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xE "PA03CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xE 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xF "PD07CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xF 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x10 "PD08CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x10 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x11 "PD09CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x11 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x12 "PD10CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x12 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x13 "PD11CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x13 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x920++0x13
|
|
line.byte 0x0 "PC03CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "PC04CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x2 "PC05CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x2 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x3 "PC06CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x3 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x4 "PC07CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x4 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x5 "PC12CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x5 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x6 "PC13CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x6 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x7 "PA04CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x7 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x8 "PA05CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x8 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x9 "PA06CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x9 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xA "PA07CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xA 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xB "PA08CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xB 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xC "PA09CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xC 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xD "PA10CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xD 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xE "PD00CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xE 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xF "PD01CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xF 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x10 "PD12CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x10 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x11 "PD13CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x11 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x12 "PD14CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x12 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x13 "PD15CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x13 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x940++0x13
|
|
line.byte 0x0 "PB01CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x0 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x1 "PB02CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x1 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x2 "PB03CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x2 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x3 "PB04CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x3 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x4 "PB05CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x4 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x5 "PB06CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x5 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x6 "PB07CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x6 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x7 "PB08CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x7 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x8 "PC00CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x8 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x9 "PC01CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x9 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xA "PC02CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xA 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xB "PA11CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xB 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xC "PA12CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xC 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xD "PA13CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xD 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xE "PA14CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xE 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0xF "PD02CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0xF 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x10 "PD03CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x10 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x11 "PD04CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x11 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x12 "PD05CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x12 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
line.byte 0x13 "PD06CFG,Alterate Output Function configuration register"
|
|
hexmask.byte 0x13 0.--3. 1. "CFG,Alterate Output Function configuration register"
|
|
group.byte 0x980++0x4
|
|
line.byte 0x0 "TI00PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x0 0.--5. 1. "CFG,Alternate function pin configuration register"
|
|
line.byte 0x1 "TI01PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x1 0.--5. 1. "CFG,Alternate function pin configuration register"
|
|
line.byte 0x2 "TI02PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x2 0.--5. 1. "CFG,Alternate function pin configuration register"
|
|
line.byte 0x3 "TI03PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x3 0.--5. 1. "CFG,Alternate function pin configuration register"
|
|
line.byte 0x4 "RXD0PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x4 0.--5. 1. "CFG,Alternate function pin configuration register"
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
group.byte 0x984++0x2
|
|
line.byte 0x0 "SDI00PCFG"
|
|
line.byte 0x1 "SCLA0PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x1 0.--5. 1. "CFG,Alternate function pin configuration register"
|
|
line.byte 0x2 "SDAA0PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x2 0.--5. 1. "CFG,Alternate function pin configuration register"
|
|
group.byte 0x9A0++0x4
|
|
line.byte 0x0 "TI10PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x0 0.--5. 1. "CFG"
|
|
line.byte 0x1 "TI11PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x1 0.--5. 1. "CFG"
|
|
line.byte 0x2 "TI12PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x2 0.--5. 1. "CFG"
|
|
line.byte 0x3 "TI13PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x3 0.--5. 1. "CFG"
|
|
line.byte 0x4 "RXD1PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x4 0.--5. 1. "CFG"
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
group.byte 0x9A4++0x0
|
|
line.byte 0x0 "IRRXDPCFG"
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
group.byte 0x9A4++0x3
|
|
line.byte 0x0 "SDI10PCFG"
|
|
line.byte 0x1 "SPIHS0_SCKIPCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x1 0.--5. 1. "CFG"
|
|
line.byte 0x2 "SPIHS0_SIPCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x2 0.--5. 1. "CFG"
|
|
line.byte 0x3 "SPIHS0_MIPCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x3 0.--5. 1. "CFG"
|
|
group.byte 0x9C0++0x4
|
|
line.byte 0x0 "TI14PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x0 0.--5. 1. "CFG"
|
|
line.byte 0x1 "TI15PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x1 0.--5. 1. "CFG"
|
|
line.byte 0x2 "TI16PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x2 0.--5. 1. "CFG"
|
|
line.byte 0x3 "TI17PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x3 0.--5. 1. "CFG"
|
|
line.byte 0x4 "RXD2PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x4 0.--5. 1. "CFG"
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
group.byte 0x9C4++0x3
|
|
line.byte 0x0 "SDI20PCFG"
|
|
line.byte 0x1 "SPIHS1_NSSPCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x1 0.--5. 1. "CFG"
|
|
line.byte 0x2 "SCLA1PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x2 0.--5. 1. "CFG"
|
|
line.byte 0x3 "SDAA1PCFG,Alternate function pin configuration register"
|
|
hexmask.byte 0x3 0.--5. 1. "CFG"
|
|
group.byte 0x9E0++0x7
|
|
line.byte 0x0 "INTP0PCFG,Alternate INTP pin configuration register"
|
|
bitfld.byte 0x0 0.--2. "CFG" "0: PC00 used as INTP0 pin,1: PC01 used as INTP0 pin,2: PC02 used as INTP0 pin,3: PC03 used as INTP0 pin,4: PC04 used as INTP0 pin,5: PC05 used as INTP0 pin,6: PC06 used as INTP0 pin,7: PC07 used as INTP0 pin"
|
|
line.byte 0x1 "INTP1PCFG,Alternate INTP pin configuration register"
|
|
bitfld.byte 0x1 0.--2. "CFG" "0: PC12 used as INTP1 pin,1: PC13 used as INTP1 pin,2: PC14 used as INTP1 pin,3: PC15 used as INTP1 pin,4: PC08 used as INTP1 pin,5: PC09 used as INTP1 pin,6: PC10 used as INTP1 pin,7: PC11 used as INTP1 pin"
|
|
line.byte 0x2 "INTP2PCFG,Alternate INTP pin configuration register"
|
|
bitfld.byte 0x2 0.--2. "CFG" "0: PA00 used as INTP2 pin,1: PA01 used as INTP2 pin,2: PA02 used as INTP2 pin,3: PA03 used as INTP2 pin,4: PA11 used as INTP2 pin,5: PA12 used as INTP2 pin,6: PA13 used as INTP2 pin,7: PA14 used as INTP2 pin"
|
|
line.byte 0x3 "INTP3PCFG,Alternate INTP pin configuration register"
|
|
bitfld.byte 0x3 0.--2. "CFG" "0: PA04 used as INTP3 pin,1: PA05 used as INTP3 pin,2: PA06 used as INTP3 pin,3: PA07 used as INTP3 pin,4: PA08 used as INTP3 pin,5: PA09 used as INTP3 pin,6: PA10 used as INTP3 pin,?"
|
|
line.byte 0x4 "INTP4PCFG,Alternate INTP pin configuration register"
|
|
bitfld.byte 0x4 0.--2. "CFG" "0: PD00 used as INTP4 pin,1: PD01 used as INTP4 pin,2: PD12 used as INTP4 pin,3: PD13 used as INTP4 pin,4: PD14 used as INTP4 pin,5: PD15 used as INTP4 pin,6: PD02 used as INTP4 pin,7: PD03 used as INTP4 pin"
|
|
line.byte 0x5 "INTP5PCFG,Alternate INTP pin configuration register"
|
|
bitfld.byte 0x5 0.--2. "CFG" "0: PD04 used as INTP5 pin,1: PD05 used as INTP5 pin,2: PD06 used as INTP5 pin,3: PD07 used as INTP5 pin,4: PD08 used as INTP5 pin,5: PD09 used as INTP5 pin,6: PD10 used as INTP5 pin,7: PD11 used as INTP5 pin"
|
|
line.byte 0x6 "INTP6PCFG,Alternate INTP pin configuration register"
|
|
bitfld.byte 0x6 0.--2. "CFG" "0: PB00 used as INTP6 pin,1: PH04 used as INTP6 pin,2: PH03 used as INTP6 pin,3: PH02 used as INTP6 pin,4: PH01 used as INTP6 pin,5: PB01 used as INTP6 pin,6: PB02 used as INTP6 pin,?"
|
|
line.byte 0x7 "INTP7PCFG,Alternate INTP pin configuration register"
|
|
bitfld.byte 0x7 0.--2. "CFG" "0: PB03 used as INTP7 pin,1: PB04 used as INTP7 pin,2: PB05 used as INTP7 pin,3: PB06 used as INTP7 pin,4: PB07 used as INTP7 pin,5: PB08 used as INTP7 pin,?,?"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "QSPI (Quad SPI Interface)"
|
|
base ad:0x64000000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "SFMSMD,Transfer Mode Control Register"
|
|
bitfld.long 0x0 15. "SFMCCE,Read instruction code select" "0,1"
|
|
bitfld.long 0x0 11. "SFMOSW,Setup time adjustment for serial transmission" "0,1"
|
|
bitfld.long 0x0 10. "SFMOHW,Hold time adjustment for serial transmission" "0,1"
|
|
bitfld.long 0x0 9. "SFMOEX,Extension select for the I/O buffer output enable signal for the serial interface" "0,1"
|
|
bitfld.long 0x0 8. "SFMMD3,SPI mode select. An initial value is determined by input to CFGMD3" "0,1"
|
|
bitfld.long 0x0 7. "SFMPAE,Function select for stopping prefetch at locations other than on byte boundaries" "0,1"
|
|
bitfld.long 0x0 6. "SFMPFE,Prefetch function select" "0,1"
|
|
bitfld.long 0x0 4.--5. "SFMSE,QSSL extension function select after SPI bus access" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "SFMRM,Serial interface read mode select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SFMSSC,Chip Selection Control Register"
|
|
bitfld.long 0x4 5. "SFMSLD,QSSL signal output timing select" "0,1"
|
|
bitfld.long 0x4 4. "SFMSHD,QSSL signal release timing select" "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SFMSW,Minimum high-level width select for QSSL signal"
|
|
line.long 0x8 "SFMSKC,Clock Control Register"
|
|
bitfld.long 0x8 5. "SFMDTY,Duty ratio correction function select for the QSPCLK signal" "0,1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SFMDV,Serial interface reference cycle select"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SFMSST,Status Register"
|
|
bitfld.long 0x0 7. "PFOFF,Prefetch function operation state" "0,1"
|
|
bitfld.long 0x0 6. "PFFUL,Prefetch buffer state" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PFCNT,Number of bytes of prefetched data"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "SFMCOM,Communication Port Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SFMD,Port for direct communication with the SPI bus"
|
|
line.long 0x4 "SFMCMD,Communication Mode Control Register"
|
|
bitfld.long 0x4 0. "DCOM,Mode select for communication with the SPI bus" "0,1"
|
|
line.long 0x8 "SFMCST,Communication Status Register"
|
|
bitfld.long 0x8 8. "EROMR,ROM access detection status in direct communication mode" "0,1"
|
|
rbitfld.long 0x8 0. "COMBSY,SPI bus cycle completion state in direct communication" "0,1"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "SFMSIC,Instruction Code Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SFMCIC,Serial flash instruction code to substitute"
|
|
line.long 0x4 "SFMSAC,Address Mode Control Register"
|
|
bitfld.long 0x4 4. "SFM4BC,Default instruction code select" "0,1"
|
|
bitfld.long 0x4 0. "SFMAS,Number of address bytes select for the serial interface" "0,1"
|
|
line.long 0x8 "SFMSDC,Dummy Cycle Control Register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "SFMXD,Mode data for serial flash (control XIP mode)"
|
|
bitfld.long 0x8 7. "SFMXEN,XIP mode permission" "0,1"
|
|
rbitfld.long 0x8 6. "SFMXST,XIP mode status" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SFMDN,Number of dummy cycles select for Fast Read instructions"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "SFMSPC,SPI Protocol Control Register"
|
|
bitfld.long 0x0 4. "SFMSDE,Minimum time select for input output switch" "0,1"
|
|
bitfld.long 0x0 0.--1. "SFMSPI,SPI protocol select" "0,1,2,3"
|
|
line.long 0x4 "SFMPMD,Port Control Register"
|
|
bitfld.long 0x4 2. "SFMWPL,WP pin specification" "0,1"
|
|
group.long 0x804++0x3
|
|
line.long 0x0 "SFMCNT1,External QSPI Address Register"
|
|
hexmask.long.byte 0x0 26.--31. 1. "QSPI_EXT,Bank switching address"
|
|
group.long 0x80C++0x7
|
|
line.long 0x0 "SFMDMA,External QSPI DMA Transfer Software Trigger Register"
|
|
bitfld.long 0x0 0. "QSPIDMATRG,External QSPI DMA Transfer Software Trigger Bit" "0,1"
|
|
line.long 0x4 "SFMCRPT,External QSPI Crypto Transfer Control Register"
|
|
bitfld.long 0x4 0. "QSPICRPT,External QSPI Crypto Transfer Enable Bit" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "RST (Reset Function)"
|
|
base ad:0x40020420
|
|
rgroup.byte 0x20++0x0
|
|
line.byte 0x0 "RESF,Reset flag register"
|
|
bitfld.byte 0x0 7. "SYSRF,Internal reset request by system reset request(AIRCR.SYSRESETREQ)" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
|
bitfld.byte 0x0 4. "WDTRF,Internal reset request by watchdog timer(WDT)" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
|
newline
|
|
bitfld.byte 0x0 2. "RPERF,Internal reset request by RAM parity" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
|
bitfld.byte 0x0 1. "IAWRF,Internal reset request by illegal-memory access" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
|
newline
|
|
bitfld.byte 0x0 0. "LVIRF,Internal reset request by voltage detector" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40044F00
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "SUBCUD,Watch error correction register"
|
|
bitfld.word 0x0 15. "DEV,watch error correction timing" "0,1"
|
|
hexmask.word 0x0 0.--12. 1. "F,watch error correction value"
|
|
group.word 0x50++0x1
|
|
line.word 0x0 "ITMC,15-bit interval timer control register"
|
|
bitfld.word 0x0 15. "RINTE,15-bit interval timer operation control" "0,1"
|
|
hexmask.word 0x0 0.--14. 1. "ITCMP,15-bit interval timer compare value"
|
|
group.byte 0x52++0x6
|
|
line.byte 0x0 "SEC,Second count register"
|
|
line.byte 0x1 "MIN,Minute count register"
|
|
line.byte 0x2 "HOUR,Hour count register"
|
|
line.byte 0x3 "WEEK,Week count register"
|
|
line.byte 0x4 "DAY,Day count register"
|
|
line.byte 0x5 "MONTH,Month count register"
|
|
line.byte 0x6 "YEAR,Year count register"
|
|
group.byte 0x5A++0x4
|
|
line.byte 0x0 "ALARMWM,Alarm minute register"
|
|
line.byte 0x1 "ALARMWH,Alarm hour register"
|
|
line.byte 0x2 "ALARMWW,Alarm week register"
|
|
line.byte 0x3 "RTCC0,Real-time clock control register 0"
|
|
bitfld.byte 0x3 7. "RTCE,Real-time clock operation control" "0,1"
|
|
bitfld.byte 0x3 5. "RCLOE,RTC1HZ pin output enable" "0,1"
|
|
bitfld.byte 0x3 3. "AMPM,Selection of 12-/24-hour system" "0,1"
|
|
bitfld.byte 0x3 0.--2. "CT,Constant-period interrupt (INTRTC) selection" "0,1,2,3,4,5,6,7"
|
|
line.byte 0x4 "RTCC1,Real-time clock control register 1"
|
|
bitfld.byte 0x4 7. "WALE,Alarm operation control" "0,1"
|
|
bitfld.byte 0x4 6. "WALIE,Control of alarm interrupt (INTRTC) function operation" "0,1"
|
|
bitfld.byte 0x4 4. "WAFG,Alarm detection status flag" "0,1"
|
|
bitfld.byte 0x4 3. "RIFG,Constant-period interrupt status flag" "0,1"
|
|
bitfld.byte 0x4 1. "RWST,Wait status flag of real-time clock" "0,1"
|
|
bitfld.byte 0x4 0. "RWAIT,Wait control of real-time clock" "0,1"
|
|
tree.end
|
|
tree "SAF (High-Speed Cyclic Redundancy Check)"
|
|
base ad:0x40020100
|
|
group.byte 0x1710++0x0
|
|
line.byte 0x0 "CRC0CTL,Flash memory CRC control register"
|
|
bitfld.byte 0x0 7. "CRC0EN,Control of high-speed CRC operation" "0,1"
|
|
hexmask.byte 0x0 0.--6. 1. "FEA,High-speed CRC operation range"
|
|
group.word 0x1712++0x1
|
|
line.word 0x0 "PGCRCL,Flash memory CRC operation result register"
|
|
group.byte 0x232AC++0x0
|
|
line.byte 0x0 "CRCIN,CRC input register"
|
|
group.word 0x231FA++0x1
|
|
line.word 0x0 "CRCD,CRC data register"
|
|
group.byte 0x325++0x0
|
|
line.byte 0x0 "RPECTL,RAM parity error control register"
|
|
bitfld.byte 0x0 7. "RPERDIS,Disable RAM parity error reset" "0: Enable parity error reset,1: Disable parity error reset"
|
|
bitfld.byte 0x0 0. "RPEF,Parity error status flag" "0: No parity error has occurred,1: Parity error has occurred"
|
|
group.long 0x20378++0x3
|
|
line.long 0x0 "SFRGD,SFR guard control register"
|
|
tree.end
|
|
tree "SCI (Serial Communication Interface)"
|
|
base ad:0x0
|
|
sif (cpuis("BAT32G137*"))
|
|
tree "SCI0"
|
|
base ad:0x40041100
|
|
rgroup.word 0x0++0x7
|
|
line.word 0x0 "SSR00,Serial status register mn"
|
|
bitfld.word 0x0 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x2 "SSR01,Serial status register mn"
|
|
bitfld.word 0x2 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x4 "SSR02,Serial status register mn"
|
|
bitfld.word 0x4 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x4 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x4 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x4 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x4 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x6 "SSR03,Serial status register mn"
|
|
bitfld.word 0x6 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x6 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x6 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x6 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x6 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
group.word 0x8++0x17
|
|
line.word 0x0 "SIR00,Serial flag clear trigger register mn"
|
|
bitfld.word 0x0 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x2 "SIR01,Serial flag clear trigger register mn"
|
|
bitfld.word 0x2 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x4 "SIR02,Serial flag clear trigger register mn"
|
|
bitfld.word 0x4 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x4 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x4 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x6 "SIR03,Serial flag clear trigger register mn"
|
|
bitfld.word 0x6 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x6 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x6 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x8 "SMR00,Serial mode register mn"
|
|
bitfld.word 0x8 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x8 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x8 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x8 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0x8 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0xA "SMR01,Serial mode register mn"
|
|
bitfld.word 0xA 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0xA 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xA 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0xA 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0xA 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0xC "SMR02,Serial mode register mn"
|
|
bitfld.word 0xC 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0xC 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xC 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0xC 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0xC 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0xE "SMR03,Serial mode register mn"
|
|
bitfld.word 0xE 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0xE 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xE 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0xE 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0xE 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0x10 "SCR00,Serial communication operation setting register mn"
|
|
bitfld.word 0x10 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x10 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x10 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x10 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x10 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x10 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x10 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x10 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x10 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0x12 "SCR01,Serial communication operation setting register mn"
|
|
bitfld.word 0x12 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x12 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x12 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x12 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x12 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x12 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x12 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x12 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x12 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0x14 "SCR02,Serial communication operation setting register mn"
|
|
bitfld.word 0x14 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x14 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x14 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x14 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x14 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x14 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x14 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x14 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x14 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0x16 "SCR03,Serial communication operation setting register mn"
|
|
bitfld.word 0x16 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x16 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x16 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x16 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x16 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x16 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x16 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x16 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x16 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
rgroup.word 0x20++0x1
|
|
line.word 0x0 "SE0,Serial channel enable status register m"
|
|
bitfld.word 0x0 3. "SE03,Indication of operation enable/stop status of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "SE02,Indication of operation enable/stop status of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "SE01,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SE00,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x22++0x9
|
|
line.word 0x0 "SS0,Serial channel start register 0"
|
|
bitfld.word 0x0 3. "SS03,Operation start trigger of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "SS02,Operation start trigger of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "SS01,Operation start trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SS00,Operation start trigger of channel 0" "0,1"
|
|
line.word 0x2 "ST0,Serial channel stop register 0"
|
|
bitfld.word 0x2 3. "ST03,Operation stop trigger of channel 3" "0,1"
|
|
bitfld.word 0x2 2. "ST02,Operation stop trigger of channel 2" "0,1"
|
|
bitfld.word 0x2 1. "ST01,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "ST00,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "SPS0,Serial clock select register 0"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS01,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS00,Prescaler 0"
|
|
line.word 0x6 "SO0,Serial output register 0"
|
|
bitfld.word 0x6 11. "CKO03,Serial clock output of channel 3" "0,1"
|
|
bitfld.word 0x6 10. "CKO02,Serial clock output of channel 2" "0,1"
|
|
bitfld.word 0x6 9. "CKO01,Serial clock output of channel 1" "0,1"
|
|
bitfld.word 0x6 8. "CKO00,Serial clock output of channel 0" "0,1"
|
|
bitfld.word 0x6 3. "SO03,Serial data output of channel 3" "0,1"
|
|
bitfld.word 0x6 2. "SO02,Serial data output of channel 2" "0,1"
|
|
bitfld.word 0x6 1. "SO01,Serial data output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "SO00,Serial data output of channel 0" "0,1"
|
|
line.word 0x8 "SOE0,Serial output enable register 0"
|
|
bitfld.word 0x8 3. "SOE03,Serial output enable of channel 3" "0,1"
|
|
bitfld.word 0x8 2. "SOE02,Serial output enable of channel 2" "0,1"
|
|
bitfld.word 0x8 1. "SOE01,Serial output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "SOE00,Serial output enable of channel 0" "0,1"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "SOL0,Serial output level register 0"
|
|
bitfld.word 0x0 2. "SOL02,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x0 0. "SOL00,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x210)++0x1
|
|
line.word 0x0 "SDR0$1,Serial data register 0%s"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x244)++0x1
|
|
line.word 0x0 "SDR0$1,Serial data register 0%s"
|
|
repeat.end
|
|
group.byte 0x210++0x0
|
|
line.byte 0x0 "SIO00,SPI data register"
|
|
group.byte 0x212++0x0
|
|
line.byte 0x0 "SIO01,SPI data register"
|
|
group.byte 0x244++0x0
|
|
line.byte 0x0 "SIO10,SPI data register"
|
|
group.byte 0x246++0x0
|
|
line.byte 0x0 "SIO11,SPI data register"
|
|
group.byte 0x210++0x0
|
|
line.byte 0x0 "TXD0,UART transmit data register"
|
|
group.byte 0x212++0x0
|
|
line.byte 0x0 "RXD0,UART receive data register"
|
|
group.byte 0x244++0x0
|
|
line.byte 0x0 "TXD1,UART transmit data register"
|
|
group.byte 0x246++0x0
|
|
line.byte 0x0 "RXD1,UART receive data register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G137*"))
|
|
tree "SCI1"
|
|
base ad:0x40041540
|
|
rgroup.word 0x0++0x3
|
|
line.word 0x0 "SSR10,Serial status register mn"
|
|
bitfld.word 0x0 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x2 "SSR11,Serial status register mn"
|
|
bitfld.word 0x2 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
group.word 0x8++0x3
|
|
line.word 0x0 "SIR10,Serial flag clear trigger register mn"
|
|
bitfld.word 0x0 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x2 "SIR11,Serial flag clear trigger register mn"
|
|
bitfld.word 0x2 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "SMR10,Serial mode register mn"
|
|
bitfld.word 0x0 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x0 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x0 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x0 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0x2 "SMR11,Serial mode register mn"
|
|
bitfld.word 0x2 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x2 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x2 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x2 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0x2 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "SCR10,Serial communication operation setting register mn"
|
|
bitfld.word 0x0 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x0 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x0 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x0 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x0 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x0 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x0 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x0 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0x2 "SCR11,Serial communication operation setting register mn"
|
|
bitfld.word 0x2 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x2 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x2 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x2 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x2 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x2 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x2 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x2 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
rgroup.word 0x20++0x1
|
|
line.word 0x0 "SE1,Serial channel enable status register 1"
|
|
bitfld.word 0x0 1. "SE11,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SE10,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x22++0x9
|
|
line.word 0x0 "SS1,Serial channel start register 1"
|
|
bitfld.word 0x0 1. "SS11,Operation start trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SS10,Operation start trigger of channel 0" "0,1"
|
|
line.word 0x2 "ST1,Serial channel stop register 1"
|
|
bitfld.word 0x2 1. "ST11,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "ST10,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "SPS1,Serial clock select register 1"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS11,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS10,Prescaler 0"
|
|
line.word 0x6 "SO1,Serial output register 1"
|
|
bitfld.word 0x6 9. "CKO11,Serial clock output of channel 1" "0,1"
|
|
bitfld.word 0x6 8. "CKO10,Serial clock output of channel 0" "0,1"
|
|
bitfld.word 0x6 1. "SO11,Serial data output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "SO10,Serial data output of channel 0" "0,1"
|
|
line.word 0x8 "SOE1,Serial output enable register 1"
|
|
bitfld.word 0x8 1. "SOE11,Serial output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "SOE10,Serial output enable of channel 0" "0,1"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "SOL1,Serial output level register 1"
|
|
bitfld.word 0x0 0. "SOL10,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x208)++0x1
|
|
line.word 0x0 "SDR1$1,Serial data register 1%s"
|
|
repeat.end
|
|
group.byte 0x208++0x0
|
|
line.byte 0x0 "SIO20,SPI data register"
|
|
group.byte 0x20A++0x0
|
|
line.byte 0x0 "SIO21,SPI data register"
|
|
group.byte 0x208++0x0
|
|
line.byte 0x0 "TXD2,UART transmit data register"
|
|
group.byte 0x20A++0x0
|
|
line.byte 0x0 "RXD2,UART receive data register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "SCI0"
|
|
base ad:0x40041000
|
|
rgroup.word 0x0++0x3
|
|
line.word 0x0 "SSR00,Serial status register mn"
|
|
bitfld.word 0x0 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x2 "SSR01,Serial status register mn"
|
|
bitfld.word 0x2 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
group.word 0x4++0xB
|
|
line.word 0x0 "SIR00,Serial flag clear trigger register mn"
|
|
bitfld.word 0x0 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x2 "SIR01,Serial flag clear trigger register mn"
|
|
bitfld.word 0x2 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x4 "SMR00,Serial mode register mn"
|
|
bitfld.word 0x4 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x4 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x4 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x4 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x4 0.--2. "MD,Setting of operation mode of channel n" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "SMR01,Serial mode register mn"
|
|
bitfld.word 0x6 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x6 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x6 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x6 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x6 0.--2. "MD,Setting of operation mode of channel n" "0,1,2,3,4,5,6,7"
|
|
line.word 0x8 "SCR00,Serial communication operation setting register mn"
|
|
bitfld.word 0x8 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x8 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x8 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x8 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x8 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x8 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x8 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x8 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
hexmask.word.byte 0x8 0.--3. 1. "DLS,Setting of data length in SPI and UART modes"
|
|
line.word 0xA "SCR01,Serial communication operation setting register mn"
|
|
bitfld.word 0xA 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0xA 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0xA 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0xA 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0xA 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0xA 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0xA 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0xA 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
hexmask.word.byte 0xA 0.--3. 1. "DLS,Setting of data length in SPI and UART modes"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "SE0,Serial channel enable status register m"
|
|
bitfld.word 0x0 1. "SE01,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SE00,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x12++0x9
|
|
line.word 0x0 "SS0,Serial channel start register 0"
|
|
bitfld.word 0x0 1. "SS01,Operation start trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SS00,Operation start trigger of channel 0" "0,1"
|
|
line.word 0x2 "ST0,Serial channel stop register 0"
|
|
bitfld.word 0x2 1. "ST01,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "ST00,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "SPS0,Serial clock select register 0"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS01,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS00,Prescaler 0"
|
|
line.word 0x6 "SO0,Serial output register 0"
|
|
bitfld.word 0x6 9. "CKO01,Serial clock output of channel 1" "0,1"
|
|
bitfld.word 0x6 8. "CKO00,Serial clock output of channel 0" "0,1"
|
|
bitfld.word 0x6 1. "SO01,Serial data output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "SO00,Serial data output of channel 0" "0,1"
|
|
line.word 0x8 "SOE0,Serial output enable register 0"
|
|
bitfld.word 0x8 1. "SOE01,Serial output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "SOE00,Serial output enable of channel 0" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SOL0,Serial output level register 0"
|
|
bitfld.word 0x0 0. "SOL00,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x110)++0x1
|
|
line.word 0x0 "SDR0$1,Serial data register 0%s"
|
|
repeat.end
|
|
group.byte 0x110++0x0
|
|
line.byte 0x0 "SIO00,SPI data register"
|
|
group.byte 0x112++0x0
|
|
line.byte 0x0 "SIO01,SPI data register"
|
|
group.byte 0x110++0x0
|
|
line.byte 0x0 "TXD0,UART transmit data register"
|
|
group.byte 0x112++0x0
|
|
line.byte 0x0 "RXD0,UART receive data register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "SCI1"
|
|
base ad:0x40041200
|
|
rgroup.word 0x0++0x3
|
|
line.word 0x0 "SSR10,Serial status register mn"
|
|
bitfld.word 0x0 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x2 "SSR11,Serial status register mn"
|
|
bitfld.word 0x2 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
group.word 0x4++0xB
|
|
line.word 0x0 "SIR10,Serial flag clear trigger register mn"
|
|
bitfld.word 0x0 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x2 "SIR11,Serial flag clear trigger register mn"
|
|
bitfld.word 0x2 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x4 "SMR10,Serial mode register mn"
|
|
bitfld.word 0x4 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x4 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x4 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x4 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x4 0.--2. "MD,Setting of operation mode of channel n" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "SMR11,Serial mode register mn"
|
|
bitfld.word 0x6 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x6 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x6 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x6 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x6 0.--2. "MD,Setting of operation mode of channel n" "0,1,2,3,4,5,6,7"
|
|
line.word 0x8 "SCR10,Serial communication operation setting register mn"
|
|
bitfld.word 0x8 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x8 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x8 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x8 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x8 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x8 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x8 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x8 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
hexmask.word.byte 0x8 0.--3. 1. "DLS,Setting of data length in SPI and UART modes"
|
|
line.word 0xA "SCR11,Serial communication operation setting register mn"
|
|
bitfld.word 0xA 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0xA 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0xA 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0xA 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0xA 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0xA 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0xA 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0xA 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
hexmask.word.byte 0xA 0.--3. 1. "DLS,Setting of data length in SPI and UART modes"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "SE1,Serial channel enable status register 1"
|
|
bitfld.word 0x0 1. "SE11,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SE10,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x12++0x9
|
|
line.word 0x0 "SS1,Serial channel start register 1"
|
|
bitfld.word 0x0 1. "SS11,Operation start trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SS10,Operation start trigger of channel 0" "0,1"
|
|
line.word 0x2 "ST1,Serial channel stop register 1"
|
|
bitfld.word 0x2 1. "ST11,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "ST10,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "SPS1,Serial clock select register 1"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS11,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS10,Prescaler 0"
|
|
line.word 0x6 "SO1,Serial output register 1"
|
|
bitfld.word 0x6 9. "CKO11,Serial clock output of channel 1" "0,1"
|
|
bitfld.word 0x6 8. "CKO10,Serial clock output of channel 0" "0,1"
|
|
bitfld.word 0x6 1. "SO11,Serial data output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "SO10,Serial data output of channel 0" "0,1"
|
|
line.word 0x8 "SOE1,Serial output enable register 1"
|
|
bitfld.word 0x8 1. "SOE11,Serial output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "SOE10,Serial output enable of channel 0" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SOL1,Serial output level register 1"
|
|
bitfld.word 0x0 0. "SOL10,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x110)++0x1
|
|
line.word 0x0 "SDR1$1,Serial data register 1%s"
|
|
repeat.end
|
|
group.byte 0x110++0x0
|
|
line.byte 0x0 "SIO10,SPI data register"
|
|
group.byte 0x112++0x0
|
|
line.byte 0x0 "SIO11,SPI data register"
|
|
group.byte 0x110++0x0
|
|
line.byte 0x0 "TXD1,UART transmit data register"
|
|
group.byte 0x112++0x0
|
|
line.byte 0x0 "RXD1,UART receive data register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "SCI2"
|
|
base ad:0x40041400
|
|
rgroup.word 0x0++0x3
|
|
line.word 0x0 "SSR20,Serial status register mn"
|
|
bitfld.word 0x0 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x2 "SSR21,Serial status register mn"
|
|
bitfld.word 0x2 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
group.word 0x4++0xB
|
|
line.word 0x0 "SIR20,Serial flag clear trigger register mn"
|
|
bitfld.word 0x0 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x2 "SIR21,Serial flag clear trigger register mn"
|
|
bitfld.word 0x2 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x4 "SMR20,Serial mode register mn"
|
|
bitfld.word 0x4 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x4 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x4 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x4 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x4 0.--2. "MD,Setting of operation mode of channel n" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "SMR21,Serial mode register mn"
|
|
bitfld.word 0x6 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x6 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x6 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x6 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x6 0.--2. "MD,Setting of operation mode of channel n" "0,1,2,3,4,5,6,7"
|
|
line.word 0x8 "SCR20,Serial communication operation setting register mn"
|
|
bitfld.word 0x8 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x8 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x8 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x8 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x8 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x8 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x8 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x8 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
hexmask.word.byte 0x8 0.--3. 1. "DLS,Setting of data length in SPI and UART modes"
|
|
line.word 0xA "SCR21,Serial communication operation setting register mn"
|
|
bitfld.word 0xA 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0xA 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0xA 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0xA 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0xA 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0xA 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0xA 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0xA 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
hexmask.word.byte 0xA 0.--3. 1. "DLS,Setting of data length in SPI and UART modes"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "SE2,Serial channel enable status register 2"
|
|
bitfld.word 0x0 1. "SE21,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SE20,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x12++0x9
|
|
line.word 0x0 "SS2,Serial channel start register 2"
|
|
bitfld.word 0x0 1. "SS21,Operation start trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SS20,Operation start trigger of channel 0" "0,1"
|
|
line.word 0x2 "ST2,Serial channel stop register 2"
|
|
bitfld.word 0x2 1. "ST21,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "ST20,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "SPS2,Serial clock select register 0"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS21,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS20,Prescaler 0"
|
|
line.word 0x6 "SO2,Serial output register 0"
|
|
bitfld.word 0x6 9. "CKO11,Serial clock output of channel 1" "0,1"
|
|
bitfld.word 0x6 8. "CKO20,Serial clock output of channel 0" "0,1"
|
|
bitfld.word 0x6 1. "SO21,Serial data output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "SO20,Serial data output of channel 0" "0,1"
|
|
line.word 0x8 "SOE2,Serial output enable register 2"
|
|
bitfld.word 0x8 1. "SOE21,Serial output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "SOE20,Serial output enable of channel 0" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SOL2,Serial output level register 2"
|
|
bitfld.word 0x0 0. "SOL20,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x110)++0x1
|
|
line.word 0x0 "SDR2$1,Serial data register 2%s"
|
|
repeat.end
|
|
group.byte 0x110++0x0
|
|
line.byte 0x0 "SIO20,SPI data register"
|
|
group.byte 0x112++0x0
|
|
line.byte 0x0 "SIO21,SPI data register"
|
|
group.byte 0x110++0x0
|
|
line.byte 0x0 "TXD2,UART transmit data register"
|
|
group.byte 0x112++0x0
|
|
line.byte 0x0 "RXD2,UART receive data register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "SCI0"
|
|
base ad:0x40041100
|
|
rgroup.word 0x0++0x7
|
|
line.word 0x0 "SSR00,Serial status register mn"
|
|
bitfld.word 0x0 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x2 "SSR01,Serial status register mn"
|
|
bitfld.word 0x2 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x4 "SSR02,Serial status register mn"
|
|
bitfld.word 0x4 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x4 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x4 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x4 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x4 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x6 "SSR03,Serial status register mn"
|
|
bitfld.word 0x6 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x6 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x6 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x6 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x6 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
group.word 0x8++0x17
|
|
line.word 0x0 "SIR00,Serial flag clear trigger register mn"
|
|
bitfld.word 0x0 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x2 "SIR01,Serial flag clear trigger register mn"
|
|
bitfld.word 0x2 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x4 "SIR02,Serial flag clear trigger register mn"
|
|
bitfld.word 0x4 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x4 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x4 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x6 "SIR03,Serial flag clear trigger register mn"
|
|
bitfld.word 0x6 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x6 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x6 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x8 "SMR00,Serial mode register mn"
|
|
bitfld.word 0x8 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x8 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x8 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x8 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0x8 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0xA "SMR01,Serial mode register mn"
|
|
bitfld.word 0xA 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0xA 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xA 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0xA 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0xA 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0xC "SMR02,Serial mode register mn"
|
|
bitfld.word 0xC 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0xC 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xC 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0xC 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0xC 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0xE "SMR03,Serial mode register mn"
|
|
bitfld.word 0xE 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0xE 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xE 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0xE 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
hexmask.word.byte 0xE 0.--3. 1. "MD,Setting of operation mode of channel n"
|
|
line.word 0x10 "SCR00,Serial communication operation setting register mn"
|
|
bitfld.word 0x10 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x10 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x10 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x10 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x10 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x10 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x10 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x10 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x10 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0x12 "SCR01,Serial communication operation setting register mn"
|
|
bitfld.word 0x12 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x12 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x12 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x12 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x12 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x12 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x12 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x12 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x12 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0x14 "SCR02,Serial communication operation setting register mn"
|
|
bitfld.word 0x14 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x14 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x14 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x14 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x14 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x14 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x14 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x14 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x14 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0x16 "SCR03,Serial communication operation setting register mn"
|
|
bitfld.word 0x16 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x16 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x16 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x16 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x16 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x16 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x16 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x16 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x16 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
rgroup.word 0x20++0x1
|
|
line.word 0x0 "SE0,Serial channel enable status register m"
|
|
bitfld.word 0x0 3. "SE03,Indication of operation enable/stop status of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "SE02,Indication of operation enable/stop status of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "SE01,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SE00,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x22++0x9
|
|
line.word 0x0 "SS0,Serial channel start register 0"
|
|
bitfld.word 0x0 3. "SS03,Operation start trigger of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "SS02,Operation start trigger of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "SS01,Operation start trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SS00,Operation start trigger of channel 0" "0,1"
|
|
line.word 0x2 "ST0,Serial channel stop register 0"
|
|
bitfld.word 0x2 3. "ST03,Operation stop trigger of channel 3" "0,1"
|
|
bitfld.word 0x2 2. "ST02,Operation stop trigger of channel 2" "0,1"
|
|
bitfld.word 0x2 1. "ST01,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "ST00,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "SPS0,Serial clock select register 0"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS01,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS00,Prescaler 0"
|
|
line.word 0x6 "SO0,Serial output register 0"
|
|
bitfld.word 0x6 11. "CKO03,Serial clock output of channel 3" "0,1"
|
|
bitfld.word 0x6 10. "CKO02,Serial clock output of channel 2" "0,1"
|
|
bitfld.word 0x6 9. "CKO01,Serial clock output of channel 1" "0,1"
|
|
bitfld.word 0x6 8. "CKO00,Serial clock output of channel 0" "0,1"
|
|
bitfld.word 0x6 3. "SO03,Serial data output of channel 3" "0,1"
|
|
bitfld.word 0x6 2. "SO02,Serial data output of channel 2" "0,1"
|
|
bitfld.word 0x6 1. "SO01,Serial data output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "SO00,Serial data output of channel 0" "0,1"
|
|
line.word 0x8 "SOE0,Serial output enable register 0"
|
|
bitfld.word 0x8 3. "SOE03,Serial output enable of channel 3" "0,1"
|
|
bitfld.word 0x8 2. "SOE02,Serial output enable of channel 2" "0,1"
|
|
bitfld.word 0x8 1. "SOE01,Serial output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "SOE00,Serial output enable of channel 0" "0,1"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "SOL0,Serial output level register 0"
|
|
bitfld.word 0x0 2. "SOL02,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x0 0. "SOL00,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x210)++0x1
|
|
line.word 0x0 "SDR0$1,Serial data register 0%s"
|
|
repeat.end
|
|
group.byte 0x210++0x0
|
|
line.byte 0x0 "SIO00,SPI data register"
|
|
group.byte 0x212++0x0
|
|
line.byte 0x0 "SIO01,SPI data register"
|
|
group.byte 0x214++0x0
|
|
line.byte 0x0 "SIO10,SPI data register"
|
|
group.byte 0x216++0x0
|
|
line.byte 0x0 "SIO11,SPI data register"
|
|
group.byte 0x210++0x0
|
|
line.byte 0x0 "TXD0,UART transmit data register"
|
|
group.byte 0x212++0x0
|
|
line.byte 0x0 "RXD0,UART receive data register"
|
|
group.byte 0x214++0x0
|
|
line.byte 0x0 "TXD1,UART transmit data register"
|
|
group.byte 0x216++0x0
|
|
line.byte 0x0 "RXD1,UART receive data register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "SCI1"
|
|
base ad:0x40041400
|
|
rgroup.word 0x0++0x3
|
|
line.word 0x0 "SSR10,Serial status register mn"
|
|
bitfld.word 0x0 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x2 "SSR11,Serial status register mn"
|
|
bitfld.word 0x2 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
group.word 0x4++0xB
|
|
line.word 0x0 "SIR10,Serial flag clear trigger register mn"
|
|
bitfld.word 0x0 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x2 "SIR11,Serial flag clear trigger register mn"
|
|
bitfld.word 0x2 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x4 "SMR10,Serial mode register mn"
|
|
bitfld.word 0x4 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x4 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x4 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x4 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x4 0.--2. "MD,Setting of operation mode of channel n" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "SMR11,Serial mode register mn"
|
|
bitfld.word 0x6 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x6 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x6 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x6 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x6 0.--2. "MD,Setting of operation mode of channel n" "0,1,2,3,4,5,6,7"
|
|
line.word 0x8 "SCR10,Serial communication operation setting register mn"
|
|
bitfld.word 0x8 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x8 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x8 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x8 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x8 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x8 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x8 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x8 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
hexmask.word.byte 0x8 0.--3. 1. "DLS,Setting of data length in SPI and UART modes"
|
|
line.word 0xA "SCR11,Serial communication operation setting register mn"
|
|
bitfld.word 0xA 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0xA 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0xA 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0xA 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0xA 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0xA 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0xA 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0xA 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
hexmask.word.byte 0xA 0.--3. 1. "DLS,Setting of data length in SPI and UART modes"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "SE1,Serial channel enable status register 1"
|
|
bitfld.word 0x0 1. "SE11,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SE10,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x12++0x9
|
|
line.word 0x0 "SS1,Serial channel start register 1"
|
|
bitfld.word 0x0 1. "SS11,Operation start trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SS10,Operation start trigger of channel 0" "0,1"
|
|
line.word 0x2 "ST1,Serial channel stop register 1"
|
|
bitfld.word 0x2 1. "ST11,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "ST10,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "SPS1,Serial clock select register 1"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS11,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS10,Prescaler 0"
|
|
line.word 0x6 "SO1,Serial output register 1"
|
|
bitfld.word 0x6 9. "CKO11,Serial clock output of channel 1" "0,1"
|
|
bitfld.word 0x6 8. "CKO10,Serial clock output of channel 0" "0,1"
|
|
bitfld.word 0x6 1. "SO11,Serial data output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "SO10,Serial data output of channel 0" "0,1"
|
|
line.word 0x8 "SOE1,Serial output enable register 1"
|
|
bitfld.word 0x8 1. "SOE11,Serial output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "SOE10,Serial output enable of channel 0" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SOL1,Serial output level register 1"
|
|
bitfld.word 0x0 0. "SOL10,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x110)++0x1
|
|
line.word 0x0 "SDR1$1,Serial data register 1%s"
|
|
repeat.end
|
|
group.byte 0x110++0x0
|
|
line.byte 0x0 "SIO20,SPI data register"
|
|
group.byte 0x112++0x0
|
|
line.byte 0x0 "SIO21,SPI data register"
|
|
group.byte 0x110++0x0
|
|
line.byte 0x0 "TXD2,UART transmit data register"
|
|
group.byte 0x112++0x0
|
|
line.byte 0x0 "RXD2,UART receive data register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "SCI2"
|
|
base ad:0x40041600
|
|
rgroup.word 0x0++0x3
|
|
line.word 0x0 "SSR20,Serial status register mn"
|
|
bitfld.word 0x0 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x0 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
line.word 0x2 "SSR21,Serial status register mn"
|
|
bitfld.word 0x2 6. "TSF,Communication status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 5. "BFF,Buffer register status indication flag of channel n" "0,1"
|
|
bitfld.word 0x2 2. "FEF,Framing error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PEF,Parity error detection flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVF,Overrun error detection flag of channel n" "0,1"
|
|
group.word 0x4++0xB
|
|
line.word 0x0 "SIR20,Serial flag clear trigger register mn"
|
|
bitfld.word 0x0 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x0 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x0 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x2 "SIR21,Serial flag clear trigger register mn"
|
|
bitfld.word 0x2 2. "FECT,Clear trigger of framing error flag of channel n" "0,1"
|
|
bitfld.word 0x2 1. "PECT,Clear trigger of parity error flag of channel n" "0,1"
|
|
bitfld.word 0x2 0. "OVCT,Clear trigger of overrun error flag of channel n" "0,1"
|
|
line.word 0x4 "SMR20,Serial mode register mn"
|
|
bitfld.word 0x4 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x4 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x4 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x4 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x4 0.--2. "MD,Setting of operation mode of channel n" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "SMR21,Serial mode register mn"
|
|
bitfld.word 0x6 15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1"
|
|
bitfld.word 0x6 14. "CCS,Selection of transfer clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x6 8. "STS,Selection of start trigger source" "0,1"
|
|
bitfld.word 0x6 6. "SIS,Controls inversion of level of receive data of channel n in UART mode" "0,1"
|
|
bitfld.word 0x6 0.--2. "MD,Setting of operation mode of channel n" "0,1,2,3,4,5,6,7"
|
|
line.word 0x8 "SCR20,Serial communication operation setting register mn"
|
|
bitfld.word 0x8 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0x8 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0x8 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0x8 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0x8 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0x8 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x8 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0x8 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
line.word 0xA "SCR21,Serial communication operation setting register mn"
|
|
bitfld.word 0xA 15. "TXE,Transmission enable" "0,1"
|
|
bitfld.word 0xA 14. "RXE,Reception enable" "0,1"
|
|
bitfld.word 0xA 13. "DAP,Selection of data phase in SPI mode" "0,1"
|
|
bitfld.word 0xA 12. "CKP,Selection of clock phase in SPI mode" "0,1"
|
|
bitfld.word 0xA 10. "EOC,Mask control of error interrupt signal (INTSREx (x = 0 to 2))" "0,1"
|
|
bitfld.word 0xA 8.--9. "PTC,Setting of parity bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0xA 7. "DIR,Selection of data transfer sequence in SPI and UART modes" "0,1"
|
|
bitfld.word 0xA 4.--5. "SLC,Setting of stop bit in UART mode" "0,1,2,3"
|
|
bitfld.word 0xA 0.--1. "DLS,Setting of data length in SPI and UART modes" "0,1,2,3"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "SE2,Serial channel enable status register 2"
|
|
bitfld.word 0x0 1. "SE21,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SE20,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x12++0x9
|
|
line.word 0x0 "SS2,Serial channel start register 2"
|
|
bitfld.word 0x0 1. "SS21,Operation start trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "SS20,Operation start trigger of channel 0" "0,1"
|
|
line.word 0x2 "ST2,Serial channel stop register 2"
|
|
bitfld.word 0x2 1. "ST21,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "ST20,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "SPS2,Serial clock select register 0"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS21,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS20,Prescaler 0"
|
|
line.word 0x6 "SO2,Serial output register 0"
|
|
bitfld.word 0x6 9. "CKO21,Serial clock output of channel 1" "0,1"
|
|
bitfld.word 0x6 8. "CKO20,Serial clock output of channel 0" "0,1"
|
|
bitfld.word 0x6 1. "SO21,Serial data output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "SO20,Serial data output of channel 0" "0,1"
|
|
line.word 0x8 "SOE2,Serial output enable register 2"
|
|
bitfld.word 0x8 1. "SOE21,Serial output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "SOE20,Serial output enable of channel 0" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SOL2,Serial output level register 2"
|
|
bitfld.word 0x0 0. "SOL20,Selects inversion of the level of the transmit data of channel n in UART mode" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x110)++0x1
|
|
line.word 0x0 "SDR2$1,Serial data register 2%s"
|
|
repeat.end
|
|
group.byte 0x110++0x0
|
|
line.byte 0x0 "SIO30,SPI data register"
|
|
group.byte 0x112++0x0
|
|
line.byte 0x0 "SIO31,SPI data register"
|
|
group.byte 0x110++0x0
|
|
line.byte 0x0 "TXD3,UART transmit data register"
|
|
group.byte 0x112++0x0
|
|
line.byte 0x0 "RXD3,UART receive data register"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("BAT32G157*")||cpuis("BAT32G179*"))
|
|
tree "SPIHS (Serial Interface SPI)"
|
|
base ad:0x0
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "SPIHS0"
|
|
base ad:0x40042400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPIM0,SPI mode control register"
|
|
bitfld.long 0x0 7. "SPIE,SPI operation enable" "0,1"
|
|
bitfld.long 0x0 6. "TRMD,Transfer and Receive mode" "0,1"
|
|
bitfld.long 0x0 5. "NSSE,NSS pin enable" "0,1"
|
|
bitfld.long 0x0 4. "DIR,MSB of LSB mode select" "0,1"
|
|
bitfld.long 0x0 3. "INTMD,interrupt source select" "0,1"
|
|
bitfld.long 0x0 2. "DLS,data length control" "0,1"
|
|
bitfld.long 0x0 1. "RECMD,Receive mode selection" "0,1"
|
|
line.long 0x4 "SPIC0,SPI control register"
|
|
bitfld.long 0x4 4. "CKP,Selection of clock phase for SPI" "0,1"
|
|
bitfld.long 0x4 3. "DAP,Selection of data phase for SPI" "0,1"
|
|
bitfld.long 0x4 0.--2. "CKS,Operation clock control" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "SDRO0,Data buffer of transmission"
|
|
line.long 0xC "SDRI0,Data buffer of reception"
|
|
line.long 0x10 "SPIS0,SPI status register"
|
|
bitfld.long 0x10 1. "SDRIF,Receive buffer non-empty flag" "0,1"
|
|
bitfld.long 0x10 0. "SPTF,SPI transmission status flag" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "SPIHS1"
|
|
base ad:0x40042800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPIM1,SPI mode control register"
|
|
bitfld.long 0x0 7. "SPIE,SPI operation enable" "0,1"
|
|
bitfld.long 0x0 6. "TRMD,Transfer and Receive mode" "0,1"
|
|
bitfld.long 0x0 5. "NSSE,NSS pin enable" "0,1"
|
|
bitfld.long 0x0 4. "DIR,MSB of LSB mode select" "0,1"
|
|
bitfld.long 0x0 3. "INTMD,interrupt source select" "0,1"
|
|
bitfld.long 0x0 2. "DLS,data length control" "0,1"
|
|
bitfld.long 0x0 1. "RECMD,Receive mode selection" "0,1"
|
|
line.long 0x4 "SPIC1,SPI control register"
|
|
bitfld.long 0x4 4. "CKP,Selection of clock phase for SPI" "0,1"
|
|
bitfld.long 0x4 3. "DAP,Selection of data phase for SPI" "0,1"
|
|
bitfld.long 0x4 0.--2. "CKS,Operation clock control" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "SDRO1,Data buffer of transmission"
|
|
line.long 0xC "SDRI1,Data buffer of reception"
|
|
line.long 0x10 "SPIS1,SPI status register"
|
|
bitfld.long 0x10 1. "SDRIF,Receive buffer non-empty flag" "0,1"
|
|
bitfld.long 0x10 0. "SPTF,SPI transmission status flag" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
tree "SPIHS0"
|
|
base ad:0x40046C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPIM0,SPI mode control register"
|
|
bitfld.long 0x0 7. "SPIE,SPI operation enable" "0,1"
|
|
bitfld.long 0x0 6. "TRMD,Transfer and Receive mode" "0,1"
|
|
bitfld.long 0x0 5. "NSSE,NSS pin enable" "0,1"
|
|
bitfld.long 0x0 4. "DIR,MSB of LSB mode select" "0,1"
|
|
bitfld.long 0x0 3. "INTMD,interrupt source select" "0,1"
|
|
bitfld.long 0x0 2. "DLS,data length control" "0,1"
|
|
bitfld.long 0x0 1. "RECMD,Receive mode selection" "0,1"
|
|
line.long 0x4 "SPIC0,SPI control register"
|
|
bitfld.long 0x4 4. "CKP,Selection of clock phase for SPI" "0,1"
|
|
bitfld.long 0x4 3. "DAP,Selection of data phase for SPI" "0,1"
|
|
bitfld.long 0x4 0.--2. "CKS,Operation clock control" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "SDRO0,Data buffer of transmission"
|
|
line.long 0xC "SDRI0,Data buffer of reception"
|
|
line.long 0x10 "SPIS0,SPI status register"
|
|
bitfld.long 0x10 1. "SDRIF,Receive buffer non-empty flag" "0,1"
|
|
bitfld.long 0x10 0. "SPTF,SPI transmission status flag" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
tree "SPIHS1"
|
|
base ad:0x40047000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPIM1,SPI mode control register"
|
|
bitfld.long 0x0 7. "SPIE,SPI operation enable" "0,1"
|
|
bitfld.long 0x0 6. "TRMD,Transfer and Receive mode" "0,1"
|
|
bitfld.long 0x0 5. "NSSE,NSS pin enable" "0,1"
|
|
bitfld.long 0x0 4. "DIR,MSB of LSB mode select" "0,1"
|
|
bitfld.long 0x0 3. "INTMD,interrupt source select" "0,1"
|
|
bitfld.long 0x0 2. "DLS,data length control" "0,1"
|
|
bitfld.long 0x0 1. "RECMD,Receive mode selection" "0,1"
|
|
line.long 0x4 "SPIC1,SPI control register"
|
|
bitfld.long 0x4 4. "CKP,Selection of clock phase for SPI" "0,1"
|
|
bitfld.long 0x4 3. "DAP,Selection of data phase for SPI" "0,1"
|
|
bitfld.long 0x4 0.--2. "CKS,Operation clock control" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "SDRO1,Data buffer of transmission"
|
|
line.long 0xC "SDRI1,Data buffer of reception"
|
|
line.long 0x10 "SPIS1,SPI status register"
|
|
bitfld.long 0x10 1. "SDRIF,Receive buffer non-empty flag" "0,1"
|
|
bitfld.long 0x10 0. "SPTF,SPI transmission status flag" "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "SSI (Serial Sound Interface)"
|
|
base ad:0x40090000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "SSICR,Control Register"
|
|
bitfld.long 0x0 30. "CKS,Select an Audio Clock for Master Mode Communication" "0,1"
|
|
bitfld.long 0x0 29. "TUIEN,Transmit Underflow Interrupt Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "TOIEN,Transmit Overflow Interrupt Output Enable" "0,1"
|
|
bitfld.long 0x0 27. "RUIEN,Receive Underflow Interrupt Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "ROIEN,Receive Overflow Interrupt Output Enable" "0,1"
|
|
bitfld.long 0x0 25. "IIEN,Idle Mode Interrupt Output Enable" "0,1"
|
|
bitfld.long 0x0 19.--21. "DWL,Select Data Word Length" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "SWL,Select System Word Length" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 14. "MST,Master Enable" "0,1"
|
|
bitfld.long 0x0 13. "BCKP,Select Bit Clock Polarity" "0,1"
|
|
bitfld.long 0x0 12. "LRCKP,Select the Initial Value and Polarity of LR Clock/Frame Synchronization Signal" "0,1"
|
|
bitfld.long 0x0 11. "SPDP,Select Serial Padding Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SDTA,Select Serial Data Alignment" "0,1"
|
|
bitfld.long 0x0 9. "PDTA,Select Placement Data Alignment" "0,1"
|
|
bitfld.long 0x0 8. "DEL,Select Serial Data Delay" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CKDV,Select Bit Clock Division Ratio"
|
|
bitfld.long 0x0 3. "MUEN,Mute Enable" "0,1"
|
|
bitfld.long 0x0 1. "TEN,Transmission Enable" "0,1"
|
|
bitfld.long 0x0 0. "REN,Reception Enable" "0,1"
|
|
line.long 0x4 "SSISR,Status Register"
|
|
bitfld.long 0x4 29. "TUIRQ,Transmit Underflow Error Status Flag" "0,1"
|
|
bitfld.long 0x4 28. "TOIRQ,Transmit Overflow Error Status Flag" "0,1"
|
|
bitfld.long 0x4 27. "RUIRQ,Receive Underflow Error Status Flag" "0,1"
|
|
bitfld.long 0x4 26. "ROIRQ,Receive Overflow Error Status Flag" "0,1"
|
|
bitfld.long 0x4 25. "IIRQ,Idle Mode Status Flag" "0,1"
|
|
group.long 0x10++0x17
|
|
line.long 0x0 "SSIFCR,FIFO Control Register"
|
|
bitfld.long 0x0 31. "AUCKE,AUDIO_MCK Enable in Master Mode Communication" "0,1"
|
|
bitfld.long 0x0 16. "SSIRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 11. "BSW,Byte Swap Enable" "0,1"
|
|
bitfld.long 0x0 4. "TIE,Transmit Data Empty Interrupt Output Enable" "0,1"
|
|
bitfld.long 0x0 3. "RIE,Receive Data Full Interrupt Output Enable" "0,1"
|
|
bitfld.long 0x0 1. "TFRST,Transmit FIFO Data Register Reset" "0,1"
|
|
bitfld.long 0x0 0. "RFRST,Receive FIFO Data Register Reset" "0,1"
|
|
line.long 0x4 "SSIFSR,FIFO Status Register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "TDC,Number of Transmit FIFO Data Indication Flag"
|
|
bitfld.long 0x4 15. "TDE,Transmit Data Empty Flag" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "RDC,Number of Receive FIFO Data Indication Flag"
|
|
bitfld.long 0x4 0. "RDF,Receive Data Full Flag" "0,1"
|
|
line.long 0x8 "SSIFTDR,Transmit FIFO Data Register"
|
|
line.long 0xC "SSIFRDR,Receive FIFO Data Register"
|
|
line.long 0x10 "SSITDMR,TDM Mode Register"
|
|
bitfld.long 0x10 9. "BCKASTP,Enable Stopping BCK Output When SSIE is in Idle Status" "0,1"
|
|
rbitfld.long 0x10 8. "LRCONT,Enable LRCK/FS Continuation" "0,1"
|
|
bitfld.long 0x10 0.--1. "OMOD,Audio Format Select" "0,1,2,3"
|
|
line.long 0x14 "SSISCR,Status Control Register"
|
|
bitfld.long 0x14 8.--10. "TDES,TDE Setting Condition Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "RDFS,RDF Setting Condition Select" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
endif
|
|
tree "TM (Timer)"
|
|
base ad:0x0
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G157*"))
|
|
tree "TM40"
|
|
base ad:0x40041D80
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
rgroup.word ($2)++0x1
|
|
line.word 0x0 "TCR0$1,Timer count register 0%s"
|
|
repeat.end
|
|
group.word 0x10++0x7
|
|
line.word 0x0 "TMR00,Timer mode register mn"
|
|
bitfld.word 0x0 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x0 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x0 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x0 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x2 "TMR01,Timer mode register mn"
|
|
bitfld.word 0x2 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x2 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x2 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x2 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x2 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x4 "TMR02,Timer mode register mn"
|
|
bitfld.word 0x4 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x4 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x4 11. "MASTER,Selection between using channel n independently or simultaneously with another channel (as a slave or master)" "0,1"
|
|
bitfld.word 0x4 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x4 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x4 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x6 "TMR03,Timer mode register mn"
|
|
bitfld.word 0x6 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x6 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x6 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x6 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x6 0.--3. 1. "MD,Operation mode of channel n"
|
|
rgroup.word 0x20++0x7
|
|
line.word 0x0 "TSR00,Timer status register mn"
|
|
bitfld.word 0x0 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x2 "TSR01,Timer status register mn"
|
|
bitfld.word 0x2 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x4 "TSR02,Timer status register mn"
|
|
bitfld.word 0x4 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x6 "TSR03,Timer status register mn"
|
|
bitfld.word 0x6 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
rgroup.word 0x30++0x1
|
|
line.word 0x0 "TE0,Timer channel enable status register m"
|
|
bitfld.word 0x0 11. "TEH03,Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 9. "TEH01,Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 3. "TE03,Indication of operation enable/stop status of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "TE02,Indication of operation enable/stop status of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "TE01,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "TE00,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x32++0xD
|
|
line.word 0x0 "TS0,Timer channel start register 0"
|
|
bitfld.word 0x0 11. "TSH03,Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 9. "TSH01,Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 3. "TS03,Operation enable (start) trigger of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "TS02,Operation enable (start) trigger of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "TS01,Operation enable (start) trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "TS00,Operation enable (start) trigger of channel 0" "0,1"
|
|
line.word 0x2 "TT0,Timer channel stop register 0"
|
|
bitfld.word 0x2 11. "TTH03,Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x2 9. "TTH01,Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x2 3. "TT03,Operation stop trigger of channel 3" "0,1"
|
|
bitfld.word 0x2 2. "TT02,Operation stop trigger of channel 2" "0,1"
|
|
bitfld.word 0x2 1. "TT01,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "TT00,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "TPS0,Timer clock select register 0"
|
|
bitfld.word 0x4 12.--13. "PRS03,Prescaler 3" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "PRS02,Prescaler 2" "0,1,2,3"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS01,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS00,Prescaler 0"
|
|
line.word 0x6 "TO0,Timer output register 0"
|
|
bitfld.word 0x6 3. "TO03,Timer output of channel 3" "0,1"
|
|
bitfld.word 0x6 2. "TO02,Timer output of channel 2" "0,1"
|
|
bitfld.word 0x6 1. "TO01,Timer output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "TO00,Timer output of channel 0" "0,1"
|
|
line.word 0x8 "TOE0,Timer output enable register 0"
|
|
bitfld.word 0x8 3. "TOE03,Timer output enable of channel 3" "0,1"
|
|
bitfld.word 0x8 2. "TOE02,Timer output enable of channel 2" "0,1"
|
|
bitfld.word 0x8 1. "TOE01,Timer output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "TOE00,Timer output enable of channel 0" "0,1"
|
|
line.word 0xA "TOL0,Timer output level register 0"
|
|
bitfld.word 0xA 3. "TOL03,Control of timer output level of channel 3" "0,1"
|
|
bitfld.word 0xA 2. "TOL02,Control of timer output level of channel 2" "0,1"
|
|
bitfld.word 0xA 1. "TOL01,Control of timer output level of channel 1" "0,1"
|
|
line.word 0xC "TOM0,Timer output mode register 0"
|
|
bitfld.word 0xC 3. "TOM03,Control of timer output mode of channel 3" "0,1"
|
|
bitfld.word 0xC 2. "TOM02,Control of timer output mode of channel 2" "0,1"
|
|
bitfld.word 0xC 1. "TOM01,Control of timer output mode of channel 1" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x198)++0x1
|
|
line.word 0x0 "TDR0$1,Timer data register 0%s"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x1E4)++0x1
|
|
line.word 0x0 "TDR0$1,Timer data register 0%s"
|
|
repeat.end
|
|
group.byte 0x19A++0x1
|
|
line.byte 0x0 "TDR01L,Timer data lower register 01"
|
|
line.byte 0x1 "TDR01H,Timer data higher register 01"
|
|
group.byte 0x1E6++0x1
|
|
line.byte 0x0 "TDR03L,Timer data lower register 03"
|
|
line.byte 0x1 "TDR03H,Timer data higher register 03"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "TMA"
|
|
base ad:0x40042240
|
|
group.byte 0x0++0x3
|
|
line.byte 0x0 "TACR0,Timer control register 0"
|
|
bitfld.byte 0x0 5. "TUNDF,Timer underflow flag" "0,1"
|
|
bitfld.byte 0x0 4. "TEDGF,Active edge flag" "0,1"
|
|
bitfld.byte 0x0 2. "TSTOP,Timer count forced stop" "0,1"
|
|
bitfld.byte 0x0 1. "TCSTF,Timer count status flag" "0,1"
|
|
bitfld.byte 0x0 0. "TSTART,Timer count start" "0,1"
|
|
line.byte 0x1 "TAIOC0,Timer I/O control register 0"
|
|
bitfld.byte 0x1 6.--7. "TIOGT,TAIO count control" "0,1,2,3"
|
|
bitfld.byte 0x1 4.--5. "TIPF,TAIO input filter select" "0,1,2,3"
|
|
bitfld.byte 0x1 2. "TOENA,TAO output enable" "0,1"
|
|
bitfld.byte 0x1 0. "TEDGSEL,I/O polarity switch" "0,1"
|
|
line.byte 0x2 "TAMR0,Timer mode register 0"
|
|
bitfld.byte 0x2 4.--6. "TCK,Timer count source select" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x2 3. "TEDGPL,TAIO edge polarity select" "0,1"
|
|
bitfld.byte 0x2 0.--2. "TMOD,Operation mode select" "0,1,2,3,4,5,6,7"
|
|
line.byte 0x3 "TAISR0,Timer event pin select register 0"
|
|
bitfld.byte 0x3 0.--2. "RCCPSEL,Timer output signal select" "0,1,2,3,4,5,6,7"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "TA0,Timer counter register 0"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "TMB"
|
|
base ad:0x40042650
|
|
group.byte 0x0++0x5
|
|
line.byte 0x0 "TBMR,Timer mode register"
|
|
bitfld.byte 0x0 7. "TBSTART,Timer count start" "0,1"
|
|
bitfld.byte 0x0 6. "TBELCICE,EVENTC input capture request select" "0,1"
|
|
bitfld.byte 0x0 4.--5. "TBDFCK,Digital filter function clock select" "0,1,2,3"
|
|
bitfld.byte 0x0 3. "TBDFB,Digital filer function select for TBIO1 pin" "0,1"
|
|
bitfld.byte 0x0 2. "TBDFA,Digital filer function select for TBIO0 pin" "0,1"
|
|
bitfld.byte 0x0 1. "TBMDF,Phase counting mode select" "0,1"
|
|
bitfld.byte 0x0 0. "TBPWM,PWM mode select" "0,1"
|
|
line.byte 0x1 "TBCNTC,Timer count control register"
|
|
bitfld.byte 0x1 7. "CNTEN7,counter enable 7" "0,1"
|
|
bitfld.byte 0x1 6. "CNTEN6,counter enable 6" "0,1"
|
|
bitfld.byte 0x1 5. "CNTEN5,counter enable 5" "0,1"
|
|
bitfld.byte 0x1 4. "CNTEN4,counter enable 4" "0,1"
|
|
bitfld.byte 0x1 3. "CNTEN3,counter enable 3" "0,1"
|
|
bitfld.byte 0x1 2. "CNTEN2,counter enable 2" "0,1"
|
|
bitfld.byte 0x1 1. "CNTEN1,counter enable 1" "0,1"
|
|
bitfld.byte 0x1 0. "CNTEN0,counter enable 0" "0,1"
|
|
line.byte 0x2 "TBCR,Timer control register"
|
|
bitfld.byte 0x2 5.--6. "TBCCLR,TB register clear source select" "0,1,2,3"
|
|
bitfld.byte 0x2 3.--4. "TBCKEG,External clock active edge select" "0,1,2,3"
|
|
bitfld.byte 0x2 0.--2. "TBTCK,Count source select" "0,1,2,3,4,5,6,7"
|
|
line.byte 0x3 "TBIER,Timer interrupt enable register"
|
|
bitfld.byte 0x3 3. "TBOVIE,Overflow interrupt enable" "0,1"
|
|
bitfld.byte 0x3 2. "TBUDIE,Underflow interrupt enable" "0,1"
|
|
bitfld.byte 0x3 1. "TBIMIEB,Input-capture/compare-match interrupt enable B" "0,1"
|
|
bitfld.byte 0x3 0. "TBIMIEA,Input-capture/compare-match interrupt enable A" "0,1"
|
|
line.byte 0x4 "TBSR,Timer status enable register"
|
|
bitfld.byte 0x4 4. "TBDIRF,Count direction flag" "0,1"
|
|
bitfld.byte 0x4 3. "TBOVF,Overflow flag" "0,1"
|
|
bitfld.byte 0x4 2. "TBUDF,Underflow flag" "0,1"
|
|
bitfld.byte 0x4 1. "TBIMFB,Input-capture/compare-match flag B" "0,1"
|
|
bitfld.byte 0x4 0. "TBIMFA,Input-capture/compare-match flag A" "0,1"
|
|
line.byte 0x5 "TBIOR,Timer I/O control register"
|
|
bitfld.byte 0x5 7. "TBBUFB,TBGRD register function select" "0,1"
|
|
bitfld.byte 0x5 4.--6. "TBIOB,TBGRB mode select and control" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x5 3. "TBBUFA,TBGRC register function select" "0,1"
|
|
bitfld.byte 0x5 0.--2. "TBIOA,TBGRA mode select and control" "0,1,2,3,4,5,6,7"
|
|
group.word 0x6++0x1
|
|
line.word 0x0 "TB,Timer counter register"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x8)++0x1
|
|
line.word 0x0 "TBGR$1,Timer general register %s"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "TMC"
|
|
base ad:0x40042C50
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "TC,Timer counter register"
|
|
line.word 0x2 "TCBUF,Timer count buffer register"
|
|
group.byte 0x4++0x2
|
|
line.byte 0x0 "TCCR1,Timer control register 1"
|
|
bitfld.byte 0x0 5.--7. "TCK,Selects count source" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x0 4. "START_MD,Selects count start source" "0,1"
|
|
bitfld.byte 0x0 3. "TRIG_MD_SW,Signal for enabling TC counter reset by software" "0,1"
|
|
bitfld.byte 0x0 2. "TRIG_MD_HW,Selects operation in a count mode selected by a trigger from timer M" "0,1"
|
|
bitfld.byte 0x0 1. "TM_TRIG,Selects a hardware start trigger from timer M" "0,1"
|
|
bitfld.byte 0x0 0. "OVIE,Enables overflow interrupt" "0,1"
|
|
line.byte 0x1 "TCCR2,Timer control register 2"
|
|
bitfld.byte 0x1 1.--2. "CMP1_TCR,Selects operation to be performed when a trigger is generated from comparator 1" "0,1,2,3"
|
|
bitfld.byte 0x1 0. "TSTART,counter start" "0,1"
|
|
line.byte 0x2 "TCSR,Timer status register"
|
|
bitfld.byte 0x2 1. "TCSB,Counter status flag" "0,1"
|
|
bitfld.byte 0x2 0. "TCOVF,Overflow status of TC counter" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "TMM (BLDC Motor Control Timer)"
|
|
base ad:0x40042A60
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "TMELC,Timer ELC register"
|
|
bitfld.byte 0x0 5. "ELCOBE1,ELC event input 1 enable for timer M pulse output forced cutoff" "0,1"
|
|
bitfld.byte 0x0 4. "ELCICE1,ELC event input 1 select for timer M input capture D1" "0,1"
|
|
bitfld.byte 0x0 1. "ELCOBE0,ELC event input 0 enable for timer M pulse output forced cutoff" "0,1"
|
|
bitfld.byte 0x0 0. "ELCICE0,ELC event input 0 select for timer M input capture D0" "0,1"
|
|
group.byte 0x3++0x8
|
|
line.byte 0x0 "TMSTR,Timer start register"
|
|
bitfld.byte 0x0 3. "CSEL1,TM1 count operation select" "0,1"
|
|
bitfld.byte 0x0 2. "CSEL0,TM0 count operation select" "0,1"
|
|
bitfld.byte 0x0 1. "TSTART1,TM1 count start flag" "0,1"
|
|
bitfld.byte 0x0 0. "TSTART0,TM0 count start flag" "0,1"
|
|
line.byte 0x1 "TMMR,Timer mode register"
|
|
bitfld.byte 0x1 7. "TMBFD1,TMGRD1 register function select" "0,1"
|
|
bitfld.byte 0x1 6. "TMBFC1,TMGRC1 register function select" "0,1"
|
|
bitfld.byte 0x1 5. "TMBFD0,TMGRD0 register function select" "0,1"
|
|
bitfld.byte 0x1 4. "TMBFC0,TMGRC0 register function select" "0,1"
|
|
bitfld.byte 0x1 0. "TMSYNC,TMs synchronous" "0,1"
|
|
line.byte 0x2 "TMPMR,PWM function select register"
|
|
bitfld.byte 0x2 6. "TMPWMD1,PWM function of TMIOD1 select" "0,1"
|
|
bitfld.byte 0x2 5. "TMPWMC1,PWM function of TMIOC1 select" "0,1"
|
|
bitfld.byte 0x2 4. "TMPWMB1,PWM function of TMIOB1 select" "0,1"
|
|
bitfld.byte 0x2 2. "TMPWMD0,PWM function of TMIOD0 select" "0,1"
|
|
bitfld.byte 0x2 1. "TMPWMC0,PWM function of TMIOC0 select" "0,1"
|
|
bitfld.byte 0x2 0. "TMPWMB0,PWM function of TMIOB0 select" "0,1"
|
|
line.byte 0x3 "TMFCR,Timer function control register"
|
|
bitfld.byte 0x3 7. "PWM3,PWM3 mode select" "0,1"
|
|
bitfld.byte 0x3 6. "STCLK,External clock input select" "0,1"
|
|
bitfld.byte 0x3 3. "OLS1,Counter-Phase output level select" "0,1"
|
|
bitfld.byte 0x3 2. "OLS0,Phase output level select" "0,1"
|
|
bitfld.byte 0x3 0.--1. "CMD,Combination mode select" "0,1,2,3"
|
|
line.byte 0x4 "TMOER1,Timer output master enable register 1"
|
|
bitfld.byte 0x4 7. "ED1,TMIOD1 output disable" "0,1"
|
|
bitfld.byte 0x4 6. "EC1,TMIOC1 output disable" "0,1"
|
|
bitfld.byte 0x4 5. "EB1,TMIOB1 output disable" "0,1"
|
|
bitfld.byte 0x4 4. "EA1,TMIOA1 output disable" "0,1"
|
|
bitfld.byte 0x4 3. "ED0,TMIOD0 output disable" "0,1"
|
|
bitfld.byte 0x4 2. "EC0,TMIOC0 output disable" "0,1"
|
|
bitfld.byte 0x4 1. "EB0,TMIOB0 output disable" "0,1"
|
|
bitfld.byte 0x4 0. "EA0,TMIOA0 output disable" "0,1"
|
|
line.byte 0x5 "TMOER2,Timer output master enable register 2"
|
|
bitfld.byte 0x5 7. "TMPTO,INTP0 pin of pulse output forced cutoff signal input enabled" "0,1"
|
|
bitfld.byte 0x5 0. "TMSHUTS,Forced cutoff flag" "0,1"
|
|
line.byte 0x6 "TMOCR,Timer output control register"
|
|
bitfld.byte 0x6 7. "TOD1,TMIOD1 initial output level select" "0,1"
|
|
bitfld.byte 0x6 6. "TOC1,TMIOC1 initial output level select" "0,1"
|
|
bitfld.byte 0x6 5. "TOB1,TMIOB1 initial output level select" "0,1"
|
|
bitfld.byte 0x6 4. "TOA1,TMIOA1 initial output level select" "0,1"
|
|
bitfld.byte 0x6 3. "TOD0,TMIOD0 initial output level select" "0,1"
|
|
bitfld.byte 0x6 2. "TOC0,TMIOC0 initial output level select" "0,1"
|
|
bitfld.byte 0x6 1. "TOB0,TMIOB0 initial output level select" "0,1"
|
|
bitfld.byte 0x6 0. "TOA0,TMIOA0 initial output level select" "0,1"
|
|
line.byte 0x7 "TMDF0,Digital filter function select register 0"
|
|
bitfld.byte 0x7 6.--7. "DFCK,Clock select for digital filter function" "0,1,2,3"
|
|
bitfld.byte 0x7 3. "DFD,TMIODi pin digital filter function select" "0,1"
|
|
bitfld.byte 0x7 2. "DFC,TMIOCi pin digital filter function select" "0,1"
|
|
bitfld.byte 0x7 1. "DFB,TMIOBi pin digital filter function select" "0,1"
|
|
bitfld.byte 0x7 0. "DFA,TMIOAi pin digital filter function select" "0,1"
|
|
line.byte 0x8 "TMDF1,Digital filter function select register 1"
|
|
bitfld.byte 0x8 6.--7. "DFCK,Clock select for digital filter function" "0,1,2,3"
|
|
bitfld.byte 0x8 3. "DFD,TMIODi pin digital filter function select" "0,1"
|
|
bitfld.byte 0x8 2. "DFC,TMIOCi pin digital filter function select" "0,1"
|
|
bitfld.byte 0x8 1. "DFB,TMIOBi pin digital filter function select" "0,1"
|
|
bitfld.byte 0x8 0. "DFA,TMIOAi pin digital filter function select" "0,1"
|
|
group.byte 0x10++0x0
|
|
line.byte 0x0 "TMCR0,Timer control register 0"
|
|
bitfld.byte 0x0 5.--7. "CCLR,TMi counter clear select" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x0 3.--4. "CKEG,External clock edge select" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--2. "TCK,Count source select" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x20++0x0
|
|
line.byte 0x0 "TMCR1,Timer control register 1"
|
|
bitfld.byte 0x0 5.--7. "CCLR,TMi counter clear select" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x0 3.--4. "CKEG,External clock edge select" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--2. "TCK,Count source select" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x0 "TMIORA0,Timer I/O control register A0"
|
|
bitfld.byte 0x0 4.--6. "IOB,TMGRB mode control" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x0 0.--2. "IOA,TMGRA mode control" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x21++0x0
|
|
line.byte 0x0 "TMIORA1,Timer I/O control register A1"
|
|
bitfld.byte 0x0 4.--6. "IOB,TMGRB mode control" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x0 0.--2. "IOA,TMGRA mode control" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x12++0x0
|
|
line.byte 0x0 "TMIORC0,Timer I/O control register C0"
|
|
hexmask.byte 0x0 4.--7. 1. "IOD,TMGRD mode control"
|
|
hexmask.byte 0x0 0.--3. 1. "IOC,TMGRC mode control"
|
|
group.byte 0x22++0x0
|
|
line.byte 0x0 "TMIORC1,Timer I/O control register C1"
|
|
hexmask.byte 0x0 4.--7. 1. "IOD,TMGRD mode control"
|
|
hexmask.byte 0x0 0.--3. 1. "IOC,TMGRC mode control"
|
|
group.byte 0x13++0x0
|
|
line.byte 0x0 "TMSR0,Timer status register 0"
|
|
bitfld.byte 0x0 4. "OVF,Overflow flag" "0,1"
|
|
bitfld.byte 0x0 3. "IMFD,Input capture/compare match flag D" "0,1"
|
|
bitfld.byte 0x0 2. "IMFC,Input capture/compare match flag C" "0,1"
|
|
bitfld.byte 0x0 1. "IMFB,Input capture/compare match flag B" "0,1"
|
|
bitfld.byte 0x0 0. "IMFA,Input capture/compare match flag A" "0,1"
|
|
group.byte 0x23++0x0
|
|
line.byte 0x0 "TMSR1,Timer status register 1"
|
|
bitfld.byte 0x0 5. "UDF,Underflow flag" "0,1"
|
|
bitfld.byte 0x0 4. "OVF,Overflow flag" "0,1"
|
|
bitfld.byte 0x0 3. "IMFD,Input capture/compare match flag D" "0,1"
|
|
bitfld.byte 0x0 2. "IMFC,Input capture/compare match flag C" "0,1"
|
|
bitfld.byte 0x0 1. "IMFB,Input capture/compare match flag B" "0,1"
|
|
bitfld.byte 0x0 0. "IMFA,Input capture/compare match flag A" "0,1"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "TMIER0,Timer interrupt enable register 0"
|
|
bitfld.byte 0x0 4. "OVIE,Overflow/underflow interrupt enable" "0,1"
|
|
bitfld.byte 0x0 3. "IMIED,Input capture/compare match interrupt enable D" "0,1"
|
|
bitfld.byte 0x0 2. "IMIEC,Input capture/compare match interrupt enable C" "0,1"
|
|
bitfld.byte 0x0 1. "IMIEB,Input capture/compare match interrupt enable B" "0,1"
|
|
bitfld.byte 0x0 0. "IMIEA,Input capture/compare match interrupt enable A" "0,1"
|
|
group.byte 0x24++0x0
|
|
line.byte 0x0 "TMIER1,Timer interrupt enable register 1"
|
|
bitfld.byte 0x0 4. "OVIE,Overflow/underflow interrupt enable" "0,1"
|
|
bitfld.byte 0x0 3. "IMIED,Input capture/compare match interrupt enable D" "0,1"
|
|
bitfld.byte 0x0 2. "IMIEC,Input capture/compare match interrupt enable C" "0,1"
|
|
bitfld.byte 0x0 1. "IMIEB,Input capture/compare match interrupt enable B" "0,1"
|
|
bitfld.byte 0x0 0. "IMIEA,Input capture/compare match interrupt enable A" "0,1"
|
|
group.byte 0x15++0x0
|
|
line.byte 0x0 "TMPOCR0,PWM output level control register 0"
|
|
bitfld.byte 0x0 2. "POLD,PWM output level control D" "0,1"
|
|
bitfld.byte 0x0 1. "POLC,PWM output level control C" "0,1"
|
|
bitfld.byte 0x0 0. "POLB,PWM output level control B" "0,1"
|
|
group.byte 0x25++0x0
|
|
line.byte 0x0 "TMPOCR1,PWM output level control register 1"
|
|
bitfld.byte 0x0 2. "POLD,PWM output level control D" "0,1"
|
|
bitfld.byte 0x0 1. "POLC,PWM output level control C" "0,1"
|
|
bitfld.byte 0x0 0. "POLB,PWM output level control B" "0,1"
|
|
group.word 0x16++0x1
|
|
line.word 0x0 "TM0,Timer M counter 0"
|
|
group.word 0x26++0x1
|
|
line.word 0x0 "TM1,Timer M counter 1"
|
|
group.word 0x18++0x1
|
|
line.word 0x0 "TMGRA0,Timer M general register A0"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TMGRA1,Timer M general register A1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "TMGRB0,Timer M general register B0"
|
|
group.word 0x2A++0x1
|
|
line.word 0x0 "TMGRB1,Timer M general register B1"
|
|
group.word 0xF8++0x1
|
|
line.word 0x0 "TMGRC0,Timer M general register C0"
|
|
group.word 0xFC++0x1
|
|
line.word 0x0 "TMGRC1,Timer M general register C1"
|
|
group.word 0xFA++0x1
|
|
line.word 0x0 "TMGRD0,Timer M general register D0"
|
|
group.word 0xFE++0x1
|
|
line.word 0x0 "TMGRD1,Timer M general register D1"
|
|
group.byte 0x11F8++0x3
|
|
line.byte 0x0 "OPCTL0,PWMOPA control register 0"
|
|
bitfld.byte 0x0 6. "HAZAD_SET,Output cutoff hazard control selection" "0,1"
|
|
bitfld.byte 0x0 5. "IN_EG,Output forced cutoff source edge/output forced cutoff release edge selection" "0,1"
|
|
bitfld.byte 0x0 3.--4. "IN_SEL,Cutoff source selection" "0,1,2,3"
|
|
bitfld.byte 0x0 2. "ACT,When software release is selected: Software release timing selection" "0,1"
|
|
bitfld.byte 0x0 1. "HZ_REL,When software release is selected: Output cutoff release control" "0,1"
|
|
bitfld.byte 0x0 0. "HS_SEL,Output forced cutoff release mode selection" "0,1"
|
|
line.byte 0x1 "OPDF0,PWMOPA cutoff control register 0"
|
|
bitfld.byte 0x1 6.--7. "DFD0,TMIOD0 pin output forced cutoff control" "0,1,2,3"
|
|
bitfld.byte 0x1 4.--5. "DFC0,TMIOC0 pin output forced cutoff control" "0,1,2,3"
|
|
bitfld.byte 0x1 2.--3. "DFB0,TMIOB0 pin output forced cutoff control" "0,1,2,3"
|
|
bitfld.byte 0x1 0.--1. "DFA0,TMIOA0 pin output forced cutoff control" "0,1,2,3"
|
|
line.byte 0x2 "OPDF1,PWMOPA cutoff control register 1"
|
|
bitfld.byte 0x2 6.--7. "DFD1,TMIOD1 pin output forced cutoff control" "0,1,2,3"
|
|
bitfld.byte 0x2 4.--5. "DFC1,TMIOC1 pin output forced cutoff control" "0,1,2,3"
|
|
bitfld.byte 0x2 2.--3. "DFB1,TMIOB1 pin output forced cutoff control" "0,1,2,3"
|
|
bitfld.byte 0x2 0.--1. "DFA1,TMIOA1 pin output forced cutoff control" "0,1,2,3"
|
|
line.byte 0x3 "OPEDGE,PWMOPA edge selection register"
|
|
bitfld.byte 0x3 0.--1. "EG,Output forced cutoff release edge selection" "0,1,2,3"
|
|
rgroup.byte 0x11FC++0x0
|
|
line.byte 0x0 "OPSR,PWMOPA status register"
|
|
bitfld.byte 0x0 2. "HZOF1,cutoff state" "0,1"
|
|
bitfld.byte 0x0 1. "HZOF0,cutoff state" "0,1"
|
|
bitfld.byte 0x0 0. "HZIF0,Output cutoff source state" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "TM81"
|
|
base ad:0x40042180
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
rgroup.word ($2)++0x1
|
|
line.word 0x0 "TCR1$1,Timer count register 0%s"
|
|
repeat.end
|
|
group.word 0x10++0xF
|
|
line.word 0x0 "TMR10,Timer mode register mn"
|
|
bitfld.word 0x0 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x0 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x0 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x0 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x2 "TMR11,Timer mode register mn"
|
|
bitfld.word 0x2 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x2 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x2 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x2 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x2 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x4 "TMR12,Timer mode register mn"
|
|
bitfld.word 0x4 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x4 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x4 11. "MASTER,Selection between using channel n independently or simultaneously with another channel (as a slave or master)" "0,1"
|
|
bitfld.word 0x4 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x4 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x4 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x6 "TMR13,Timer mode register mn"
|
|
bitfld.word 0x6 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x6 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x6 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x6 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x6 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x8 "TMR14,Timer mode register mn"
|
|
bitfld.word 0x8 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x8 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x8 11. "MASTER,Selection between using channel n independently or simultaneously with another channel (as a slave or master)" "0,1"
|
|
bitfld.word 0x8 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x8 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x8 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0xA "TMR15,Timer mode register mn"
|
|
bitfld.word 0xA 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0xA 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xA 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0xA 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0xA 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0xC "TMR16,Timer mode register mn"
|
|
bitfld.word 0xC 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0xC 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xC 11. "MASTER,Selection between using channel n independently or simultaneously with another channel (as a slave or master)" "0,1"
|
|
bitfld.word 0xC 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0xC 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0xC 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0xE "TMR17,Timer mode register mn"
|
|
bitfld.word 0xE 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0xE 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xE 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0xE 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0xE 0.--3. 1. "MD,Operation mode of channel n"
|
|
rgroup.word 0x20++0x11
|
|
line.word 0x0 "TSR10,Timer status register mn"
|
|
bitfld.word 0x0 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x2 "TSR11,Timer status register mn"
|
|
bitfld.word 0x2 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x4 "TSR12,Timer status register mn"
|
|
bitfld.word 0x4 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x6 "TSR13,Timer status register mn"
|
|
bitfld.word 0x6 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x8 "TSR14,Timer status register mn"
|
|
bitfld.word 0x8 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0xA "TSR15,Timer status register mn"
|
|
bitfld.word 0xA 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0xC "TSR16,Timer status register mn"
|
|
bitfld.word 0xC 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0xE "TSR17,Timer status register mn"
|
|
bitfld.word 0xE 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x10 "TE1,Timer channel enable status register m"
|
|
bitfld.word 0x10 7. "TE17,Indication of operation enable/stop status of channel 7" "0,1"
|
|
bitfld.word 0x10 6. "TE16,Indication of operation enable/stop status of channel 6" "0,1"
|
|
bitfld.word 0x10 5. "TE15,Indication of operation enable/stop status of channel 5" "0,1"
|
|
bitfld.word 0x10 4. "TE14,Indication of operation enable/stop status of channel 4" "0,1"
|
|
bitfld.word 0x10 3. "TE13,Indication of operation enable/stop status of channel 3" "0,1"
|
|
bitfld.word 0x10 2. "TE12,Indication of operation enable/stop status of channel 2" "0,1"
|
|
bitfld.word 0x10 1. "TE11,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x10 0. "TE10,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x32++0xD
|
|
line.word 0x0 "TS1,Timer channel start register 0"
|
|
bitfld.word 0x0 7. "TS17,Operation enable (start) trigger of channel 7" "0,1"
|
|
bitfld.word 0x0 6. "TS16,Operation enable (start) trigger of channel 6" "0,1"
|
|
bitfld.word 0x0 5. "TS15,Operation enable (start) trigger of channel 5" "0,1"
|
|
bitfld.word 0x0 4. "TS14,Operation enable (start) trigger of channel 4" "0,1"
|
|
bitfld.word 0x0 3. "TS13,Operation enable (start) trigger of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "TS12,Operation enable (start) trigger of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "TS11,Operation enable (start) trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "TS10,Operation enable (start) trigger of channel 0" "0,1"
|
|
line.word 0x2 "TT1,Timer channel stop register 0"
|
|
bitfld.word 0x2 7. "TT17,Operation stop trigger of channel 7" "0,1"
|
|
bitfld.word 0x2 6. "TT16,Operation stop trigger of channel 6" "0,1"
|
|
bitfld.word 0x2 5. "TT15,Operation stop trigger of channel 5" "0,1"
|
|
bitfld.word 0x2 4. "TT14,Operation stop trigger of channel 4" "0,1"
|
|
bitfld.word 0x2 3. "TT13,Operation stop trigger of channel 3" "0,1"
|
|
bitfld.word 0x2 2. "TT12,Operation stop trigger of channel 2" "0,1"
|
|
bitfld.word 0x2 1. "TT11,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "TT10,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "TPS1,Timer clock select register 0"
|
|
bitfld.word 0x4 12.--13. "PRS13,Prescaler 3" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "PRS12,Prescaler 2" "0,1,2,3"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS11,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS10,Prescaler 0"
|
|
line.word 0x6 "TO1,Timer output register 0"
|
|
bitfld.word 0x6 7. "TO17,Timer output of channel 7" "0,1"
|
|
bitfld.word 0x6 6. "TO16,Timer output of channel 6" "0,1"
|
|
bitfld.word 0x6 5. "TO15,Timer output of channel 5" "0,1"
|
|
bitfld.word 0x6 4. "TO14,Timer output of channel 4" "0,1"
|
|
bitfld.word 0x6 3. "TO13,Timer output of channel 3" "0,1"
|
|
bitfld.word 0x6 2. "TO12,Timer output of channel 2" "0,1"
|
|
bitfld.word 0x6 1. "TO11,Timer output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "TO10,Timer output of channel 0" "0,1"
|
|
line.word 0x8 "TOE1,Timer output enable register 0"
|
|
bitfld.word 0x8 7. "TOE17,Timer output enable of channel 7" "0,1"
|
|
bitfld.word 0x8 6. "TOE16,Timer output enable of channel 6" "0,1"
|
|
bitfld.word 0x8 5. "TOE15,Timer output enable of channel 5" "0,1"
|
|
bitfld.word 0x8 4. "TOE14,Timer output enable of channel 4" "0,1"
|
|
bitfld.word 0x8 3. "TOE13,Timer output enable of channel 3" "0,1"
|
|
bitfld.word 0x8 2. "TOE12,Timer output enable of channel 2" "0,1"
|
|
bitfld.word 0x8 1. "TOE11,Timer output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "TOE10,Timer output enable of channel 0" "0,1"
|
|
line.word 0xA "TOL1,Timer output level register 0"
|
|
bitfld.word 0xA 7. "TOL17,Control of timer output level of channel 7" "0,1"
|
|
bitfld.word 0xA 6. "TOL16,Control of timer output level of channel 6" "0,1"
|
|
bitfld.word 0xA 5. "TOL15,Control of timer output level of channel 5" "0,1"
|
|
bitfld.word 0xA 4. "TOL14,Control of timer output level of channel 4" "0,1"
|
|
bitfld.word 0xA 3. "TOL13,Control of timer output level of channel 3" "0,1"
|
|
bitfld.word 0xA 2. "TOL12,Control of timer output level of channel 2" "0,1"
|
|
bitfld.word 0xA 1. "TOL11,Control of timer output level of channel 1" "0,1"
|
|
line.word 0xC "TOM1,Timer output mode register 0"
|
|
bitfld.word 0xC 7. "TOM17,Control of timer output mode of channel 7" "0,1"
|
|
bitfld.word 0xC 6. "TOM16,Control of timer output mode of channel 6" "0,1"
|
|
bitfld.word 0xC 5. "TOM15,Control of timer output mode of channel 5" "0,1"
|
|
bitfld.word 0xC 4. "TOM14,Control of timer output mode of channel 4" "0,1"
|
|
bitfld.word 0xC 3. "TOM13,Control of timer output mode of channel 3" "0,1"
|
|
bitfld.word 0xC 2. "TOM12,Control of timer output mode of channel 2" "0,1"
|
|
bitfld.word 0xC 1. "TOM11,Control of timer output mode of channel 1" "0,1"
|
|
group.word 0x198++0x3
|
|
line.word 0x0 "TDR10,Timer data register 00"
|
|
line.word 0x2 "TDR11,Timer data register 01"
|
|
group.byte 0x19A++0x1
|
|
line.byte 0x0 "TDR11L,Timer data lower register 11"
|
|
line.byte 0x1 "TDR11H,Timer data higher register 11"
|
|
group.word 0x1E4++0x3
|
|
line.word 0x0 "TDR12,Timer data register 02"
|
|
line.word 0x2 "TDR13,Timer data register 03"
|
|
group.byte 0x1E6++0x1
|
|
line.byte 0x0 "TDR13L,Timer data lower register 13"
|
|
line.byte 0x1 "TDR13H,Timer data higher register 13"
|
|
group.word 0x1E8++0x7
|
|
line.word 0x0 "TDR14,Timer data register 04"
|
|
line.word 0x2 "TDR15,Timer data register 05"
|
|
line.word 0x4 "TDR16,Timer data register 06"
|
|
line.word 0x6 "TDR17,Timer data register 07"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "TM40"
|
|
base ad:0x40041D80
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
rgroup.word ($2)++0x1
|
|
line.word 0x0 "TCR0$1,Timer count register 0%s"
|
|
repeat.end
|
|
group.word 0x10++0x7
|
|
line.word 0x0 "TMR00,Timer mode register mn"
|
|
bitfld.word 0x0 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x0 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x0 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x0 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x2 "TMR01,Timer mode register mn"
|
|
bitfld.word 0x2 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x2 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x2 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x2 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x2 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x4 "TMR02,Timer mode register mn"
|
|
bitfld.word 0x4 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x4 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x4 11. "MASTER,Selection between using channel n independently or simultaneously with another channel (as a slave or master)" "0,1"
|
|
bitfld.word 0x4 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x4 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x4 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x6 "TMR03,Timer mode register mn"
|
|
bitfld.word 0x6 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x6 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x6 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x6 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x6 0.--3. 1. "MD,Operation mode of channel n"
|
|
rgroup.word 0x20++0x7
|
|
line.word 0x0 "TSR00,Timer status register mn"
|
|
bitfld.word 0x0 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x2 "TSR01,Timer status register mn"
|
|
bitfld.word 0x2 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x4 "TSR02,Timer status register mn"
|
|
bitfld.word 0x4 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x6 "TSR03,Timer status register mn"
|
|
bitfld.word 0x6 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
rgroup.word 0x30++0x1
|
|
line.word 0x0 "TE0,Timer channel enable status register m"
|
|
bitfld.word 0x0 11. "TEH03,Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 9. "TEH01,Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 3. "TE03,Indication of operation enable/stop status of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "TE02,Indication of operation enable/stop status of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "TE01,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "TE00,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x32++0xD
|
|
line.word 0x0 "TS0,Timer channel start register 0"
|
|
bitfld.word 0x0 11. "TSH03,Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 9. "TSH01,Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x0 3. "TS03,Operation enable (start) trigger of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "TS02,Operation enable (start) trigger of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "TS01,Operation enable (start) trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "TS00,Operation enable (start) trigger of channel 0" "0,1"
|
|
line.word 0x2 "TT0,Timer channel stop register 0"
|
|
bitfld.word 0x2 11. "TTH03,Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x2 9. "TTH01,Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode" "0,1"
|
|
bitfld.word 0x2 3. "TT03,Operation stop trigger of channel 3" "0,1"
|
|
bitfld.word 0x2 2. "TT02,Operation stop trigger of channel 2" "0,1"
|
|
bitfld.word 0x2 1. "TT01,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "TT00,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "TPS0,Timer clock select register 0"
|
|
bitfld.word 0x4 12.--13. "PRS03,Prescaler 3" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "PRS02,Prescaler 2" "0,1,2,3"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS01,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS00,Prescaler 0"
|
|
line.word 0x6 "TO0,Timer output register 0"
|
|
bitfld.word 0x6 3. "TO03,Timer output of channel 3" "0,1"
|
|
bitfld.word 0x6 2. "TO02,Timer output of channel 2" "0,1"
|
|
bitfld.word 0x6 1. "TO01,Timer output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "TO00,Timer output of channel 0" "0,1"
|
|
line.word 0x8 "TOE0,Timer output enable register 0"
|
|
bitfld.word 0x8 3. "TOE03,Timer output enable of channel 3" "0,1"
|
|
bitfld.word 0x8 2. "TOE02,Timer output enable of channel 2" "0,1"
|
|
bitfld.word 0x8 1. "TOE01,Timer output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "TOE00,Timer output enable of channel 0" "0,1"
|
|
line.word 0xA "TOL0,Timer output level register 0"
|
|
bitfld.word 0xA 3. "TOL03,Control of timer output level of channel 3" "0,1"
|
|
bitfld.word 0xA 2. "TOL02,Control of timer output level of channel 2" "0,1"
|
|
bitfld.word 0xA 1. "TOL01,Control of timer output level of channel 1" "0,1"
|
|
line.word 0xC "TOM0,Timer output mode register 0"
|
|
bitfld.word 0xC 3. "TOM03,Control of timer output mode of channel 3" "0,1"
|
|
bitfld.word 0xC 2. "TOM02,Control of timer output mode of channel 2" "0,1"
|
|
bitfld.word 0xC 1. "TOM01,Control of timer output mode of channel 1" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x190)++0x1
|
|
line.word 0x0 "TDR0$1,Timer data register 0%s"
|
|
repeat.end
|
|
group.byte 0x192++0x1
|
|
line.byte 0x0 "TDR01L,Timer data lower register 01"
|
|
line.byte 0x1 "TDR01H,Timer data higher register 01"
|
|
group.byte 0x196++0x1
|
|
line.byte 0x0 "TDR03L,Timer data lower register 03"
|
|
line.byte 0x1 "TDR03H,Timer data higher register 03"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
tree "TM81"
|
|
base ad:0x40045D80
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
rgroup.word ($2)++0x1
|
|
line.word 0x0 "TCR1$1,Timer count register 0%s"
|
|
repeat.end
|
|
group.word 0x10++0xF
|
|
line.word 0x0 "TMR10,Timer mode register mn"
|
|
bitfld.word 0x0 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x0 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x0 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x0 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x2 "TMR11,Timer mode register mn"
|
|
bitfld.word 0x2 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x2 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x2 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x2 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x2 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x4 "TMR12,Timer mode register mn"
|
|
bitfld.word 0x4 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x4 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x4 11. "MASTER,Selection between using channel n independently or simultaneously with another channel (as a slave or master)" "0,1"
|
|
bitfld.word 0x4 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x4 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x4 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x6 "TMR13,Timer mode register mn"
|
|
bitfld.word 0x6 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x6 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x6 11. "SPLIT,Selection of 8 or 16-bit timer operation for channels 1 and 3" "0,1"
|
|
bitfld.word 0x6 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x6 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0x8 "TMR14,Timer mode register mn"
|
|
bitfld.word 0x8 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0x8 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0x8 11. "MASTER,Selection between using channel n independently or simultaneously with another channel (as a slave or master)" "0,1"
|
|
bitfld.word 0x8 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x8 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0x8 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0xA "TMR15,Timer mode register mn"
|
|
bitfld.word 0xA 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0xA 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xA 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0xA 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0xA 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0xC "TMR16,Timer mode register mn"
|
|
bitfld.word 0xC 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0xC 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xC 11. "MASTER,Selection between using channel n independently or simultaneously with another channel (as a slave or master)" "0,1"
|
|
bitfld.word 0xC 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0xC 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0xC 0.--3. 1. "MD,Operation mode of channel n"
|
|
line.word 0xE "TMR17,Timer mode register mn"
|
|
bitfld.word 0xE 14.--15. "CKS,Selection of operation clock (fMCK) of channel n" "0,1,2,3"
|
|
bitfld.word 0xE 12. "CCS,Selection of count clock (fTCLK) of channel n" "0,1"
|
|
bitfld.word 0xE 8.--10. "STS,Setting of start trigger or capture trigger of channel n" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0xE 6.--7. "CIS,Selection of TImn pin input valid edge" "0,1,2,3"
|
|
hexmask.word.byte 0xE 0.--3. 1. "MD,Operation mode of channel n"
|
|
rgroup.word 0x20++0x11
|
|
line.word 0x0 "TSR10,Timer status register mn"
|
|
bitfld.word 0x0 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x2 "TSR11,Timer status register mn"
|
|
bitfld.word 0x2 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x4 "TSR12,Timer status register mn"
|
|
bitfld.word 0x4 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x6 "TSR13,Timer status register mn"
|
|
bitfld.word 0x6 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x8 "TSR14,Timer status register mn"
|
|
bitfld.word 0x8 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0xA "TSR15,Timer status register mn"
|
|
bitfld.word 0xA 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0xC "TSR16,Timer status register mn"
|
|
bitfld.word 0xC 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0xE "TSR17,Timer status register mn"
|
|
bitfld.word 0xE 0. "OVF,Counter overflow status of channel n" "0,1"
|
|
line.word 0x10 "TE1,Timer channel enable status register m"
|
|
bitfld.word 0x10 7. "TE17,Indication of operation enable/stop status of channel 7" "0,1"
|
|
bitfld.word 0x10 6. "TE16,Indication of operation enable/stop status of channel 6" "0,1"
|
|
bitfld.word 0x10 5. "TE15,Indication of operation enable/stop status of channel 5" "0,1"
|
|
bitfld.word 0x10 4. "TE14,Indication of operation enable/stop status of channel 4" "0,1"
|
|
bitfld.word 0x10 3. "TE13,Indication of operation enable/stop status of channel 3" "0,1"
|
|
bitfld.word 0x10 2. "TE12,Indication of operation enable/stop status of channel 2" "0,1"
|
|
bitfld.word 0x10 1. "TE11,Indication of operation enable/stop status of channel 1" "0,1"
|
|
bitfld.word 0x10 0. "TE10,Indication of operation enable/stop status of channel 0" "0,1"
|
|
group.word 0x32++0xD
|
|
line.word 0x0 "TS1,Timer channel start register 0"
|
|
bitfld.word 0x0 7. "TS17,Operation enable (start) trigger of channel 7" "0,1"
|
|
bitfld.word 0x0 6. "TS16,Operation enable (start) trigger of channel 6" "0,1"
|
|
bitfld.word 0x0 5. "TS15,Operation enable (start) trigger of channel 5" "0,1"
|
|
bitfld.word 0x0 4. "TS14,Operation enable (start) trigger of channel 4" "0,1"
|
|
bitfld.word 0x0 3. "TS13,Operation enable (start) trigger of channel 3" "0,1"
|
|
bitfld.word 0x0 2. "TS12,Operation enable (start) trigger of channel 2" "0,1"
|
|
bitfld.word 0x0 1. "TS11,Operation enable (start) trigger of channel 1" "0,1"
|
|
bitfld.word 0x0 0. "TS10,Operation enable (start) trigger of channel 0" "0,1"
|
|
line.word 0x2 "TT1,Timer channel stop register 0"
|
|
bitfld.word 0x2 7. "TT17,Operation stop trigger of channel 7" "0,1"
|
|
bitfld.word 0x2 6. "TT16,Operation stop trigger of channel 6" "0,1"
|
|
bitfld.word 0x2 5. "TT15,Operation stop trigger of channel 5" "0,1"
|
|
bitfld.word 0x2 4. "TT14,Operation stop trigger of channel 4" "0,1"
|
|
bitfld.word 0x2 3. "TT13,Operation stop trigger of channel 3" "0,1"
|
|
bitfld.word 0x2 2. "TT12,Operation stop trigger of channel 2" "0,1"
|
|
bitfld.word 0x2 1. "TT11,Operation stop trigger of channel 1" "0,1"
|
|
bitfld.word 0x2 0. "TT10,Operation stop trigger of channel 0" "0,1"
|
|
line.word 0x4 "TPS1,Timer clock select register 0"
|
|
bitfld.word 0x4 12.--13. "PRS13,Prescaler 3" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "PRS12,Prescaler 2" "0,1,2,3"
|
|
hexmask.word.byte 0x4 4.--7. 1. "PRS11,Prescaler 1"
|
|
hexmask.word.byte 0x4 0.--3. 1. "PRS10,Prescaler 0"
|
|
line.word 0x6 "TO1,Timer output register 0"
|
|
bitfld.word 0x6 7. "TO17,Timer output of channel 7" "0,1"
|
|
bitfld.word 0x6 6. "TO16,Timer output of channel 6" "0,1"
|
|
bitfld.word 0x6 5. "TO15,Timer output of channel 5" "0,1"
|
|
bitfld.word 0x6 4. "TO14,Timer output of channel 4" "0,1"
|
|
bitfld.word 0x6 3. "TO13,Timer output of channel 3" "0,1"
|
|
bitfld.word 0x6 2. "TO12,Timer output of channel 2" "0,1"
|
|
bitfld.word 0x6 1. "TO11,Timer output of channel 1" "0,1"
|
|
bitfld.word 0x6 0. "TO10,Timer output of channel 0" "0,1"
|
|
line.word 0x8 "TOE1,Timer output enable register 0"
|
|
bitfld.word 0x8 7. "TOE17,Timer output enable of channel 7" "0,1"
|
|
bitfld.word 0x8 6. "TOE16,Timer output enable of channel 6" "0,1"
|
|
bitfld.word 0x8 5. "TOE15,Timer output enable of channel 5" "0,1"
|
|
bitfld.word 0x8 4. "TOE14,Timer output enable of channel 4" "0,1"
|
|
bitfld.word 0x8 3. "TOE13,Timer output enable of channel 3" "0,1"
|
|
bitfld.word 0x8 2. "TOE12,Timer output enable of channel 2" "0,1"
|
|
bitfld.word 0x8 1. "TOE11,Timer output enable of channel 1" "0,1"
|
|
bitfld.word 0x8 0. "TOE10,Timer output enable of channel 0" "0,1"
|
|
line.word 0xA "TOL1,Timer output level register 0"
|
|
bitfld.word 0xA 7. "TOL17,Control of timer output level of channel 7" "0,1"
|
|
bitfld.word 0xA 6. "TOL16,Control of timer output level of channel 6" "0,1"
|
|
bitfld.word 0xA 5. "TOL15,Control of timer output level of channel 5" "0,1"
|
|
bitfld.word 0xA 4. "TOL14,Control of timer output level of channel 4" "0,1"
|
|
bitfld.word 0xA 3. "TOL13,Control of timer output level of channel 3" "0,1"
|
|
bitfld.word 0xA 2. "TOL12,Control of timer output level of channel 2" "0,1"
|
|
bitfld.word 0xA 1. "TOL11,Control of timer output level of channel 1" "0,1"
|
|
line.word 0xC "TOM1,Timer output mode register 0"
|
|
bitfld.word 0xC 7. "TOM17,Control of timer output mode of channel 7" "0,1"
|
|
bitfld.word 0xC 6. "TOM16,Control of timer output mode of channel 6" "0,1"
|
|
bitfld.word 0xC 5. "TOM15,Control of timer output mode of channel 5" "0,1"
|
|
bitfld.word 0xC 4. "TOM14,Control of timer output mode of channel 4" "0,1"
|
|
bitfld.word 0xC 3. "TOM13,Control of timer output mode of channel 3" "0,1"
|
|
bitfld.word 0xC 2. "TOM12,Control of timer output mode of channel 2" "0,1"
|
|
bitfld.word 0xC 1. "TOM11,Control of timer output mode of channel 1" "0,1"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x190)++0x1
|
|
line.word 0x0 "TDR1$1,Timer data register 0%s"
|
|
repeat.end
|
|
group.byte 0x192++0x1
|
|
line.byte 0x0 "TDR11L,Timer data lower register 11"
|
|
line.byte 0x1 "TDR11H,Timer data higher register 11"
|
|
group.byte 0x196++0x1
|
|
line.byte 0x0 "TDR13L,Timer data lower register 13"
|
|
line.byte 0x1 "TDR13H,Timer data higher register 13"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("BAT32G137*"))
|
|
base ad:0x500668
|
|
elif (cpuis("BAT32G157*"))
|
|
base ad:0x8500C68
|
|
elif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
base ad:0x500C68
|
|
endif
|
|
tree "TSN (Temperature Sensor Calibration Data)"
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "TSN85,The A/D conversion value of Temperature Sensor at 85 degrees and 3.0V reference voltage"
|
|
line.long 0x4 "TSN25,The A/D conversion value of Temperature Sensor at 25 degrees and 3.0V reference voltage"
|
|
tree.end
|
|
sif (cpuis("BAT32G137*"))
|
|
base ad:0x50084C
|
|
elif (cpuis("BAT32G157*"))
|
|
base ad:0x8500E4C
|
|
elif (cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
base ad:0x500E4C
|
|
endif
|
|
tree "UID (128-bit Unique ID)"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "UID$1,UID word %s"
|
|
repeat.end
|
|
tree.end
|
|
sif (cpuis("BAT32G157*"))
|
|
tree "USBF (USB 2.0 Full-Speed Module)"
|
|
base ad:0x40080000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SYSCFG,System Configuration Control Register"
|
|
bitfld.word 0x0 10. "SCKE,USB Clock Enable" "0,1"
|
|
bitfld.word 0x0 8. "CNEN,CNEN Single-Ended Receiver Enable" "0,1"
|
|
bitfld.word 0x0 6. "DCFM,Controller Function Select" "0,1"
|
|
bitfld.word 0x0 5. "DRPD,D+/D- Line Resistor Control" "0,1"
|
|
bitfld.word 0x0 4. "DPRPU,D+ Line Resistor Control" "0,1"
|
|
bitfld.word 0x0 3. "DMRPU,D- Line Resistor Control" "0,1"
|
|
bitfld.word 0x0 0. "USBE,USBFS Operation Enable" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SYSSTS0,System Configuration Status Register 0"
|
|
bitfld.word 0x0 14.--15. "OVCMON,External USB_OVRCURA/USB_OVRCURB Input Pin Monitor" "0,1,2,3"
|
|
bitfld.word 0x0 6. "HTACT,USB Host Sequencer Status Monitor" "0,1"
|
|
bitfld.word 0x0 2. "DMRPU,External ID0 Input Pin Monitor" "0,1"
|
|
bitfld.word 0x0 0.--1. "LNST,USB Data Line Status Monitor" "0,1,2,3"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "DVSTCTR0,Device State Control Register 0"
|
|
bitfld.word 0x0 11. "HNPBTOA,Host Negotiation Protocol (HNP) Control" "0,1"
|
|
bitfld.word 0x0 10. "EXICEN,USB_EXICEN Output Pin Contro" "0,1"
|
|
bitfld.word 0x0 9. "VBUSEN,USB_VBUSEN Output Pin Control" "0,1"
|
|
bitfld.word 0x0 8. "WKUP,Wakeup Output" "0,1"
|
|
bitfld.word 0x0 7. "RWUPE,Wakeup Detection Enable" "0,1"
|
|
bitfld.word 0x0 6. "USBRST,USB Bus Reset Output" "0,1"
|
|
bitfld.word 0x0 5. "RESUME,Resume Output" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "UACT,USB Bus Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "RHST,USB Bus Reset Status" "0,1,2,3,4,5,6,7"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "CFIFO,CFIFO Port Register"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "CFIFOL,CFIFO Port Register"
|
|
group.word 0x18++0x1
|
|
line.word 0x0 "D0FIFO,D0FIFO Port Register"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "D0FIFOL,D0FIFO Port Register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "D1FIFO,D1FIFO Port Register"
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x0 "D1FIFOL,D1FIFO Port Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "CFIFOSEL,CFIFO Port Select Register"
|
|
bitfld.word 0x0 15. "RCNT,Read Count Mode" "0,1"
|
|
bitfld.word 0x0 14. "REW,USB_EXICEN Output Pin Contro" "0,1"
|
|
bitfld.word 0x0 10. "MBW,CFIFO Port Access Bit Width" "0,1"
|
|
bitfld.word 0x0 8. "BIGEND,CFIFO Port Endian Control" "0,1"
|
|
bitfld.word 0x0 5. "ISEL,CFIFO Port Access Direction When DCP is Selected" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURPIPE,CFIFO Port Access Pipe Specification"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "D0FIFOSEL,D0FIFO Port Select Register"
|
|
bitfld.word 0x0 15. "RCNT,Read Count Mode" "0,1"
|
|
bitfld.word 0x0 14. "REW,USB_EXICEN Output Pin Contro" "0,1"
|
|
bitfld.word 0x0 13. "DCLRM,Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read" "0,1"
|
|
bitfld.word 0x0 12. "DREQE,DMA/DTC Transfer Request Enable" "0,1"
|
|
bitfld.word 0x0 10. "MBW,FIFO Port Access Bit Width" "0,1"
|
|
bitfld.word 0x0 8. "BIGEND,FIFO Port Endian Control" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURPIPE,FIFO Port Access Pipe Specification"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "D1FIFOSEL,D1FIFO Port Select Register"
|
|
bitfld.word 0x0 15. "RCNT,Read Count Mode" "0,1"
|
|
bitfld.word 0x0 14. "REW,USB_EXICEN Output Pin Contro" "0,1"
|
|
bitfld.word 0x0 13. "DCLRM,Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read" "0,1"
|
|
bitfld.word 0x0 12. "DREQE,DMA/DTC Transfer Request Enable" "0,1"
|
|
bitfld.word 0x0 10. "MBW,FIFO Port Access Bit Width" "0,1"
|
|
bitfld.word 0x0 8. "BIGEND,FIFO Port Endian Control" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURPIPE,FIFO Port Access Pipe Specification"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "CFIFOCTR,CFIFO Port Control Register"
|
|
bitfld.word 0x0 15. "BVAL,Buffer Memory Valid Flag" "0,1"
|
|
bitfld.word 0x0 14. "BCLR,CPU Buffer Clear" "0,1"
|
|
bitfld.word 0x0 13. "FRDY,FIFO Port Ready" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "DTLN,Receive Data Length"
|
|
group.word 0x2A++0x1
|
|
line.word 0x0 "D0FIFOCTR,D1FIFO Port Control Register"
|
|
bitfld.word 0x0 15. "BVAL,Buffer Memory Valid Flag" "0,1"
|
|
bitfld.word 0x0 14. "BCLR,CPU Buffer Clear" "0,1"
|
|
bitfld.word 0x0 13. "FRDY,FIFO Port Ready" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "DTLN,Receive Data Length"
|
|
group.word 0x2E++0x5
|
|
line.word 0x0 "D1FIFOCTR,D1FIFO Port Control Register"
|
|
bitfld.word 0x0 15. "BVAL,Buffer Memory Valid Flag" "0,1"
|
|
bitfld.word 0x0 14. "BCLR,CPU Buffer Clear" "0,1"
|
|
bitfld.word 0x0 13. "FRDY,FIFO Port Ready" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "DTLN,Receive Data Length"
|
|
line.word 0x2 "INTENB0,Interrupt Enable Register 0"
|
|
bitfld.word 0x2 15. "VBSE,VBUS Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 14. "RSME,Resume Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 13. "SOFE,Frame Number Update Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 12. "DVSE,Device State Transition Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 11. "CTRE,Control Transfer Stage Transition Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 10. "BEMPE,Buffer Empty Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 9. "NRDYE,Buffer Not Ready Response Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "BRDYE,Buffer Ready Interrupt Enable" "0,1"
|
|
line.word 0x4 "INTENB1,Interrupt Enable Register 1"
|
|
bitfld.word 0x4 15. "OVRCRE,Overcurrent Input Change Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 14. "BCHGE,USB Bus Change Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 12. "DTCHE,Disconnection Detection Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 11. "ATTCHE,Connection Detection Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 6. "EOFERRE,Setup Transaction Error Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 5. "SIGNE,Setup Transaction Error Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 4. "SACKE,Setup Transaction Normal Response Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 0. "PDDETINTE0,PDDETINT0 Detection Interrupt Enable" "0,1"
|
|
group.word 0x36++0x7
|
|
line.word 0x0 "BRDYENB,BRDY Interrupt Enable Register"
|
|
bitfld.word 0x0 9. "PIPE9BRDYE,BRDY Interrupt Enable for Pipe 9" "0,1"
|
|
bitfld.word 0x0 8. "PIPE8BRDYE,BRDY Interrupt Enable for Pipe 8" "0,1"
|
|
bitfld.word 0x0 7. "PIPE7BRDYE,BRDY Interrupt Enable for Pipe 7" "0,1"
|
|
bitfld.word 0x0 6. "PIPE6BRDYE,BRDY Interrupt Enable for Pipe 6" "0,1"
|
|
bitfld.word 0x0 5. "PIPE5BRDYE,BRDY Interrupt Enable for Pipe 5" "0,1"
|
|
bitfld.word 0x0 4. "PIPE4BRDYE,BRDY Interrupt Enable for Pipe 4" "0,1"
|
|
bitfld.word 0x0 3. "PIPE3BRDYE,BRDY Interrupt Enable for Pipe 3" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PIPE2BRDYE,BRDY Interrupt Enable for Pipe 2" "0,1"
|
|
bitfld.word 0x0 1. "PIPE1BRDYE,BRDY Interrupt Enable for Pipe 1" "0,1"
|
|
bitfld.word 0x0 0. "PIPE0BRDYE,BRDY Interrupt Enable for Pipe 0" "0,1"
|
|
line.word 0x2 "NRDYENB,NRDY Interrupt Enable Register"
|
|
bitfld.word 0x2 9. "PIPE9NRDYE,NRDY Interrupt Enable for Pipe 9" "0,1"
|
|
bitfld.word 0x2 8. "PIPE8NRDYE,NRDY Interrupt Enable for Pipe 8" "0,1"
|
|
bitfld.word 0x2 7. "PIPE7NRDYE,NRDY Interrupt Enable for Pipe 7" "0,1"
|
|
bitfld.word 0x2 6. "PIPE6NRDYE,NRDY Interrupt Enable for Pipe 6" "0,1"
|
|
bitfld.word 0x2 5. "PIPE5NRDYE,NRDY Interrupt Enable for Pipe 5" "0,1"
|
|
bitfld.word 0x2 4. "PIPE4NRDYE,NRDY Interrupt Enable for Pipe 4" "0,1"
|
|
bitfld.word 0x2 3. "PIPE3NRDYE,NRDY Interrupt Enable for Pipe 3" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "PIPE2NRDYE,NRDY Interrupt Enable for Pipe 2" "0,1"
|
|
bitfld.word 0x2 1. "PIPE1NRDYE,NRDY Interrupt Enable for Pipe 1" "0,1"
|
|
bitfld.word 0x2 0. "PIPE0NRDYE,NRDY Interrupt Enable for Pipe 0" "0,1"
|
|
line.word 0x4 "BEMPENB,BEMP Interrupt Enable Register"
|
|
bitfld.word 0x4 9. "PIPE9BEMPE,BEMP Interrupt Enable for Pipe 9" "0,1"
|
|
bitfld.word 0x4 8. "PIPE8BEMPE,BEMP Interrupt Enable for Pipe 8" "0,1"
|
|
bitfld.word 0x4 7. "PIPE7BEMPE,BEMP Interrupt Enable for Pipe 7" "0,1"
|
|
bitfld.word 0x4 6. "PIPE6BEMPE,BEMP Interrupt Enable for Pipe 6" "0,1"
|
|
bitfld.word 0x4 5. "PIPE5BEMPE,BEMP Interrupt Enable for Pipe 5" "0,1"
|
|
bitfld.word 0x4 4. "PIPE4BEMPE,BEMP Interrupt Enable for Pipe 4" "0,1"
|
|
bitfld.word 0x4 3. "PIPE3BEMPE,BEMP Interrupt Enable for Pipe 3" "0,1"
|
|
newline
|
|
bitfld.word 0x4 2. "PIPE2BEMPE,BEMP Interrupt Enable for Pipe 2" "0,1"
|
|
bitfld.word 0x4 1. "PIPE1BEMPE,BEMP Interrupt Enable for Pipe 1" "0,1"
|
|
bitfld.word 0x4 0. "PIPE0BEMPE,BEMP Interrupt Enable for Pipe 0" "0,1"
|
|
line.word 0x6 "SOFCFG,SOF Output Configuration Register"
|
|
bitfld.word 0x6 8. "TRNENSEL,Transaction-Enabled Time Select" "0,1"
|
|
bitfld.word 0x6 6. "BRDYM,BRDY Interrupt Status Clear Timing" "0,1"
|
|
bitfld.word 0x6 4. "EDGESTS,Edge Interrupt Output Status Monitor" "0,1"
|
|
group.word 0x40++0x3
|
|
line.word 0x0 "INTSTS0,Interrupt Status Register 0"
|
|
bitfld.word 0x0 15. "VBINT,VBUS Interrupt Status" "0,1"
|
|
bitfld.word 0x0 14. "RESM,Resume Interrupt Status" "0,1"
|
|
bitfld.word 0x0 13. "SOFR,Frame Number Update Interrupt Status" "0,1"
|
|
bitfld.word 0x0 12. "DVST,Device State Transition Interrupt Status" "0,1"
|
|
bitfld.word 0x0 11. "CTRT,Control Transfer Stage Transition Interrupt Status" "0,1"
|
|
bitfld.word 0x0 10. "BEMP,Buffer Empty Interrupt Status" "0,1"
|
|
bitfld.word 0x0 9. "NRDY,Buffer Not Ready Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "BRDY,Buffer Ready Interrupt Status" "0,1"
|
|
bitfld.word 0x0 7. "VBSTS,VBUS Input Status" "0,1"
|
|
bitfld.word 0x0 4.--6. "DVSQ,Device State" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 3. "VALID,USB Request Reception" "0,1"
|
|
bitfld.word 0x0 0.--2. "CTSQ,Control Transfer Stage" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "INTSTS1,Interrupt Status Register 1"
|
|
bitfld.word 0x2 15. "OVRCR,Overcurrent Input Change Interrupt Status" "0,1"
|
|
bitfld.word 0x2 14. "BCHG,USB Bus Change Interrupt Status" "0,1"
|
|
bitfld.word 0x2 12. "DTCH,Disconnection Detection Interrupt Status" "0,1"
|
|
bitfld.word 0x2 11. "ATTCH,Connection Detection Interrupt Status" "0,1"
|
|
bitfld.word 0x2 6. "EOFERR,Setup Transaction Error Interrupt Status" "0,1"
|
|
bitfld.word 0x2 5. "SIGN,Setup Transaction Error Interrupt Status" "0,1"
|
|
bitfld.word 0x2 4. "SACK,Setup Transaction Normal Response Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "PDDETINT0,PDDETINT0 Detection Interrupt Status" "0,1"
|
|
group.word 0x46++0x7
|
|
line.word 0x0 "BRDYSTS,BRDY Interrupt Status Register"
|
|
bitfld.word 0x0 9. "PIPE9BRDY,BRDY Interrupt Status for Pipe 9" "0,1"
|
|
bitfld.word 0x0 8. "PIPE8BRDY,BRDY Interrupt Status for Pipe 8" "0,1"
|
|
bitfld.word 0x0 7. "PIPE7BRDY,BRDY Interrupt Status for Pipe 7" "0,1"
|
|
bitfld.word 0x0 6. "PIPE6BRDY,BRDY Interrupt Status for Pipe 6" "0,1"
|
|
bitfld.word 0x0 5. "PIPE5BRDY,BRDY Interrupt Status for Pipe 5" "0,1"
|
|
bitfld.word 0x0 4. "PIPE4BRDY,BRDY Interrupt Status for Pipe 4" "0,1"
|
|
bitfld.word 0x0 3. "PIPE3BRDY,BRDY Interrupt Status for Pipe 3" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PIPE2BRDY,BRDY Interrupt Status for Pipe 2" "0,1"
|
|
bitfld.word 0x0 1. "PIPE1BRDY,BRDY Interrupt Status for Pipe 1" "0,1"
|
|
bitfld.word 0x0 0. "PIPE0BRDY,BRDY Interrupt Status for Pipe 0" "0,1"
|
|
line.word 0x2 "NRDYSTS,NRDY Interrupt Status Register"
|
|
bitfld.word 0x2 9. "PIPE9NRDY,NRDY Interrupt Status for Pipe 9" "0,1"
|
|
bitfld.word 0x2 8. "PIPE8NRDY,NRDY Interrupt Status for Pipe 8" "0,1"
|
|
bitfld.word 0x2 7. "PIPE7NRDY,NRDY Interrupt Status for Pipe 7" "0,1"
|
|
bitfld.word 0x2 6. "PIPE6NRDY,NRDY Interrupt Status for Pipe 6" "0,1"
|
|
bitfld.word 0x2 5. "PIPE5NRDY,NRDY Interrupt Status for Pipe 5" "0,1"
|
|
bitfld.word 0x2 4. "PIPE4NRDY,NRDY Interrupt Status for Pipe 4" "0,1"
|
|
bitfld.word 0x2 3. "PIPE3NRDY,NRDY Interrupt Status for Pipe 3" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "PIPE2NRDY,NRDY Interrupt Status for Pipe 2" "0,1"
|
|
bitfld.word 0x2 1. "PIPE1NRDY,NRDY Interrupt Status for Pipe 1" "0,1"
|
|
bitfld.word 0x2 0. "PIPE0NRDY,NRDY Interrupt Status for Pipe 0" "0,1"
|
|
line.word 0x4 "BEMPSTS,BEMP Interrupt Status Register"
|
|
bitfld.word 0x4 9. "PIPE9BEMP,BEMP Interrupt Status for Pipe 9" "0,1"
|
|
bitfld.word 0x4 8. "PIPE8BEMP,BEMP Interrupt Status for Pipe 8" "0,1"
|
|
bitfld.word 0x4 7. "PIPE7BEMP,BEMP Interrupt Status for Pipe 7" "0,1"
|
|
bitfld.word 0x4 6. "PIPE6BEMP,BEMP Interrupt Status for Pipe 6" "0,1"
|
|
bitfld.word 0x4 5. "PIPE5BEMP,BEMP Interrupt Status for Pipe 5" "0,1"
|
|
bitfld.word 0x4 4. "PIPE4BEMP,BEMP Interrupt Status for Pipe 4" "0,1"
|
|
bitfld.word 0x4 3. "PIPE3BEMP,BEMP Interrupt Status for Pipe 3" "0,1"
|
|
newline
|
|
bitfld.word 0x4 2. "PIPE2BEMP,BEMP Interrupt Status for Pipe 2" "0,1"
|
|
bitfld.word 0x4 1. "PIPE1BEMP,BEMP Interrupt Status for Pipe 1" "0,1"
|
|
bitfld.word 0x4 0. "PIPE0BEMP,BEMP Interrupt Status for Pipe 0" "0,1"
|
|
line.word 0x6 "FRMNUM,Frame Number Register"
|
|
bitfld.word 0x6 15. "OVRN,Overrun/Underrun Detection Status" "0,1"
|
|
bitfld.word 0x6 14. "CRCE,Receive Data Error" "0,1"
|
|
hexmask.word 0x6 0.--10. 1. "FRNM,Frame Number"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "USBREQ,USB Request Type Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "BREQUEST,Request"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BMREQUESTTYPE,Request Type"
|
|
group.word 0x56++0xB
|
|
line.word 0x0 "USBVAL,USB Request Value Register"
|
|
line.word 0x2 "USBINDX,USB Request Index Register"
|
|
line.word 0x4 "USBLENG,USB Request Length Register"
|
|
line.word 0x6 "DCPCFG,DCP Configuration Register"
|
|
bitfld.word 0x6 7. "SHTNAK,Pipe Disabled at End of Transfer" "0,1"
|
|
bitfld.word 0x6 4. "DIR,Transfer Direction" "0,1"
|
|
line.word 0x8 "DCPMAXP,DCP Maximum Packet Size Register"
|
|
hexmask.word.byte 0x8 12.--15. 1. "DEVSEL,Device Select"
|
|
hexmask.word.byte 0x8 0.--6. 1. "MXPS,Maximum Packet Size"
|
|
line.word 0xA "DCPCTR,DCP Control Register"
|
|
bitfld.word 0xA 15. "BSTS,Buffer Status" "0,1"
|
|
bitfld.word 0xA 14. "SUREQ,Setup Token Transmission" "0,1"
|
|
bitfld.word 0xA 11. "SUREQCLR,SUREQ Bit Clear" "0,1"
|
|
bitfld.word 0xA 8. "SQCLR,Sequence Toggle Bit Clear" "0,1"
|
|
bitfld.word 0xA 7. "SQSET,Sequence Toggle Bit Set" "0,1"
|
|
bitfld.word 0xA 6. "SQMON,Sequence Toggle Bit Monitor" "0,1"
|
|
bitfld.word 0xA 5. "PBUSY,Pipe Busy" "0,1"
|
|
newline
|
|
bitfld.word 0xA 2. "CCPL,Control Transfer End Enable" "0,1"
|
|
bitfld.word 0xA 0.--1. "PID,Response PID" "0,1,2,3"
|
|
group.word 0x64++0x1
|
|
line.word 0x0 "PIPESEL,Pipe Window Select Register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "PIPESEL,Pipe Window Select"
|
|
group.word 0x68++0x1
|
|
line.word 0x0 "PIPECFG,Pipe Configuration Register"
|
|
bitfld.word 0x0 14.--15. "TYPE,Transfer Type" "0,1,2,3"
|
|
bitfld.word 0x0 10. "BFRE,BRDY Interrupt Operation Specification" "0,1"
|
|
bitfld.word 0x0 9. "DBLB,Double Buffer Mode" "0,1"
|
|
bitfld.word 0x0 7. "SHTNAK,Pipe Disabled at End of Transfer" "0,1"
|
|
bitfld.word 0x0 4. "DIR,Transfer Direction" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "EPNUM,Endpoint Number"
|
|
group.word 0x6C++0x15
|
|
line.word 0x0 "PIPEMAXP,Pipe Maximum Packet Size Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DEVSEL,Device Select"
|
|
hexmask.word 0x0 0.--8. 1. "MXPS,Maximum Packet Size"
|
|
line.word 0x2 "PIPEPERI,Pipe Cycle Control Register"
|
|
bitfld.word 0x2 12. "IFIS,Isochronous IN Buffer Flush" "0,1"
|
|
bitfld.word 0x2 0.--2. "IITV,Interval Error Detection Interval" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "PIPE1CTR,PIPE1 Control Registers"
|
|
bitfld.word 0x4 15. "BSTS,Buffer Status" "0,1"
|
|
bitfld.word 0x4 14. "INBUFM,Transmit Buffer Monitor" "0,1"
|
|
bitfld.word 0x4 10. "ATREPM,Auto Response Mode" "0,1"
|
|
bitfld.word 0x4 9. "ACLRM,Auto Buffer Clear Mode" "0,1"
|
|
bitfld.word 0x4 8. "SQCLR,Sequence Toggle Bit Clear" "0,1"
|
|
bitfld.word 0x4 7. "SQSET,Sequence Toggle Bit Set" "0,1"
|
|
bitfld.word 0x4 6. "SQMON,Sequence Toggle Bit Confirmation" "0,1"
|
|
newline
|
|
bitfld.word 0x4 5. "PBUSY,Pipe Busy" "0,1"
|
|
bitfld.word 0x4 0.--1. "PID,Response PID" "0,1,2,3"
|
|
line.word 0x6 "PIPE2CTR,PIPE2 Control Registers"
|
|
bitfld.word 0x6 15. "BSTS,Buffer Status" "0,1"
|
|
bitfld.word 0x6 14. "INBUFM,Transmit Buffer Monitor" "0,1"
|
|
bitfld.word 0x6 10. "ATREPM,Auto Response Mode" "0,1"
|
|
bitfld.word 0x6 9. "ACLRM,Auto Buffer Clear Mode" "0,1"
|
|
bitfld.word 0x6 8. "SQCLR,Sequence Toggle Bit Clear" "0,1"
|
|
bitfld.word 0x6 7. "SQSET,Sequence Toggle Bit Set" "0,1"
|
|
bitfld.word 0x6 6. "SQMON,Sequence Toggle Bit Confirmation" "0,1"
|
|
newline
|
|
bitfld.word 0x6 5. "PBUSY,Pipe Busy" "0,1"
|
|
bitfld.word 0x6 0.--1. "PID,Response PID" "0,1,2,3"
|
|
line.word 0x8 "PIPE3CTR,PIPE3 Control Registers"
|
|
bitfld.word 0x8 15. "BSTS,Buffer Status" "0,1"
|
|
bitfld.word 0x8 14. "INBUFM,Transmit Buffer Monitor" "0,1"
|
|
bitfld.word 0x8 10. "ATREPM,Auto Response Mode" "0,1"
|
|
bitfld.word 0x8 9. "ACLRM,Auto Buffer Clear Mode" "0,1"
|
|
bitfld.word 0x8 8. "SQCLR,Sequence Toggle Bit Clear" "0,1"
|
|
bitfld.word 0x8 7. "SQSET,Sequence Toggle Bit Set" "0,1"
|
|
bitfld.word 0x8 6. "SQMON,Sequence Toggle Bit Confirmation" "0,1"
|
|
newline
|
|
bitfld.word 0x8 5. "PBUSY,Pipe Busy" "0,1"
|
|
bitfld.word 0x8 0.--1. "PID,Response PID" "0,1,2,3"
|
|
line.word 0xA "PIPE4CTR,PIPE4 Control Registers"
|
|
bitfld.word 0xA 15. "BSTS,Buffer Status" "0,1"
|
|
bitfld.word 0xA 14. "INBUFM,Transmit Buffer Monitor" "0,1"
|
|
bitfld.word 0xA 10. "ATREPM,Auto Response Mode" "0,1"
|
|
bitfld.word 0xA 9. "ACLRM,Auto Buffer Clear Mode" "0,1"
|
|
bitfld.word 0xA 8. "SQCLR,Sequence Toggle Bit Clear" "0,1"
|
|
bitfld.word 0xA 7. "SQSET,Sequence Toggle Bit Set" "0,1"
|
|
bitfld.word 0xA 6. "SQMON,Sequence Toggle Bit Confirmation" "0,1"
|
|
newline
|
|
bitfld.word 0xA 5. "PBUSY,Pipe Busy" "0,1"
|
|
bitfld.word 0xA 0.--1. "PID,Response PID" "0,1,2,3"
|
|
line.word 0xC "PIPE5CTR,PIPE5 Control Registers"
|
|
bitfld.word 0xC 15. "BSTS,Buffer Status" "0,1"
|
|
bitfld.word 0xC 14. "INBUFM,Transmit Buffer Monitor" "0,1"
|
|
bitfld.word 0xC 10. "ATREPM,Auto Response Mode" "0,1"
|
|
bitfld.word 0xC 9. "ACLRM,Auto Buffer Clear Mode" "0,1"
|
|
bitfld.word 0xC 8. "SQCLR,Sequence Toggle Bit Clear" "0,1"
|
|
bitfld.word 0xC 7. "SQSET,Sequence Toggle Bit Set" "0,1"
|
|
bitfld.word 0xC 6. "SQMON,Sequence Toggle Bit Confirmation" "0,1"
|
|
newline
|
|
bitfld.word 0xC 5. "PBUSY,Pipe Busy" "0,1"
|
|
bitfld.word 0xC 0.--1. "PID,Response PID" "0,1,2,3"
|
|
line.word 0xE "PIPE6CTR,PIPE6 Control Registers"
|
|
bitfld.word 0xE 15. "BSTS,Buffer Status" "0,1"
|
|
bitfld.word 0xE 9. "ACLRM,Auto Buffer Clear Mode" "0,1"
|
|
bitfld.word 0xE 8. "SQCLR,Sequence Toggle Bit Clear" "0,1"
|
|
bitfld.word 0xE 7. "SQSET,Sequence Toggle Bit Set" "0,1"
|
|
bitfld.word 0xE 6. "SQMON,Sequence Toggle Bit Confirmation" "0,1"
|
|
bitfld.word 0xE 5. "PBUSY,Pipe Busy" "0,1"
|
|
bitfld.word 0xE 0.--1. "PID,Response PID" "0,1,2,3"
|
|
line.word 0x10 "PIPE7CTR,PIPE7 Control Registers"
|
|
bitfld.word 0x10 15. "BSTS,Buffer Status" "0,1"
|
|
bitfld.word 0x10 9. "ACLRM,Auto Buffer Clear Mode" "0,1"
|
|
bitfld.word 0x10 8. "SQCLR,Sequence Toggle Bit Clear" "0,1"
|
|
bitfld.word 0x10 7. "SQSET,Sequence Toggle Bit Set" "0,1"
|
|
bitfld.word 0x10 6. "SQMON,Sequence Toggle Bit Confirmation" "0,1"
|
|
bitfld.word 0x10 5. "PBUSY,Pipe Busy" "0,1"
|
|
bitfld.word 0x10 0.--1. "PID,Response PID" "0,1,2,3"
|
|
line.word 0x12 "PIPE8CTR,PIPE8 Control Registers"
|
|
bitfld.word 0x12 15. "BSTS,Buffer Status" "0,1"
|
|
bitfld.word 0x12 9. "ACLRM,Auto Buffer Clear Mode" "0,1"
|
|
bitfld.word 0x12 8. "SQCLR,Sequence Toggle Bit Clear" "0,1"
|
|
bitfld.word 0x12 7. "SQSET,Sequence Toggle Bit Set" "0,1"
|
|
bitfld.word 0x12 6. "SQMON,Sequence Toggle Bit Confirmation" "0,1"
|
|
bitfld.word 0x12 5. "PBUSY,Pipe Busy" "0,1"
|
|
bitfld.word 0x12 0.--1. "PID,Response PID" "0,1,2,3"
|
|
line.word 0x14 "PIPE9CTR,PIPE9 Control Registers"
|
|
bitfld.word 0x14 15. "BSTS,Buffer Status" "0,1"
|
|
bitfld.word 0x14 9. "ACLRM,Auto Buffer Clear Mode" "0,1"
|
|
bitfld.word 0x14 8. "SQCLR,Sequence Toggle Bit Clear" "0,1"
|
|
bitfld.word 0x14 7. "SQSET,Sequence Toggle Bit Set" "0,1"
|
|
bitfld.word 0x14 6. "SQMON,Sequence Toggle Bit Confirmation" "0,1"
|
|
bitfld.word 0x14 5. "PBUSY,Pipe Busy" "0,1"
|
|
bitfld.word 0x14 0.--1. "PID,Response PID" "0,1,2,3"
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x90)++0x1
|
|
line.word 0x0 "PIPE$1TRE,PIPE%s Transaction Counter Enable Register"
|
|
bitfld.word 0x0 9. "TRENB,Transaction Counter Enable" "0,1"
|
|
bitfld.word 0x0 8. "TRCLR,Transaction Counter Clear" "0,1"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x92)++0x1
|
|
line.word 0x0 "PIPE$1TRN,PIPE%s Transaction Counter Register"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0xD0)++0x1
|
|
line.word 0x0 "DEVADDn$1,Device Address %s Configuration Register"
|
|
bitfld.word 0x0 6.--7. "USBSPD,Transfer Speed of Communication Target Device" "0,1,2,3"
|
|
repeat.end
|
|
group.word 0xCC++0x1
|
|
line.word 0x0 "USBMC,USB Module Control Register"
|
|
bitfld.word 0x0 7. "VDCEN,USB Regulator On/Off Control" "0,1"
|
|
bitfld.word 0x0 0. "VDDUSBE,USB Reference Power Supply Circuit On/Off Control" "0,1"
|
|
group.word 0xB0++0x1
|
|
line.word 0x0 "USBBCCTRL,BC Control Register 0"
|
|
bitfld.word 0x0 9. "PDDETSTS0,D+ Pin 0.6 V Input Detection Status" "0,1"
|
|
bitfld.word 0x0 8. "CHGDETSTS0,D- Pin 0.6 V Input Detection Status" "0,1"
|
|
bitfld.word 0x0 7. "BATCHGE0,BC (Battery Charger) Function General Enable Control" "0,1"
|
|
bitfld.word 0x0 5. "VDMSRCE0,D- Pin VDMSRC (0.6 V) Output Contro" "0,1"
|
|
bitfld.word 0x0 4. "IDPSINKE0,D+ Pin 0.6 V Input Detection (Comparator and Sink) Control" "0,1"
|
|
bitfld.word 0x0 3. "VDPSRCE0,D+ Pin VDPSRC (0.6 V) Output Contro" "0,1"
|
|
bitfld.word 0x0 2. "IDMSINKE0,D- Pin 0.6 V Input Detection (Comparator and Sink) Control" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "IDPSRCE0,D+ Pin IDPSRC Output Control" "0,1"
|
|
bitfld.word 0x0 0. "RPDME0,D- Pin Pull-Down Control" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("BAT32G137*")||cpuis("BAT32G139*")||cpuis("BAT32G179*"))
|
|
base ad:0x40021000
|
|
elif (cpuis("BAT32G157*"))
|
|
base ad:0x40020404
|
|
endif
|
|
tree "WDT (Watchdog Timer)"
|
|
sif (cpuis("BAT32G137*"))
|
|
group.byte 0x1++0x0
|
|
line.byte 0x0 "WDTE,Watchdog timer enable register"
|
|
endif
|
|
sif (cpuis("BAT32G157*"))
|
|
group.byte 0x1++0x1
|
|
line.byte 0x0 "LOCKCTL,Lockup Watchdog timer enable register"
|
|
line.byte 0x1 "PRCR,Lockup Watchdog timer enable protect register"
|
|
group.byte 0xBFD++0x0
|
|
line.byte 0x0 "WDTE,Watchdog timer enable register"
|
|
endif
|
|
sif (cpuis("BAT32G139*"))
|
|
group.byte 0x1++0x0
|
|
line.byte 0x0 "WDTE,Watchdog timer enable register"
|
|
endif
|
|
sif (cpuis("BAT32G179*"))
|
|
group.byte 0x1++0x0
|
|
line.byte 0x0 "WDTE,Watchdog timer enable register"
|
|
endif
|
|
tree.end
|
|
newline
|
|
AUTOINDENT.OFF
|