424 lines
15 KiB
Plaintext
424 lines
15 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: LX61210 Specific Menu
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; @Props: Released
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; @Author: BWR, KRZ
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; @Changelog: 2022-06-14 BWR
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; 2022-06-30 KRZ
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; @Manufacturer: LX_SEMICON - LX Semicon Co., Ltd.
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; @Core: Cortex-M4F
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; @Chip: LX61210
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; @Copyright: (C) 2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menlx61210.men 19311 2025-03-31 12:37:24Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)&&CPU.FEATURE(MPUTRANSLATION)
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(
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popup "[:mmu]MMU/MPU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU/MPU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU/MPU Table List" "MMU.List.PageTable"
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IF CPU.FEATURE(ITLBDUMP)||CPU.FEATURE(DTLBDUMP)||CPU.FEATURE(TLB0DUMP)||CPU.FEATURE(TLB1DUMP)
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(
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separator
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)
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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ELSE
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(
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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IF CPU.FEATURE(ITLBDUMP)||CPU.FEATURE(DTLBDUMP)||CPU.FEATURE(TLB0DUMP)||CPU.FEATURE(TLB1DUMP)
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(
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separator
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)
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF CPU.FEATURE(MPUTRANSLATION)
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(
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popup "[:mmu]MPU"
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(
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menuitem "[:mmu]MPU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MPU Table List" "MMU.List.PageTable"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHEDUMP)||CPU.FEATURE(L1DCACHEDUMP)||CPU.FEATURE(L2CACHEDUMP)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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popup "ADC;Analog-to-Digital Converter"
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(
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menuitem "ADC0" "per , ""ADC (Analog-to-Digital Converter),ADC0"""
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menuitem "ADC1" "per , ""ADC (Analog-to-Digital Converter),ADC1"""
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)
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menuitem "ANACON;Analog Controller Unit" "per , ""ANACON (Analog Controller Unit)"""
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menuitem "CCU;System Clock Controller" "per , ""CCU (System Clock Controller)"""
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menuitem "CFCTRL;Flash Controller" "per , ""CFCTRL (Flash Controller)"""
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menuitem "CMC;Clock Monitoring Circuit" "per , ""CMC (Clock Monitoring Circuit)"""
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menuitem "DFCTRL;Flash Controller" "per , ""DFCTRL (Flash Controller)"""
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menuitem "DMA;Direct Memory Access" "per , ""DMA (Direct Memory Access)"""
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popup "DNF;Digital Noise Filter"
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(
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menuitem "DNFA" "per , ""DNF (Digital Noise Filter),DNFA"""
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menuitem "DNFB" "per , ""DNF (Digital Noise Filter),DNFB"""
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menuitem "DNFC" "per , ""DNF (Digital Noise Filter),DNFC"""
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menuitem "DNFD" "per , ""DNF (Digital Noise Filter),DNFD"""
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menuitem "DNFX" "per , ""DNF (Digital Noise Filter),DNFX"""
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)
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popup "GPIO;General Purpose I/O"
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(
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menuitem "GPIOA" "per , ""GPIO (General Purpose I/O),GPIOA"""
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menuitem "GPIOB" "per , ""GPIO (General Purpose I/O),GPIOB"""
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menuitem "GPIOC" "per , ""GPIO (General Purpose I/O),GPIOC"""
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menuitem "GPIOD" "per , ""GPIO (General Purpose I/O),GPIOD"""
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menuitem "GPIOX" "per , ""GPIO (General Purpose I/O),GPIOX"""
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)
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menuitem "GPIOM;GPIO Management" "per , ""GPIOM (GPIO Management)"""
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popup "GPIOPD;General Purpose I/O Port Division"
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(
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menuitem "GPPDA" "per , ""GPIOPD (General Purpose I/O Port Division),GPPDA"""
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menuitem "GPPDB" "per , ""GPIOPD (General Purpose I/O Port Division),GPPDB"""
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menuitem "GPPDC" "per , ""GPIOPD (General Purpose I/O Port Division),GPPDC"""
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menuitem "GPPDD" "per , ""GPIOPD (General Purpose I/O Port Division),GPPDD"""
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menuitem "GPPDX" "per , ""GPIOPD (General Purpose I/O Port Division),GPPDX"""
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)
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menuitem "I2CM;Inter-Integrated Circuit for Master" "per , ""I2CM (Inter-Integrated Circuit for Master)"""
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popup "I2CS;Inter-Integrated Circuit for Slave"
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(
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menuitem "I2CS0" "per , ""I2CS (Inter-Integrated Circuit for Slave),I2CS0"""
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menuitem "I2CS1" "per , ""I2CS (Inter-Integrated Circuit for Slave),I2CS1"""
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)
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menuitem "ICU;System Interrupt Controller" "per , ""ICU (System Interrupt Controller)"""
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popup "IOC;I/O Controller"
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(
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menuitem "IOCA" "per , ""IOC (I/O Controller),IOCA"""
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menuitem "IOCB" "per , ""IOC (I/O Controller),IOCB"""
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menuitem "IOCC" "per , ""IOC (I/O Controller),IOCC"""
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menuitem "IOCD" "per , ""IOC (I/O Controller),IOCD"""
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menuitem "IOCX" "per , ""IOC (I/O Controller),IOCX"""
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)
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menuitem "IOCPTC;I/O Controller for Protection" "per , ""IOCPTC (I/O Controller for Protection)"""
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menuitem "IWDT;Independent Watchdog Timer" "per , ""IWDT (Independent Watchdog Timer)"""
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popup "MFTP;Multi-Function Timer P Unit"
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(
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menuitem "MFTP0" "per , ""MFTP (Multi-Function Timer P Unit),MFTP0"""
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menuitem "MFTP1" "per , ""MFTP (Multi-Function Timer P Unit),MFTP1"""
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menuitem "MFTP2" "per , ""MFTP (Multi-Function Timer P Unit),MFTP2"""
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menuitem "MFTP3" "per , ""MFTP (Multi-Function Timer P Unit),MFTP3"""
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menuitem "MFTP4" "per , ""MFTP (Multi-Function Timer P Unit),MFTP4"""
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menuitem "MFTP5" "per , ""MFTP (Multi-Function Timer P Unit),MFTP5"""
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menuitem "MFTP6" "per , ""MFTP (Multi-Function Timer P Unit),MFTP6"""
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menuitem "MFTP7" "per , ""MFTP (Multi-Function Timer P Unit),MFTP7"""
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menuitem "MFTPC;Common" "per , ""MFTP (Multi-Function Timer P Unit),MFTPC (Common)"""
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)
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popup "MFTR;Multi-Function Timer R Unit"
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(
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menuitem "MFTR0" "per , ""MFTR (Multi-Function Timer R Unit),MFTR0"""
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menuitem "MFTR1" "per , ""MFTR (Multi-Function Timer R Unit),MFTR1"""
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menuitem "MFTR2" "per , ""MFTR (Multi-Function Timer R Unit),MFTR2"""
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menuitem "MFTR3" "per , ""MFTR (Multi-Function Timer R Unit),MFTR3"""
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menuitem "MFTR4" "per , ""MFTR (Multi-Function Timer R Unit),MFTR4"""
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menuitem "MFTRC;Common" "per , ""MFTR (Multi-Function Timer R Unit),MFTRC (Common)"""
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)
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menuitem "PMU;System Power Management Controller" "per , ""PMU (Program Memory Unit)"""
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menuitem "RCU;System Reset Controller" "per , ""RCU (System Reset Controller)"""
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popup "SPI;Serial Peripheral Interface"
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(
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menuitem "SPI0" "per , ""SPI (Serial Peripheral Interface),SPI0"""
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menuitem "SPI1" "per , ""SPI (Serial Peripheral Interface),SPI1"""
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)
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popup "SRCTRL;SRAM Controller"
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(
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menuitem "SRCTRL0" "per , ""SRCTRL (SRAM Controller),SRCTRL0"""
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menuitem "SRCTRL1" "per , ""SRCTRL (SRAM Controller),SRCTRL1"""
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)
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popup "TMS;Simple Timers"
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(
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menuitem "TMS00" "per , ""TMS (Simple Timers),TMS00"""
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menuitem "TMS01" "per , ""TMS (Simple Timers),TMS01"""
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menuitem "TMS02" "per , ""TMS (Simple Timers),TMS02"""
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menuitem "TMS03" "per , ""TMS (Simple Timers),TMS03"""
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menuitem "TMS10" "per , ""TMS (Simple Timers),TMS10"""
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menuitem "TMS11" "per , ""TMS (Simple Timers),TMS11"""
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menuitem "TMS12" "per , ""TMS (Simple Timers),TMS12"""
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menuitem "TMS13" "per , ""TMS (Simple Timers),TMS13"""
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menuitem "TMS20" "per , ""TMS (Simple Timers),TMS20"""
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menuitem "TMS21" "per , ""TMS (Simple Timers),TMS21"""
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menuitem "TMS22" "per , ""TMS (Simple Timers),TMS22"""
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menuitem "TMS23" "per , ""TMS (Simple Timers),TMS23"""
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)
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popup "UART;Universal Asynchronous Receiver/Transmitter"
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(
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menuitem "UART0" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART0"""
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menuitem "UART1" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART1"""
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menuitem "UART2" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART2"""
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menuitem "UART3" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART3"""
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menuitem "UART4" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART4"""
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)
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menuitem "WDT;Watchdog Timer" "per , ""WDT (Watchdog Timer Unit)"""
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)
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)
|